FPGA-FAQ    0030

How to initialize SRL16E

Vendor Xilinx
FAQ Entry Author Philip Freidin / Ray Andraka
FAQ Entry Editor Philip Freidin
FAQ Entry Date 3/2/2002

Q. How to initialize SRL16E


          Lifted and edited from the article archive. Article author is Ray Andraka.
          Additional code from Ray, not posted to the news group.

    You need to initialize these twice.  Once with a generic for the
    simulation, and once with an INIT= attribute for the back end tools.

    The generic has to be ignored during synthesis, which means it must be
    surrounded by translate_off/on pragmas.  Note that the format for the
    generic is different than that for the attribute.  In the example
    below, itoh is an integer to hex string conversion, and int2bit_vec is
    an integer to bit_vector conversion.  These are used to get the
    correct formats for the two init strings.

 attribute INIT   of U1 : label is itoh(lut_init);  --INIT= attribute to pass to PAR through synplicity

         U1: SRL16E
         --synthesis translate_off
         generic map (     -- init generic is for simulation model, not seen by Synplicity or PAR
           INIT => int2bit_vec(lut_init,16))
         --synthesis translate_on

  port map (
   Q  => y,
   A0 => tap(0),
   A1 => tap(1),
   A2 => tap(2),
   A3 => tap(3),
   D  => ldi(i),
   CLK => clk,
   CE => we );


--  convert 16 bit integer to 4 digit ascii hex string
--  for INIT= attribute for PAR

function itoh (val:natural) return string is
         type hex_lut is array (0 to 15) of character;-- string (1 to 1);
         constant hextable:hex_lut :=
                 ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 
                  'B', 'C', 'D', 'E', 'F');
         variable temp: natural;
         variable ret_string: string (4 downto 1);
                 for i in 1 to 4 loop
                         ret_string(i) := hextable(temp mod 16);
                         temp:= temp/16;
                 end loop;
                 return ret_string;
end itoh;

-- convert integer to bit vector for INIT attribute simulations

function int2bit_vec(A: integer; SIZE: integer) return BIT_VECTOR is
         variable RESULT: BIT_VECTOR(SIZE-1 downto 0);
         variable TMP: integer;
                 for i in 0 to SIZE-1 loop
                         if TMP mod 2 = 1 then RESULT(i):='1';
                         else RESULT(i):='0';
                         end if;
                         TMP:=TMP / 2;
                 end loop;
         return RESULT;
end int2bit_vec;