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Messages from 600

Article: 600
Subject: Re: PCB design with Xilinx
From: brown@hercules (Paul Brown)
Date: 16 Jan 1995 17:33:12 GMT
Links: << >>  << T >>  << A >>
postmaster@lsantist.dfrf.nasa.gov wrote:

: In article <3f14rd$ati@hptemp1.cc.umr.edu>, <weathert@ee.umr.edu> writes:
: > 
: > 	I am currently designing a board that is using both 240 pin and 208
: > pin quadflat pack packages for the 4013 and 4010 xilinx chips respectively.
: > My problem is finding specifications for the design of the footprint of these
: > chips.  I am using Mentor graphics boardstation which contains some basic
: > pads but nothing very complex.  I have checked several books both at our
: > library at UMR and others through interlibrary loan.  If anyone could point
: > me to reference material to design the pads for these chips I would appreciate
: > the time spent.
: > William Eatherton
: > 

: I have never been able to find a "specification" for Plastic Quad Flat Packs.  
: These are Japanese standards which differs from similar "JEDEC" standards used 
: by most American engineers.  There are lots of pitfalls for the unaware.  One of
: the problems is that these standards are metric but most boards designed in the 
: U.S. are based on an english grid.  If you simply convert the metric dimensions 
: to english so as to match the grid, you end up with an error that accumulates the 
: farther you get from the datum.  This is specially bad in large package such as 
: 208 or 240 pins where there is little room for error; It simply won't work!  The 
: only solution I am aware of is to use a PCB layout system that can accomodate both 
: an english and a metric grid and a PCB designer that can use it effectively.  
: Some years back, I heard that JEDEC was working on standards to sort out the 
: differences, but I don't know what became of it.

: I have always been able to avoid the problem by using ceramic PGA packages, but 
: board space constrains will force me to adopt these metric packages in my current 
: design.  My approach will be to use IPC-D-275 for general guidelines.  As a final 
: authority, I will rely on my PCB fabricator and board assembly house to check the 
: work of my PCB designer, since these folks deal with these problems every day.

: Document Engineering has the IPC spec (and most other technical specs).  Their 
: voice number is (818)782-1010.  You might want to check out the Xilinx Customer 
: Support BBS at (408)559-9327.

: BTW, I would be very interested in reading other opinions on this subject.

: --
: Lou Santisteban   
: Computer Sciences Corporation     Email - lsantist@lsantist.dfrf.nasa.gov
: P.O. Box 387                      Phone - (805)258-3786
: Edwards, CA 93523-0387            Fax   - (805)258-3567
: "The difference between good and excellent is details", Unknown

: I DO NOT SPEAK FOR CSC, NASA, OR ANYONE ELSE BUT MYSELF!



The Package outline can be obtained from XILINX or distributors, the outline
for a 208 pin package is as follows


	<------------------1.205------------------->
	    <--------------1.102--------------->
	     <-------------1.004-------------->
	     ||||||||||||||||||||||||||||||||||
             ----------------------------------
        ----|                                  |----

Package is square, 52 pins along each edge, pin on bottom left corner when
viewing from the top marked by double circle, pin number count anti-clockwise
pitch of pins is .5mm precisely converting to approx 19.7 thou (19.6848).


The package dimensions caught us out as the data sheet specifies 20 thou pitch
which will lead to a pad space out over the whole device edge.


Hope this help Paul Brown.


Article: 601
Subject: Re: Xilinx marketing knuckleheads
From: dh@fncrd7.fnal.gov (don husby)
Date: 16 Jan 1995 21:16:44 GMT
Links: << >>  << T >>  << A >>
bobe@soul.tv.tek.com (Bob Elkind) writes:
>dh@fncrd7.fnal.gov (don husby) writes (heavily edited! -- BE):

>[...]
>>Fully covered functions:	5-bits			6-bits
>>				1 independent FF	4 independent usable FF
>                                ^
>				| I think this is 2 independent FFs,
>				| depending on your definition of the term

Sorry only one: when using the full 5-bit function, there's only one 
input left over to be used by the flip flops.

>[...]
>>4 CLB?	1 PFU	4-bit loadable up/down counter with synchronous reset.
> ^
> | I believe this can be implemented with 2 CLBs, 2 bits per CLB, using the
> | fast carry and add/sub control features.  You may have to do a bit of
> | manual, custom macro layout work to do it, but that's life.

The counter can be implemented, but adding the synchronous pre-load 
and/or pre-set requires two extra CLBs.




Article: 602
Subject: Mercury Computer System described on the WWW
From: dspadmin@dspnet.uucp (DSPnet Administrator)
Date: 17 Jan 1995 01:17:00 GMT
Links: << >>  << T >>  << A >>

DSP Product NEWS on the World Wide Web

Mercury Computer Products has just introduced on DSPnet two product documents.

The first product:

Race SERIES 9U - MCV9 describes the System Module, Environment. The Raceway
Communications Fabric as well as the Interlink Module and the Software
environment. 


The second document:

"Embedded Systems for Realtime Airborne Applications" describes Mercury's
Product profile and the Technology

	-------------------------------------------------------------

Access on the WWW through a browser.    http://www.dspnet.com

Access through a dialup line.         telnet dspnet.com  (login as lynx)



Article: 603
Subject: ACTEL and EXEMPLAR
From: ajs@sheffield.ac.uk (Andrew Shelley)
Date: 17 Jan 1995 17:03:18 GMT
Links: << >>  << T >>  << A >>
	I am currently writing some VHDL to synthesise into ACTEL FPGAs. Does anybody know how to tell exemplar to use the clock distribution lines as it is currently routing the clock through standard routing tracks (massive skew).

Ta







Article: 604
Subject: Re: Motorola FPGA
From: benzene@neocad.com (Dave Bennett)
Date: 17 Jan 1995 20:01:14 -0700
Links: << >>  << T >>  << A >>
Chuang Hsien-Ho (eea80593@twis.EE.NCTU.edu.tw) wrote:
: I want to find some information about look-up table-based FPGA
: made be Motorola. Could anyone help me? Thanks.

: --
: ===============================
: Hsien-Ho Chuang     
: eea80593@yankees.ee.nctu.edu.tw
: ===============================

Motorola's MPA1000 series of FPGAs is now sampling.  They are not LUT-based,
but are SRAM and therefore reprogrammable.  You should be able to get info
about price, availability, and data books from your nearest Hamilton/Hallmark
distributor.

The layout software is available from Motorola or NeoCAD.  For information
about it call 1-800-888-FPGA.


Dave Bennett
NeoCAD, Inc.


Article: 605
Subject: Ray Andraka's services
From: lfadden@harris.com (Lee Fadden)
Date: Wed, 18 Jan 1995 03:04:17 GMT
Links: << >>  << T >>  << A >>
Ray,
  Are you out there?  Try my e-mail again (lfadden@harris.com).  If it 
bounces, post here.  Thanks.


Lee F.


Article: 606
Subject: Re: ACTEL and EXEMPLAR
From: jason@cad.ccl.itri.org.tw (Jason Wang)
Date: Wed, 18 Jan 1995 05:59:04 GMT
Links: << >>  << T >>  << A >>
Andrew Shelley (ajs@sheffield.ac.uk) wrote:
: 	I am currently writing some VHDL to synthesise into ACTEL FPGAs. Does anybody know how to tell exemplar to use the clock distribution lines as it is currently routing the clock through standard routing tracks (massive skew).

You got to give the control file the following setting :
"BUFFER_SIG CLKBUF u'r_clk_name"

Pls refer to P5-5 on Core User manual

                                        Jason
--
 CCCC    CCCC   L        王子欣, 工研院電通所 自動化設計發展部
C    C  C    C  L        Jason Wang, Design Automation Development Dep.
C       C       L        Computer & Communication Research Lab., ITRI, Taiwan
C       C       L        E-mail: jason@cad.ccl.itri.org.tw
C    C  C    C  L        TEL: 886-35-917593
 CCCC    CCCC   LLLLLL   FAX: 886-35-820025


Article: 607
Subject: FPGAs and Hardware Compilation : job offer
From: Ian.Page@comlab.oxford.ac.uk
Date: Wed, 18 Jan 95 12:10:12 GMT
Links: << >>  << T >>  << A >>
There is a vacancy in the Oxford Hardware Compilation Research Group
for a Research Assistant, tenable for a little over one year, to work
on the Esprit OMI/HORN project (Open Microprocessor Initiative/Highly
Optimised Reusable Nucleus).  We are looking for someone to start as
soon as possible and this is an informal posting to see who might be
out there and interested to join this fast-growing, (and rather
exciting!), research group.

Our work is primarily about making computer programs go faster by
replacing the computer with something better. The `something better'
is application-specific hardware. Such hardware can operate many times
faster than a general-purpose computer in many applications.

The novelty of our approach is that we believe that much hardware can,
and should, be designed automatically.  To this end we build compilers
and systems which allow programmers to write programs which are then
automatically turned into hardware.  By using state-of-art FPGAs
(Field Programmable Gate Arrays), the construction of the
automatically designed hardware can also be automatic. As an example,
new application-specific hardware, and even complete microprocessors,
have been designed, implemented and worked within five minutes; by
simply writing the program you want to be executed.  We are working
towards the day when computer users will neither know, nor care, that
the command they just executed might have brought new computers into
being which existed only for the duration of the computation.

The ideal candidate for this job will probably have a good first
degree in either Computing or Electronic Engineering. Someone with
appropriate doctoral research or industrial experience would also find
the post interesting and challenging. The work is essentially
interdisciplinary, so we are looking for someone with breadth as well
as depth. Previous experience of parallel programming, SML
programming, or digital hardware design would be useful.  The person
appointed will be working as part of a growing team which is working
on a broad range of topics. This means that there is scope for
orienting the work towards the skills and interests of the person
appointed. 

For those who might wish to see what sort of work might be involved,
we have put some material onto the world-wide web.  This can be
browsed by using the following URL:

     http://www.comlab.ox.ac.uk/oucl/hwcomp.html

If you are interested, please reply by email if possible, to:

  Ian Page,
  Oxford University Computing Laboratory,
  Wolfson Building, Parks Road, 
  Oxford OX1 3QD, U.K.
  
  Tel. +44-1865-273853 (direct), 273838 (switchboard), 273839 (fax)



Article: 608
Subject: pci source code
From: arin@rapid.fi.uib.no (Arin Kjempenes)
Date: 18 Jan 1995 14:03:07 GMT
Links: << >>  << T >>  << A >>
I'm building a PCI target, and I'm looking for sourcecode
on how to implement it a CPLD.

I'm using ALTERA so AHDL code would be great,
but I'll appreciate other languages as well.

I have made a target myself but I'm not pleased with
the configuration-register soultion, so any tips
(sourcecode) are welcome.  

(I'm using few of the configurationregisters so I want 
to implement them inside the PLD.) 

I've got AP-396 from INTEL, which contains sourcecode
(PALASM2) for both master and target, but they are 
using an external configuration-registers.


-- 
Arin Morten Kjempenes        Phone:  +47-55-212712
Fysisk institutt                     +47-55-291802,277
Universitetet i Bergen       Fax:    +47-55-318334
Allegt. 55                   E-mail:
N-5007 Bergen                Arin.Kjempenes@fi.uib.no
 


Article: 609
Subject: Multiple FPGAs
From: eleventh@nyx10.cs.du.edu (Edward Leventhal)
Date: 18 Jan 1995 09:24:40 -0700
Links: << >>  << T >>  << A >>
Hi,

    A few months ago, I believe someone had posted a question regarding
a tool to take a design and 'automatically' break it up such that it
could be placed in several FPGAs.  As I recall, someone did give
the name of such a product.  Could someone please repost this?

Thanks,
   Ed



Article: 610
Subject: Partitioning and synthesis
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 18 Jan 1995 16:26:27 GMT
Links: << >>  << T >>  << A >>
I am interested in hearing about experiences with partitioning / synthesis / 
retargeting software that attempts to handle FPGAs and CPLDs.  I hope the 
following blurbs will stimulate discussion.  Please don't limit your response 
to just these interests.

Some vendor specific software claims to partion between multiple devices.  
Presumably this works well between members of a the same family.  How 
well does it work between different family / technology types?

Some vendor independent tools claim to partion between multiple CPLDs, FPGAs 
and ASICs.  How well does they work?  Are the end results are actually 
efficient for different device types?  How well do they handle area and 
speed optimization/tradeoffs?  

How are Cadence, Mentor, Synopsys, Viewlogic, etc. efforts going?  Granted, 
they all have various synthesis, targeting, paritioning tools.  But how well 
does it work to take a huge design and automatically partition *and* map 
into a *combination* of FPGAs, CPLDs and gate arrays?

Has anyone actually used some of the new partitioning software I've heard of - 
ASYL+, Software & Technologies, others?  

Many years ago (pre-FPGA and pre-CPLD days), Silvar-Lisco had a system 
partitioning tool.  Did this fade away or what? 

What is the entry point?  Verilog, VHDL, EDIF, etc.  If verilog and VHDL are 
not supported, how good is the optimization?  Ie, if your language is not 
supported and you synthesize to some generic EDIF first, how good is the end 
result?

What links exist to improve targeting area and performance for specific 
programmable devices?

Are there any system level comparisions of efficiency for different tools that 
can be shared?  For example, two different tools mapping to the same FPGAs or 
the same tool mapping to two different FPGAs.

Is the tool best for emulation, prototyping, system partitioning or what?  Why? 
For example, are individual devices sufficiently optimized for production use 
or does the tool emphasize quick, automatic mapping?

How much manual intervention is required?  Can you guide the process interactively?

---
~ Bill Wolf, Raleigh NC           ~          I can see         ~
~ wolf@aur.alcatel.com            ~           the fog          ~
~ My opinions, NOT my employer's  ~  at the end of the tunnel  ~




Article: 611
Subject: Question on Xilinx Development System
From: arif@arcturus (Arif Khan)
Date: 18 Jan 1995 21:02:37 GMT
Links: << >>  << T >>  << A >>
I have a question about the Xilinx Development Boards. 
Is there some way to modify the existing Xilinx 4000 development board to 
support the X4013? 

Alternatively, is there another development board with a X4013 available?

Thanks in advance.

Arif



Article: 612
Subject: Re: Multiple FPGAs
From: rogerng@ee.umanitoba.ca (Roger Ng)
Date: 18 Jan 1995 23:55:00 GMT
Links: << >>  << T >>  << A >>
In article ji2@nyx10.cs.du.edu, eleventh@nyx10.cs.du.edu (Edward Leventhal) writes:
>Hi,
>
>    A few months ago, I believe someone had posted a question regarding
>a tool to take a design and 'automatically' break it up such that it
>could be placed in several FPGAs.  As I recall, someone did give
>the name of such a product.  Could someone please repost this?
>
>Thanks,
>   Ed
>


Try NeoCAD!! It is able partition the design into multi Xilinx FPGAs.

Roger

---
                            \\\//
                            (o o)
-------------------------ooO-(_)-Ooo---------------------------  
  Roger Ng                  Electrical & Computer Engineering
  (204)474-7360             University of Manitoba
  rogerng@ee.UManitoba.CA   Canada, R3T 5V6
---------------------------------------------------------------



Article: 613
Subject: Re: [shin]OrCad .sch to Xilinx .xdf conversion seeking
From: Kin Hing Leung <calvinl@cs.ucla.edu>
Date: 19 Jan 1995 01:29:36 GMT
Links: << >>  << T >>  << A >>
gshin@netcom.com (George Shin) wrote:
>
> Does anyone come across utility that will allow taking in Orcad .sch or
> OrCad netlist file format and convert to Xilinx's .xdf format (suitable
> for using its FPGA)?  Thanks much in advance.  If i'm going about in wrong
> directoy, please let me know.  Thanks again.
> 
As far as I know, Xilinx supports quite a lot of front-end tools.
Orcad should be one of them.  Did you ask Xilinx about that?
There should be a set of library (symbol) for Orcad schematic
editor (You can't use the symbol/library in Orcad).  Different
Xilinx FPGA series may require different set of library.  Then
it is most likely that the schematic will be converted to EDIF
netlist.  There is an utility from Xilinx which convert a EDIF 
file to XNF file which is used for the Xilinx 's Place & Route tools.

Calvin 



Article: 614
Subject: Re: Multiple FPGAs
From: NDCX09A@prodigy.com (James Dickson)
Date: 19 Jan 1995 01:33:59 GMT
Links: << >>  << T >>  << A >>
Altera's design tools also have the capability of compiling a design into 
multiple FPGAs.  However my experience in letting the compiler make the 
decisions on how to partition a design into multiple devices has resulted 
in unfavorable interconnects.  Manually assigning partitions in a design 
have resulted in a much better solution.


-
  JAMES DICKSON  NDCX09A@prodigy.com




Article: 615
Subject: Re: ACTEL and EXEMPLAR
From: tcmayo@eng106 (Tom Mayo)
Date: Thu, 19 Jan 1995 02:54:43 GMT
Links: << >>  << T >>  << A >>
Andrew Shelley (ajs@sheffield.ac.uk) wrote:
: 	I am currently writing some VHDL to synthesise into ACTEL FPGAs.
:   Does anybody know how to tell exemplar to use the clock distribution
:   lines as it is currently routing the clock through standard routing
:   tracks (massive skew).
:
: Ta

Sure, just create a <design>.ctr file in the directory in which your
design lives, and put the information in there.  For example:

MAX_LOAD 1000 CLOCK
MAX_LOAD 4 RESET

or whatever.

Good Luck.

-Tom  N1RMU  tcmayo@mntr02.psf.ge.com






Article: 616
Subject: NeoCAD Experience
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 19 Jan 1995 16:58:25 GMT
Links: << >>  << T >>  << A >>
When NeoCAD first started selling, they pushed their tool as a better 
place and route tool for Xilinx.  Faster, higher utilization, etc. 
And it could retarget to other vendors.  Obviously, vendor independence 
is attractive for lots of reasons.  I'll take that as a given - please 
don't get into that for this thread.  

Since Xilinx has significantly improved their place and route tools over 
the last few years, I am currious whether NeoCAD produces better results 
if you are just concerned with placing and routing Xilinx devices.

Does anyone have benchmarks for the latest Xilinx versus the latest NeoCAD 
software releases?

Perchance a breakdown of 3000 and 4000 families?

Is NeoCAD keeping up with the proliferation of Xilinx products?  What kind 
of lag is there for support of new devices and families?  Which families 
are currently supported?  Does it support X-blocks?

Are there synthesis issues?  To optimize designs it is important to link 
verilog/vhdl synthesis with placement and routing.  Do these links exist?
Is timing information passed directly or must the user enter it twice?

In general, is there anything you especially like or dislike about NeoCAD tools?

What is the latest update on CAE vendors like Cadence, Mentor, Viewlogic 
working with NeoCAD.  Are they reselling NeoCAD, developing their own FPGA 
place and route tools, both, or doing nothing?  (Anyone from Cadence, Mentor, 
Viewlogic, etc. care to post the official line on this?)

Finally, how good is NeoCAD support for the latest Actel devices?  About 
a year ago, I heard that Actel was worried about NeoCAD cutting into 
their CAD revenue and was not working with them.

Since NeoCAD is well represented in this group, I presume they will respond, 
which is appropriate.  I hope we will also hear lots of direct user feedback. 

Thanks!

---
~ Bill Wolf, Raleigh NC           ~          I can see         ~
~ wolf@aur.alcatel.com            ~           the fog          ~
~ My opinions, NOT my employer's  ~  at the end of the tunnel  ~




Article: 617
Subject: Re: ViewLogic simulation without master reset
From: randraka@ids.net
Date: Thu, 19 Jan 95 17:34:24 GMT
Links: << >>  << T >>  << A >>
In Article <SAMSON.95Jan16081952@ptd10c.erim.org>
samson@ptd10c.erim.org (Joe Samson) writes:
>>sometimes the unknowns get resolved (sometimes not)  also you might try 
>>checking to see of your simulator will allow you to initialize gates (I can 
>>initialize them to all 0, all 1, postive logic state, or negative state).
>
>I think that the real problem that the original poster is having is that 
>because the flip-flops don't have resets, the device doesn't have predictable
>outputs after reset, and so he can't generate test vectors for the
>semi-custom fab line.
>My only suggestion is to go back to the original design and put in some
>resets - enough so that you can guarantee known outputs after some number
>of clocks. If there isn't a spare input pin available for reset, maybe
>you could use a combination of inputs to recognize a reset (for example,
>if there were separate read and write enable inputs, having both asserted
>simultaneously could be decoded as a reset).
>--
>+===============================================================+
>+ Joe Samson                               (313) 994-1200 x2878 +
>+ Research Engineer, ERIM                                       +
>+ P.O. Box 134001                         email samson@erim.org +
>+ Ann Arbor, MI 48113-4001                                      +
>+===============================================================+

The omission of resets where initial state is a don't care is a very powerful
tool in FPGAs where your number of input terms is limited.  This can make the
difference of adding an extra level of logic with the attendant loss in
performance.  The logic can be designed to settle to a known value after a few
clock cycles as a result of a strategically placed reset.  The problem with
simulating  this is that the simulator is starting with unknowns (depicted as X
which is neither 1 nor 0).  The X's can propagate through the circuit
indefinitely without getting resolved.  In the case of the physical hardware
the state is unknown, but it consists of 1's and 0's so it can eventually
settle to a known state (with a proper design).  An simple example of this 
is a continuosly running counter used for a clock divider.  You don't care what
the initial state is, only the pattern being generated.  In a simulator, the
initial states of the flip flops are X's, not 1 or 0's.  This means the next
state will also be X's, since it is dependent upon the value of the previous
state which is X.
 
Clearly, one need not add resets to the logic to make the circuit simulatable. 
What is required is some way of initializing the subject Flops to 1's and 0's.  
One way to do this in Viewlogic is to use the assign and release statements to
force the flops for one clock cycle as I detailed in my previous post.  You can
assign any initial value to any number of the flops using this technique.  In
fact, you can assign a random initial state using the waveform command.  In
this case your command file would contain:

v init <list of flops to be initialized>
wfm init 0=rand
c
r init

This assigns the list of flops to a vector for convenience, assigns a random
start value, runs it for one clock cycle (assuming you've already set up your
clocks), then releases the init vector allowing the circuit to take over. 

-Ray Andraka
the Andraka Consulting Group
401/884-7930    FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital design firm specializing in
maximizing the performance of FPGAs.  Our services include complete design,
development, simulation, and integration of these devices and their surrounding
circuits.  We also evaluate, troubleshoot and improve existing designs.



Article: 618
Subject: Re: Partitioning and synthesis
From: wieler <rwieler@ee.umanitoba.ca>
Date: 19 Jan 1995 18:06:17 GMT
Links: << >>  << T >>  << A >>
wolf@aur.alcatel.com (William J. Wolf) wrote:
>
> I am interested in hearing about experiences with partitioning / synthesis / 
> retargeting software that attempts to handle FPGAs and CPLDs.  I hope the 
> following blurbs will stimulate discussion.  Please don't limit your response 
> to just these interests.
<bunch of stuff snipped>

Ok let me pass on a few comments on the partitioning side.  I have 
recently begun to use NeoCAD for automatically partitioning fairly
large design, and it appears to work quite well.  It is possible
to partition between various type of fpgas, in the same family and
speed grade.  i.e. it allows the user to partition to any xc4000 -6
device, however you could not use a 3000 series device or a different
speed grade within the same partition.  This seems to be a fairly
reasonable limitation given the various fpga configurations in each 
family.  I don't know the limitations for other fpga vendors but i'm 
sure they run along the same line.  The partitioning software also 
lets the user guide the partioning process through the use of a 
guide file, although I have not yet had to place any constraints on 
my designs so I have only used the automatic partitioning.

Cheers
Richard Wieler
University of Manitoba




Article: 619
Subject: Re: [shin]OrCad .sch to Xilinx .xdf conversion seeking
From: dlr@testeng.ksc.nasa.gov (Doug Reed)
Date: 19 Jan 1995 21:17:29 GMT
Links: << >>  << T >>  << A >>
In article <3fkfa0$aoa@delphi.cs.ucla.edu> Kin Hing Leung <calvinl@cs.ucla.edu> writes:
>gshin@netcom.com (George Shin) wrote:
>>
>> Does anyone come across utility that will allow taking in Orcad .sch or
>> OrCad netlist file format and convert to Xilinx's .xdf format (suitable
>> for using its FPGA)?  Thanks much in advance.  If i'm going about in wrong
>> directoy, please let me know.  Thanks again.
>> 
>As far as I know, Xilinx supports quite a lot of front-end tools.
>Orcad should be one of them.  Did you ask Xilinx about that?
>There should be a set of library (symbol) for Orcad schematic
>editor (You can't use the symbol/library in Orcad).  Different
>Xilinx FPGA series may require different set of library.  Then
>it is most likely that the schematic will be converted to EDIF
>netlist.  There is an utility from Xilinx which convert a EDIF 
>file to XNF file which is used for the Xilinx 's Place & Route tools.
>
>Calvin 
>
In the '94 Xilinx catalog, pages 7-16 and 7-17 list the two OrCAD
packages that are available. Both packages include what you need,
the Logic Library, and the XNF Interface. You can email Dan Chan
(dchan@xilinx.com) for more info.

Regards,

-- 
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| SnailMail: LSO-336, KSC,FL  32899 -------------------------------------|
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |


Article: 620
Subject: Re: Partitioning and synthesis
From: rogerng@ee.umanitoba.ca (Roger Ng)
Date: 20 Jan 1995 02:27:25 GMT
Links: << >>  << T >>  << A >>
>wolf@aur.alcatel.com (William J. Wolf) wrote:
>>
>> I am interested in hearing about experiences with partitioning / synthesis / 
>> retargeting software that attempts to handle FPGAs and CPLDs.  I hope the 
>> following blurbs will stimulate discussion.  Please don't limit your response 
>> to just these interests.
><bunch of stuff snipped>
>

Beside NeoCad, I use PLD Synthesis 2(From Minc) to partition the design into 
multiple FPGAs and CPLD. After design partitioning, you could use XACT or NeoCad
for Place and Route. Also, PLD S2 is able to synthesis a design into different 
PAL, PLD, CPLD and FPGAs. I think it is pretty good synthesus tool for PLD 
design since it has rich family of library.

Roger Ng

---
                            \\\//
                            (o o)
-------------------------ooO-(_)-Ooo---------------------------  
  Roger Ng                  Electrical & Computer Engineering
  (204)474-7360             University of Manitoba
  rogerng@ee.UManitoba.CA   Canada, R3T 5V6
----------------------------------------------------------------


Article: 621
Subject: Re: NeoCAD Experience
From: ars@world.std.com (Alan R Sieving)
Date: Fri, 20 Jan 1995 07:18:23 GMT
Links: << >>  << T >>  << A >>
wolf@aur.alcatel.com (William J. Wolf) wrote:

>Since Xilinx has significantly improved their place and route tools over 
>the last few years, I am currious whether NeoCAD produces better results 
>if you are just concerned with placing and routing Xilinx devices.

>Is NeoCAD keeping up with the proliferation of Xilinx products?  What kind 
>of lag is there for support of new devices and families?  Which families 
>are currently supported?  Does it support X-blocks?

A lot of good questions in your note.  I'll offer my views on only a
few items.

First, when I was doing several XC3090/3190 designs 18 months ago, I
found that the NeoCad tools were a big help-- They were easy to use (I
gave the tool partitioned files from APR, and let it do the placement
and routing to meet my timespecs.)  With careful design (i.e. only one
logic level between FFs), I was able to easily get 64 MHz from a
3190-3, and 32 MHz from a 3090-125.  The Xilinx tools at the time were
not as capable of meeting the timespecs.

Recently we have been doing more XC4000 work here, and have XACT 5.1
and NeoCad 6.1 or thereabouts.  The other folks here haven't found a
compelling advantage to the NeoCad tools for the 4000 series, and we
have the further problem that we have now been putting timespecs on
the schematic (using Viewlogic Pro series), and NeoCad doesn't listen
to these.  So, our usage of NeoCad has dropped-- less comparative
advantage, and some additional effort required.

>From our perspective, NeoCad is moving its focus away from Xilinx--
the support for the XC3100A series (with enhanced routing resources)
was only recently announced.  We further understand that NeoCad is not
planning to support the 400xH series (e.g. the 4005H with Higher I/O
counts).  For us, this is a major drawback.  I wish that NeoCad would
do otherwise, but I'm sure they are busy with the ATT and Motorola
products these days, and it seems they are a bigger fish in those
smaller ponds.

Again, these are just my perspectives as a customer (I really liked
NeoCad 18 months ago, but now they seem lukewarm towards the XC4000).
I'd really like for NeoCad to prove me wrong (i.e. support the 4005H,
or make their tools accept schematic-based timespecs, or come up with
a better mousetrap than PPR), but I presume they've refocused their
efforts.





-- 
  --al.
Alan Sieving,  ars@quickware.com   or   ars@world.std.com
Quickware Engineering & Design,  225 Riverview Ave Waltham, MA, 02154-3874
W: 617-647-3800,  FAX: 617-647-3311   800-237-1185 for fast PDP-11's.


Article: 622
Subject: Re: ACTEL and EXEMPLAR
From: cshelor@cpdsc.com (Charles Shelor)
Date: 20 Jan 1995 13:41:03 GMT
Links: << >>  << T >>  << A >>

>Andrew Shelley (ajs@sheffield.ac.uk) wrote:
>: 	I am currently writing some VHDL to synthesise into ACTEL FPGAs.
>:   Does anybody know how to tell exemplar to use the clock distribution
>:   lines as it is currently routing the clock through standard routing
>:   tracks (massive skew).
>:
>: Ta
>
>Sure, just create a <design>.ctr file in the directory in which your
>design lives, and put the information in there.  For example:
>
>MAX_LOAD 1000 CLOCK
>MAX_LOAD 4 RESET
>
>or whatever.
>
>Good Luck.
>
>-Tom  N1RMU  tcmayo@mntr02.psf.ge.com
>
>
>
>

Wouldn't this be much easier if synthesis vendors would use VHDL attributes
for this type of information?  Placement constraints, timing constraints,
loading constraints, ... could all be managed in a device independent manner.
This information would also remain with the source code where it would be
a visible reminder of the constraints during the design and later the
maintenance of the circuit.

Charles F. Shelor


SHELOR ENGINEERING              VHDL Training, Consulting, and models
3308 Hollow Creek Rd            (817) 467-9367
Arlington,  TX  76017-5346      cfshelor@acm.org




Article: 623
Subject: 3 Verilog/FPGA Designers Needed For OVI Panel
From: jcooley@world.std.com (John Cooley)
Date: Fri, 20 Jan 1995 17:49:20 GMT
Links: << >>  << T >>  << A >>
A few Verilog FPGA designers are needed for EE Times Richard Goering's 
panel discussion on designing FPGA's using Verilog in the upcoming OVI 
meeting.  (They already have two EDA vendor reps & an industry analyst
-- they want the three remaining panelists to be users of the tools.)

If interested or just curious, contact Nanette Collins at (617) 437-1822,
(408) 481-1318 or e-mail her at "71604.1423@compuserve.com"

                                        - John Cooley
                                          the ESNUG guy

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer


Article: 624
Subject: Quickie International Verilog Conference Info
From: jcooley@world.std.com (John Cooley)
Date: Fri, 20 Jan 1995 21:43:09 GMT
Links: << >>  << T >>  << A >>
I wrote:
>A few Verilog FPGA designers are needed for EE Times Richard Goering's 
>panel discussion on designing FPGA's using Verilog in the upcoming OVI 

Which prompted some engineers to ask me details about the upcoming Verilog
conference.  Here's what I know:

     Location: Santa Clara Convention Center,  Santa Clara, CA

        Dates: March 27th - 28th  (a Monday & Tuesday)

 Nearby Hotel: Santa Clara Westin (which used to be the DoubleTree Inn.)

    More Info: e-mail "ivcinfo@ivcconf.com" or FAX (303) 530-4334

The advanced programs are being sent out this week and the e-mail info
address should be working now or very soon.
                                              - John Cooley
                                                the ESNUG guy

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer




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