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Messages from 3600

Article: 3600
Subject: ANNOUNCE: New Model of the Month - 16 bit ADC
From: Rob Hurley <rob@doulos.co.uk>
Date: Tue, 02 Jul 1996 17:57:34 GMT
Links: << >>  << T >>  << A >>


ANNOUNCEMENT: Immediate Release


		 Model of the Month
		====================

This month's model is:

	
	16 bit ADC (Analog to Digital Converter) in Verilog HDL

You can find it at http://www.doulos.co.uk. 

You can also access previous Models and Tips of the Month from the 
same site.
____________________________________________________________________

Also *** NEW *** for this month are:

	TIP of the MONTH:  Using Deferred Constants

	The Doulos HLD Information Centre

	Additions to our 'Hardware Engineers Guide to VHDL' series
	
____________________________________________________________________

Also visit the Doulos site for:
	
	
	VHDL Quick Reference Card
	
	VHDL 93 Update Reference Card


_____________________________________________________________________

Also details of the latest Doulos VHDL and Verilog training
courses and how to get a FREE online VHDL tutorial.

	'TRAINING THAT GIVES YOU THE WINNING EDGE'

Tim Pagden
DOULOS
Church Hatch				Tel: +44 1425 471 223
22 Market Place				Fax: +44 1425 471 573
Ringwood BH24 1AW			Email: info@doulos.co.uk
UK




Article: 3601
Subject: Re: INDUSTRY GADFLY "Why I Hate Wally"
From: Steven Bird <steve@vizef.demon.co.uk>
Date: Tue, 2 Jul 1996 19:01:12 +0100
Links: << >>  << T >>  << A >>
>
>Yes, but has the situation changed? I'd say no. Tools have become bigger,
>slower, contain at least as many bugs as they used to do. Perhaps the bigger
>market has made the tools a *little less* overpriced, but otherwise the
>situation essentially stays the same.

I have been 'beaten' over the head (almost literally) by engineering
managers claiming/stating that if they shipped their electronic products
with as many bugs as the EDA software they use, they would go out of
business overnight. Probably true, but this is partly due to a
fundimental difference between sw/hw. When you look at hardware products
they tend to follow the theme of identifying a market niche/requirement,
spec the product and then design and manufacture it and then sell it
whilst the window is open. This (simplistic) cycle is repeated for the
next product. In the fast moving consumer market, each sucessive
generation of product is, in terms of the physical aspects (not the
intellectual), substantially a new design not an iteration of its
predecessor.

Software products are *completely* different. Successive generations of
a software simulator are not re-writes, you take whats there and add new
functions (benifits, of course, not features). You now have a got a
tiger by the proverbials (I mean tail!). It is unrealistic for the
original product architects to be able to predict the future
requirements of the tool (say 5-10 years out) when laying down the
architecture. So as time progresses the accomodation of new hardware
design practices becomes more and more difficult *BUT* starting from
scratch could involve huge (>50 man years) amounts of time to start with
new code. 

Why should this be the case, well we don't have the advantage of picking
a 4 million transistor cpu off the shelf to use in our products, we
would have to write the cpu first... This is because the 'resuse'
feature is really non-existant, sure you can buy libraries with basic
building blocks, but they're not in the same league as a cpu. This is
not a whine but a statement of reality (as I see it, of course :) )

>  I still believe that integrated, but *extensible*, frameworks are a way to
>go for speedier tools. Integration by itself doesn't imply anything about
>user interfaces, or openness for other vendor's tools but merely that
>communication between tools is more efficient than simply via ASCII files.
>  For me, the imbalance between FPGAs reconfigurable within milli-seconds and
>tools that take hours to place and route seems very inappropriate. 

I think this ignores the complexities of the issues faced by the
software development teams. Somebody once asked me why place and route
takes so long. My answer, given 100 cells to place you have 100 possible
locations for the first cell, 99 choices for the second, 98 the third,
i.e. 100 factorial which is approximately 10 to the power 158! Given a
super computer running at several billion ips, a year of processing
would only yield 10 power 16 instructions in 1 year.

As for Frameworks, from a vendors point of view they offer little in
terms of sales revenue and consume a considerable amount of engineering
resource. Not a defense, but a reason...

>Tools should
>allow user interaction at all stages of the design, rather than offer push-
>button solutions. This, of course, requires fast tools which, I believe, well
>integrated tools can offer more easily than loosely coupled ones.
>



------------------------------------------------
Steven Bird

VIZEF Limited
Tel: 44 (0)1628 481571
Fax: 44 (0)1628 483902
------------------------------------------------


Article: 3602
Subject: Re: LCA to Schematic
From: Brad L Taylor <blt@emf.net>
Date: Tue, 02 Jul 1996 16:03:37 -0700
Links: << >>  << T >>  << A >>
Michael D. Scott wrote:
> 
> Hi,
>         I have an LCA file for XACT 5.0 which was spun off a
> Viewlogic schematic.  This chip had a few flaws so we made a few
> changes directly in the LCA file without really documenting the changes
> (I know, it's bad practice but it is done).  Is there a way to convert this
> LCA file back into a schematic ?

Yes, but I don't remember exactly how. It goes something like this
- convert .lca to .xnf with lca2xnf
- convert .xnf to .wir with xnf2wir
- use viewgen to create a schematic from the .wir file.

However:
- Viewgen crashes randomly with big (and small) files
- The resulting schematic is your worst nightmare. All high level 
  info is lost and you are left with a random ratsnest of gates.
- I don't know if this path is supported by the new viewlogic toolset.


Article: 3603
Subject: Re: INDUSTRY GADFLY "Why I Hate Wally"
From: jolo@jaguar.ece.cmu.edu (Joseph LoCicero IV)
Date: 2 Jul 1996 23:11:31 GMT
Links: << >>  << T >>  << A >>
Patrick Madden (pickle@nocturne.cs.ucla.edu) wrote:
: I don't see any real advantages in a framework, while there are a lot
: of disadvantages.  Faster execution times might be possible, but the
: difference would be slight.  The only real plus is that maybe you
: could prevent your customer from using someone elses tool....  But no
: one would have a framework for that reason, would they? :-).

Patrick (and John, who made a similar point):

	I disagree with this point.  Frameworks, in the general sense of
the term, are not just common databases that store design data.  Rather,
they are supposed to encompass the methodology of the design process.
Perhaps the fact that we have received such terrible "frameworks" from 
Cadence and Mentor in the past has corrupted our thinking to the point that
we are afraid of frameworks entirely.  However, excellent research (some
by my colleagues here at CMU) has proven that frameworks are much more
capable than, say, DFII.

	What the EDA community needs to do is to redefine the notion of
frameworks as a means to help formalize the design process at multiple
levels of abstraction, not just as an interface to a database and a few
GUIs.  Though this isn't a great short-term goal (like standardizing on
a file interchange format, which I agree *HAS* to happen), it is key to
developing the corporate institutional memory that must exist for a
company to remain successful for the long haul.

l8r,
---
- Joseph LoCicero, IV	    | Grey is not the color I expected	           -
- jolo@ece.cmu.edu          | On someone who's so often touched by grace   -
- Think smarter, not harder | The eyes that hold the promise of perfection -
- Team OS/2--Use Warp! 	    | Will find the flaw that no one can erase...  -


Article: 3604
Subject: Re: Using MAX+plusII under UNIX
From: Andreas Hofmann <eedanho@eede.ericsson.se>
Date: Wed, 03 Jul 1996 07:17:36 +0200
Links: << >>  << T >>  << A >>
There seems to be some problems with the implementation of their user
interface. I couldn't see the problem you described, but I have a nice
oddity, too. If I try to get the online help from the menu HELP the 
message appears:

out of memory for displaying help. Try closing some applications
and requesting help again.

So far no response from ALTERA! But instead we use the winhelp from the
bin directory which is the same, without the context sensivity.
We are using olvwm and mvwm under SunOS 4.1.3 and SunOS 4.1.4 on sparc2,
sparc5, sparc10 and sparc20. (MAX+PLUS II 6.1)

I hope that all this will have an end with the new revision coming soon.
I think that they know that there is a lot to improve at their current 
userinterface, I just don't know when they will start to change it.

/// Andreas
-- 
   _/ _/ _/  EED/E/X/A/ Andreas Hofmann    Phone : +49-5121-707-378
  _/ _/ _/   Ericsson Eurolab Deutschland  FAX   : +49-5121-707-333
 _/ _/ _/    Daimlerring 9                 Memo	 : EED.EEDANHO
_/ _/ _/     31135 Hildesheim - Germany    mailto: eedanho@eede.ericsson.se


Article: 3605
Subject: Re: LCA to Schematic
From: raghu@cse.iitb.ernet.in (Raghavendra G Jorapur)
Date: Wed, 3 Jul 1996 06:46:05 GMT
Links: << >>  << T >>  << A >>
Michael D. Scott (mscott5@ede.sanders.lockheed.com) wrote:
: Hi,
: 	I have an LCA file for XACT 5.0 which was spun off a 
: Viewlogic schematic.  This chip had a few flaws so we made a few
: changes directly in the LCA file without really documenting the changes
: (I know, it's bad practice but it is done).  Is there a way to convert this
: LCA file back into a schematic in either Viewlogic or Mentor without having
: to go through by hand?  What software packages would be needed?  It is
: strictly for documenting purposes.
: 
: Thanks
: 
: Please email response to
: mscott5@ede.sanders.lockheed.com

you can convert a .lca file to xnf format  using command lca2xnf .

xnf files can then be converted into viewlogic's wir  file format
using command wir2xnf.

Then, use viewgen to generate viewlogic schematics from wir files
using viewgen.

But , this schematic will be  tool generated one ( that too after 
routing) and  will be  entirely different than your origional  
schematics (at least in appearance).   Hence it is mostly useless 
for your documentation purpose.

-Raghu
Article: 3606
Subject: FSM encoding in VHDL with MAX+plusII
From: klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth)
Date: 3 Jul 1996 09:37:37 GMT
Links: << >>  << T >>  << A >>

One of the great features of Alteras AHDL is the possibility
to identify outputs of a FSM with bits of the state encoding:

  SUBDESIGN ctrl (
    resetn, clk: INPUT;
    a,b: INPUT;
    x,y,z: OUTPUT;
  )
  VARIABLE
    MACHINE OF BITS (x,y,z) WITH STATES (
      init   = B"000",
      state1 = B"101",
      state2 = B"110",
      state3 = B"110",
      state4 = B"100",
      ...
    );
  BEGIN
    ...
  END;

My question is: Is there a similar way to describe such a FSM in VHDL?

I do have read the VHDL booklet of the MAX+plusII documentation and
I do know how to do manual state assignment. The example above should
look something like 

  ENTITY ctrl IS
    PORT ( resetn, clk: IN std_logic;
           a, b: IN std_logic;
           x,y,z: OUT std_logic
         );
  END ctrl;

  ARCHITECTURE output_encoding OF ctrl IS
    TYPE state_t IS (init, state1, state2, state3, state4, ...);
    ATTRIBUTE ENUM_ENCODING: STRING;
    ATTRIBUTE ENUM_ENCODING OF state_t: TYPE IS "000 101 110 110 100";
    ...
   BEGIN
    ...
  END output_encoding;

But how do I access a bit of the state encoding to assign it to the
corresponding output signal?

Any help appreciated.

Thanks, Andre'. 
-- 
---------------------------------------------------------------------------
Andre' Klindworth                       Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de      Vogt-Koelln-Str.30, D-22527 Hamburg
http://tech-www.informatik.uni-hamburg.de/Personal/klindwor/Klindworth.html


Article: 3607
Subject: CHDL '97
From: lsanchez@yeti.dit.upm.es (Luis Sanchez Fernandez)
Date: 3 Jul 1996 10:33:58 GMT
Links: << >>  << T >>  << A >>

Dear all,

please find below the Call for Papers for the Conference on Computer
Hardware Description Languages and Their Applications 1997, CHDL'97,
that will be held in Toledo (Spain) in April 1997.

You can also find information on this event in the following URL:

	http://www.dit.upm.es/~cdk/org/ifip/chdl97.html

Kind regards,

Luis Sanchez

----------------------------------------------------------------------------

Call for Papers

CHDL '97

XIII IFIP WG 10.5 Conference on Computer Hardware Description Languages and
Their Applications 1997

                               Silver Jubilee

                                  [Toledo]

              Hotel Beatriz - Toledo, Spain - 20-25 April 1997

----------------------------------------------------------------------------
CHDL has been held every other year since 1973, rotating between locations
in Europe, North America and Asia. The conference originated under IEEE/ACM
sponsorship and since 1981 has been organized by IFIP Working Group 10.2
(now WG 10.5).

The topic has had a significant history with over 100 HDLs published in the
1970s. Since the mid-1980s, HDLs have become commonplace in system design
and VLSI. This can be attributed to many factors including:

   * the advancing complexity of digital electronics, leading to more
     sophisticated modeling, simulation, and verification tools.
   * the migration of VLSI design to high-level synthesis based on HDLs
   * advances in microelectronics CAD toward support of system-level design
   * the increasing prevalence of generic and programmable components, of
     software-hardware and mixed digital-analog hybrid designs.

Presently, we are in a consolidation phase, in which languages and standards
are increasingly being used, at the same time as the scope is being
broadened to additional application areas (such as analog, microwave or
system-level design).

CHDL'97 will present the latest developments in the area in the form of
tutorials, invited talks, panel sessions and reviewed papers. In 1997, CHDL
will be celebrating its Silver Jubilee, and this will be a very special
occasion to learn from the past and look forward to what we might expect
from the future.

CHDL'97 will be held in conjunction with other workshops on closely related
areas:

   * the Spring '97 Working Conference of the VHDL Forum for CAD in Europe
   * the Esprit NADA workshop (about New Hardware Design Methods).
   * the Workshop on Libraries, Component Modelling and Quality Assurance

An exhibition will be held in parallel to these events.
----------------------------------------------------------------------------

Topics

The topics of CHDL include several emerging design methods and technologies
based on HDLs, including

   * Hardware Description Languages, Standards
   * Formal Methods
   * Verification and Validation
   * Design Analysis and Test
   * System-Level Specification and Design
   * High-Level Synthesis
   * Design Systems and Tools
   * New Application Areas

----------------------------------------------------------------------------

Submission of Papers

Contributions on these or related topics are solicited. Papers on original
research, experiences, reviews, and tutorial articles are welcome. Proposals
for special sessions are also invited (please contact the Program Chair).
Accepted papers will appear in proceedings published by Chapman & Hall. A
best-paper award will be given.

Papers (6 copies) should be submitted by 1 October 1996 to the Program
Chair. A cover page should specify

  1. title;
  2. authors and affiliation;
  3. mailing address, phone and fax numbers, and e-mail address of the
     primary author;
  4. a brief abstract; and
  5. one or two topics from the list to which the paper belongs.

Submissions should use A4 or 8.5" x 11" paper and be at most 20 pages in
length (minimum line spacing 1 1/2). Submission by e-mail to the Program
Chair <chdl97@iro.umontreal.ca> of PostScript files is preferred, but since
there may be printing or transmission problems, it is suggested that paper
copies be also sent by regular mail.

Important dates:

   * Submission deadline: 1 October 1996
   * Notification of acceptance/rejection: 29 November 1996
   * Camera-ready version: 22 December 1996
   * Conference: 20-25 April 1997

----------------------------------------------------------------------------

Toledo

Toledo is without doubt one of the cities with the greatest density of
monuments in the world. Nearly all the different stages of Spanish art are
represented in Toledo, which has Moorish-Mudejar-Jewish buildings, such as
the Transito and Santa Maria la Blanca Synagogues; Gothic structures, such
as the splendid cathedral; and Renaissance buildings. In the 16th century,
the city became home to El Greco, and Toledo has many of his paintings,
among which is "The Burial of the Count of Orgaz", his masterpiece, which is
housed in the Mudejar Church of Santo Tome. Among its many museums, of
special note is the one located in the old Santa Cruz Hospital.

----------------------------------------------------------------------------

General Chair

Prof. Dr. Carlos Delgado Kloos
Universidad Politecnica de Madrid
ETSI Telecomunicacion
Ciudad Universitaria
E-28040 Madrid (Spain)

Tel: (+34-1) 5495700 ext 438
Fax: (+34-1) 3367333
E-mail: cdk@dit.upm.es

Program Chair

Prof. Dr. Eduard Cerny
Dept. IRO
Universite de Montreal
C.P. 6128, Succ. Centre-Ville
Montreal (Quebec)
Canada H3C 3J7

Tel: (+1-514) 343-7472
Fax: (+1-514) 343-5834
E-mail: cerny@iro.umontreal.ca

Exhibition Chair

Dr. Serafin Olcoz Yanguas
TGI - Tecnologia y Gestion de la Innovacion
C/Velazquez, 134 bis
E-28006 Madrid (Spain)

Tel: (+34-1) 396-4925
Fax: (+34-1) 396-4841
E-mail: sera@www.tgi.es

Local Arrangements

Natividad Martinez Madrid
Ingenieria Telematica
Universidad Carlos III de Madrid
C/Butarque, 15
E-28911 Leganes/Madrid (Spain)

Tel: (+34-1) 624-9903
Fax: (+34-1) 624-9430
E-mail: nmadrid@ing.uc3m.es

Asia-Pacific Representative

Prof. Masaharu Imai
Department of Information and Computer Sciences
Toyohashi University of Technology
Toyohashi 441 (Japan)

Tel: (+81-532) 42-0111, ext 509
Fax: (+81-532) 48--9079
E-mail: imai@tutics.tut.ac.jp

Program Committee

   * David Agnew, Canada
   * François Anceau, France
   * Przemyslaw Bakowski, France
   * Mario R Barbacci, USA
   * Howard Barringer, UK
   * Graham Birtwistle, UK
   * Dominique Borrione, France
   * Raul Camposano, USA
   * Eduard Cerny, Canada
   * Luc Claesen, Belgium
   * Edmund M Clarke, USA
   * Francisco Corella, USA
   * Werner Damm, Germany
   * Carlos Delgado Kloos, Spain
   * Nikil D Dutt, USA
   * Hans Eveking, Germany
   * Norbert Fristacky, Slovakia
   * Masahiro Fujita, Japan
   * Ganesh Gopalakrishnan, USA
   * Werner Grass, Germany
   * Rainer Hartenstein, Germany
   * Graham Hellestrand, Australia
   * Masaharu Imai, Japan
   * Steven D Johnson, USA
   * Thomas Kropf, Germany
   * David C Luckham, USA
   * Paul Menchini, USA
   * Jean Mermet, France
   * Wolfgang Nebel, Germany
   * Adam Pawlak, Germany
   * Robert Piloty, Germany
   * Paolo Prinetto, Italy
   * Franz Rammig, Germany
   * Peter Schwarz, Germany
   * Jørgen Staunstrup, Denmark
   * P A Subrahmanyam, USA
   * Flavio Wagner, Brazil
   * Ronald Waxman, USA
   * Akihiko Yamada, Japan
   * Michael Yoeli, Isreal



Article: 3608
Subject: Re: Need recommendation for PCI interface on 68332
From: Richard Meacham <R.Meacham@sheffield.ac.uk>
Date: Wed, 03 Jul 1996 11:56:52 +0100
Links: << >>  << T >>  << A >>
Perhaps you would consider using a synthesizable macro for your PCI.
Synopsys and Virtual Chips spring to mind as suppliers of PCI cores.

Regards,

Richard Meacham
Contract Researcher


Article: 3609
Subject: Re: INDUSTRY GADFLY "Why I Hate Wally"
From: ft63@dial.pipex.com (Peter)
Date: Wed, 03 Jul 1996 15:42:41 GMT
Links: << >>  << T >>  << A >>

> Tools should
>allow user interaction at all stages of the design, rather than offer push-
>button solutions.

I would disagree with this one. When doing an FPGA design, I am only
interested in getting a working device. I am *not* interested in
floorplanning and all that nonsense which FPGA seminars spend so much
time on. The only time all this interaction is required (in some
designs) is when the technology is being pushed to its limits, in
terms of hardware delays and/or the place/route software's ability.

I have done dozens of FPGA (Xilinx) designs and have never had to do
any interaction, except on the last one where I had to get the latest
software version to get it to route.

The bulk of the FPGA design learning curve is in the "interaction"
part - another reason to avoid this.

Peter.


Article: 3610
Subject: Re: LCA to Schematic
From: ft63@dial.pipex.com (Peter)
Date: Wed, 03 Jul 1996 15:42:42 GMT
Links: << >>  << T >>  << A >>


>However:
>- Viewgen crashes randomly with big (and small) files

I found this too, and found it was caused/affected by the version of
QEMM I was using. This is with the 1991 DOS v4.1 software, which is
otherwise completely solid.

>- The resulting schematic is your worst nightmare. All high level 
>  info is lost and you are left with a random ratsnest of gates.

This will always be the case with any synthesised schematic. But one
can then at least use that schematic to port the design to a different
technology (ASIC, etc). I have used the route you give (CUPL -> PALASM
-> XNF -> WIR -> VIEWGEN) very successfully, doing all sorts of state
machines and completely avoiding HDLs.

Peter.
Article: 3611
Subject: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
From: ft63@dial.pipex.com (Peter)
Date: Wed, 03 Jul 1996 15:42:43 GMT
Links: << >>  << T >>  << A >>
How do you do an all-digital ADC??
Article: 3612
Subject: FPGA job
From: biggs@qcktrn.com ( Tom Biggs )
Date: 3 Jul 1996 16:25:42 GMT
Links: << >>  << T >>  << A >>

Our group at Quickturn has openings for people with Xilinx and board design
experience. (There are also many software openings in other groups).

Here is the official listing: 

* Hardware Design Engineer

- responsible for design, development, and implementation of next gen.
  emulation systems based on PowerPC multi-processing 
- requires BS/MSEE with 3+ years related design experience including VME
  bus, embedded systems, Xilinx FPGA, memory and JTAG

E-mail questions/resumes to choi@quickturn.com

Other job openings can be seen at our Web site at www.quickturn.com


Article: 3613
Subject: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 1)
From: jcooley@world.std.com (John Cooley)
Date: Wed, 3 Jul 1996 16:50:12 GMT
Links: << >>  << T >>  << A >>

    For those of you who wish to follow the Cadence/Avant! lawsuit in
    gory detail, I'm posting both Cadence's and Avant!'s sides in their
    own words.
                                             - John Cooley

    Part 1 of 3 "Cadence's View"

--------------------

        What follows is no run-of-the-mill claim of trade secret
misappropriation and copyright infringement.  Rather, this brief describes
one of the most egregious, and sordid, episodes of individual greed and
corporate theft that Silicon Valley has ever experienced.
        Preliminary injunction discovery has confirmed that Avant! is a
corporation seeded with Cadence computer source code stolen by Avant!'s
four founders (themselves former Cadence employees), and thereafter
sustained by regular infusions of updated Cadence source code and trade
secrets filched by subsequently departing Cadence engineers recruited to
Avant!.  Two months after one of those engineers, Mitsuru Igusa, quit
Cadence for a job he refused to describe, he was caught red-handed at his
home with copies of the most up-to-date source code for two of Cadence's
top products, FRoute=81 and QPlace=81, which Igusa was cosmetically altering=
 to
conceal their origin.  Igusa then became an under-the-table "consultant"
for Avant!, paid from a slush fund called the Saurus Fund.  The Saurus Fund
was operated by Avant!'s Director of Business Operations, Shiao-Li Huang,
and was funded by Avant!'s top officers and directors: Chairman of the
Board and CEO Gerald Hsu; Director and Vice President of Asian Operations
Yun-Chun Cho; Vice President of Engineering Tzyh-Lin Wuu; and Vice
President of Technology Yuh-Zen Liao.  Wuu and Liao alone funneled over
$70,000 to the Saurus Fund. Igusa was formally charged by the District
Attorney with felony theft of Cadence trade secrets in August, 1995.
        Igusa and former Cadence employee Chih-Liang Cheng both provided
Cadence's latest trade secret source code to Avant!, which has since shown
up in Avant!'s source code directories and most recent product releases.
Igusa and Cheng have taken the Fifth as to all questions pertaining to
their removal of source code from Cadence and provision of that code to
Avant!.  Huang, Liao, and Wuu likewise have taken the Fifth concerning
their payments to Igusa and Cheng.  Their payments to the slush fund
manager correspond neatly with Avant!'s recruitment of Cheng, Cheng's
removal of source code from Cadence, and Huang's contemporaneous withdrawal
of over $10,000 in cash from various bank accounts.  Other payments from
Wuu and Liao to Huang correspond neatly with payments from Huang to Igusa
of over $30,000.
        Independent experts retained by Cadence have only begun to analyze
the gigabytes of source code produced by Avant!.  But, their analysis
confirms that Cadence source code was slavishly copied in developing the
initial version of Avant!'s primary product, ArcCell, and that the copied
code remains present in even the most recent release of ArcCell.  Expert
analysis also confirms that Avant! used the source code for Cadence's
=46Route=81 and VSize=81 products more recently stolen by Igusa and Cheng to
write a recent revision of ArcCell, and to create one of Avant!'s newest
products, ArcCell XO, which was first released in January, 1996.  Finally,
notwithstanding Avant!'s public protestations that any match-ups of its
computer code with Cadence's was coincidence or traceable to public domain
sources, and that it had no relationship with Igusa, Avant! has now
admitted that it did receive source code from Igusa, which was incorporated
into its source code directory.
        Accordingly, Cadence seeks an injunction barring Avant! (1) from
any further sales or shipments of ArcCell, ArcCell XO, or any equivalent,
renamed product; and (2) from any further use of any software trade secrets
stolen from Cadence, and (3) from any further infringement of copyrighted
Cadence source code.
II.   FACTUAL BACKGROUND
A.      Cadence And Its Copyrighted, Trade Secret Products
        Since its inception in 1988, Cadence has been the industry leader
in the field of Integrated Circuit Design Automation ("ICDA").  Declaration
of James P. Douglas ("Douglas Dec.") at =B6 15.   ICDA refers generally to
the field of automated software tools for the design and creation of
sophisticated integrated circuits.  One of the principal reasons for
Cadence's success in this sector of the software industry is its
development of cutting-edge "place and route" and compaction programs.  Id.
As set forth in more detail in the Declarations of Randall Davis, Carl
Sechen, and Jeffrey Markham, these programs automatically determine the
optimal placement of each of the thousands, and sometimes millions, of
microscopic components to be placed on a given chip ("placement"), the
optimal means of routing the electrical connections between each component
("routing"), and the optimal means for reducing the size of the die needed
to contain the components ("compaction").  Cadence's key place-and-route
and compaction programs, called QPlace=81, FRoute=81, and VSize=81 are
incorporated into Cadence's Cell Ensemble=81, Cell3 Ensemble=81, and Gate
Ensemble=81 products.  Markham Dec. at =B68.
        To protect its proprietary information, Cadence has obtained
copyrights for its place-and-route source code programs, and it has
zealously guarded the source code for these programs as valuable trade
secrets.  Declaration of Ragesh K. Tangri, Exh. 1; Declaration of Carl
Smith; Declaration of John Broadhead.  Since before 1991 all Cadence
employees, as a condition of their employment, have been required to sign
agreements acknowledging the proprietary trade secret character of the
source code used to create these programs, and promising to maintain the
confidentiality of Cadence's trade secrets.  Declaration of Adele A. Healy
at =B6 3.
B.      Avant! Is Founded (On Stolen Cadence Source Code)
        In early 1991, four senior Cadence employees, Tzyh-Lih "Steven"
Wuu, Yun-Chung "Eric" Cho, Michael Mon-Yen Tsai, and Yuh-Zen ("Y.Z.") Liao
decided to leave Cadence and form their own company to compete with
Cadence.  Cho and Tsai both submitted letters on February 22, 1991,
resigning effective March 8, 1991.  Healy Dec., Exhs. T, U.  Liao and Wuu
submitted their letters 5 days later, on February 27, 1991, resigning
effective March 12, 1991.  Healy Dec., Exhs. V, W.  The four employees
incorporated their new company, on February 28, 1991 -- only one day after
Wuu and Liao submitted their resignations, and before any of them left
Cadence's employment.  Tangri Dec. Exh. 5 at 28:20-22.
        Avant!'s founders decided to give their new venture a headstart by
taking Cadence source code with them when they left.  Davis Dec. =B6=B6 4-6
(detailing the blatant plagiarism of Cadence source code in Avant!'s early
products, and its continued use in Avant!'s most recent products).  Liao
and Wuu have taken the Fifth in response to questions whether they took,
and then used, Cadence source code to develop ArcCell and whether such code
is being used in Avant!'s current versions of ArcCell and ArcCell XO.
Tangri Dec. Exhibit 2 at 14:2-13; id. Exh. 3 at 12:25-13:14.  Although all
four founders signed non-disclosure agreements when they were first
employed by Cadence (or its predecessors), they refused en masse to sign a
standard agreement re-affirming their non-disclosure obligations during
their exit interviews.  Healy Dec. Exhs. B - E, and P - S (unsigned
reaffirmations), (employment/NDAs).
        Avant!'s product cycle is consistent with the founders' theft of
Cadence source code.  Avant! released ArcCell just over two years after its
founders left Cadence with source code in hand.  This is a remarkably brief
period of time to develop, test, debug, and release a complex
place-and-route software product like ArcCell.  See Sechen Dec. =B6=B6 21-23=
.
C. Avant! Recruits Hsu, Whose Job It Had Been To Direct Cadence's
Competitive Efforts Against Avant!
        Avant!'s initial ArcCell product did not generate significant sales
when it was first introduced. Douglas Dec. =B6 19.  To boost its lagging
sales, Avant! decided to hire Cadence Vice President Gerald Hsu as its CEO.
Hsu's job had been to direct Cadence's competition with Avant!,
particularly in the Japanese market.  Tangri Dec. Exh. 7 at 10:23-11:18;
id. Exh. 8 at 227:22-228:1. Because Hsu, by virtue of his position,
necessarily possessed a great deal of highly confidential Cadence business
information, Cadence objected to Hsu's going to work for the very company
with which he had been competing.  Protracted negotiations were concluded
by a settlement and general release between Hsu\Avant! and Cadence.  Tangri
Dec. Exh. 9.  The settlement released all claims between the parties "which
they may have against each other at the time of the execution of this
agreement," June 6, 1994.  Id. (emphasis added).  Neither party released
the other from claims based on any future activities.  The agreement also
barred Avant! from soliciting or hiring any Cadence employees until January
1, 1995 (with the exception of two employees already hired, one of whom was
Hsu's "right hand" assistant, Shiao-li Huang).
D. During the Hands-off Period, Avant! Recruits Igusa, Who Steals Cadence Co=
de
        Shortly after Hsu began work at Avant! in July, 1994, he commenced
a renewed campaign to upgrade Avant!'s software by obtaining recent Cadence
source code.   To that end, in early August, 1994, Hsu directed Huang to
arrange a meeting with Mitsuru Igusa, a senior Cadence place-and-route
engineer.  Tangri Dec. Exh. 10; id. Exh. 11 at 27:11-22; id. Exh. 8 at
37-40; Declaration of Eric Rogoyski at =B6 5.  After swearing a fellow
employee to secrecy, Igusa met with Hsu and Huang.  Id. Hsu offered Igusa a
job at Avant!, but told Igusa he could not openly hire him until January,
1995 (because of the settlement agreement with Cadence).  Tangri Dec. Exh.
11 at 30:15-31:17.  Hsu's offer induced Igusa to leave Cadence almost
immediately.  Although Cadence promised Igusa a substantial raise and paid
time-off to pursue further education if he would stay, Igusa quit Cadence
in mid-September, 1994, refusing "for legal reasons" to admit to Cadence
management that he was going to join Avant!.  Declaration of Joseph
Costello =B6 4; Rogoyski Dec. =B6 7.  Igusa was more candid with a friend an=
d
co-worker, Rick Cole, and even arranged for Hsu to speak with Cole about
jumping ship as well.  Declaration of Rick Cole at =B6 3.  When he left,
Igusa, like the Avant! founders before him, refused to sign an affirmation
of his existing confidentiality agreement with Cadence, citing "legal
reasons."  Costello Dec. Exh. A; Healy Dec. Exh. I.
        Based on Igusa's lack of candor, and on Igusa's electronic transfer
of a large amount of computer information immediately before his departure,
Cadence suspected that Igusa might have taken Cadence source code with him.
Tangri Dec. Exh. 13.  Cadence reported its suspicions to the Santa Clara
District Attorney's office, which obtained a warrant to search Igusa's home
in mid-November, 1994.  Id.
        The search of Igusa's home revealed that Igusa had stolen a large
amount of source code for numerous Cadence products, which he had
transferred both to a Sun IPX workstation and to portable floppy diskettes.
Affidavit of Senior Criminal Investigator John Smith in Support of Search
Warrant, Tangri Dec. Exh. 13; Rogoyski Dec. =B63.     Igusa's attorney
subsequently stated to the press that Igusa only took the source code
because he felt a certain pride of authorship.  Tangri Dec. Exh. 14.  This
does not explain why Igusa had been stripping Cadence copyright notices
from the source code and had been cosmetically altering the code in ways
designed to conceal its Cadence origins before the stolen code was seized.
Id. Exh. 13; Rogoyski Dec. =B6 4.
        The District Attorney's search of Igusa's computer also disclosed a
file that apparently functioned as Igusa's appointment calendar. Tangri
Dec. Exh. 13.  That file contained an entry indicating that on September
27, 1994 -- just two weeks after his departure from Cadence -- Igusa
calendared a lunch appointment with "YZ" and "SL" (apparent references to
Avant!'s Vice President of Technology, Y.Z. Liao, and its Director of
Business Operations, Shiao-Li Huang) regarding an "nblock placer + gridless
router."  Id.  The file also showed an October 18, 1994 meeting between
Igusa and "YZ," and a November 1, 1994 meeting between Igusa and "SW" (an
apparent reference to Avant! Vice President of Engineering Tzyh-Lih
"Steven" Wuu).  Id.  When questioned about the recruitment of, and meetings
with, Igusa, and about whether Igusa had delivered portions of the stolen
Cadence source code to Avant!, Avant! managers Liao, Wuu, and Huang all
took the Fifth.  Tangri Dec. Exhibit 2 at 20:9-21:11, 33-42; id.  Exh. 3 at
15:22-25; id. Exh. 11 at 27:19-28:26.
        Avant!'s plans to have Igusa modify and disguise the origins of
Cadence's source code, and to hire Igusa as an employee, apparently were
interrupted by the search of Igusa's home and the seizure of the source
code he had stolen from Cadence.  As described below, however, Igusa either
gave at least some of Cadence's latest source code to Avant! before his
copies were seized, or managed to hide copies from the search and later
gave those copies to Avant!.
        There are, however, many ways to skin a cat.  When Igusa was
busted, Avant! simply resorted to recruiting other Cadence engineers to tap
their knowledge of Cadence's trade secrets, and to obtain additional copies
of Cadence's source code.  Avant! recruited Cadence place-and-route
engineers Ping-San Tzeng, Sheng-Chun "Paul" Lo, and Chih-Liang Cheng.
Tzeng joined Avant! in January, 1995, and Lo interviewed with Hsu and Huang
during January, eventually joining Avant! in April, 1995.  Tangri Dec. Exh.
16 at 56:5-21, 67:8-12.
E.      Cheng Brings Additional Stolen Source Code To Avant!
        Cheng was interviewed by Avant! Board Chairman and President Gerald
Hsu during the first days of January; he received an offer letter from Hsu
on January 12, 1995.  Tangri Dec. Exh. 15.   During his exit interview at
Cadence on January 27, 1995, Cheng specifically acknowledged that one of
the new programs he had been working on while at Cadence, VSize,=81 was in
particular a Cadence trade secret.  Healy Dec. Exh. 0.  What he did not
acknowledge was that he had already copied the VSize=81 source code onto a
portable tape and was planning to deliver (or had already delivered) it to
his new employer, Avant!.
        On January 11, 1995 -- after having interviewed with Avant! --
Cheng created a ".tar" file (essentially, a compressed file comprised of
numerous other files) on his workstation.  Declaration of William Woo =B6=B6
5-7.  That file, which Cheng named "byebye.tar" in a not-so-cute reference
to his impending departure, contained source code for many of the same
Cadence programs seized from Igusa, such as FRoute=81, GRoute=81, and QPlace=
,=81
as well as the new, and as yet unreleased Cadence compaction program,
VSize.=81  Id. Exh. A; Johnson Dec. =B66.
        Cheng's workstation at Cadence did not have a tape drive.  Woo Dec.
=B6 11.  Moments after creating byebye.tar, however, Cheng transferred that
file to the workstation of another engineer which did have a tape drive.
Id. =B6 10.  The obvious -- indeed the only -- reason to make such a transfe=
r
was to allow Cheng to copy byebye.tar onto a tape, and take it with him.
Cheng has taken the Fifth as to all questions concerning his copying of the
byebye.tar file for Avant!.  Tangri Dec. Exh. 18 at 19:24-20:16, 40:12-17.
But, as described below, source code contained in the byebye.tar file,
including VSize=81 source code, appears in Avant! source code created after
Cheng joined Avant!.
        Cheng apparently got paid a bounty for heisting Cadence's source
code.  While Cadence has not been able to identify and trace all of the
accounts and transactions of Avant!'s participants because of their Fifth
Amendment assertions, Cadence has discovered that on January 5, 1995 --
while Avant! was recruiting Cheng -- Huang withdrew at least $9,000 cash
from two different bank accounts.  Tangri Dec. Exh. 19.  In apparent
reimbursement for Huang's "expenses," Avant! Vice President of Technology
Y.Z. Liao wrote Huang a cheque for $14,000 on January 8, 1995.  Id.  A
little over a month later, on February 22, 1995, Huang withdrew another
$4,000 in cash from one of her accounts.  Id.  On that occasion, Avant!
Vice President of Engineering Wuu reimbursed Huang with a $10,300 cheque
dated February 24, 1995. Id.  This pattern of pay-offs by Huang and
reimbursement by Avant! managers was to be repeated later with Mitsuru
Igusa.  Huang, Wuu, Liao, and Cheng have all taken the Fifth when asked to
explain these financial transactions.  Tangri Dec. Exh. 11 at 66-100; id.
Exh. 3 at 28:17-35:17; id. Exh. 2 at 27:8-31:24; id. Exh. 18 at 33:21-23.
They have also taken the Fifth when asked whether Cheng delivered Cadence's
trade secrets to Avant!.  Id.  Exh. 18 at 33:18-23.


=46. When the Cloud Left By The Search Appears To Lift, Avant! Goes Back To
The Igusa Well
        Apparently reassured by the lack of any obvious activity in the
District Attorney's investigation of the Igusa case, Hsu decided to
re-visit the issue of hiring Igusa during the first half of 1995.  On one
or two occasions, Hsu proposed to the other members of Avant!'s board of
directors that Avant! should openly hire Igusa.  Tangri Dec. Exh. 8 at
58:6-60:4, 66:4-14, 76:11-78:5; id. Exh. 4 at 77:12-79:7; id. Exh. 7 at
30:18-31:13.  Avant!'s outside directors rejected the proposal, fearing the
repercussions of employing someone currently under investigation by the
District Attorney for stealing Cadence trade secrets.  Id. Exh. 7 at
37:9-25; id. Exh. 21 at 38:22-39:19.  A suggestion was made, however, that
"individuals" within Avant! could "help" Igusa financially so long as the
payments did not come directly from Avant! as a corporation, and could
"invest" in Igusa's work.  Id. Exh. 8 at 62:1-63:2; id. Exh. 4 at
77:12-79:7; id. Exh. 7 at 39:2-24; id. Exh. 21 at 40:11-25.
        Avant! Chairman Hsu (usually accompanied by his assistant, Shiao-Li
Huang) met with Igusa on various occasions between the beginning of 1995
and late Summer of that year, always, according to Hsu, for purely "social"
discussions.  Tangri Dec. Exh. 8 at 90:8-10, 115:25-116:12, 117:24-118:6,
129:16-131:8.  One of those meetings was at Avant! prior to June 6, 1995;
Hsu could not explain why Igusa was there.  Id. Exh. 8 at 83.  Although
Hsu, Avant!'s Board Chairman, CEO and President, has not taken the Fifth
regarding his contacts with Igusa, his recollection of these meetings is
amazingly poor.  In response to extensive examination concerning the facts
and circumstances of his meetings with Igusa, Hsu repeatedly asserted that
he could remember virtually nothing about his meetings or discussions,
other than that they were of a "social" nature.  Tangri Dec. Exh. 8 at
37:3-40:7, 79:2-81:3, 85:2-88:2, 167:15-170:15.  Indeed, the only fact that
Hsu could recall about one mid-1995 lunch with Igusa was that he consumed a
very large burrito.  Id. Exh. 8. at 168:22. Hsu responded "don't remember"
or "don't recall" 396 times during his one-day deposition. Tangri Dec. =B6
10.
        Cadence, however, has pieced together the following.   Hsu, either
accompanied by Huang or alone, met with Igusa on multiple occasions between
August 11, 1994 and December 6, 1995, when Avant!'s offices were searched
by the District Attorney.  Tangri Dec. Exh. 10.  On August 1, 1995, Igusa
moved into the MBA Center, a building located approximately two blocks from
Avant!'s Sunnyvale headquarters.  Id. Exh. 22 at 10:25-11:6.  Although
Igusa initially rented his office under the name "Igusa Consulting," he
soon requested that the name be changed to "K2 Design Systems."  Id. Exh.
22 at 39:18-40:8, Exhs. 3-5.  "K2" is an apparent reference to Avant!'s
"K-Team," the engineering group created by Hsu to compete with Cadence as
part of what Hsu has publicly referred to as his "JFK" ("Just F_____ing
Kill" Cadence) campaign.  Id. Exh. 8 at 254:13-255:14.
        At the same time that Igusa rented his office in the MBA Center,
Shiao-Li Huang and Tzyh-Lih Wuu rented an office in the same building
(notwithstanding that they both had offices nearby at Avant!).  Tangri Dec.
Exh. 22 at 20:2-15.  Huang arranged for the rental, though Wuu actually
signed the lease.  The rental was for a business listed as the "Saurus
=46und," but there is no public record of any such entity.  According to the
building manager, Wuu and Huang moved computers into the Saurus Fund
office, just down the hall from Igusa and, although the office apparently
was used regularly, Wuu and Huang were almost never seen during normal
business hours.  Id. Exh. 22 at 25-26.  Wuu and Huang both have taken the
=46ifth in response to all questions about their activities in connection
with the Saurus Fund and Igusa; Igusa has obtained a stay of proceedings
against him and has refused to testify at all based on the Fifth Amendment
and his pending prosecution. Id. Exh. 3 at 36:17-40:7; Id. Exh. 11 at
41:20-50:1; Id. Exh. 23.
        One tangible product of the Wuu\Igusa collaboration is a
substantial quantity of Cadence source code which Avant! admits was
provided to Avant! by Igusa, but which nevertheless lists Wuu as the author
on all of the source code files.  Tangri Dec. Exh. 24 at 35:15-36:7 and
Exh. 102.  Though Avant! produced those source code files during discovery,
it claims to have no knowledge about the files on the disk, or how they
came into its possession, other than information (which Avant! will not
reveal) provided to it under a joint-defense privilege. Id. Exh. 25. The
other tangible product is a document Cadence's investigators retrieved from
Igusa's trash at his MBA Center office on October 20, 1995, and dated
October 18, 1995, establishing that Igusa was still secretly modifying
stolen Cadence source code even after he was charged with six felonies: the
document is a printout of source code taken from Cadence's QPlace=81 product=
.
Boynton Dec. =B6 2-4; Sechen Dec. =B6 69.
        Of the source code files on the "Igusa disk," approximately a dozen
can be found on Avant!'s fileserver, apparently placed there by Wuu.
Tangri Dec. Exh. 24 at 35:15-36:7.  Wuu also apparently modified four of
those files sometime between late November and December 15, 1995.  Id.
Because Wuu is taking the Fifth in response to all questions about what
Igusa gave him (and what use Wuu made of it), further information about the
fruits of Wuu's and Igusa's collaborative efforts is not available.  Tangri
Dec. Exh. 3 at 22:26-23:17.  What is clear, however, is that at least one
of the files that Igusa provided to Avant! contains trade secret source
code from a critical Cadence program: FRoute.=81  Teig Dec., =B6=B6 79-103.
Article: 3614
Subject: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 2)
From: jcooley@world.std.com (John Cooley)
Date: Wed, 3 Jul 1996 16:52:10 GMT
Links: << >>  << T >>  << A >>
    For those of you who wish to follow the Cadence/Avant! lawsuit in
    gory detail, I'm posting both Cadence's and Avant!'s sides in their
    own words.
                                             - John Cooley

    Part 2 of 3 "Cadence's View (continued)"

--------------------

G.      Like Cheng, Igusa Gets Paid For His Efforts
        Igusa was not doing volunteer work for Avant!, and he was not
working on a personal project for himself and Tzyh-Lih Wuu, as Avant!'s
Chairman Hsu has suggested.  Huang paid Igusa $15,000 in cheques drawn
biweekly during July and August, 1995, and Igusa (ostensibly unemployed)
purchased a $17,500 money order with unexplained funds at [____________].
(where Huang banked), which he then deposited into his own bank account at
[__________].  Tangri Dec. Exhs. 19, 26.  These traceable payments appear
to have stopped shortly after Igusa was arrested and charged with felony
misappropriation of trade secrets in early August, 1995.  But on October
20, 1995, Igusa drove two blocks to Avant!'s parking lot where he was met
and handed an envelope by Avant! Vice President of Technology Y.Z. Liao,
after which Igusa drove off.  Hughes Dec.; Baross Dec.  Huang, Wuu, and
Liao have all taken the Fifth in response to all questions concerning the
total amount, timing, and purpose of the payments to Igusa, as well as to
all questions about what Avant! received from Igusa in return.  Id. Exh. 11
at 31:12-21, 34:15-38:17; id. Exh. 3 at 30-35.
        Avant! Chairman Hsu, although not taking the Fifth, responded to a
Request to Admit that he was aware of Huang's payments to Igusa by stating
that he "lacks present recollection of information or belief necessary to
respond to this Request."  Id. Exh. 36.   In fairness to Hsu, he is
consistent.  He testified in deposition that he is incapable of remembering
events of over a month ago.  Tangri Dec. Exh. 8 at 46.
        Nor was Huang paying Igusa out of her own pocket without filling it
up again.  During 1995, she received over $130,000 from Avant! Vice
Presidents Yun-Chung Cho, Tzyh-Lih Wuu and Yuh-Zen Liao.  Tangri Dec. =B6 21=
,
Exhs. 19, 27.  Huang, Wuu, and Liao all have taken the Fifth in response to
questions about their financial arrangements.
        Avant!'s directors Cho and Hsu, who have testified, have offered an
improbable explanation.  Tangri Dec. Exh. 4 at 86-118; id. Exh. 8 at
70-116.  While their accounts differ in important respects, the gist of
their story is this.  At some point in the first half of 1995, Hsu decided
it would be a good idea for Cho, Wuu, Liao, and himself each to contribute
$50,000 to an investment fund to be managed by Shiao-Li Huang.  Id. Exh. 4
at 95:18-24; id. Exh. 8 at 71:16-72:24.  Cho dates the proposal after
Avant!'s IPO on June 6, 1995, when the original founders (including Cho,
Wuu, and Liao but not Hsu) had an opportunity to cash in some of their
stock.  Id. Exh. 4 at 86:13-24.  Hsu dates the proposal anywhere between
early to mid-1995, presumably to account for the $25,000 inexplicably paid
by Liao and Wuu to Huang in January and February, 1995.  Id. Exh. 8 at 59.
According to Hsu and Cho, some of their money was to be used to invest in
possible "start-up" businesses (essentially a form of venture capital); but
the only such "business" they could identify was undefined business having
to do with Mitsuru Igusa. Id. Exh. 8 at 170:10-171:25; id. Exh. 4 at
114:4-115:3.  While Huang was to manage the "investment," her consideration
was also never defined.  Id. Exh. 8 at 72.
        Hsu and Cho differ on why Igusa was to receive money from the
pooled fund.  Cho was under the distinct impression from what he was told
by Hsu that Igusa himself actually was one of the "start-up" businesses the
Avant! managers were supposed to be investing in, though he could not say
that he ever knew, or was told, what kind of "business" Igusa was to do, or
how much Igusa was to get.  Tangri Dec. Exh. 4 at 84:14-85:13,
113:7-116:17.  Hsu testified that he was vaguely aware that Wuu was
"helping Igusa" work on a software project, but claims inconsistently that
1) he knew nothing about any payments to or from Huang for Igusa (id. Exh.
8 at 15-16), and 2) the payments were to be made to Igusa as a form of
"humanitarian" assistance, with nothing expected in return.  Id. Exh. 8 at
115:3-19, 172:5-174:21.  Liao and Wuu have taken the Fifth on all questions
concerning their payments to Huang's fund; Huang has taken the Fifth on all
questions concerning the money she received or paid out.  Id. Exh. 2 at
27:8-31:24; Exh. 3 at 28:17-35:17; Exh. 11 at 66-100.
        The divergence between Hsu's and Cho's implausible stories is not
that surprising: according to Cho, they only discussed Cho's $50,000
investment twice.  On the first occasion, Hsu vaguely outlined the plan,
and Cho agreed to kick in his $50,000.  Tangri Dec. Exh. 4 at 89:12-90:14.
On the second occasion, Hsu simply asked Cho whether he had paid up yet
and, when Cho indicated that he had not, directed him to do so promptly
(which Cho then did).  Id. Exh. 4 at 140:23-141:8.
        Cho paid over his $50,000 with no more information than that.  To
Cho's knowledge, Huang's fund never incorporated.  No formal partnership
documents existed.  There was no business plan, no description of the
potential investments, no accounting of the funds paid or received, and no
agreement concerning profits, losses, or the return of capital.  Indeed, so
far as Cho knows, no documents, other than his five cancelled cheques, even
indicate the fund's existence.  Other than something having to do with
Igusa, Cho had no understanding of what start-up ventures the fund would
invest in, or who would make the investment decisions.  Amazingly, he never
discussed the fund with the other two investors, Liao and Wuu, nor did he
discuss it with Huang.  He has never received any indication of how much of
his investment has been invested or, if it has, in what.  Nor has he ever
asked Huang whether he has made or lost any money, or whatever became of
his five uncashed $5,000 cheques.  Tangri Dec. Exh. 4. 90-108.  This
alleged "venture capital" business was a phantom by any measure.
H. Avant! Gets Searched, Giving It A Pretext To Resist Discovery
        On December 5, 1995, the District Attorney searched Avant!'s
corporate headquarters in Sunnyvale and seized computers, disks, and backup
tapes.  Tangri Dec. Exh. 13.  Since then, Avant! has repeatedly represented
that it is unable to provide to Cadence information responsive to Cadence's
discovery requests because some materials have been seized by the District
Attorney and therefore are no longer accessible to Avant!.  See, e.g.,
Tangri Dec. Exh. 29.
        At the same time, however, Avant! has doggedly prevented the
District Attorney from sharing with both Cadence and Avant! any of the
material seized by the District Attorney.  Tangri Dec. Exhs. 30, 31.  In
spite of the fact that Cadence would have received the seized material in
discovery had it never been seized, Avant! continues to object to any
disclosure of the seized material to person's authorized to receive such
material under the Protective Order entered in this case.   Id.
        Avant! has also engaged in a relentless campaign to obstruct
expedited discovery in this case, which is too lengthy to describe in this
motion.  However, a tactic repeated twice so far has prevented Cadence from
analyzing Avant! source code before the filing of this motion, just as
Avant! has prevented Cadence from analyzing the District Attorney's
evidence.  On the eve of the deposition of one of its engineers, Sheng-Chun
Lo, Avant! conveniently and inexplicably produced an additional diskette of
source code, thus preventing any examination of Lo concerning the source
code produced.  Tangri Dec. Exhs. 33, 16.  Avant! pulled this stunt again,
barely a week before the filing of this motion, producing an additional
disk of source code.  Id. Exh. 34.  Cadence may seek an opportunity to
supplement this motion to identify additional source code stolen by Avant!,
though the evidence of misappropriation and copyright infringement is
already so overwhelming that entry of a preliminary injunction is amply
justified.
III.   SUMMARY OF EXPERT FINDINGS
        Even the limited discovery obtained and analyzed to date has
revealed massive trade secret misappropriation and copyright infringement
by Avant!.  Notwithstanding Avant!'s foot-dragging, Cadence's experts
M.I.T. Professor Randall Davis, Ph.D.; University of Washington Associate
Professor Carl Sechen, Ph.D.; Stanford University Lecturer Margaret
Johnson, Ph.D.; and place-and-route expert Steven Teig have established
that:
(1)     Avant!'s current products incorporate Cadence source code first
written by Cadence after June 6, 1994:  Avant!'s ArcCell XO product, first
released only months ago, contains code directly derived from Cadence's
copyrighted and trade secret VSize=81 program, written in part by Cadence
employee Chih-Liang Cheng just before he departed Cadence in February,
1995, as well as core global and detailed router algorithms (from FRoute=81
and QRoute=81) translated by Mitsuru Igusa from their original Mainsail
language to the C language, just before he departed Cadence in September,
1994;
(2)     Avant!'s current products incorporate Cadence source code first
used by Avant! after June 6, 1994;  ArcCell XO's global router, detailed
router, [_] variable die-size routines, and memory allocation routines
copied from Cadence's QPlace=81 all appear in Avant!'s products, for the
first time, in releases 3.1.1 (May 1995).
(3)     Avant!'s current products incorporate massive amounts of literally
and near-literally copied Cadence source code first used by Avant! prior to
May, 1994 and thereafter continually reused by Avant! in all subsequent
versions of its products, through and including Avant!'s January, 1996
versions of ArcCell and ArcCell XO -- specifically, large portions of
Cadence's Design Framework II=81 database structure, user interface, and
program environment; and
(4)     As recently as December, 1995, Avant! continued to receive
purloined Cadence source code from Mitsuru Igusa, apparently via Igusa,
Wuu, Liao, and the Lo K2\Saurus Fund enterprise at the MBA Center,
specifically code for block placement routines derived from Cadence's
QPlace,=81 and core proprietary routing algorithms derived from Cadence's
trade secret GRoute=81 and FRoute=81 can be found in Avant!'s ArcCell XO
version 5.0 source code libraries and elsewhere.

II.   LEGAL ARGUMENT
        To obtain a preliminary injunction, Cadence must show either "(1) a
likelihood of success on the merits and the possibility of irreparable
injury, or (2) the existence of serious questions going to the merits and
the balance of hardships tipping in [Cadence's] favor."  Diamontiney v.
Borg, 918 F.2d 793, 795 (9th Cir. 1990) (internal quotations and citations
omitted).  "These two formulations represent two points on a sliding scale.
. . ."  Id.  "Where a party can show a strong chance of success on the
merits, he need show only a possibility of irreparable harm."  Bernard v.
Air Line Pilots Association, Int'l, 873 F.2d 213, 217 (9th Cir. 1989)
(citation omitted).
A. Cadence Has An Overwhelming Likelihood Of Prevailing On Its Trade Secret
Claims
        Avant!'s theft of Cadence's source code, its direct incorporation
of Cadence source code into Avant!'s source code, its derivative use of
Cadence source code, and its direct use of Cadence proprietary software
architecture, each constitutes misappropriation of Cadence's trade secrets
under the Uniform Trade Secret Act ("UTSA"), California Civil Code Section
3426.1.
1. Cadence's Source Code And Software Design And Architecture Constitute
Protectible Trade Secrets
        Trade secret protection extends not just to Cadence's source code,
but to all Cadence proprietary information, processes, structure,
development information and know-how that its source code embodies.  Civil
Code Section 3426.1 defines this broad protection as follows:
        A trade secret is:

a. information, including a formula, pattern, compilation, program, device,
method or technique, that

(1) derives independent economic value, actual or potential, from not being
generally known to the public or to other persons who can obtain economic
value from its disclosure or use; and

(2) is the subject of efforts that are reasonable under the circumstances
to maintain secrecy.
"The definition includes information that has commercial value from a
negative viewpoint, for example, the results of lengthy and expensive
research which proves that a certain process will not work could be of
great value to a competitor."  Legislative Committee Comment -- Senate 1984
West's Annot. Civil Code =A7 3426.1.
        As explained in more detail in Section 2 below, in the software
arena, courts extend trade secret protection not only to the source code
itself, but also to software manuals, formulas and methods of calculation,
structure and organization of modules, data flow, control flow, nesting,
data structures and algorithms, and procedures and processes of operation.
See generally, Gates Rubber v. Bando Chemical Industries, 9 F.3d 823 (10th
Cir. 1993); Trandes Corp. v. Guy F. Atkinson Co., 996 F.2d 655 (4th Cir.),
cert. denied 114 S. Ct. 442 (1993).
        Cadence's intellectual property at issue in this case plainly
qualifies as trade secrets under the UTSA.  It readily meets the standard
for having independent economic value, because it is of more than
sufficient value to provide an actual or potential advantage over others
who do not possess the information.  See, Religious Technology Center,
supra, 1995 U.S. Dist. LEXIS 16184 (N.D. Cal. 1995.   Cadence has also
taken reasonable security measures to protect its trade secrets.


2. Avant!'s Conduct Constitutes Misappropriation Under The Uniform Trade
Secret Act
        Misappropriation occurs when a person uses the trade secret of
another without express or implied consent and, at the time of use, knew or
had reason to know that the information was (i) derived from a person who
had used improper means to acquire it, or (ii) from a person who owed a
duty to maintain the secret.  Civil Code =A7 3426.
        While direct copying of a trade secret such as Avant! engaged in
here is the most obvious and blatant form of misappropriation, equally
actionable misappropriation occurs if the defendant substantially
appropriates the trade secret.  See, 3 Milgrim, Milgrim on Trade Secrets, =
=A7
15.01[1][d][vi] pp. 15-88.  The recent Restatement Third, Unfair
Competition, Section 40, comment c, captures this long-settled principle:
                The unauthorized use need not extend to every aspect or
feature of the trade secret; use of any substantial portion of the secret
is sufficient to subject the actor to liability.  Similarly, the actor need
not use the trade secret in its original form.  Thus, an actor is liable
for using the trade secret with independently created improvements or
modifications if the result is substantially derived from the trade secret.
Courts routinely find misappropriation where, as Avant! has also done here,
information is substantially derived from another party's trade secrets.
See, e.g., Sokol Crystal Products v. DSC Communications Corp., 15 F.3d
1427, 1432 (7th Cir. 1994) (upholding jury verdict finding substantial
similarity); General Electric v. Chien-Min Sung, 843 F.Supp. 776 (D. Mass
1994) (issuing injunction against the use of information substantially
derived from trade secrets); Cybertek Computer Products, Inc. v. Whitfield,
203 U.S.P.Q. (BNA) 1020 (Cal. Super. Ct. 1977) (similarity of computer
databases "is of obvious importance, and must be given weight").
        When misappropriation of computer software is at issue, courts
examine not only the literal source code, but also the software program's
design, structure and architecture to determine if those "structural" trade
secrets have been misappropriated.  The decision in Integrated Cash Inquiry
Mgmt. Serv., Inc. v. Digital Transactions, Inc., 732 F.Supp. 370 (S.D.N.Y.
1989) illustrates this point.  There, even though source code had not been
directly copied, the court held that knowledge concerning which "functions
and relation-ships among the modules would and would not work" were trade
secrets which had been misappropriated.  In Cybertek Computer, the court
likewise found that similarities in the design and design choices in the
defendant's software constituted strong evidence of misappropriation.
Cybertek, 203 U.S.P.Q. at 1025.
        Such "structural" trade secrets are inherent in a computer program,
and their misappropriation is just as serious as direct copying of source
code.  A computer program represents far more than just its literal source
and object code.  Embodied in that code are the ideas and concepts of
software design and architecture necessary to achieve the program's desired
function.  Thus, a computer program is not "built" from the "bottom up,"
but from the "top down."  A computer programmer first defines the overall
function of the program, and then decomposes that function by designing a
series of more specific subtasks.  This decomposition process may involve
potentially millions of proprietary design decisions:
                Decisions made at this stage of the programming process can
profoundly affect the quality of the resulting program . . . .  Different
programmers faced with the same problem would ordinarily be expected to
produce somewhat different decompositions.
Englund, 88 Mich. L. Rev. 34, 39 (1990); see generally, Ogilvie, 91 Mich.
L. Rev. 526.  The decomposition process is enormously complex; it requires
teams of programmers to develop, design and then write the millions of
characters that make up Cadence proprietary software programs used by
chipmakers for their sophisticated integrated circuit designs.  Davis Dec.
=B6 42.
        Modeling code after a competitor's proprietary code is a
particularly effective (though illegal) method to reduce the time, man
hours and skill set required to develop an efficient and competitive
software program for the design of complex custom integrated circuits.
Davis Dec. =B6 50-55.  There is already overwhelming evidence that Avant! ha=
s
resorted to this illegal method to obtain an illegal head start, copying
directly from Cadence source code and using Cadence proprietary design
solutions and architectural structures to derive Avant! source code.
Consider these specific Avant! thefts of Cadence's trade secrets:
a.      VSize=81 Misappropriation.
        A striking example of Avant!'s misappropriation of Cadence's most
valuable trade secrets is its duplication of Cadence's recent VSize=81
program.  VSize=81 is quite valuable, because it allows integrated circuit
designers to reduce the size of the silicon die and implement variable die
size designs more quickly.  Markham Dec. =B6 7.  As set forth in detail in
the declarations of Professors Carl Sechen and Dr. Johnson, in developing
VSize=81 Cadence [______________
__________________________________________________________] to add variable
die-size functionality to its Cell3 product.  Thus, VSize=81 contains certai=
n
unique and unusual features peculiar to Cadence's [__________].  The fact
that the identical features appear in Avant!'s version of VSize,=81 called
[___] is unmistakable evidence of copying by Avant!.  If further
confirmation of Avant!'s theft were needed, Cheng's creation of byebye.tar
(which included the source code for VSize=81), and his and Huang's invocatio=
n
of the Fifth Amendment on the subjects of (1) Huang's cash payments to him
and (2) his theft of Cadence source code, confirm that Avant!
misappropriated VSize=81.
        By June 17, 1995, using the C programming language instead of
Mainsail, Avant! had copied VSize.=81  Johnson Dec. =B6=B6 17, 25; Sechen=
 Dec. =B6=B6
24-34.  Avant!'s derivative copy of VSize,=81 released for the first time as
part of ArcCell XO 5.0 in December 1995, is called [___]  it adds to
ArcCell the same variable die-size functionality as VSize=81 added to
Cadence's Cell3 Ensemble,=81 including the features peculiar to Cadence's
[_____________].
        Cheng's copying of VSize=81 as he bade "bye bye" to Cadence
establishes Avant!'s access to Cadence's VSize=81 trade secrets.  Rather tha=
n
attempt to suggest how Avant! independently came to acquire its version of
VSize=81 in a fraction of the sixteen man months it took Cadence to develop
VSize=81, Markham Dec. =B6 7, Cheng has taken the Fifth in response to all
questions about his misappropriation of VSize=81 and his development of
highly similar source code for Avant!.  Tangri Dec. Exh. 18 at 25-32.  The
Court should draw the adverse inference that truthful responses would tend
to incriminate Cheng and his employer Avant!.  See note 20, supra.
        Expert comparison of Cadence's VSize=81 data structures and
algorithms with Avant!'s [________] modules confirms Cheng and Avant!'s
misappropriation.  Cadence's experts have identified five areas of
comparability which all show copying of Cadence's VSize=81 trade secrets:
        =85First, like Cadence, Avant! implemented a [____________________]
by [______________  ____________________].  Johnson Dec. =B6=B6 18-20; Seche=
n
Dec. =B6 29.  This is unique in the industry;

        =85Second, Cadence's methodology of employing [___________] is
unique, but Avant! uses the same trade secret technique in "[_]."

        =85Third, the data structures in Cadence Vsize=81 and Avant!'s "[_]"
modules closely correspond to each other, even though there are many
different methods to build data structures for [_____]. Johnson Dec. =B6=B6
23-30; Sechen Dec. =B6 33;

        =85Fourth, the algorithm used to build [_____________] is the same,
even though there are many different ways to construct and maintain
[___________]. Johnson Dec. =B6=B6 31-35; Sechen Dec. =B6 33; and

        =85Fifth, the use of
[_________________________________________________________], described by
Professor Sechen as "shockingly creative," is replicated in Avant!'s "[_]."
Johnson Dec. =B6=B6 36-37; Sechen Dec. =B6 32.

Any one of these likenesses alone would be strong evidence of trade secret
misappropriation.  But all five, when combined with the facts of Cheng's
common authorship, his copying of VSize=81 in the "byebye.tar" file, Avant!'=
s
extraordinarily short development time [__________  ______], and Cheng's,
Liao's, and Huang's invocation of the Fifth, allow only one, inescapable
conclusion:  Defendants Cheng and Avant! stole VSize.=81
b.      Global and Local Router Misappropriation.
        Avant! has also recently misappropriated Cadence's groundbreaking
and trade secret global and detailed router software.  As set forth in the
declarations of Steven L. Teig and Professor Sechen, these routers were
originally invented by Teig and Eriq Nequist for Cadence's predecessor,
Tangent Systems, where they were code-named [__________________
___________].  They were later incorporated into Cadence's Gate Ensemble=81
and Cell3 Ensemble,=81 where they were referred to as GRoute=81 (for Global
Router) and FRoute=81.  This proprietary routing technology, which is the
heart of Cadence's product line, is a unique variant of a routing algorithm
known as [__________________].
        After Teig and Nequist left, Cadence assigned Sheng-Chun Lo and
Ping-San Tzeng to try to develop a better router, to be called QRoute=81.
Markham Dec. =B6 9.  After more than a year of effort, however, QRoute=81
turned out to be no better than FRoute=81, so Cadence assigned Igusa to
optimize FRoute=81, and to translate it from the Mainsail programming
language to the C programming language.  Id.  Igusa completed most of this
assignment before he quit Cadence in September, 1994.  Id. =B6 10.  As set
forth above, Igusa took the revised source code with him when he left.
        Avant!'s new ArcCell XO global and local routers contain striking
and unmistakable structural similarities to unpublished trade secret
techniques found in Cadence's routers, confirming Avant!'s
misappropriation.  These multiple correspondences include:
        =85Functionally identical implementations of
[__________________________ ______________] router. Teig Dec. =B6=B6 31-35.

        =85An array of [______________________________________].  Teig Decl.
=B6=B6 37-40.

        =85Use of [_________________________________].  Teig Decl. =B6=B6 41=
-43.

        =85Use of a [_________________________________________].  Teig. Decl=
.
=B6=B6 44-47.

        =85Initial [_____________________________________].  Teig Decl. =B6=
=B6 50-54.

        =85Numerous quirks, unique nomenclatures, and outright bugs
duplicated from   Cadence's routers to Avant!'s.  See, e.g. Teig Dec. =B6=B6=
 9,
48-49, 70-73, 75.

        Each of these clear instances of misappropriation involves core
Cadence trade secret techniques and algorithms.  Sechen Dec. =B6=B6 35-50.
These facts, combined with Avant!'s access and the Fifth Amendment
assertions of the misappropriators, demonstrate Avant!'s theft of Cadence's
global routing system and its illegal use in Avant!'s ArcCell XO=81.
Avant!'s local router similarly contains numerous indicia of copying.  Id.
        And finally, there is the mysterious disk containing Cadence's
[______________] algorithm and derivative copies of Cadence's QPlace=81 that
Avant! has identified as having been provided to it, somehow, by Mitsuru
Igusa.  Avant!'s Lo has testified that he experimented with and rejected
the use of [______________] as unworkable,  and then accepted Igusa's
wildly coincidental offer of a disk containing [______________] that Igusa
just happened to bring to a "social" lunch with Lo.  Lo contends he never
bothered to look at Igusa's disk.  He claims he stashed it unreviewed in
his glove compartment and then discarded it, despite Lo's own failed
attempts to implement [______________] and Igusa's assurances that Lo was
free to use Igusa's version.  Tangri Dec. Exh. 16 at 152-162.
        Avant!, however, did not give up on [______________], if indeed Lo
did.  Shortly thereafter, in August 1995, Wuu, Huang, and Igusa set up
their K2/Saurus Fund enterprise at the MBA Center.  One of the fruits of
that enterprise was the [______________] algorithm, in the form of a file
named [_____].  The copy of that file on the Igusa disk produced by Avant!
contains a header identifying Wuu as the author, but he is not:  the
[______________] algorithm on the Avant! disk, described in detail by
Steven Teig, is Cadence's, right down to sharing the same bugs and
eccentricities.  Teig Dec. =B6=B6 79-104.  Once again, when Avant!'s own R&D
hit a snag, it went back to the Igusa well, misappropriating Cadence's
code.
c.      QPlace=81 Misappropriation.
        Avant! also misappropriated portions of Cadence's QPlace=81 source
code.  QPlace=81 files were found both in Cheng's "byebye.tar" file and on
the floppy disk produced by Avant! and admittedly provided to Avant! by
Igusa.  Analysis of the disk reveals that the "[_]" files thereon are
closely derived from Cadence's QPlace.=81  Sechen Dec. =B6=B6 51-68.  As wit=
h
[_____], Wuu is falsely identified as the author of the [_] files, which
were placed on the Avant! file server 1995.  Id., Attachment 4.  Wuu has
taken the Fifth in response to all questions regarding the actual origin of
the [_] files.  Tangri Dec. Exh. 3 at 21:3-25:21.  The misappropriated
QPlace=81 files obviously were furnished by Igusa, not authored by Wuu.
d.      Database Misappropriation.
        The foregoing three examples are of recent misappropriation of core
algorithmic routines contained in Cadence's placement and routing
algorithms -- misappropriations conducted through elaborate means of covert
slush fund payments, off-site rewriting, shell businesses, and the like.
        In the beginning, however, Avant!'s founders were not so subtle.
Scores of Cadence source code files were simply copied wholesale in
creating Avant!'s ArcCell products.  That copying spanned a wide range of
program modules, and the copied portions have been retained and replicated
in Avant!'s most recent 5.0 releases of ArcCell and ArcCell XO.
        While this copying is found throughout Avant!'s ArcCell product, it
is most literal in the underlying user interface, database management, and
utility layers.  These "chassis" parts form the core of Cadence's Design
=46ramework II=81 and Symbad source code files, and they have been largely
incorporated into the most recent versions of Avant!'s ArcCell and ArcCell
XO products released only months ago.  Indeed, Avant!'s literal copying of
Cadence's functional routines, database structures, and hundreds of user
interface messages -- including repeated replications of typographical
errors, misspellings, and other quirks--is so pervasive and blatant that
M.I.T. Professor Davis, who has been selected as an expert in most of the
major software cases in this country for the past decade, has described it
as "among the most substantial and blatant copying of code that I have
seen."  Davis Dec. =B6 13.
        Unlike the algorithmic and structural copying detailed by Mr. Teig,
Professor Sechen, and Dr. Johnson, there is nothing subtle about the scores
of examples of copying set forth in Professor Davis' declaration. There can
be no doubt here:  Avant! is using proprietary source code stolen from
Cadence.
        In sum, Avant! has been, and is, using misappropriated Cadence
trade secrets, and Avant! has sold, and is selling, software built on the
theft of Cadence's trade secrets.  Grave and egregious misappropriation has
occurred.  Once misappropriation has been demonstrated, "the burden then
shifts to the defendant and places upon the defendant a heavy burden of
persuasion to show that the production was a result of independent
development and not from the use of information confidentially secured."
Cybertek, 203 U.S.P.Q. at 1024-25; see Carter-Bare Co. v. Munsingwear,
Inc., 723 F.2d 707, 714 (9th Cir. 1984); see also Bolt Associates, Inc. v.
Alpine Geophysical Associates, Inc., 365 F.2d. 742, 749 (3d. Cir. 1966).
Article: 3615
Subject: Their Own Words: Cadence vs. Avant! (Avant!'s Side)
From: jcooley@world.std.com (John Cooley)
Date: Wed, 3 Jul 1996 16:56:52 GMT
Links: << >>  << T >>  << A >>
    For those of you who wish to follow the Cadence/Avant! lawsuit in
    gory detail, I'm posting both Cadence's and Avant!'s sides in their
    own words.
                                             - John Cooley

    Part 3 of 3 "Avant!'s View"

--------------------

EXPERTS FIND COMPLETE LACK OF TECHNICAL EVIDENCE 
IN CADENCE LAWSUIT AGAINST AVANT!

- Court papers state no copyright infringement, no trade secret
misappropriation -


SUNNYVALE, Calif. - June 28, 1996 - Experts have confirmed that no Avant!
product infringes any Cadence copyright or contains any Cadence trade secret,
according to court papers filed today by Avant! Corporation opposing
Cadence's motion for preliminary injunction. Avant!s papers rely on
admissions of Cadences experts made under cross-examination and on the
detailed findings of nationally recognized experts, who testified on Avant!s
behalf.

According to Avant! spokesperson Lois DuBois, Avant! has been waiting for
months to respond in court to Cadences accusations. Hard evidence -- from
Cadences experts as well as Avant!s -- now confirms that Cadence has
resorted to baseless litigation because it cannot compete with Avant! in the
marketplace.

Avant!'s court filing states that the only source code similarities
Cadence's experts have identified concern low-level code from old database,
graphic utilities, and related software -- not Avant!s place and route code.
This low-level code is covered by a 1994 settlement agreement releasing all
Cadence claims against Avant!. To avoid any dispute, however, Avant! has
removed the code from its products through a "clean room" process.
Avant!s and Cadences experts also confirm that no Avant! product uses code
that is linked to former Cadence employee Mitsuru Igusa, who is alleged to
have taken code from Cadence. Avant! accuses Cadence of relying on
cloak-and-dagger melodrama about Igusa in an attempt to compensate for
Cadences complete lack of technical evidence.

With respect to Avant!s place and route software, Cadences only claims
turn out to be allegations that the software was "derived" from Cadence trade
secrets, Avant!s papers state. The presence of Cadences so-called trade
secrets is so pervasive in public literature that Avant!s experts have
cited, merely as examples, hundreds of books and articles discussing in
detail the allegedly misappropriated techniques. Cadences experts have
admitted that they never examined the literature in which Cadences purported
trade secrets appear. For example, one of Cadences purported "secret
formulas" is published in Mathematics for Elementary School Teachers.

The papers filed by Avant! in Case No. CV 95-20828 RMW (PVT) are currently
under seal until confidentiality issues are resolved, but will be available
in the near future at the United States District Court in San Jose,
California.

Avant! Corporation (Nasdaq:AVNT) develops, markets, and supports integrated 
circuit design automation (ICDA) software for deep submicron integrated
circuits (ICs), microprocessors, microcontrollers, application-specific
standard products (ASSPs), and complex application-specific integrated
circuits (ASICs). Company headquarters are located in Sunnyvale, California,
telephone (408) 738-8881.
Article: 3616
Subject: Problems with ORCA c40 FPGAs
From: kh@pvimage.com (Kevin Harney)
Date: Wed, 3 Jul 1996 19:08:18 GMT
Links: << >>  << T >>  << A >>
We have been using c40 ORCAs in an image recognition product, and have
been having problems with everything from the place place and route tools, 
to the parts not meeting spec. If you have had either a positive or a negative
experience with the ATT ORCA chips, please share your story with me.
I can be reached at:

Kevin Harney
kh@pvimage.com


Article: 3617
Subject: Re: FPGA Companies
From: john@flower.aud.temple.edu (John W. Schwegler)
Date: 3 Jul 1996 19:49:20 GMT
Links: << >>  << T >>  << A >>
John L. Smith, Principal Engineer (univis@univision.com) wrote:
: > I have for a long time wondered if anyone will make FLASH-based FPGAs.

: Altera's (formerly Intel's) FLEX family is flash based.

We were looking at using the Altera flash-based FPGAs for some 
small projects here.  Rather than wire a bunch of discrete components
together, we want to put all the logic on a single chip (it's not too
involved).  We're absolute newbies with regard to FPGAs;
are there any comments, good or bad, about these (Altera) FPGAs?

-john
--
______________________________________________________________________________
"Genius may have its limitations,       | John Schwegler
   but stupidity is not thus            | Temple U. Auditory Research Dept.
   handicapped."                        | john@flower.aud.temple.edu
         - Elbert Hubbard               | (215) 707-3687 FAX 707-3650


Article: 3618
Subject: Re: FSM encoding in VHDL with MAX+plusII
From: "J. Scott Dickson" <jsdickson@anet.rockwell.com>
Date: Wed, 3 Jul 1996 20:43:27 GMT
Links: << >>  << T >>  << A >>
I like to set the bit values for a FSM also, which I would do with AHDL, 
but it is just as easy in VHDL:

CASE State is
  WHEN "0001" =>
    ...
    STATE <= "0010";
  WHEN "0010" =>
    ...
  WHEN OTHERS =>




Andre Klindworth wrote:
> 
> One of the great features of Alteras AHDL is the possibility
> to identify outputs of a FSM with bits of the state encoding:
> 
>   SUBDESIGN ctrl (
>     resetn, clk: INPUT;
>     a,b: INPUT;
>     x,y,z: OUTPUT;
>   )
>   VARIABLE
>     MACHINE OF BITS (x,y,z) WITH STATES (
>       init   = B"000",
>       state1 = B"101",
>       state2 = B"110",
>       state3 = B"110",
>       state4 = B"100",
>       ...
>     );
>   BEGIN
>     ...
>   END;
> 
> My question is: Is there a similar way to describe such a FSM in VHDL?
> 
> I do have read the VHDL booklet of the MAX+plusII documentation and
> I do know how to do manual state assignment. The example above should
> look something like
> 
>   ENTITY ctrl IS
>     PORT ( resetn, clk: IN std_logic;
>            a, b: IN std_logic;
>            x,y,z: OUT std_logic
>          );
>   END ctrl;
> 
>   ARCHITECTURE output_encoding OF ctrl IS
>     TYPE state_t IS (init, state1, state2, state3, state4, ...);
>     ATTRIBUTE ENUM_ENCODING: STRING;
>     ATTRIBUTE ENUM_ENCODING OF state_t: TYPE IS "000 101 110 110 100";
>     ...
>    BEGIN
>     ...
>   END output_encoding;
> 
> But how do I access a bit of the state encoding to assign it to the
> corresponding output signal?
> 
> Any help appreciated.
> 
> Thanks, Andre'.
> --
> ---------------------------------------------------------------------------
> Andre' Klindworth                       Universitaet Hamburg, FB Informatik
> klindwor@informatik.uni-hamburg.de      Vogt-Koelln-Str.30, D-22527 Hamburg
> http://tech-www.informatik.uni-hamburg.de/Personal/klindwor/Klindworth.html


Article: 3619
Subject: Re: FPGA Companies
From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN)
Date: Thu, 4 Jul 1996 09:22:28 +800
Links: << >>  << T >>  << A >>
Hi,

from my personal experience, ALTERA is a nice choice
because its development tool (no matter schematic or
interface with other VHDL tools) is very easy to use
and user friendly.

However, as far as performance is concerned (operating
freqency and utilization), it needs a lot of skill
of tuning.  And sometimes you have to understand its
architecture in detal.

One drawback of ALTERA FPGA is the pin-fix after the
first pin placement.  If you use more than 80% of the
logic elements, it might be impossible to preserve
the pin assignment.

Another possible concern is its large power consumption.

Anyway, ALTERA FPGAs are quite cheap!

All the statement above is my personal opinion only.

Regards,

Felix K.C. CHEN

In article <4reis0$dil@cronkite.ocis.temple.edu>
John W. Schwegler <john@flower.aud.temple.edu> wrote:
> John L. Smith, Principal Engineer (univis@univision.com) wrote:
> : > I have for a long time wondered if anyone will make FLASH-based FPGAs.
> 
> : Altera's (formerly Intel's) FLEX family is flash based.
> 
> We were looking at using the Altera flash-based FPGAs for some 
> small projects here.  Rather than wire a bunch of discrete components
> together, we want to put all the logic on a single chip (it's not too
> involved).  We're absolute newbies with regard to FPGAs;
> are there any comments, good or bad, about these (Altera) FPGAs?
> 
> -john
> --
> ______________________________________________________________________________
> "Genius may have its limitations,       | John Schwegler
>    but stupidity is not thus            | Temple U. Auditory Research Dept.
>    handicapped."                        | john@flower.aud.temple.edu
>          - Elbert Hubbard               | (215) 707-3687 FAX 707-3650
> 
-- 
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw

Machines and tools are only as
good as the people who use it.
---------------------------------


Article: 3620
Subject: Re: FSM encoding in VHDL with MAX+plusII
From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN)
Date: Thu, 4 Jul 1996 09:29:09 +800
Links: << >>  << T >>  << A >>
Hey friends,

you can write your VHDL in "abstract" and let the
VHDL synthesizer do the binding between state bits and
output signals.

Obviously you need one-hot encoding to make each
of the state vector bit a output signal.
It is easy by synthsize the FSM in one-hot encoding
and then write statements like below:

out0 <= '1' when state=s0 else '0';
out1 <= '1' when state=s1 else '0';
...

Really you do not have to worry which bit of state
is assigned to out0.  This VHDL file works well for
other FSM encoding too.

People who are used to ABEL/PALASM/AHDL are apt to
thinking logically instead of behaviorally.  But
it is just a step away.

Regards,

Felix K.C. CHEN
 
-- 
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw

Machines and tools are only as
good as the people who use it.
---------------------------------


Article: 3621
Subject: RE: Sanity check for 100K gate DSP FPGA project
From: Jack Ogawa <jacko@Altera.COM>
Date: Thu, 4 Jul 1996 01:34:05 GMT
Links: << >>  << T >>  << A >>
David Decker writes:

>I'm asking for a sanity check at the start of this large project, from
>those of you who have been here, and done this.
>Am I all wet?
>Would VHDL etc. make this a piece of cake?
>Are there any third party tools for DSP that would make schematic
>entry easier?
>Is there another chip family/tool set intended for DSP designs, that
>would make all this easier?

Altera offers a kit which specifically addresses DSP applications, which is 
available free of cost.  It is comprised of:
An 8-, 16-, 24-, 32-, and 64-tap FIR filter macrofunction, with 
parameterized data widths, capable of up to 105 Msamples per second, in 
both serial and parallel configurations.
A floating point adder/subtractor, with parameterized mantissa and exponent 
widths.
A high-speed parallel divider, with parameterized dividend and divisor 
widths.
A floating point multiplier, with parameterized mantissa and exponent 
widths.

In addition, support documentation is included.

The functions are developed with Altera's FLEX 8000 and FLEX 10K 
architectures in mind, and have received very favorable response both in 
performance and ease-of-use from our customers.  In fact, the June 20, 1996 
copy of EDN covers this kit and the overall design experience of a DSP 
application with FLEX 10K in detail.  Of course, you can be the final 
judge.

All of these macrofunctions are supported with Altera's MAX+PLUS II 
development environment, which offers fully integrated design capture, 
compilation, verification, and programming support.

To obtain a copy of a kit, please contact 800-800-3753, hit 0 for the 
operator, and ask for extension 7144 and request a copy of the DSP design 
kit.

Good Luck!
Jack Ogawa
Product Marketing
Altera Corp.



Article: 3622
Subject: Re: FSM encoding in VHDL with MAX+plusII
From: Lance Gin <c43lyg@dso.hac.com>
Date: Wed, 03 Jul 1996 19:29:45 -0700
Links: << >>  << T >>  << A >>
Andre Klindworth wrote:

(snip) ...

> 
> My question is: Is there a similar way to describe such a FSM in VHDL?
> 
> I do have read the VHDL booklet of the MAX+plusII documentation and
> I do know how to do manual state assignment. The example above should
> look something like
> 
>   ENTITY ctrl IS
>     PORT ( resetn, clk: IN std_logic;
>            a, b: IN std_logic;
>            x,y,z: OUT std_logic
>          );
>   END ctrl;
> 
>   ARCHITECTURE output_encoding OF ctrl IS
>     TYPE state_t IS (init, state1, state2, state3, state4, ...);
>     ATTRIBUTE ENUM_ENCODING: STRING;
>     ATTRIBUTE ENUM_ENCODING OF state_t: TYPE IS "000 101 110 110 100";
>     ...
>    BEGIN
>     ...
>   END output_encoding;
> 
> But how do I access a bit of the state encoding to assign it to the
> corresponding output signal?

i recently had a thread in this newsgroup on a very similar topic (so
thanks to everyone who contributed to the solutions below). in my case,
i was also using enumerated types for my FSM states and needed the
entity to output the state vector:

-- option 1: this is a very simple way to do it, but it is *verbose*,
-- especially for large state machines:

TYPE states IS (state1, state2, ...);

PROCESS (curr_st)
BEGIN
  CASE curr_state IS
    WHEN state1 =>
      state_vector <= "00";
    WHEN state2 =>
      state_vector <= "01";
    ...
    WHEN OTHERS =>
      state_vector <= "00";
  END CASE;
END PROCESS;

-- option 2: this is a more *compact* way to code using an array of
-- vectors whose indices are the state enumerated types. make sure
-- your synthesizer can handle "named" arrays.

TYPE states IS (state1, state2, ...);

PROCESS (curr_st)

  TYPE vect_array IS ARRAY(states'HIGH DOWNTO states'LOW)
    OF std_logic_vector(1 DOWNTO 0);
  CONSTANT state_out : vect_array := (state1 => "00",
                                      state2 => "01",
                                      ...
                                      others => "00"
                                      );

BEGIN

  state_vector <= state_out( curr_st );

END PROCESS;
      
in either case, just remember that if you change your manually specified
state assignments, you will need to update this section of code. if your
synthesizer is using a deterministic method for *automatically* doing state
assignments and it is known to you, then you may be able to write code
which will automatically figure out the state vector value to output
(which is what i did for mentor autologic II). i won't describe this here
because it depends on your synthesizer.

either of the two options should serve you well.

-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________


Article: 3623
Subject: Re: LCA to Schematic
From: David Pashley <david@fpga.demon.co.uk>
Date: Thu, 04 Jul 96 08:43:28 GMT
Links: << >>  << T >>  << A >>
In article <31D9AAC9.7097@emf.net> blt@emf.net "Brad L Taylor" writes:

"Michael D. Scott wrote:
"> 
"> Hi,
">         I have an LCA file for XACT 5.0 which was spun off a
"> Viewlogic schematic.  This chip had a few flaws so we made a few
"> changes directly in the LCA file without really documenting the changes
"> (I know, it's bad practice but it is done).  Is there a way to convert this
"> LCA file back into a schematic ?
"
"Yes, but I don't remember exactly how. It goes something like this
"- convert .lca to .xnf with lca2xnf
"- convert .xnf to .wir with xnf2wir
"- use viewgen to create a schematic from the .wir file.
"
"However:
"- Viewgen crashes randomly with big (and small) files

Perhaps your Windows setup is broken. If you give details including 
precise s/w versions, someone will probably come to your aid.

"- The resulting schematic is your worst nightmare. All high level 
"  info is lost and you are left with a random ratsnest of gates.

That's because your .LCA file doesn't have any high-level info to 
start with.

"- I don't know if this path is supported by the new viewlogic toolset.

Yes it is. However, if you don't have Viewgen (or even if you do), 
there's a very neat low-cost product called SmartViewer that brings 
up your .xnf file in one window, and generates schematics in another 
as you probe signals or blocks in the .xnf. By clicking on the .xnf, 
you can ask questions like "show me all the logic between these two 
points" or "show me everything upstream of this point". It's a 
useful tool, and also supports PALASM-type input.

David Pashley



Article: 3624
Subject: Re: FSM encoding in VHDL with MAX+plusII
From: Oliver Weber <sz1306@stud.uni-erlangen.de>
Date: Thu, 04 Jul 1996 22:55:30 +0100
Links: << >>  << T >>  << A >>
Andre Klindworth wrote:
> 
> One of the great features of Alteras AHDL is the possibility
> to identify outputs of a FSM with bits of the state encoding:
> 
>   SUBDESIGN ctrl (
>     resetn, clk: INPUT;
>     a,b: INPUT;
> ................


jeah, I think i have the right link for you :

http://www.nf.fh-nuernberg.de/arbgrp/vhdl/docu1.html


------------------------------------------------------------------
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/ 90489 Nuernberg               /  weber@nf.fh-nuernberg.de      /
/ Tel: +49 911 554290           /                                /
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/ http://www.nf.fh-nuernberg.de /                                /
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