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Messages from 3975

Article: 3975
Subject: Re: Anyone know about Viewlogic v4 with QEMM?
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 28 Aug 1996 07:45:39 GMT
Links: << >>  << T >>  << A >>
In article <32202045.30373@news.alt.net> ft63@dial.pipex.com (Peter) writes:
>Hello,
>
>I am using Viewdraw/Viewsim (DOS version 4.1) with QEMM7.03.

I am using QEMM 6.0 .  I paid money for 6.02, 7.5, and chose not to waste
anymore money when 8.0 came out. I have only been successful with the 6.0
version. The same command line options all fail to create a reliable
system with any of the following versions. This is not to say that QEMM
is a poor product, but I am really pissed when the functionality changes
between versions.

>
>I have upgraded to QEMM7.5, and find that Viewlogic crashes (reboots
>the PC) immediately at startup. Reverting to QEMM7.03 makes it OK
>again, and this is no big deal since 7.05 has only one useful feature
                                      7.5
>I can see.

As you can see, I stayed with 6.0

>Xilinx always used to say that one "must" run their Viewdraw etc under
>QEMM, and in fact they used to include QEMM, as well as the classic
>3-button PC Mouse :), in the package.
>But I never established why QEMM was really needed. The only sort-of
>explanation I ever got was that only QEMM supported the inter-program
>communication used by the various DOS extenders used.

The problem is that each program has a DIFFERENT DOS extender linked into
it (or so it seems) or called at runtime. Because Viewlogic stopped
working on the 4.1 DOS version about 4 or 5 years ago, and was written
before DOS extenders were commonly available, it has its own (non
compatible with anything else) DOS extender linked in. As development on
this product stopped years ago, it was never rebuilt with any of the third
party DOS extenders, which would have removed most of the problems that
are caused when trying to use this version of their software with anything
else. Various version of Xilinx software have been created with any of the
following DOS extenders: DOS16/M (from rational systems), DOS4/G (from
rational), and Phar Lap DOS extender (several versions). 

Each of these DOS extenders use their own memory management mechanisms
unless they find a memory mannager in memory already, in which case they 
defer to the memory manager (QEMM or some other manager) for basic 
allocation of memory via a set of calls called VCPI. (DPMI is a more
recent system, with better facilities, but not all the DOS extenders know 
about it).

Unfortunately, because the DOS extender within the VL 4.1 tools predates
the VCPI stuff, it always does its own low level stuff, and does not
communicate at all with other DOS extenders (if there is no shared memory
manager in memory), and communicates just barely with the older versions
of QEMM (and as far as I can tell, not with the more recent versions). 

If you were just loading and running each program separately, you wouldn't
see any problems. Unfortunately several programs need to spawn other
programs, the most obvious one is XDM and XMAKE, but also XDE, XDELAY,
WORKVIEW, and others if you shell out to DOS, and most unfortunately, the
WIR2XNF program which while being a Xilinx program (with a DOS extender
linked in), may have to make calls to CHECK, which is part of the
Viewlogic kit that does not use compatible DOS extenders. 
So you can have a worst case situation that might look like:
XDM -> XMAKE -> WIR2XNF -> CHECK

So if you don't have a memory manager to co-ordinate stuff, the last call
above will bring your system down as the same memory can be allocated to
multiple programs. With QEMM in there, when CHECK asks for memory, you
may be lucky, and it doesn't get memory already in use by the other three
programs.

You may also be able to get success with himem and emm386 (you would need
both), but I don't think I have ever made it work. VL 4.1 definitely will
not work in a Windows DOS box, although the Xilinx programs (most recent
versions) will. The more recent version of VL software from Xilinx is the
ProSeries, and it is so bad (the user interface), that it is easy to
understand why so many expierenced users stick with the old VL 4.1 with
DOS, inspite of the memory manager hassels. Of course, once you have it
working (i.e. QEMM version, with functional command line), then the system
is quite useable and one can be quite productive.

>
>The obvious answer (upgrading to a Windows version of all this) is not
>on because I have tried it, and the DOS version is far better.
>
>Peter.

I have the same expierence. The latest stuff from Viewlogic under NT looks
fairly good, but the Xilinx tools arent there yet.

Philip.

Article: 3976
Subject: Re: INDUSTRY GADFLY: EDA Goes OJ
From: jcooley@world.std.com (John Cooley)
Date: Wed, 28 Aug 1996 14:54:42 GMT
Links: << >>  << T >>  << A >>
Steven R. Eckert <eckert@netcom.com> wrote:
>I wonder about the "courts as competent" numbers. Precisely how was the
>question asked? You seem to equate granting the injunction with seeing
>the courts as competent... or at least you indicate that others might.
>Did I read that wrong?


Steve, here are the two question exactly as worded.  They were separate;
that is, I didn't interlink them.

  1.) "As an engineer, I believe that the American legal system is generally
       capable of rendering justice in technically complex lawsuits."
       Please answer TRUE or FALSE:___________

  2.) "As an engineer, if I were the judge in the Cadence/Avant! lawsuit,
       I ( WOULD / WOULD NOT ) grant Cadence's Sept. 11 request for an
       injuction to prevent the further sales of Avant! products that are
       alleged to contain Cadence technology."  Please choose WOULD or
       WOULD NOT:____________________

There were more questions about what engineers used as sources of info on
the case and how the case effected their views about doing future business
with Cadence, Avant!, and other P&R vendors that followed these two.  That
data point (concerning how EDA vendors and EDA users saw the courts) was
based on responses from just these two question (above) though.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3977
Subject: DO I REALLY NEED A XCHECKER CABLE?
From: sjadam@trog.dra.hmg.gb (The Vincer)
Date: 28 Aug 1996 15:45:09 GMT
Links: << >>  << T >>  << A >>
I'm currently evaluating the Xilinx tool set with a 60-day
evaluation kit and I've reached a point where I want to 
program a XC4010 in serial slave mode. I have read that the
XChecker command sends the bitstream to a serial port which
is (in my case) a RS-232 port, however, I presume that the
FPGA accepts TTL data and the XChecker cable performs a 
RS-232/TTL conversion (please correct me if I'm wrong). My 
problem is that I don't have an XChecker or XDownload cable
and I don't have time to procure one, therefore I wonder
if I can make up a cable to do the job. Can this be done 
and if so what does it entail?
I'm further confused by the fact that Xilinx documentation
always shows the computer port as 9-way with a STRB and
D0 - D7 data bits with no reference as to how this maps to 
a 25-way RS-232 interface.
So the question is do I really need an XChecker cable and 
if not where do I begin?

Thanks in advance,

T.V.

Article: 3978
Subject: Re: USB Host Core for FPGA/Gate Array
From: Ray Andraka <randraka@ids.net>
Date: Wed, 28 Aug 1996 10:55:49 -0700
Links: << >>  << T >>  << A >>
Scott Kroeger wrote:
> 
> Hi All,
> 
> Do any of you know of a USB host interface (UHCI) design available for
> an FPGA (any vendor will do)?  I am aware of an Actel function block
> that fits in a mid-size 3200DX part (but they don't say which part and
> the two central parts in the family are 10K and 20K gates, quite a
> difference).
> I do believe Xilinx has a USB core either available or available within 
the next few weeks. I don't recall whether it was one of their free 
reference designs or a Logicore (you pay for it) design.  The paid for 
cores are very reasonably priced considering the design time you'd incur 
by designing it yourself,  and are tested designs.  The reference designs 
are intended as a guide to doing your own design.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
mailto:randraka@ids.net
http://www.ids.net/~randraka/
 
The Andraka Consulting Group is a digital hardware design firm 
specializing in high performance FPGA designs.  Services include 
complete design, development, simulation, and integration of these 
devices and the surrounding circuits.  We also evaluate,troubleshoot, 
and improve existing designs. Please call or write for a free 
brochure or visit our web site.
Article: 3979
Subject: Re: INDUSTRY GADFLY: EDA Goes OJ
From: Paul Micheletti <paul.micheletti@sandiegoca.ncr.com>
Date: Wed, 28 Aug 1996 12:17:30 -0700
Links: << >>  << T >>  << A >>
John Cooley replied to his own posting:
> 
> John Cooley <jcooley@world.std.com> wrote:
> >The biggest surprise came when I later compiled the 36 additional responses
> >from EDA employees.  This group was three times as likely (42 percent versus
> >the EDA users' 13 percent) to grant Cadence's injunction.  And EDA makers
> >were twice as likely (53 percent vs. 27 percent) to see the courts as
> >competent -- which helps explain why the EDA industry is so litigious!
> 
> This result from the survey still kind of stumps me.  Why are EDA vendors
> significantly more legalistic than their customers?  I can't seem to figure
> this one out.  Any insights anyone?

I think this is the NIMBY factor in action.  Many people that don't like
litigation will immediately start being litigious when something close
and dear to them is threatened.  I think that the EDA industry would 
naturally react this way towards a suit in their field.  I highly doubt
that they would have reacted with such a large deviation from non-EDA
folks if the lawsuit in question involved a Defense contractor (or another
highly technical subject) instead of an EDA company.
Article: 3980
Subject: Re: DO I REALLY NEED A XCHECKER CABLE?
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Wed, 28 Aug 1996 15:47:37 -0500
Links: << >>  << T >>  << A >>
The Vincer wrote:
> 
> I'm currently evaluating the Xilinx tool set with a 60-day
> evaluation kit and I've reached a point where I want to
> program a XC4010 in serial slave mode. I have read that the
> XChecker command sends the bitstream to a serial port which
> is (in my case) a RS-232 port, however, I presume that the
> FPGA accepts TTL data and the XChecker cable performs a
> RS-232/TTL conversion (please correct me if I'm wrong). My
> problem is that I don't have an XChecker or XDownload cable
> and I don't have time to procure one, therefore I wonder
> if I can make up a cable to do the job. Can this be done
> and if so what does it entail?
> I'm further confused by the fact that Xilinx documentation
> always shows the computer port as 9-way with a STRB and
> D0 - D7 data bits with no reference as to how this maps to
> a 25-way RS-232 interface.
> So the question is do I really need an XChecker cable and
> if not where do I begin?


The fancy XChecker cable does much more than level conversion (there's a
Xilinx XC3020 in it I think).  It also does protocol conversion.

The following is a wiring diagram for a XChecker compatible PC parallel
port cable that may configure an XC4000 (I've only used it on XC3000 and
don't remember the difference in serial configuration between the two
families).

Below the wiring diagram is a short program that downloads an intel .mcs
format hexfile via the cable (I used QuickC). 

Hope this helps,
Scott 

/*
   A simple program to download intel hex format Xilinx bitmap files to
   Xilinx devices in slave serial mode from the PC parallel port (LPT1).
   
   Scott Kroeger Copyright 1989

  Wiring:

	LPT Port Pin	Port Name	Xilinx Pin
	2				D0----------DIn
	3				D1----------CClk
	6				D4----|<----*Prog/Done
	13				SelectIn----*Prog/Done
					
	Note: -|<- = Schottky diode.

*/

#include <stdio.h>
#include <ctype.h>
#include <fcntl.h>
#include <conio.h>

main(argc,argv)

char *argv[];
int argc;

{
	FILE *in;
	int doReset;

	printf("Xilinx downloader version 1.0\n" );

	if (argc < 2) {
		printf("correct usage is: download infile\n");
		exit(1);
	}

	in = fopen (argv[argc-1],"rt");
	if(in == NULL){
		printf("can't open input file: %s\n",argv[argc-1]);
		exit (1);
	}

	doReset=1;
	if( strstr(argv[1],"-r") ) doReset = 0;

	download(in,doReset);

	fclose(in);
	return (0);
}

download(in,doReset)
FILE *in;
int doReset;
{
	register int c,byteCount;
	outp(0x378,0x03); /* assert prog */
	if(doReset){
		printf("Reset the device and press a key when ready.\n");
		while (kbhit()==0);
	}
	outp(0x378,0x13); /* release prog */
	if (inp(0x379) & 0x10) {
		printf("Done did not stay low, loading stopped.\n");
	}
	getc(in);   /* discard first record */
	while ((c=getc(in)) != EOF){
		if(c == ':') {
			if(byteCount = GetByte(in)){
				downloadRecord(byteCount,in);
			}
		}
	}
	if (inp(0x379) & 0x10)
		printf("Load Done.\n");
	else
		printf("Done did not go high, bad load.\n");
}

downloadRecord(byteCount,in)
FILE *in;
int byteCount;
{
	int a;
	GetByte(in);    /* discard load address and record type */
	GetByte(in);
	GetByte(in);

	for(;byteCount>0;byteCount--){
		SendByte(GetByte(in));
	}
}

GetByte(in)
FILE *in;
{
	int     b,temp;
	temp = getc(in);
	b=toupper(temp)-'0';
	if (b > 9) b-=7;
	temp=b<<4;

	b = getc(in);
	b=toupper(b)-'0';
	if (b > 9) b-=7;
	b=b+temp;
	return(b);
}

SendByte(byte)
int byte;
{
	int bit;

	for (bit=0;bit<=7;bit++) {
		disable();
		if(byte & 1) {
			outp(0x378,0x11); /* Data = 1, CClk = 0 */
			outp(0x378,0x11); /* waste time to avoid overruns */
			outp(0x378,0x13); /* Data = 1, CClk = 1 */
			outp(0x378,0x13);
		}
		else {
			outp(0x378,0x10); /* Data = 0, CClk = 0 */
			outp(0x378,0x10);
			outp(0x378,0x12); /* Data = 0, CClk = 1 */
			outp(0x378,0x12);
		}
		enable();
		byte = byte >> 1;
	}
}
Article: 3981
Subject: Re: DO I REALLY NEED A XCHECKER CABLE?
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Wed, 28 Aug 1996 15:49:21 -0500
Links: << >>  << T >>  << A >>
The Vincer wrote:
> 
> I'm currently evaluating the Xilinx tool set with a 60-day
> evaluation kit and I've reached a point where I want to
> program a XC4010 in serial slave mode. I have read that the
> XChecker command sends the bitstream to a serial port which
> is (in my case) a RS-232 port, however, I presume that the
> FPGA accepts TTL data and the XChecker cable performs a
> RS-232/TTL conversion (please correct me if I'm wrong). My
> problem is that I don't have an XChecker or XDownload cable
> and I don't have time to procure one, therefore I wonder
> if I can make up a cable to do the job. Can this be done
> and if so what does it entail?
> I'm further confused by the fact that Xilinx documentation
> always shows the computer port as 9-way with a STRB and
> D0 - D7 data bits with no reference as to how this maps to
> a 25-way RS-232 interface.
> So the question is do I really need an XChecker cable and
> if not where do I begin?


The fancy XChecker cable does much more than level conversion (there's a
Xilinx XC3020 in it I think).  It also does protocol conversion.

The following is a wiring diagram for a XChecker compatible PC parallel
port cable that may configure an XC4000 (I've only used it on XC3000 and
don't remember the difference in serial configuration between the two
families).

Below the wiring diagram is a short program that downloads an intel .mcs
format hexfile via the cable (I used QuickC).

If you use the program, watch out for the enable() and disable() calls. 
Another newsgroupie discovered an error in my original program which was
fixed by the interrupt calls.  I just patched them back into my listing
but never recompiled the program, so I don't know if I typed everything
in correctly. 

Hope this helps,
Scott 

/*
   A simple program to download intel hex format Xilinx bitmap files to
   Xilinx devices in slave serial mode from the PC parallel port (LPT1).
   
   Scott Kroeger Copyright 1989

  Wiring:

	LPT Port Pin	Port Name	Xilinx Pin
	2				D0----------DIn
	3				D1----------CClk
	6				D4----|<----*Prog/Done
	13				SelectIn----*Prog/Done
					
	Note: -|<- = Schottky diode.

*/

#include <stdio.h>
#include <ctype.h>
#include <fcntl.h>
#include <conio.h>

main(argc,argv)

char *argv[];
int argc;

{
	FILE *in;
	int doReset;

	printf("Xilinx downloader version 1.0\n" );

	if (argc < 2) {
		printf("correct usage is: download infile\n");
		exit(1);
	}

	in = fopen (argv[argc-1],"rt");
	if(in == NULL){
		printf("can't open input file: %s\n",argv[argc-1]);
		exit (1);
	}

	doReset=1;
	if( strstr(argv[1],"-r") ) doReset = 0;

	download(in,doReset);

	fclose(in);
	return (0);
}

download(in,doReset)
FILE *in;
int doReset;
{
	register int c,byteCount;
	outp(0x378,0x03); /* assert prog */
	if(doReset){
		printf("Reset the device and press a key when ready.\n");
		while (kbhit()==0);
	}
	outp(0x378,0x13); /* release prog */
	if (inp(0x379) & 0x10) {
		printf("Done did not stay low, loading stopped.\n");
	}
	getc(in);   /* discard first record */
	while ((c=getc(in)) != EOF){
		if(c == ':') {
			if(byteCount = GetByte(in)){
				downloadRecord(byteCount,in);
			}
		}
	}
	if (inp(0x379) & 0x10)
		printf("Load Done.\n");
	else
		printf("Done did not go high, bad load.\n");
}

downloadRecord(byteCount,in)
FILE *in;
int byteCount;
{
	int a;
	GetByte(in);    /* discard load address and record type */
	GetByte(in);
	GetByte(in);

	for(;byteCount>0;byteCount--){
		SendByte(GetByte(in));
	}
}

GetByte(in)
FILE *in;
{
	int     b,temp;
	temp = getc(in);
	b=toupper(temp)-'0';
	if (b > 9) b-=7;
	temp=b<<4;

	b = getc(in);
	b=toupper(b)-'0';
	if (b > 9) b-=7;
	b=b+temp;
	return(b);
}

SendByte(byte)
int byte;
{
	int bit;

	for (bit=0;bit<=7;bit++) {
		disable();
		if(byte & 1) {
			outp(0x378,0x11); /* Data = 1, CClk = 0 */
			outp(0x378,0x11); /* waste time to avoid overruns */
			outp(0x378,0x13); /* Data = 1, CClk = 1 */
			outp(0x378,0x13);
		}
		else {
			outp(0x378,0x10); /* Data = 0, CClk = 0 */
			outp(0x378,0x10);
			outp(0x378,0x12); /* Data = 0, CClk = 1 */
			outp(0x378,0x12);
		}
		enable();
		byte = byte >> 1;
	}
}
Article: 3982
Subject: RAM inside FLEX 10k
From: janoss@vcd.hp.com (Janos Szamosfalvi)
Date: 28 Aug 1996 22:28:06 GMT
Links: << >>  << T >>  << A >>
Does anyone know the speed of the RAM (real life) that can 
be implemented using a FLEX 10K device?    Also, is there 
any extra routing requirement?  (aside from the needed data/
addr/write/read/oe/etc. connections)   Anything else I should 
be aware of?

Thanks,
	Janos

Article: 3983
Subject: DES in Xilinx
From: erc@nai.net (Ed Caceres)
Date: 28 Aug 1996 23:40:31 GMT
Links: << >>  << T >>  << A >>
HI!

Does anyone know of a Xilinx design which implements DES, and preferably
triple-DES in hardware?

I know it's not the strongest - but this application requies this crypto
method specifically.

TIA,
Ed C.



Article: 3984
Subject: Re: Anyone know about Viewlogic v4 with QEMM?
From: ft63@dial.pipex.com (Peter)
Date: Thu, 29 Aug 1996 15:22:07 GMT
Links: << >>  << T >>  << A >>
Philip,

Thank you for such a detailed explanation.

>Each of these DOS extenders use their own memory management mechanisms
>unless they find a memory mannager in memory already, in which case they 
>defer to the memory manager (QEMM or some other manager) for basic 
>allocation of memory via a set of calls called VCPI.

One general comment I think one can make is that *no* DOS extender
dated 1992 or earlier will work in a Windows DOS box, and this
includes the 1991-dated extenders (Rational & Phar Lap) used by the X.
DOS kit.

It is curious that the current XACT6 DOS kit runs *much* faster in a
DOS box (except PPR which is of course entirely CPU-bound) than under
straight DOS 6.2. It is as if XMAKE (or whatever) disabled SMARTDRV
and set BUFFERS=1 while running :-> The HD is really getting thrashed.

>You may also be able to get success with himem and emm386 (you would need
>both), but I don't think I have ever made it work. 

I have made it work in a quick limited test, about 1 year ago.

>The more recent version of VL software from Xilinx is the
>ProSeries, and it is so bad (the user interface), that it is easy to
>understand why so many expierenced users stick with the old VL 4.1 with
>DOS, inspite of the memory manager hassels. 

I had PRO on loan for a week (c. 1 year ago) and sent it back. It was
not too bad as far as Windows-based schematic entry apps go (most are
truly awful, presumably written by people who never had to draw
schematics) but it was a far cry productivity-wise from VL4.1, even
after spending 2-3 days with it full-time.

>I have the same expierence. The latest stuff from Viewlogic under NT looks
>fairly good, but the Xilinx tools arent there yet.

The NT tools were announced in a Xilinx seminar in 1993, as
"imminent"!

Peter.
Article: 3985
Subject: Re: DES in Xilinx
From: ft63@dial.pipex.com (Peter)
Date: Thu, 29 Aug 1996 15:22:18 GMT
Links: << >>  << T >>  << A >>

You would need a sizeable FPGA for this, especially as the S-boxes
have 6 inputs, and the CLBs have only 5 (how inconvenient!).

You will need a means of converting the S-boxes into logic or boolean
equations, which is a pain because they don't minimise (it would be a
pretty weak algorithm if they did minimise). Else you can possibly
implement them using XC4k RAM, and load them from the Host CPU's
firmware.

I have never actually done this, but when I looked at this problem a
few years ago I concluded that the best way to do the S-boxes was
using an external EPROM. The rest of the algorithm then becomes quite
easy.

However, unless you need speed, you will find it quicker (should take
~3 days) to implement DES in a single-chip microcontroller, and treat
that as your black-box "co-processor". Using e.g. a H8/325 you should
get ~5000 bytes/sec and at about $13 (OTP part, 100+) this is a lot
cheaper than the required size FPGA. And you can very much improve on
this speed if you are clever and collapse parts of the algorithm
together. I don't know how to do this but I know many people have done
it, in PC (80x86) implementations.

Peter.
Article: 3986
Subject: Re: INDUSTRY GADFLY: EDA Goes OJ
From: atg@nic.com (ATG Technology)
Date: 29 Aug 1996 12:53:57 -0400
Links: << >>  << T >>  << A >>
Paul Micheletti <paul.micheletti@sandiegoca.ncr.com> writes:

>John Cooley replied to his own posting:
>> 
>> This result from the survey still kind of stumps me.  Why are EDA vendors
>> significantly more legalistic than their customers?  I can't seem to figure
>> this one out.  Any insights anyone?

>I think this is the NIMBY factor in action.  Many people that don't like
>litigation will immediately start being litigious when something close
>and dear to them is threatened.  I think that the EDA industry would 
>naturally react this way towards a suit in their field.  I highly doubt
>that they would have reacted with such a large deviation from non-EDA
>folks if the lawsuit in question involved a Defense contractor (or another
>highly technical subject) instead of an EDA company.

I (as an EDA person) feel similarly.  They are sensitive to a perceived
injustice that strikes close to home.  But notice the way they lean.
Those in this field seem to recognize the feasibility of the Cadence
claims.  If they thought that it was a case of a "big fish" trying to
squash the competition - another sensitive issue - the reaction would have 
been quite different.  Most EDA companies are much smaller than the
average electronics company (their customers), so the average employee
is closer to the business issues.
Disclaimer:  I work in EDA but have no connection to either company
and no inside knowledge of the situation.

--
Sean P. Morley                                (tel) 201-236-3635
VP Product Engineering                        (fax) 201-236-3655
ATG Technology, Inc.                          smorley@atgtech.com

Article: 3987
Subject: Viewlogic to Synopsys VHDL ?
From: schmitt <schmitt@informatik.hu-berlin.de>
Date: Thu, 29 Aug 1996 18:20:23 +0100
Links: << >>  << T >>  << A >>
Hi everyone.
I want to reuse parts of an existing XC4000 design (Viewlogic)
with the FPGA Compiler 3.4 by Synopsys.
I think it should be possible by reading a postroute XNF file
with XNF Reader.
My problem is:
Because of using only parts of the design there some unconnected
signals which will be connected to the new design parts later. 
Therefore I need ports on these signals. 
But XNF Reader produces only ports for I/O pads.

Does anybody know how to infer ports on internal signals? 

I would appreciate any comments to this mail:

schmitt@informatik.hu-berlin.de

Article: 3988
Subject: Re: USB Host Core for FPGA/Gate Array
From: waynet@goodnet.com (Wayne Turner)
Date: Thu, 29 Aug 96 18:02:36 GMT
Links: << >>  << T >>  << A >>
Virtual Chips (www.vchips.com) has USB cores and test suites in synthesizable 
Verilog and VHDL.  They are part of the Altera Megafunctions Partners Program 
and can optimize for Altera architecture on MOST of their designs.  Check the 
web site and good luck...

Wayne Turner


In article <3223BDD5.5E7@mei.com>, Scott.Kroeger@mei.com wrote:
>Hi All,
>
>Do any of you know of a USB host interface (UHCI) design available for
>an FPGA (any vendor will do)?  I am aware of an Actel function block
>that fits in a mid-size 3200DX part (but they don't say which part and
>the two central parts in the family are 10K and 20K gates, quite a
>difference).
>
>I've not seen a stand alone host interface ship (for non PCI, non intel
>CPU) yet.  If you know of an off-the-shelf stand alone host controller
>with a simple CPU bus interface, please let me know.
>
>I'd also appreciate any information on approximate gate count
>implementations of the USB host interface.
>
>Also, does anybody know of a peripheral side USB controller other than
>Intel's 82930 and the impending Atmel part?
>
>Thanks,
>Scott
Article: 3989
Subject: WTB: Configurable computer??
From: muliani <103350.1222@CompuServe.COM>
Date: 29 Aug 1996 20:59:16 GMT
Links: << >>  << T >>  << A >>
         Hi, I want to buy the configurable computing hardware/
development toolkit with the following features:
	1. The programmer/OS can order several ALU and determine
            the type of ALU.
        2. The programmer/OS can determine the Cross Bar connection/
           configuration.
We want to write kernel/driver for such hardware for a new advance
parallel portable O/S that can run on multiple types of CPU within
a single system. The same application can run on different types
of platform and system configuration without re-compilation.
           Is there such commercial hardware/system for general
purpose "REAL LIFE" applications?
Thank you very much in advance for the reply
Best regards
MULIANI
-- 
		
Article: 3990
Subject: Generic FPGA toolkits for PC
From: Deepak Tripathi <Deepak_Tripathi@ccm.sc.intel.com>
Date: Thu, 29 Aug 1996 15:28:01 -0700
Links: << >>  << T >>  << A >>
Hello All,
This is possibly a FAQ:
How do I go about getting myself a generic fpga toolkit (PC/Windows NT)?
This is purely for non-commercial purposes and hence the price tag has
to be very attractive :-). I would defn. like to get a high-quality 
toolkit but I obviously need information on the kind of trade-offs I'd 
have to make (or be forced to make as would most likely be the case)
if I don't intend to part with a lot of cash. Also is it too unrealistic
to expect a completely generic toolkit that can target a variety of fpga 
families in the bargain basement?

Is there a web-site/archive where I might find relevant information? If
any of you have experience/opinions to share, that'll  be very welcome
as well.

Thanks in advance, 

Deepak "How cheap can I get, that's the question" Tripathi.

Deepak_Tripathi@ccm.sc.intel.com

NOTE: The opinions expressed are entirely my own and do not reflect
those of my employers.
Article: 3991
Subject: HELP:preserve state signal syntax in Exemplar .ctr file
From: courtrig@syr.lmco.com (Glenn Courtright)
Date: 29 Aug 1996 22:30:29 GMT
Links: << >>  << T >>  << A >>

Can anyone show me the syntax for preserving a state signal in
an Exemplar .ctr file?

Article: 3992
Subject: Re: DES in Xilinx
From: gregor.glawitsch@utimaco.co.at (Gregor Glawitsch)
Date: 30 Aug 1996 07:03:15 GMT
Links: << >>  << T >>  << A >>
In article <502ldf$dt0@a3bsrv.nai.net>, erc@nai.net (Ed Caceres) says:
>Does anyone know of a Xilinx design which implements DES, and preferably
>triple-DES in hardware?
>
>I know it's not the strongest - but this application requies this crypto
>method specifically.

Take a look at the LUCID Technologies (was AT&T) ORCA FPGAs...
They are MUCH better suited to DES than XILINX FPGAs.
We figured out that we would get by with a 10x10 or at most a 12x12
ORCA FPGA.
Yes, S-Boxes can be done internally in an ORCA.

Hope that helps.

Gregor Glawitsch
Utimaco Safe Concept GmbH
Linz, Austria
Gregor.Glawitsch@utimaco.co.at
Article: 3993
Subject: VHDL/VERILOG SIMULATORS
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 30 Aug 1996 08:40:58 -0400
Links: << >>  << T >>  << A >>
I am starting the test vector and simulation phase of an ASIC design. I 
am currently using VHDL. I would like to hear some pros/cons of VHDL vs. 
VERILOG. Also I would like to hear any recommendations and or comments 
about simulators. I currently have MODEL TECHNOLOGY SIMULATOR. I have 
heard some good things about FRONTLINE, which is a VERILOG simulator. 
Has anyone out there had any experience with using a verilog simulator 
on VHDL code? Any other simulation comments would also be appreciated. 
This newsgroup is great in that it allows us all to learn from each 
others experiences. So please feel free in sending me any experiences 
about the above subjects.


Thank You in Advance,

Richard Schwarz
Article: 3994
Subject: Re: Anyone know about Viewlogic v4 with QEMM?
From: eteam@aracnet.com (bob elkind)
Date: Fri, 30 Aug 1996 14:31:38 +0100
Links: << >>  << T >>  << A >>
Philip Freidin (fliptron):

<lots snipped>

= You may also be able to get success with himem and emm386
= (you would need both), but I don't think I have ever made
= it work. VL 4.1 definitely will not work in a
= Windows DOS box, although the Xilinx programs (most recent
= versions) will. The more recent version of VL software
= from Xilinx is the ProSeries, and it is so bad (the user
= interface),

I OBJECT to this statement!  There's lots more to complain
about than the ProSeries user interface!  (oops, you can't
get it anymore, so I'll keep quiet... but it *was* pretty rank!).

= that it is easy to understand why so many
= experienced users stick with the old VL 4.1 with
= DOS, inspite of the memory manager hassels. Of course,
= once you have it working (i.e. QEMM version, with
= functional command line), then the system
= is quite useable and one can be quite productive.
= 
= >The obvious answer (upgrading to a Windows version of all
= >this) is not on because I have tried it, and the DOS
= >version is far better.
= >
= >Peter.
= 
= I have the same experience. The latest stuff from Viewlogic
= under NT looks fairly good, but the Xilinx tools arent
= there yet.
= 
= Philip.

The underlying problem here is that there's a mess in the PC
based CAD SW market.  W95 and NT didn't *solve* all the
problems, they resulted in a proliferation (by two, mutually
incompatible) of run-time memory management (OS) architectures,
compounding the problems of an already-fragmented "development
target" for CAD SW developers.  What a mess!  Some or most
of these problems would functionally disappear if not for the
need for license/copy protection (e.g. dongles)!  Talk about
the tail wagging the dog!

Let's see... there is/was

DOS and manual overlays
DOS with VCPI
DOS with DPMI
Windows 3 on top of DOS, running DOS shells
Win95 (but not NT)
NT (but not Win95)

Anybody remember the good old days of DOS/Win tools where only
certain video cards had decent support from certain tools
vendors?  Remember the Logitech 3-button mouse that came with
ViewLogic's tools?  Augggghhhh!

I'm not alone in having to keep NT, W95, and DOS/WfW boot
environments on my development system.  I worked for a big
company where the MIS guys couldn't understand why everyone
couldn't just use the same hardware and autoexec/config.sys
as everybody else...

And let's not get started on why some companies we know
charge double for the same SW and capabilities if it runs on
an NT machine instead of a W95 machine!

Phil (and friends), you got me started.   Grrrrrrrr!

Regards,

Bob Elkind

**************************************************************************
Bob Elkind                mailto:eteam@aracnet.com            CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************
Article: 3995
Subject: Looking for s/w to generate test vectors
From: aweir@spherecom.com (Alan Weir)
Date: Fri, 30 Aug 1996 15:12:15 GMT
Links: << >>  << T >>  << A >>
Does anyone know of a software package to generate test vectors for
simple PALS (22V10 etc). I'm using Warp 2 for the design and I don't
want to have to hand code the vectors into the Jedec file.

-- Alan

Article: 3996
Subject: Re: DES in Xilinx
From: sson@hawaii.et.byu.edu (Stacey Son)
Date: 30 Aug 1996 11:28:38 -0600
Links: << >>  << T >>  << A >>
>>>>> "Peter" == Peter  <ft63@dial.pipex.com> writes:

    Peter> You would need a sizeable FPGA for this, especially as the
    Peter> S-boxes have 6 inputs, and the CLBs have only 5 (how
    Peter> inconvenient!).

    Peter> You will need a means of converting the S-boxes into logic
    Peter> or boolean equations, which is a pain because they don't
    Peter> minimise (it would be a pretty weak algorithm if they did
    Peter> minimise). Else you can possibly implement them using XC4k
    Peter> RAM, and load them from the Host CPU's firmware.

    Peter> I have never actually done this, but when I looked at this
    Peter> problem a few years ago I concluded that the best way to do
    Peter> the S-boxes was using an external EPROM. The rest of the
    Peter> algorithm then becomes quite easy.

I implimented DES on XC3090 a few years ago.  Although, the S-boxes
did take a lot of resources a full DES design did fit on the 3090.  In
fact, the S-BOXes of my DES design took 136 CLBs or about 43% of a
3090; the whole design took 295 CLBs or about 92% of a 3090.  I put a
copy of my report for the project on
ftp://ftp.et.byu.edu/papers/desfpga.ps, BTW.

Other papers you may want to look at:

ftp://research.att.com/dist/mab/keylength.{ps,txt}.  "Minimal Key
Lengths for Symmetric Ciphers to Provide Adequate Commercial Security"
by Matt Blase, Whitfield Diffie, Ronald Rivest, Bruce Schneier,
Tsutomu Shimomura, Eric Thompson, and Michael Wiener.  Eric Thompson,
an associate of mine, used the data I presented in the paper above as
a basis for his contribution to the paper.  Other authors, namely
Shimomura, claimed it was possible to do "30 million DES keys per
second" using a single AT&T ORCA part that costs about "$200".

http://www.cs.berkeley.edu/~iang/isaac/hardware.html.  "Architectural
considerations for cryptanalytic hardware" by Ian Goldberg and David
Wagner.  The authors implimented DES using Altera FLEX8000's and show
how the S-BOXes can be implimented using MUXes (the same way I did
it).  Very well written paper.

"Efficient DES key search" Michael J. Wiener. (Crypto '93, I believe)
The author presents a fully parallel design for DES.  Although
intended for an ASIC, a lot of the design applies for FPGA's as well.

    Peter> However, unless you need speed, you will find it quicker
    Peter> (should take ~3 days) to implement DES in a single-chip
    Peter> microcontroller, and treat that as your black-box
    Peter> "co-processor". Using e.g. a H8/325 you should get ~5000
    Peter> bytes/sec and at about $13 (OTP part, 100+) this is a lot
    Peter> cheaper than the required size FPGA. And you can very much
    Peter> improve on this speed if you are clever and collapse parts
    Peter> of the algorithm together. I don't know how to do this but
    Peter> I know many people have done it, in PC (80x86)
    Peter> implementations.

I was interested in using FPGAs for brute-force cryptanalysis of DES.
Therefore, the some of the numbers in the paper are presented in terms
of keys exhausted/second.  Most the data I found published, however, was
presented in terms of DES blocks/second.  There is a difference here
since in software implimentations need to generate the schedule
serially for every key tried and the key schedule can be a significate
portion of the time (some of this time can be reduce using "key
difference tables" and counting in "gray codes").  The FPGA
implimentation, on the other hand, computes the key schedule in
parallel with DES block.  Nevertheless, a single FPGA is about 100
times faster than the best software implimentation on the fastest
workstations at the time and, most likely, a 1000 times faster if you
add the overhead of doing the key schedule for every DES block
(i.e. using for brute-force cryptanalysis).

    Peter> Peter.

-- 
-Stacey D. Son.
 stacey@son.org
Article: 3997
Subject: Announcement: public release of embedded system design software
From: luciano@ic.EECS.Berkeley.EDU (Luciano Lavagno)
Date: 31 Aug 1996 02:37:58 GMT
Links: << >>  << T >>  << A >>
Dear colleague,
it is our pleasure to announce the public availability the 
POLIS co-design environment for control-dominated embedded systems.

POLIS offers an integrated interactive environment for specification,
co-simulation, formal verification, and synthesis of embedded systems
implemented as a mix of hardware and software components.

Most of the information about POLIS, including pointers to source and object
code (for various CPUs and OSes) is available at our WEB site
http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/abstract.html

The software is available under the usual copyright rules of the 
University of California
(see also http://www-cad.eecs.berkeley.edu:80/copyright.html).

If you are interested, but do not have WEB access, please contact us via e-mail
at polis@ic.eecs.berkeley.edu.

Best regards,
		the POLIS team
(currently including Felice Balarin, Massimiliano Chiodo, Alberto Ferrari, 
Paolo Giusto, Harry Hsieh, Attila Jurecska, Marcello Lajolo, Luciano Lavagno, 
Claudio Passerone, Claudio Sansoe', Ellen Sentovich, Marco Sgroi, Kei Suzuki, 
Bassam Tabbara, Reinhard von Hanxleden, and Alberto Sangiovanni-Vincentelli)
-- 
Luciano Lavagno           +39-11-564-4150 (fax 4099)          lavagno@polito.it
Dip. di Elettronica, Politecnico, C. Duca degli Abruzzi 24, 10129 Torino, ITALY
Aug 96 - Dec 96:    +1-408-428-5326 (fax +1-510-486-0205)   luciano@cadence.com
Cadence Berkeley Labs,   1919 Addison St. #303-304,    Berkeley - CA 94704-1144
Article: 3998
Subject: Re: Looking for s/w to generate test vectors
From: DTHIBAUL <DTHIBAUL@mailgw.sanders.lockheed.com>
Date: Sat, 31 Aug 1996 18:26:33 -0700
Links: << >>  << T >>  << A >>
Alan Weir wrote:
> 
> Does anyone know of a software package to generate test vectors for
> simple PALS (22V10 etc). I'm using Warp 2 for the design and I don't
> want to have to hand code the vectors into the Jedec file.
> 
> -- Alan

If I'm not mistaken you can save the output of your sim file and use that
as test vectors -  I haven't tried it but I'm pretty sure I remember 
reading it in the documentation - this would be a very simple way to 
create test vectors.
Article: 3999
Subject: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
From: zoltan@bendor.com.au (Zoltan Kocsi)
Date: 01 Sep 1996 04:29:13 GMT
Links: << >>  << T >>  << A >>
>Xilinx conciders their bitstream format to be a trade secret.  Only one
>company ever reverse engineered it.  Xilinx bought them.

There was an article here about a month ago which said the the bitstream
format for the 6200 is publicly available, together with all info you need
to do synthesis and P&R for the chip.
I asked the local Xilinx reps, they heard nothing about it.
Is there any truth in it ?

Zoltan
-- 
*****************************************************************************
* Zoltan Kocsi                      *    I don't believe in miracles but    *
* Bendor Research Pty. Ltd.         *    I rely on them.                    *
*****************************************************************************


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