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Messages from 4525

Article: 4525
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Nov 1996 14:26:18 -0700
Links: << >>  << T >>  << A >>
Don Husby wrote:
"A free place-and-route tool would shut down a lot of Xilinx's business"

Absolutely not, it would do the opposite, it would enhance our sales..
Xilinx makes its money from selling chips, and the easier it is for the
world to design with Xilinx chips, the better for Xilinx.
That's why we have introduced the much lower priced Foundation
shrink-wrapped software package. 
Quality, easy-to-use software that makes it easy for the novice to get
started, but also allows the power-user to utilize all the powerful
features of the chip, software that is supported by a knowledgable staff
of (Field)Applications engineers, is vitally important for the success
of our customers and for the success of Xilinx.
The revenue stream created by selling that software is a secondary
consideration and is a tiny part of Xilinx revenues. 
Obviously, the business model at Synopsys, Cadence, Mentor ( and
formerly at Neocad ) is very different.

Peter Alfke
Article: 4526
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: Brad Taylor <blt@emf.net>
Date: Fri, 08 Nov 1996 13:38:32 -0800
Links: << >>  << T >>  << A >>
Don Husby wrote:
> 
> Peter Alfke  peter@xilinx.com wrote:
> > Well, well. Some people see a conspiracy at every corner.
> > But reality is different.
> > Designing place-and-route tools is a very demanding task. We have a
> > large software R&D group who has been working for years on the
> > development of such tools, and some of you may think that they still are
> > not quite perfect :-).
> > Our developers have of course access to all the detailed chip
> > information, and Xilinx puts many millions of dollars every year into
> > the development effort.
> > I don't think we would do anybody a favor if we encouraged him ( or her
> > ) to embark on an individual, underfunded development effort in an area
> > as difficult as this.
> > Just my opinion.
> 
>   On the other hand, we have one example of a company that made the effort
> to derive the "dark secrets" of xilinx internals and wrote their own
> place and route tool.  Xilinx bought them out -- ostensibly because the
> tools were BETTER than Xilinx's own tools, but probably equally as likely
> to quash the competition.
> 
>   There are a lot of good hackers out there and they produce a lot of
> good usable software.  For example the Gnu C compiler is pretty much an
> industry standard now, it's better than much of the comptetition, and it's
> free.  There's no reason to assume that a similar effort couldn't produce a
> good place and route tool.  A free place and route tool would shut down a
> lot of Xilinx's business.  The word "conspiracy" has a lot of bad
> connotations, so maybe a better phrase might be "conservative business
> practices".


I don't think the secretive nature of Xilinx is the limit here.  It is
pretty easy to figure out the bitstream format. We've had to do a fair
amount of that to handle readback formats.  The process goes something 
like this:

1- start with a blank FPGA in the XACT editor (XDE)
2- set some feature
3- make a bit file 
4- compare the bit file to the blank bit file and note what changed
5- repeat until done.

My guess is that you could completely understand the structure of the 
bitstream in a month or so of tedious work.  The man month it might take
to figure out the bitstream is rather trivial compared to the time
required to write routing software.
-
Brad
the routing software you would need

Article: 4527
Subject: Upstate NY; Senior Engineer Wanted; FPGA; High Speed Digital
From: richard_steinman@cmagroup.com
Date: 8 Nov 1996 21:46:40 GMT
Links: << >>  << T >>  << A >>

Upstate NY; Senior Engineer; FPGA; High Speed Digital. 5+ Years Exp. Must 
have: signal processing, algorithms, high speed digital design (40-50 
MegaHertz), FPGAs, and exposure to imaging &/or sensor systems applications. 
Client using ViewLogic and Spice CAE/CAD tools. 60-70% design/detailed 
design; 30-40% systems level work.

Please refer to JO# 582RJS in your response.



Richard Steinman. 
Career Marketing Associates. 
rjs@cmagroup.com  
Richard has 15 Years Experience In Nationwide Engineering,Technical & 
Scientific Search and Placement

Article: 4528
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Nov 1996 18:06:20 -0700
Links: << >>  << T >>  << A >>
Keeping details away from a potential competitor is one small
consideration. 
More critical is the thought that dozens of underfunded developers would
create software with myriads of bugs and "features", and Xilinx would
have to support all of this, since, in the user's eye "Xilinx makes the
big bucks on chip sales".
It is very difficult to tell a potential buyer of thousands of chips,
waving a big purchase order, but having a software problem: " it's your
own fault. Our chip is o.k. You just created your own software mess. We
cannot help you, we are not even going to try". 
That's not what a customer-oriented company like Xilinx does. Instead,
we try to help. That's tough enough when our customers uses any
conceivable combination of design-entry, synthesis, and simulation
tools, running on PCs under DOS, Windows 3.1, Win95, NT, and
workstations from Sun ( two different operating systems ) hp, DEC,
IBM6000, and the list goes on.
At least, we can control the core, the partitioning, placement, and
routing software and the bitstream generation. Giving up that control
would be suicidal from a technical support point of view.
CAE vendors can tell the user politely to "get lost" if he or she
doesn't use their particular software. 
Chip vendors don't have that "luxury".

My opinion...
Peter Alfke, Xilinx Applications
Article: 4529
Subject: Electronics/ Microcontroller On-Line Electronics Resource Directory
From: Todd Peterson <tpeterson@netins.net>
Date: Fri, 08 Nov 1996 19:22:33 -0600
Links: << >>  << T >>  << A >>
Our Online Electronics Resource Directory is finally completed.  A
special thanks to all of you who send us your link suggestions.

For those of you not aware of it, we at E-LAB Digital Engineering, Inc.
have compiled a hot-linked, categorized on-line directory of sites on
the internet that are of importance to electronics designers and
engineers. We now have over 500 sites in 40 categories, ranging from
distributors to code examples to manufacturers' sites.  The directory is
FREE for all to use and there is no registration of any sort.  If you'd
like, you can even have some of your favorite links added free of charge
- just e-mail us the URL.

The directory is available at our web site at
http://www.netins.net/showcase/elab

Trust us, you WILL want to set a bookmark.

Wishing you success,

Todd Peterson
E-LAB Digital Engineering, Inc.

tpeterson@netins.net

P.S. - Those of you who recently sent us link requests, don't worry -
they will be added soon.
Article: 4530
Subject: Xilinx and cost of tools
From: Mike Ciholas <mikec@flownet.com>
Date: Sat, 09 Nov 1996 10:13:36 -0600
Links: << >>  << T >>  << A >>
>Don Husby wrote:
>
>>"A free place-and-route tool would shut down a lot of Xilinx's
>>business"
>
>Absolutely not, it would do the opposite, it would enhance our
>sales..  Xilinx makes its money from selling chips, and the
>easier it is for the world to design with Xilinx chips, the
>better for Xilinx.
>
>The revenue stream created by selling that software is a
>secondary consideration and is a tiny part of Xilinx revenues.
>
>Peter Alfke

Man, you guys sure don't act like it!  I'm sorry, but I think
you're talking the talk, but not walking the walk.  *If* you
really want more people to have the ability to design in Xilinx
chips, then you wouldn't do the following things:

1. Charge money for your in house tools.  I can understand if you
charge for software you have to license (sch, sim, ...), but I
bought the 3rd party package which has no non-Xilinx tools in
it for $2700.  Some of my customers *explicitly* request that my
designs do not include a xilinx chip since they can't justify the
cost of the tools simply for the possibility that they might want
to modify the design.  If the tools were free, this would not be
an issue.

2. The software has a dongle on it!  What the hell for?  You just
want to make sure it can't work on laptops?  That users might
suffer when they loose the damn thing or it breaks?  That it
interferes with some parallel port devices?  That it doesn't
allow the software to work under DOS emulators?  Yech...

3. You charge for maintenance of software.  Why wouldn't you want
me to have the latest software?  Haven't you guys figured out
that having all these people with old versions costs you more in
tech support than just letting everybody have the latest version?

4. And the weirdest one: charge extra for tools that can be used
on more expensive chips.  What a perverse idea.  This forces
people to work extra hard to use cheaper chips thus less revenue
for you.  This also reinforces the idea that these xilinx things
aren't all that useful since you didn't let them see the true
power!

Man, I can only imagine that you guys are so enamoured with your
market position that you feel you can do no wrong (the "Microsoft
complex").  Your post did not contain one reason *why* you should
charge for your software, are there any?

I imagine that your management is so near sighted that they
cannot see the forest for the trees.  I bet they treat "software"
as a separate "business unit".  Don't you guys understand Dilbert
at all?

Mike Ciholas                            (812) 858-1355 voice
CEDAR Technologies                      (812) 858-1360 fax
5855 Fiesta Drive                       mikec@flownet.com
Newburgh, IN 47630                      mikec@lcs.mit.edu
Article: 4531
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: brian@colloquium.co.uk (Brian Drummond)
Date: Sun, 10 Nov 1996 00:00:57 GMT
Links: << >>  << T >>  << A >>
Colin Carruthers <cc@xilinx.com> wrote:

>The Xilinx XC6200 is a fine grain SRAM FPGA optimized
>for dynamic reconfiguration.  Internal architecture and
>complete programming info can be found in the datasheet...
>
>	http://www.xilinx.com/products/fpgaspec.htm
>
And it looks good...
But when will it be available other than to beta sites?

- Brian
Article: 4532
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: zoltan@bendor.com.au (Zoltan Kocsi)
Date: 10 Nov 1996 09:29:01 GMT
Links: << >>  << T >>  << A >>
In article <3280B6EC.56BC@xilinx.com> Peter Alfke <peter@xilinx.com> writes:
>Well, well. 
>Some people see a conspiracy at every corner.
>But reality is different.
>Designing place-and-route tools is a very demanding task. We have a
>large software R&D group who has been working for years on the
>development of such tools, and some of you may think that they still are
>not quite perfect :-).
>Our developers have of course access to all the detailed chip
>information, and Xilinx puts many millions of dollars every year into
>the development effort. 
>I don't think we would do anybody a favor if we encouraged him ( or her
>) to embark on an individual, underfunded development effort in an area
>as difficult as this.
>Just my opinion.
>
>Peter Alfke

Well, as far as I understand, a P&R is in the same order of complexity to a 
good optimising compiler for a not-so-nice CPU.
Now GCC is quite good.
It's code generator is based on the instruction encoding info which is
quite the same thing as the bitstream format. Luckily, CPU manufacturers
usually release the info (not always, though, maybe those CPUs are parti-
cularly complex to write a compiler for). 

You say that you wouldn't do a favour if you encouraged someone to write a
P&R tool. Do you really mean that you just withold the info from pure 
altruism ? I find it hard to believe. On the other hand, I find it
relatively easy to believe that if the info was indeed available then
the competition on the market would significantly increase and it would 
hit your SW department as well as the current third party tool makers hard.
On the other hand, your chip department might have some extra earnings
because these tools would make your chips available for those who can't
afford to buy multi-$10K stuff or refuse to create some excess income
for the Evil Empire in order to be able to run the cheap tools (and not
being able to do anything else useful with it).

Somehow I can't swallow that you say that it's better to me not to know.
Let me know and then I'll decide if it's good to me or not.
By the way, if these tools are sooo complicated that you need decades
and many million dollars per year to develop them, why not release the info ?
Noone would even try it, would they ? Even if they would, they wouldn't have
a chance to finish it ever, so why not make them happy with this useless
piece of info ?

Also, you are the (only) one who replied me when I was asking whether the
bitstream format is public for the 6200 series. Your answer was yes, you 
even sent me the data sheet (for which I again thank you).
So, if the 6200 will not make people kill themselves, why would any other
do ?

In addition, if I knocked on your door that I was a tool maker company and I 
would be happy to pay lotsa money for the info after signing an NDA I think 
you would not care that much about my mental health.

You see, it is not a conspiracy, I think, it's just greed :-)

Zoltan

-- 
*****************************************************************************
* Zoltan Kocsi                      *    I don't believe in miracles but    *
* Bendor Research Pty. Ltd.         *    I rely on them.                    *
*****************************************************************************
Article: 4533
Subject: Re: Xilinx and cost of tools
From: no.bulk.mailing@thanks.com (Peter)
Date: Sun, 10 Nov 1996 11:44:16 GMT
Links: << >>  << T >>  << A >>
Mike,

Your message is absolutely full of good points!

>1. Charge money for your in house tools.  I can understand if you
>charge for software you have to license (sch, sim, ...), but I
>bought the 3rd party package which has no non-Xilinx tools in
>it for $2700. 

By spending a **tiny** bit of their multi-million profits, Xilinx
could develop and offer non-Viewlogic tools - with Viewlogic import
capabilities of course.

Also, of course, if Xilinx were considering to drop Viewlogic tools,
Viewlogic would drop their prices anyway.

>2. The software has a dongle on it!  What the hell for?  You just
>want to make sure it can't work on laptops?  That users might
>suffer when they loose the damn thing or it breaks?  That it
>interferes with some parallel port devices?  That it doesn't
>allow the software to work under DOS emulators?  Yech...

You forgot about running under NT, as well....

Personally, because of the dongle, I am stuck with a version of
Viewlogic which I cannot afford to upgrade, for which I have to
maintain a special DOS environment, a special 8514-emulating graphics
card (the only way to get 1024x768), a special mouse... And this is
after paying $3000 for an XACT6 upgrade.

Xilinx UK told me recently that the reason for high software pricing
is to "control the amount of support they have to do"!!

IOW, they are deliberately restricting their design-ins so their
software tech support people don't have too much work to do. Perverse.

>4. And the weirdest one: charge extra for tools that can be used
>on more expensive chips.  What a perverse idea.  This forces
>people to work extra hard to use cheaper chips thus less revenue
>for you. 

Funnily enough, despite all the hype about the 5k devices being the
most "cost effective", the simple fact is that the ancient 3k are the
ones to use, unless you are spending someone else's money, or are
really packing it in. And one can use the old APR quite well with 3k.
PPR is necessary only if one is packing a 3k tightly, or for the
bigger or later devices.

>Man, I can only imagine that you guys are so enamoured with your
>market position that you feel you can do no wrong (the "Microsoft
>complex").  Your post did not contain one reason *why* you should
>charge for your software, are there any?

There are none. They should charge some nominal amount, say $200, to
cover cost of admin. A CDROM costs about $1 to press.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 4534
Subject: Re: Xilinx and cost of tools
From: timolmst@cyberramp.net
Date: Sun, 10 Nov 1996 17:06:21 GMT
Links: << >>  << T >>  << A >>
>Personally, because of the dongle, I am stuck with a version of
>Viewlogic which I cannot afford to upgrade, for which I have to
>maintain a special DOS environment, a special 8514-emulating graphics
>card (the only way to get 1024x768), a special mouse... And this is
>after paying $3000 for an XACT6 upgrade.

Not only that, they had to change the dongle between Xact 4 and 5. I
have a lisenced version of XACT v4.2, but it is not on maintainance. I
couldn;t afford to pay Xilinx the $950 a year for the maint. contract.

>>4. And the weirdest one: charge extra for tools that can be used
>>on more expensive chips.  What a perverse idea.  This forces
>>people to work extra hard to use cheaper chips thus less revenue
>>for you. 

Not only that, it forces loyal Xilinx users to consider "the other
guys". I'm not in love with either Cypress, or Lattice, but the
cheaper tools are forcing me to take another look at them. 

Their tools are cheaper to start with; $495 for Lattice, and $99 for
Cypress. Lattice decided that they wanted our business, so they just
came out and installed their developemen system on the bosses machine
for free.

TAKE HEED XILINX. With competition like that, my boss won't even
discuss Xilinx FPGA's.

Tim Olmstead
timolmst@cyberramp.net

Article: 4535
Subject: Re: Xilinx and cost of tools
From: Erik Widding <widding@worldnet.att.net>
Date: Sun, 10 Nov 1996 13:12:16 -0500
Links: << >>  << T >>  << A >>
timolmst@cyberramp.net wrote:
> 
> Not only that, it forces loyal Xilinx users to consider "the other
> guys". I'm not in love with either Cypress, or Lattice, but the
> cheaper tools are forcing me to take another look at them.
> 
> Their tools are cheaper to start with; $495 for Lattice, and $99 for
> Cypress. Lattice decided that they wanted our business, so they just
> came out and installed their developemen system on the bosses machine
> for free.
>

Maybe Xilinx is finally starting to get the hint.  Their introductory 
package (up to 5K gate devices) including simulation and sch capture is 
$595 from Marshall.  I still don't understand why there is a gate limit, 
as I am likely to be the same burden on the tech support people whether I 
am using big parts or small ones. As I understand it, everything in the 
package is unlimited, except the place and route tool.  The part about 
this that really blows my mind, through this strategy Xilinx is ensuring 
that many of the design-ins they get will not be with their newest most 
expensive parts.  

> 
> TAKE HEED XILINX. With competition like that, my boss won't even
> discuss Xilinx FPGA's.
> 

A Xilinx sales rep said something interesting to me once.  "Software 
prices are somewhat negotiable."  I was talking to the Xilinx FAE at 
Marshall (Boston) about software one afternoon.  He mentioned that they 
would be having a three day seminar in late november.  Would I be 
interested in coming, he asked, for $500 of course.  I wasn't sure that it 
fit in with my budget or schedule, I replied.

He called me back the next day, and informed me that they would throw in 
the software package for free if I attended.  Not being one to pass up a 
good deal, I will be going.  I am interested to see what they teach, 
though I am somewhat skeptical, as I have always found little value in 
being lectured on how to use software.  Though, if it is mostly an 
architecture course, I think it will be time well spent.

Moral of the story -- xilinx is learning, maybe not fast enough ;-(, and 
it never hurts to pick up the phone and speak with a sales rep.  I would 
be willing to wager, if you were to place an order for a 100 big parts, 
software would all of a sudden become quite affordable.


Just a few thoughts,
Erik Widding


BTW, the guys at Marshall Boston are very easy to deal with.
Article: 4536
Subject: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Sun, 10 Nov 1996 19:49:48 GMT
Links: << >>  << T >>  << A >>
=============================================================================

                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

   The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems.  All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium.  Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
 
   The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop.  Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:

    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:

    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

General Chair:               A. B. Kahng (UCLA and Cadence)
Past Chair:                  G. Robins (Virginia)
Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
                             W. W.-M. Dai (UC Santa Cruz) 
                             J. Frankle (Xilinx) 
                             D. D. Hill (Synopsys) 
                             M. A. B. Jackson (Motorola) 
                             J. A. G. Jess (Eindhoven)  
                             Y.-L. Lin (Tsing Hua) 
                             C. L. Liu (Illinois)
                             M. Marek-Sadowska (UC Santa Barbara)
                             M. Sarrafzadeh (Northwestern)
                             C. Sechen (Washington) 
                             K. Takamizawa (NEC)
                             M. Wiesel (Intel) 
                             D. F. Wong (Texas-Austin) 
                             E. Yoffa (IBM)

=============================================================================

Article: 4537
Subject: Re: Xilinx and cost of tools
From: Lance Gin <c43lyg@dso.hac.com>
Date: Sun, 10 Nov 1996 17:43:48 -0800
Links: << >>  << T >>  << A >>
Mike Ciholas wrote:
> 
> Man, I can only imagine that you guys are so enamoured with your
> market position that you feel you can do no wrong (the "Microsoft
> complex").  Your post did not contain one reason *why* you should
> charge for your software, are there any?
> 

interesting points. don't forget to consider the distribution system
with which "commodity" electronics parts such as fpga's are sold
and supported.

in the asic world, one often deals only with the foundry (eg. lsi logic)
and 3rd party tool vendors (eg. mentor/cadence/synopsys). the proprietary
portion of the tools are typically given away for free. but in the fpga
world, one typically purchases tools from a middleman - the distributor
(eg. hamilton, marshall, etc.). they want a cut too, especially if
you're a fat-cat unix user!

personally, i just chalk it up to the free enterprise system which so
many of us are fond of. if you're a big customer like cisco and your
volumes are huge, i'd wager you won't pay a nickel for your xilinx tools.

so, you must convince xilinx (and the reps and distributors that
work for them) that your revenue is worth some free tools and support.
otherwise, you might have to take your business to some smaller, hungier
vendors trying to increase market share (eg. lattice, etc.).

just my opinions here ... :)

-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________
Article: 4538
Subject: Re: Async with FPGA?
From: Tim Forcer <tmf@ecs.soton.ac.uk>
Date: Mon, 11 Nov 1996 14:27:33 +0000
Links: << >>  << T >>  << A >>
Scott Kroeger wrote:
> 
> David T. Wang wrote:
> >
> > Hi, I'm looking for a way to shrink some Async circuit, has anyone done
> > any work with implementing some Async stuff with an FPGA?  I have an
> > application which needs to respond to an input within a small time period,
> > ~7 to 10 ns.  unfortunately I can't just use a fast clock, so I was
> > thinking of trying to design some Asyn stuff in an FPGA.  any comments/
> > suggestions?     Thanks.
> 
> Your question is too vague to enable a concise answer.  That said:
> 
> We've proabably all done some async logic (accidently or purposely) and
> often come to regret it......
> 
> Regards,
> Scott

For incoming signal detection it is possible to use an asynchronous
state machine.  This will run at rates determined by internal DELAYs,
not clocks.  However, the state assignment and transitions need to be
set with great care.  Also, the state machine probably has to interlock
with a synchronous one.  Since the ultimate object is normally to have
synchronised data, this is not necessarily a problem.  I've got a design
in Lattice ispLSI where a 90MHz chip reliably detects events down to 9ns
long, with a chip clock of 150Hz.

No regrets!

Tim
Article: 4539
Subject: Re: UART FOR FPGAS
From: Burke.Baumann@IAC.honeywell.com (Burke Baumann)
Date: 11 Nov 1996 17:44:16 GMT
Links: << >>  << T >>  << A >>
In article <32851219.2014429@news.u-net.com>, no.bulk.mailing@thanks.com (Peter) says:

> I really wish somebody did a proper UART, even if it had just
>the standard 2-byte buffers.
>
>
>Peter.


Peter

Version 7 of Altera's MAXPLUS II software does include several MegaCore megafunctions
including a 16450, 6402, 6850 and a 8251 uart.  These are pre-verified HDL design files. These are
included with version 7.0.  I think these must be purchased from Altera because most of them are
provided by a third party vendor.  Their "Altera Megafunction Partners Program" catalog also shows
other functions such as 6502 and 8051 microprocessors and PCI interfaces.
I have not tried any of these but I thought it might be worth checking into.

Burke
Article: 4540
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: buller@bnr.ca (Jonathan Buller)
Date: 11 Nov 1996 19:41:44 GMT
Links: << >>  << T >>  << A >>
In article <3283C951.8EB@xilinx.com>, Peter Alfke  <peter@xilinx.com> wrote:
>Keeping details away from a potential competitor is one small
>consideration. 
>More critical is the thought that dozens of underfunded developers would
>create software with myriads of bugs and "features", and Xilinx would
>have to support all of this, since, in the user's eye "Xilinx makes the
>big bucks on chip sales".
>It is very difficult to tell a potential buyer of thousands of chips,
>waving a big purchase order, but having a software problem: " it's your
>own fault. Our chip is o.k. You just created your own software mess. We
>cannot help you, we are not even going to try". 

Relating this back to the compiler/PPR analogy, I have *never* talked to
anyone at Motorola when I ran into problems with GCC, or the code I
wrote for a 68K.  I can *maybe* imagine talking to them if I had
problems interfacing to their chips, or if code that was written to
their specs did not operate as they claimed.  (If pin x was supposed to
be an input line, but but kept blowing out it's driver, or if the "add
d1,d2" instruction was modifying a4...)  Perhaps Xilinx deals with a lot
of powerful, but stupid, people who would a) blame Xilinx for problems
with other people's software, b) expect Xilinx to bail them out of those
problems, and c) expect b) to happen for free.  Perhaps the Motorola 68K
people have the same problems, I wouldn't know.

However, I did work at Dallas Semiconductor for a while and heard a few
stories about what silly things people tried to do with our DS5000 (aka
8051).  (It was not anything close to what I hear Xilinx people say
Xilinx is trying to avoid...)  Companies like Cygnus are for fixing GCC,
Motorola is for fixing 68K's.  I expect that Motorola passes most
questions they get about GCC to places like Cygnus.  In fact, if I
mis-directed a question about GCC to Motorola, I would expect them to
pass me off to another source, or say "Sorry, that's not our problem,
why don't you buy our compiler, it doesn't have a problem like that..."

Notice that this last response implies that Motorola had the foresight to
allow people to program their chips without buying their compilers and
assemblers, but have a line of those tools if you want them.  I don't
expect Xilinx to supply free software, or support stuff they have no clue
about, but I would like to be able to buy the Xilinx tools if I like, or
use someone elses if I need to for whatever reason.

>That's not what a customer-oriented company like Xilinx does. Instead,
>we try to help. That's tough enough when our customers uses any
>conceivable combination of design-entry, synthesis, and simulation
>tools, running on PCs under DOS, Windows 3.1, Win95, NT, and
>workstations from Sun ( two different operating systems ) hp, DEC,
>IBM6000, and the list goes on.

At Dallas Semiconductor, we did not have our own tools, we used Intel's
8051 assembler 8-).  When customers had problems, we said "Gee, that
source looks like it should run just fine.  Your problems do not seem to
be with our chips, but with your tools.  You may want to consider
switching tools, we use ...  but you may want to look at ...  as well."
If it was something REAL easy, we'd try to give a possible work-around,
but in general, there's only so many problems you have the ability to
solve, period.  I will grant you that we had one final out that you don't
(yet?), we could ask "Does your code work on an Intel 8051?"

>At least, we can control the core, the partitioning, placement, and
>routing software and the bitstream generation. Giving up that control
>would be suicidal from a technical support point of view.
>CAE vendors can tell the user politely to "get lost" if he or she
>doesn't use their particular software. 
>Chip vendors don't have that "luxury".

We did, nobody minded, but then again, we didn't keep the 8051 opcodes
secret either.  (OK, I think maybe one or two people minded, but they
were looking for someone to do all their one-off work for them and then
give them the tools that were used too.  People like that don't have the
money or brains to make a quantity purchase anyway.)

Jon Buller
Include disclaimers, quotes, etc.  here.  SPAM'ers may not like the
results of their actions with respect to actions taken on the e-mail
addresses contained in this post.
Article: 4541
Subject: Re: Actel Designer and Win NT 4.0
From: ecp@focus-systems.on.ca (Eric Pearson)
Date: Mon, 11 Nov 1996 20:54:07 GMT
Links: << >>  << T >>  << A >>
In article <E0FH0A.55C@world.std.com>,
Jeffrey C. Marden <jmarden@world.std.com> wrote:
>Hello:
>
>Is anybody using the Actel Designer tools with Windows NT v4.0
>
>Thanks,
>
>Jeff Marden
>jmarden@world.std.com
>

Hi Jeff...

I am using this combination too <sigh>.

So far my discoveries include...

	[complaints deleted due to space limitations]

Actel does play groovy music when you are on hold.

Eric Pearson
----


-- 
Eric Pearson -- Focus Systems -- Waterloo, Ontario
     ecp@focus-systems.on.ca  (519) 746-4918
    "We Engineer Innovative Imaging Solutions"
Article: 4542
Subject: Suggest an interesting but manageable undergrad project.
From: Nanda Katikaneni <nkk219@mail.usask.ca>
Date: Mon, 11 Nov 1996 16:55:10 -0600
Links: << >>  << T >>  << A >>
Hi,

I am in search for an interesting undergrad course project on FPGA.
Any suggestions would be appreciated.

Reply by e-mail is preferred.
Many thanks,
-- nanda 
nkk219@mail.usask.ca
Article: 4543
Subject: Xilinx 9500 CPLDs
From: rick@camden.algor.co.uk (Rick Filipkiewicz)
Date: 12 Nov 1996 11:11:02 GMT
Links: << >>  << T >>  << A >>
We are considering using these for our next design as a replacement
for the Altera (ex-Intel) FLASH logic EPX880 parts. Anybody have any
experience with these ? How efficient is the fitting s/w ? Will the -5
9536 parts really run @ 100MHz ?

Thanks,
 _________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 4544
Subject: Re: Suggest an interesting but manageable undergrad project.
From: Steve Wiseman <steve@sj.co.uk>
Date: Tue, 12 Nov 1996 13:26:05 +0000
Links: << >>  << T >>  << A >>
Nanda Katikaneni wrote:

> I am in search for an interesting undergrad course project on FPGA.
> Any suggestions would be appreciated.

The world does seem to want a UART at the moment! I'm not sure it counts
as interesting, but I guess you can play with different configuration
options. (registers, compile time, you name it)
Interesting would be trying to code a dimwit video game that, with a
pair of DACs could plot vector graphics onto a 'scope. I bet you could
get some kind of cut-down asteroids into a few tens of k-gates. (maybe
using external ram for point storage)

   Steve

-- 
Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK
Desk +44 1223 578524 (Fax 578525) Group +44 1223 578518   steve@sj.co.uk
Article: 4545
Subject: Re: UART FOR FPGAS
From: no.bulk.mailing@thanks.com (Peter)
Date: Tue, 12 Nov 1996 13:47:07 GMT
Links: << >>  << T >>  << A >>

>Version 7 of Altera's MAXPLUS II software does include several MegaCore megafunctions
>including a 16450, 6402, 6850 and a 8251 uart.  These are pre-verified HDL design files. These are
>included with version 7.0.  I think these must be purchased from Altera because most of them are
>provided by a third party vendor.  Their "Altera Megafunction Partners Program" catalog also shows
>other functions such as 6502 and 8051 microprocessors and PCI interfaces.
>I have not tried any of these but I thought it might be worth checking into.

Burke,

What is really needed is a public-domain UART, and (IMO) preferably as
a schematic. It would not be complex; I reckon you could fit a 16450
in about 80 CLBs, and most of those would be the config registers. If
provided as a schematic, it would be trivial to hard-wire some of the
register bits and so free-up those registers.

There are loads of pay-as-you-use-them cores available for ASICs, and
as many of these come from 3rd parties, presumably they can be bought
for FPGA use.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 4546
Subject: Reconfig interactive report
From: sbaker@best.com
Date: 12 Nov 1996 21:15:41 GMT
Links: << >>  << T >>  << A >>
Reconfigurable Computing: a Roundtable and Report

Would you agree that  Reconfigurable Computers can be 
defined as "platforms and/or systems that significantly 
enhance the performance, cost or size (or typically all of these)
of computing systems by using reprogrammable logic devices?" 

The issues of reconfigurability -- devices, standards, languages, 
investment and other basic matters are explored online in a
Special Interactive Report "Reconfigurable Computing: Getting the
basics together." You can study the data in the report AND post 
your own comments in the continuing Discussion and Debate.

Go http://www.pldsite.com 

The roundtable viewpoints are from industry representatives 
including:

Steve Casselman, President of Virtual Computer Corp.
Andre DeHon, Research Engineer, University of Calif., Berkeley
Bo Varga, President, Giga Operations
Brad Fawcett, Apps. Engineering Group Manager, Xilinx
Rodger Hoskings, VP and Co-founder, Pentek

plus Experts join the Q&A:

Ray Andraka, Consultant
Jane Donaldson, President, Annapolis Micro Systems
Bernard Pottier, Universite de Bretagne Occidentale - France

Remember, you can participate in this interactive report 
by posting your own comments in the Discussion and Debate.



*****************************************
            SBAssociates
   ph. 408-356-5119 fx. 408-356-9018
   Stan Baker = sbaker@best.com
   Debbie Peel = reconfig@best.com
   Kathy Rogers = sba2@best.com
            web sites:
   www.pldsite.com - www.reconfig.com
****************************************
Article: 4547
Subject: Re: UART FOR FPGAS
From: wright@iecorp.com (Jason T. Wright)
Date: Tue, 12 Nov 1996 21:25:54 GMT
Links: << >>  << T >>  << A >>
no.bulk.mailing@thanks.com (Peter) wrote:

>
>>Version 7 of Altera's MAXPLUS II software does include several MegaCore megafunctions
>>including a 16450, 6402, 6850 and a 8251 uart.  These are pre-verified HDL design files. These are
>>included with version 7.0.  I think these must be purchased from Altera because most of them are
>>provided by a third party vendor.  Their "Altera Megafunction Partners Program" catalog also shows
>>other functions such as 6502 and 8051 microprocessors and PCI interfaces.
>>I have not tried any of these but I thought it might be worth checking into.
>
>Burke,
>
>What is really needed is a public-domain UART, and (IMO) preferably as
>a schematic. It would not be complex; I reckon you could fit a 16450
>in about 80 CLBs, and most of those would be the config registers. If
>provided as a schematic, it would be trivial to hard-wire some of the
>register bits and so free-up those registers.

Why a schematic rather than an HDL?  It should actually be much
simpler to hardwire in the HDL (XXX = constant), and the "generic
design" would be much more portable--i.e., not restricted to Xilinx,
ORCA, Altera, ...

With a schematic, you've got to match the	schematic entry tool
and the vendor library--or else redraw it yourself!

>There are loads of pay-as-you-use-them cores available for ASICs, and
>as many of these come from 3rd parties, presumably they can be bought
>for FPGA use.
>
>
>Peter.
>
>Return address is invalid to help stop junk mail.
>E-mail replies to z80@digiserve.com.

Jason
Article: 4548
Subject: EDIF to BLIF format conversion.
From: Ketan Poladia <poladia@suntan.eng.usf.edu>
Date: Wed, 13 Nov 1996 01:08:43 -0800
Links: << >>  << T >>  << A >>
Hello again,

	Does anyone over here know or aware of a tool (preferrably public
domain), which can convert EDIF formatted netlist file to the BLIF
formatted netlist file ? Please reply to:

poladia@suntan.eng.usf.edu

Thanking yawl !
Article: 4549
Subject: AAL5 SAR Design?
From: izzy@salsa.salsa.lcs.mit.edu (Michael Ismert)
Date: 13 Nov 1996 10:45:22 -0500
Links: << >>  << T >>  << A >>

Hi all,

Anyone out there have an AAL5 SAR design they might be willing to
share?  

On a related note: has anyone given any thought to (or does there
exist) a site where people could put up FPGA designs more or less as
freeware?  We have a slightly crufty PCI bus master/slave design that
we wouldn't mind making available for people who wanted to poke around
without spending the big bucks on Xilinx's prepackaged modules.  I
suppose this sort of thing would be primarily targetted at university
research, where people weren't so concerned about giving away their
advantage over their competition, and also weren't making devices in
very large quantities.  Perhaps such designs could be copy-lefted
under the GPL or some such thing to keep them freely available.

Anyway, just a thought.

Thanks,

Mike

-- 
Mike Ismert
Phone: 617-253-8236
E-mail: izzy@lcs.mit.edu


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