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On Sat, 09 Aug 1997 08:07:35 GMT, peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote: >If you are using XILINX serial proms I agree. XILINX is very >preditory on their pricing. So much so that it's probably illegal, >although I don't know anybody who has sued them yet. They play some >very nasty sales tactics. That's quite a statement! Would you care to elaborate? Stuart.Article: 7176
: Thomas Berndt (berndt@eas.iis.fhg.de) wrote: : : : : Hi, : : : : does anybody knows how I can download designs which are compiled with MAXPLUS2 : : over the LPT port? You need a byteblaster between the parallel port and a 10 pin download header in your circuit. MAXPLUS2 will automatically generate the needed *.sof file for you. You need a Windows PC to do a download. Read the applicable application notes very thoroughly before design and pin assignment. --- #include <Standard.Disclaimer> about this post being a personal opinionArticle: 7177
In article <t7wlo2l33l0.fsf@mandakini.eecs.umich.edu>, Kiran Nimmagadda <kirann@eecs.umich.edu> writes >hello everybody, > >i am facing some problems compiling my design in the >lattice pDS+ viewlogic software. the version of pDS+ i am using is >1.0 and lattice no longer provides support to it as it is too old(1993). > >my design is very simple...it basically consists of two counters, three >muxs and five user( i.e., me) defined macros. all the user defined macros >have only and & or gates and compile fine. i am attaching a part of the >report file and the message log... >------------------------------------------------------------------------- >excerpts from the report file.... >------------------------------------ >Fitter Parameters Used >---------------------- > > AVG_GLB_IN: 16 > AUTO: OFF > EFFORT: 4 > IGNORE_FIXED_PIN: OFF > MAX_DELAY: 2 > MAX_GLB_IN: 16 > PARAM_FILE: > PART: ispLSI1016-90LJ > TIMING_SIM: timing > TRY: > FAST_ROUTE: OFF > STRONG_ROUTE: FIXED > >Process Status >-------------- > > Design Analysis: complete > Pre-Route Netlisting: complete > Logic Partitioning: complete > Place and Route: incomplete > Post Route: incomplete > Fuse File Generation: incomplete >------------------------------------------------------------------------ >excerpts from the message log.... >------------------------------------ >dpm> pass1 elapsed time: 00:00:52 >dpm> formatting output... >LAF2LIF Version 1.50 8/19/93 >Copyright (c) Lattice Semiconductor Corp. 1991-1992. All rights reserved. > >17018 INTERNAL ERROR: - 25: yacc: Syntax error, state 58. >17018 INTERNAL ERROR: - 31: yacc: Syntax error, state 58. >17018 INTERNAL ERROR: - 33: yacc: Syntax error, state 58. >17018 INTERNAL ERROR: - 35: yacc: Syntax error, state 203. >17018 INTERNAL ERROR: - 36: yacc: Syntax error, state 203. >17018 INTERNAL ERROR: - 37: yacc: Syntax error, state 203. >17003 INTERNAL ERROR: - 130: Invalid <sym_phys_loc>: '/' >17018 INTERNAL ERROR: - 131: yacc: Syntax error, state 282. >17004 INTERNAL ERROR: - 131: Illegal pin attribute. >17003 INTERNAL ERROR: - 154: Invalid <sym_phys_loc>: '/' >17018 INTERNAL ERROR: - 155: yacc: Syntax error, state 282. >17004 INTERNAL ERROR: - 155: Illegal pin attribute. >17003 INTERNAL ERROR: - 162: Invalid <sym_phys_loc>: '/' >17018 INTERNAL ERROR: - 163: yacc: Syntax error, state 282. >17004 INTERNAL ERROR: - 163: Illegal pin attribute. >17016 INTERNAL ERROR: IOC on net RAS has no associated XPIN! >17016 INTERNAL ERROR: IOC on net W has no associated XPIN! >17016 INTERNAL ERROR: IOC on net CAS has no associated XPIN! >dpm> creating reports... >dpm> 25502 WARNING: could not open report file CASRASW.rp7 >dpm> abnormal exit. process stopped. >dpm> total elapsed time: 00:02:08 >----------------------------------------------------------------------------- > >the error numbers above are not listed in the error index in the manual and >i have no clue as to what the problem could be. if someone can give some >insight into this situation, it would be great. > >thanks a lot in advance and email replies are most welcome to >kirann@eecs.umich.edu > >regards, >kiran nimmagadda. I have seen no replies. I am no expert and apologise if I am stating the obvious. "yacc" is a standard parsing program and in this case it is unable to analyse your input file...it doesn't think it sees proper syntax. It would appear that it objects to '/'...is this a valid input token? Are you running Windows NT 4.0? There are problems with it and some Lattice programs...intermediate files seem to get scrambled in some way. As a last resort I would suggest you keep simplifying your input file till things work and then start putting things back to find out what input line makes it fail. I recommend the Lattice/Synario free CD most strongly. Regards, Nick Toop -- nick toopArticle: 7178
I have scanned through the Splash-2 book, and it mentions commercial
licensing. However, I've looked at:
http://www.super.org:8000/FPGA/splash2.html
http://pequod.ee.vt.edu/
http://www.optimagic.com/research.html
http://www.io.com/~guccione/HW_list.html
(Web searches turns up mostly Stanford's Splash-2,
which I'm sure isn't the same FPGA-based Splash-2).
And I'm not able to find commercial boards, except Wildfire from
Annapolis Micro Systems. Are there others?
Thanks in advance for any leads.
Danny Kumamoto
mailto:dnk@pobox.com http://www.pobox.com/~dnk TEL: +1 512-918-3640
Postal: 13492 Research Blvd., Suite 120-295, Austin, TX 78750-2252, U.S.A.
Article: 7179NOTICE OF VSI MEETING: THE WORLDWIDE MEMBERSHIP MEETING OF THE VIRTUAL CHIP INTERFACE ALLIANCE Friday, October 3, 1997 (after the Embedded Systems Conference) Silicon Valley Free for representatives from VSIA member companies. $150 for non-members. PROGRAM The fall membership meeting will break some new ground. It will not only present the progress of the Working Groups (DWGs) but will begin the discussion of how this work will benefit the engineering of system-level ICs. We are inviting non-members (for a fee) so we can begin to discuss the application of VSI specifications with the industry beyond the Alliance. We will also have an important keynote speaker at lunch and updates on the progress of the Alliance itself. The program will begin at 9:00 and conclude at 4:00 pm when parallel sessions for each of the six DWGs will begin, ending at 5:30pm. A cocktail reception for all attendees follows. You are invited to send as many representatives as you wish. The DWG break-out sessions at 4:00pm will include: --Design Implementation and Verification --High-level System Design --IP Protection --Mixed-Signal --On-chip Buses --Manufacturing Related Test The VSI website (www.vsi.org) will maintain a current description of the meeting as it develops further. DETAILS 9:00-5:30 pm (Reception at 5:30) Check-in and breakfast: 7:30-9:00 am TO REGISTER Please register in advance, by contacting the VSI Alliance: 15495 Los Gatos Boulevard, Los Gatos, CA 95032, USA Phone: 1-408-356-8800 Fax: 1-408-356-9018 Email: conference@vsi.org Registration info on the web. VENUE Santa Clara Marriott 2700 Mission College Blvd., Santa Clara, Calif. By special arrangement, a limited number of hotel rooms are available at the Marriott at a rate of $149, single or double occupancy per night. For reservations, call 1-800-228-9290 or 1-408-327-6808. Mention the "VSI Meeting". The special priced rooms are available on the nights of October 2nd and 3rd. You must make reservations by September 11 to get this rate. Individuals re responsible for their own billing arrangements with the hotel. Please register as soon as possible and indicate which DWG breakout session you expect to attend -- so we can make plans for a good meeting. Best regards, Stan Baker Executive Director, VSI AllianceArticle: 7180
On 10 Aug 1997 15:00:59 GMT, rstevew@armory.com (Richard Steven Walz) wrote: >In article <33ebabe0.228220832@news.m.iinet.net.au>, >David R Brooks <daveb@iinet.net.au> wrote: >>Sam Falaki <Falaki@uqtr.uquebec.ca> wrote: >> >>:> >> Has somebody tested the free actel software? Is it worth to download? >>:> >> Is programmer support included? Is the ACTIVATOR needed or is there >>:> >> a free design for a simple programming hardware. >>: >>:I managed to compile VHDL and target a very wide range of devices >>:without even going through any tutorial or reading any "help" >>:whatsoever. It's really easy to use. You can kind of guess your >>:way along and next thing you know you're done. I liked it. >> >> The software may be free (and good), but what else do you need to get >>working silicon? A big-bucks programmer, maybe? The bottom line is the >>cost of _all_ tools necessary. >> >> Please, will one of the SRAM-based FPGA vendors put out something >>similar? So we (the great impoverished <g>) can actually put their >>chips to work in real systems. >> >>-- Dave Brooks <http://www.iinet.net.au/~daveb> >>PGP public key: finger daveb@opera.iinet.net.au >> servers daveb@iinet.net.au >> fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34 >> What's all this? see http://www.iinet.net.au/~daveb/crypto.html >--------------------------------------------- >Last I looked, Altera had bought Intel's FlexPLD's and called them FlashLOGIC >or such and they are FPGA's that are SRAM and EEFLash programmable with a >LPT-JTAG cable I have the plans for that uses just one '244. I don't do PLD >that big, so I haven't bothered, but that sounds like what you just asked >for. Yes? No? All you need to do is hunt down the command to dump the SRAM >to EEFlash, (they want to sell you software to do that one tiny bit, but it >is a well known code), and you got it!! I THINK I still have that info! >Write or call them! www.altera.com . >-Steve >-- >-Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew >-Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew >Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com >Oz:.AU ftp://ftp.peninsula.apana.org.au:/pub/electronics/ftp.armory.com Altera have announced that they are to discontinue the Flashlogic family, so I wouldn't design them in. I think the last time buy for these parts has already been done. PLDShell, which was the free software, was crap anyway.Article: 7181
Tom Burgess wrote: > > Bruce Nepple wrote: > > > > An example > > Altera'a new EPF6016 is $22, decreasing to $12 (budgetary) in 1998 > > It takes a serial 260KBit EEPROM, priced at $18 (Yes, from Atmel). > > I can buy a parallel EPROM for $3. What gives? > > > > Last time I checked, (over a year ago) the Atmel parts were at rough > price parity with the non-reprogrammable Xilinx 17xxx parts and > therefore were not a bad deal, but both are still outrageous compared > to jellybean 27Cxxx EPROMs. The reason? Limited sales volume > (microscopic compared to EPROMs), captive markets, and not much > competition. I believe that the vendors would say they are providing > the serial PROMS as a service and are basically just recovering costs. > Since there is usually a microprocessor in a system that uses FPGAs, > most cost-conscious designers go for serial or parallel download, > in effect using cheap EPROM (or disk) instead of expensive serial PROMs. > > regards, tom (tburgess@drao.nrc.ca) It may also be that the FPGA vendors realise that most customers looking at FPGA do NOT include the SPROM prices when comparing brands of FPGA, and also when comparing FPGA - CPLD. This makes it a good place to do some margin recovery :-) Another option may be the new DATAFLASH devices from ATMEL. These are SPI interface, 4MBit serial FLASH devices, in larger packages than the 17xxx series, but at appx 20% lower cost than 4MB byte wide FLASH, they are targeted for answer phones ( == good volumes, and price fussy market ). I have not looked to see how they interface to FPGA bootload, but if you were choosing a F/EPROM + small uC, a DATAFLASH <- Small uC -> FPGA is an alternative. -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Reusable object modules, for i2c, SPI and SPL bus interfaces = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55 = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 7182
Fault-Simulation - Turbo Fault High Performance Fault Simulator: TurboFault combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate-level, including tri-state gates, latches, flip-flops, single and multi-port RAMS, complex bus resolution functions, and USER Defined primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will also read Standard Delay Format (SDF) timing files. Advanced Cached-Concurrent Algorithm: Turbofault utilizes a new algorithm optimed for today's computer hardware that maximizes the simulation power of workstations. Syntest Cached-Concurrent algorithm eliminates needless operations and with new Fast Queque technology combines the best of unit delay and cycle-based capabilities. No other fault simulator, hardware or software, matches the performance of TurboFault. TurboFault makes fault simulation an integral design tool for generating a quality manufacturing test set. TurboFault supports single timing delay for simulation accuracy and flexibility, without sacrificing speed. TurboFault is the fastest concurrent fault simulator based on the latest advances in cycle-based simulation technology. It simulates even *faster* than existing expensive hardware accelerated fault simulators. Fault simulation also consumes memory very quickly, so memory management is critical. TurboFault combines efficient memory management with special fault handling resulting in low memory consumption. To hear more of Turbo-Fault, please send an e-mail to Suzanne@world.std.com, please send us your company name, your name and fax #. Thanks! The staff at Syntest Technology. *ATPG* *Boundry Scan* *RAM BIST* *Design for test services* *Training* *TurboFault Simulation* *IDDQ* *Testability Analysis* -------------------------------------------------------/-/-/-/-/-/- ps. Ask about our 50% trade up offer!Article: 7183
FPGA `98
Call for Papers
1998 Sixth ACM International Symposium on
Field-Programmable Gate Arrays
DoubleTree Hotel, Monterey, California
February 22-25, 1998
http://www.ece.nwu.edu/~hauck/fpga98
==========================================================
As Field-Programmable Gate Arrays become more essential to the design of
digital systems there is increased pressure to improve their performance,
density and automatic design. This symposium follows the largest ever
gathering of this kind last year in Monterey at FPGA `97. For FPGA `98,
we are once again soliciting submissions describing novel research and
development in one or more of the following (or similar related) areas
of interest:
FPGA architecture: logic block & routing architectures, I/O structures
and circuits, new commercial architectures.
CAD for FPGAs: placement, routing, logic optimization, technology
mapping, system level partitioning, testing and
verification.
Interactions: between CAD, architecture, applications, and
programming technology.
Fast prototyping: for System level design, Multi-Chip Modules.
Applications: use of FPGAs in novel circuits, as emulators and
compiled accelerators.
Field-programmable interconnect chips and devices (FPIC/FPID.)
FPGA-based compute engines.
Field-programmable analog arrays.
==========================================================
Authors should submit 20 copies of their paper (12 pages maximum) by
September 26, 1997. Notification of acceptance will be sent by December 1,
1997. The authors of the accepted papers will be required to submit the
final camera ready copy by December 15, 1997. A proceedings of the accepted
papers will be published by ACM, and included in the ACM/SIGDA CD-ROM
publications. All submissions should be sent to:
Sinan Kaptanoglu
FPGA `98
Actel Corporation
955 East Arques Avenue,
Sunnyvale, CA 94086 USA
e-mail:sinan@actel.com
phone: (408) 522-4319
fax: (408) 522-8041
==========================================================
General Chair: Jason Cong, UCLA,
Financial Chair: Carl Ebeling, U. of Washington,
Program Chair: Sinan Kaptanoglu, Actel,
Publicity Chair: Scott Hauck, Northwestern U.
============================
Technical Program Committee:
============================
Michael Butts, Quickturn
Jason Cong, UCLA
Eugene Ding, Lucent
Carl Ebeling, U. of Washington
Scott Hauck, Northwestern U.
Dwight Hill, Synopsys
Brad Hutchings, BYU
Sinan Kaptanoglu, Actel
David Lewis, U. of Toronto
Fabrizio Lombardi, Texas A&M
Jonathan Rose, U. of Toronto
Rob Rutenbar, CMU
Malgorzata Marek-Sadowska, UCSB
Gabriele Saucier, IMAG
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
John Wawrzynek, UCB
Martin Wong, UT at Austin
============================================================================
Sponsored by ACM SIGDA, with support from Actel, Xilinx, Altera, and Lucent.
============================================================================
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| Scott A. Hauck, Assistant Professor |
| Dept. of ECE Voice: (847) 467-1849 |
| Northwestern University FAX: (847) 467-4144 |
| 2145 Sheridan Road Email: hauck@ece.nwu.edu |
| Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 7184
Wen-King Su <wen-king@myri.com> wrote in article
<5s2uji$js8@neptune.myri.com>...
> In a previous article mush@jps.net (David Decker) writes:
>
> ;2. I've seen a switch that can switch a monitor, keyboard,
> :and mouse. among up to 4 live PC boxes.
> ;(OmniView Belkin F1D066 for ~$300.00.)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
A 4-way switchbox (monitor/keyboard/mouse) costs about $50 ex tax in
Australia.
Cables are a couple of dollars each. The only thing to watch out for is
the monitor cables if you are running >800x600 @ 256 colors (buy the
'better'
monitor cable that they sell - it the one made using coax rather than
hookup wire).
The switchboxes work well, although if you are verry fussy and running at
higher
resolutions, you may notice minor ghosting. Also, some VGA cards powerup
in MONO mode if they don't see a monitor when the PC is powered on.
> :Is it any good?
> ;
> :2a. There is also the possibility of controlling multiple PCs on a
> ;network, remotely, from one PC. Carbon Copy, I think. Is this a better
> :way?
>
> Oh the shackles that microsoft made us wear. It is sad to see a whole
> lot of us getting driven to these contraptions in order to stay
productive.
> The most attractive solution is to get UNIX boxes. With a site-wide
> licence, and a shell interface, you can start any number of runs on any
> number of machines from your machine at the office, at home, or anywhere.
> We do that routinely with ORCA FPGA software, which is a close kin to
> Xilinx M1. I can start them, put them in the back ground, go away and
> log in some some where else to check on them and continue to work on
them.
> I do not currently have that luxury with the tool for another FPGA, and
> I am now sitting in my office waiting for it to finish so I can proceed
> with the next step, when I can be instead be waiting remotely at home,
> perhaps next to my pool.
>
Article: 7185Hi: I'm looking at Xilinx CPLDs for a new design and trying to match the maximum clock frequency number in the data book for XC95108-7. The maximum clock frequency on a 16bit counter I get is 83 MHz their number is 125 MHz. Can any one duplicate their results? Regards, Kayvon Irani Los Angeles, CaArticle: 7186
Steve,
I believe no matter what you ask the x86 to do...it will only do 4 DWORD
transfers per address phase....is that not true?
Austin Franklin
darkroom@ix.netcom.com
Steve Casselman <sc@vcc.com> wrote in article
<33EE1F9A.2BCA69F8@vcc.com>...
> > > I want to design a card with a PCI interface.
> > > 1. Can I make use of the DMAC of any 486/Pentium machines for data
> > > transfers ? Or do I have to use a DMAC on my card and develop
> > > an arbiter as well ?
> >
>
> This code will generate a burst write from the
> cpu to a pci board if the board can handle
> bursts.
> /*
> ** This function talks to the on board RAM
> ** On the HOT Works board.
> */
>
> void
> Pci6200::writeRAM(unsigned long addr, unsigned long * data, unsigned
> long count){
>
> unsigned long addrRAM = addr + membase;
> /* addr and membase come from the
> driver and repersent the memory
> mapped location of the board
> */
> __asm
> {
> push edi
> push ecx
> push esi
> mov esi, data
> mov edi, addrRAM
> mov ecx, count
> cld
> rep movsd
> pop esi
> pop ecx
> pop edi
> }
>
>
> } /* end Pci6200::writeRAM() */
>
> --
> Steve Casselman, President
> Virtual Computer Corporation
> http://www.vcc.com
>
>
>
Article: 7187> Have you looked at the Atmel AT17Cxxx parts? They replace the Xilinx >serials, and Atmel are usually pretty keen on pricing. You get >in-circuit programmablility as an extra. The ISP algorithm? Its just >I2C. The real problem is that if you use XILINX FPGA, but don't buy their PROMs, then XILINX starts jacking up their prices on everything you buy from them. XILINX has probably the most preditory pricing that I've ever seen. [I think it's downright illegal, but then again I'm not a lawyer]. There are two companies (that I know of) here in town that are stuck buying all XILINX FPGA and PROMs. If they buy even one part from somebody else like Altera, then XILINX will come in and increase their costs by 40% or more. ----------------------------------------------------- Wade D. Peterson | TEL: 612.722.3815 Consultant to Industry | FAX: 612.722.5841 3525 E. 27th St. No. 301 |---------- EMAIL ---------- Minneapolis, MN 55406 | peter299@maroon.tc.umn.edu ---------------- Committed to Quality ---------------Article: 7188
Hello everybody. Since I am new to this newsgroup, I wanted to check first if it is ok to post a job announcement hre. If not, could you please point me to a more reasonable newsgroup? BTW, our project involves FPGA, VHDL, PCI -- and obviously we are located in the UK. Thanks for your patience, martin -- Martin Maierhofer | "History will teach us nothing." m.maierhofer@tees.ac.uk | - StingArticle: 7189
Kayvon Irani <kirani@cinenet.net> wrote: >Hi: > I'm looking at Xilinx CPLDs for a new design and trying to match the > maximum clock frequency number in the data book for XC95108-7. The > maximum clock frequency on a 16bit counter I get is 83 MHz their number > is 125 MHz. Can any one duplicate their results? I expect you are using normal rather than local or pin feedback which introduces another 4ns delay. You can only use local feedback within a function block and pin feedback from actual output pins. This means the maximum speed of state machines and counters depends on the fit and impacts Xilinx's claims about pin locking ability of the 9500 series if you are trying to go fast. The 9536 doesn't have local feedback at all so a slower 9572 can actually be faster for some designs. I had one design where 7 bits of a 16bit bus arrived 6.5ns before the rest because only those bits could take advantage of local feedback - yuk. The design ended up in a Lattice 3000 series which worked out much better all round. Cheers Terry...Article: 7190
On Tue, 12 Aug 1997 15:06:03 GMT, peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote: >There are two companies (that I know of) here in town that are stuck >buying all XILINX FPGA and PROMs. If they buy even one part from >somebody else like Altera, then XILINX will come in and increase their >costs by 40% or more. So tell them that you have redesigned and are going to program the FPGA from a micro. If they jack up the price, then design them out, and (please) provide documentary evidence to this newsgroup. I'm sure somebody would be happy to stick a few K of GIF's on a web site to prove the point. If you've got any documentary evidence, then why don't they make it public. If it is true, you have nothing to fear, and Xilinx has EVERYTHING to lose. The bad publicity would cost them a lot more than it would cost you. If the right spin was put on it, it could cripple them. I personally would cease designing with any manufacturers product who attempted to blackmail me in such a way. It's not like Xilinx is the only vendor out there. Maybe the perceived threat was from a desparate salesman? I still can't believe it's Xilinx policy to blackmail customers with massive price rises. I know designing people out is pretty extreme, but as you assert that Xilinx will put the price up, I assume you refer to direct business, in which case the value should be high, in which case I'm sure it would be economical to do so. StuartArticle: 7191
peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote:
[snip]
:The real problem is that if you use XILINX FPGA, but don't buy their
:PROMs, then XILINX starts jacking up their prices on everything you
:buy from them. XILINX has probably the most preditory pricing that
:I've ever seen. [I think it's downright illegal, but then again I'm
:not a lawyer].
Hmm, I have done several systems using Xilinx FPGAs, that didn't use
their ROMs, for the simple reason the designs included a CPU, and
FPGAs were programmed as slaves by the CPU. So Xilinx didn't lose a
EEPROM sale there: there never was one. I'm not aware we were gouged
on price for it (maybe the Australian distributors are more
reasonable?).
Now, suppose I have FPGAs on the shelf (maybe over-bought for some
such project), and decide to use them in another project which _just
happens_ to use Atmel EEPROMs, what the **** business of Xilinx is it?
All you need do (if they ask) is tell them the project uses
slave-mode configuration. I doubt they'll bother to reverse-engineer
your product to check up.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7192Kayvon Irani wrote: > > Hi: > I'm looking at Xilinx CPLDs for a new design and trying to match the > maximum clock frequency number in the data book for XC95108-7. The > maximum clock frequency on a 16bit counter I get is 83 MHz their number > is 125 MHz. Can any one duplicate their results? > > Regards, > Kayvon Irani > Los Angeles, Ca Hello, I have recently had the same problem, although with a 10 bit counter in an XC9572-7. I solved it by forcing the use of local feedback within a function block. This can be done using the 'PARTITION' property if using ABEL HDL code as described in XAPP072 or on P2-15 of the May 97 'ISP Application Guide'. Alternately an "experimental" product called Chipviewer can be found on the Xilinx FTP site. This product allows you to produce a constraint file for use in M1 that will place the counter elements physically where ever you want it in the target device. (Buggy, but does work.) Regards, Graeme Robertson, Melbourne, AustraliaArticle: 7193
Terry Harris wrote: > > > You can only use local feedback within a function block and pin > feedback from actual output pins. The Xilinx CPLD literature p2-9 shows a timing model of the device where the local feedback is shown to originate from the Q output of the flip-flop rather than output pins. Is it perhaps incorrect? Regards, Kayvon Irani Lear AstronicsArticle: 7194
no@spam J.Szamosfalvi wrote: > > : Thomas Berndt (berndt@eas.iis.fhg.de) wrote: > : : does anybody knows how I can download designs which are compiled with MAXPLUS2 > : : over the LPT port? > > You need a byteblaster between the parallel port and a 10 pin download header > in your circuit. MAXPLUS2 will automatically generate the needed *.sof > file for you. You need a Windows PC to do a download. Read the applicable > application notes very thoroughly before design and pin assignment. After needing to do this on a client site, I have a bit of Qbasic that will launch a .rbf file through LPT1. It clashes with the Altera dongle and Iomega parallel port ZIP drive driver, though. It's also slow, but if anyone wants it, they're welcome to mail me. (It uses passive serial mode, and uses 4 connections plus ground. It seems reliable, but there's no guarantee. (If anyone knows how to get / to round _down_ to an integer result, or a shift right operator in Qbasic, I'd be interested...) SteveArticle: 7195
Kayvon Irani <kirani@cinenet.net> wrote: >Terry Harris wrote: >> > >> >> You can only use local feedback within a function block and pin >> feedback from actual output pins. > > The Xilinx CPLD literature p2-9 shows a timing model of the device where > the local feedback is shown to originate from the Q output of the flip-flop > rather than output pins. Is it perhaps incorrect? No thats right but local feedback only routes within that function block which restricts fitting if you must use it. I presume pin feedback comes from output pins using the path that would be used if the pin was an input. As far as I know pin feedback has the same timing as input pins which is significantly faster than non-local feedback. Cheers Terry...Article: 7196
In our latest design we have notice that our Altera 7K FPGA is drawing roughly 100ma of current. Stopping the clock to the chip only reduced the power consumption by 30%. I was wondering if there is any study out there that 1) explains the high power consumption of FPGA 2) compare power consumption between different FPGA vendors and different technology family. Please send/or copy your responses to davidb@proxim.com Thanks, DavidArticle: 7197
In article <5snlch$47o@thorgal.et.tudelft.nl>, <dstewart@dmicros.com> wrote: >On 10 Aug 1997 15:00:59 GMT, rstevew@armory.com (Richard Steven Walz) >wrote: > >>In article <33ebabe0.228220832@news.m.iinet.net.au>, >>David R Brooks <daveb@iinet.net.au> wrote: >>>Sam Falaki <Falaki@uqtr.uquebec.ca> wrote: >>> >>>:> >> Has somebody tested the free actel software? Is it worth to download? >>>:> >> Is programmer support included? Is the ACTIVATOR needed or is there >>>:> >> a free design for a simple programming hardware. >>>: >>>:I managed to compile VHDL and target a very wide range of devices >>>:without even going through any tutorial or reading any "help" >>>:whatsoever. It's really easy to use. You can kind of guess your >>>:way along and next thing you know you're done. I liked it. >>> >>> The software may be free (and good), but what else do you need to get >>>working silicon? A big-bucks programmer, maybe? The bottom line is the >>>cost of _all_ tools necessary. >>> >>> Please, will one of the SRAM-based FPGA vendors put out something >>>similar? So we (the great impoverished <g>) can actually put their >>>chips to work in real systems. >>> >>>-- Dave Brooks <http://www.iinet.net.au/~daveb> >>>PGP public key: finger daveb@opera.iinet.net.au >>> servers daveb@iinet.net.au >>> fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34 >>> What's all this? see http://www.iinet.net.au/~daveb/crypto.html >>--------------------------------------------- >>Last I looked, Altera had bought Intel's FlexPLD's and called them FlashLOGIC >>or such and they are FPGA's that are SRAM and EEFLash programmable with a >>LPT-JTAG cable I have the plans for that uses just one '244. I don't do PLD >>that big, so I haven't bothered, but that sounds like what you just asked >>for. Yes? No? All you need to do is hunt down the command to dump the SRAM >>to EEFlash, (they want to sell you software to do that one tiny bit, but it >>is a well known code), and you got it!! I THINK I still have that info! >>Write or call them! www.altera.com . >>-Steve >>-- >>-Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew >>-Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew >>Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com >>Oz:.AU ftp://ftp.peninsula.apana.org.au:/pub/electronics/ftp.armory.com >Altera have announced that they are to discontinue the Flashlogic >family, so I wouldn't design them in. I think the last time buy for >these parts has already been done. PLDShell, which was the free >software, was crap anyway. --------------------------- Ah! Thanks, important to know anyway. It seemed they were going to go with it for a time. I figured they would get past rev 1 of software. I guess they never did. Intel makes money again! -Steve -- -Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew -Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com Oz:.AU ftp://ftp.peninsula.apana.org.au:/pub/electronics/ftp.armory.comArticle: 7198
: >With the older Xilinx devices, one could attach a L attribute to a : >local clock net (forces it onto a long line), add a SC=1 (skew below : >1ns) attribute, and that would do it. This was with the old (1991) APR : >program. With the new devices (and using PPR) this doesn't work. M1 does support the MAXSKEW constraint which can be used for clock nets. Steve Lass Xilinx Product MarketingArticle: 7199
rstevew@armory.com (Richard Steven Walz) wrote:
[snip]
:Last I looked, Altera had bought Intel's FlexPLD's and called them FlashLOGIC
:or such and they are FPGA's that are SRAM and EEFLash programmable with a
:LPT-JTAG cable I have the plans for that uses just one '244. I don't do PLD
:that big, so I haven't bothered, but that sounds like what you just asked
:for. Yes? No? All you need to do is hunt down the command to dump the SRAM
:to EEFlash, (they want to sell you software to do that one tiny bit, but it
:is a well known code), and you got it!! I THINK I still have that info!
:Write or call them! www.altera.com .
:-Steve
ISP has to be the way to go for this kind of thing. However Altera do
not (afaik) offer free design software. A colleague is using Altera
extensively, and confirms the "Bit Blaster" (ISP adapter) is just a
'244 sold at a high price.
This seems to be the problem, everyone charges mega-$ either to
design, or to program the brutes.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
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