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Messages from 11800

Article: 11800
Subject: Re: 22V10 programming
From: Mike Treseler <tres@tc.fluke.com>
Date: Thu, 10 Sep 1998 08:27:45 -0700
Links: << >>  << T >>  << A >>
Raymond Chiu wrote:
> 
> Found one for about $220.  Does anyone have any comments about this
> model?
> 
> http://www.needhams.com/emp10.htm
> 
> Raymond Chiu wrote:
> 
> > I am receiving excellent responses: THANKS.
> >
> > Does anyone know of a $100 programming device?

No, but you could save $94 by buying an Altera 7064,
making your own byteblaster cable for programming and downloading
their free development software.

    -Mike Treseler
Article: 11801
Subject: Re: Design Security Question
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 10 Sep 1998 17:01:40 GMT
Links: << >>  << T >>  << A >>
Well Catalin, since you kept me honest yesterday, let me do the same for 
you :-) :-)

As has been pointed out many times in this group, the SRAM FPGAs can
potentially be the MOST secure form of digital logic on a board, and this
is through the use of battery back-up of the FPGA, and only loading the
bit stream once, at the factory. More secure than EPLDs, PALs, anti-fuse
FPGAs, and even ASICs. 

This technique never exposes the bitstream to the potential copier, and
the level of effort to open the package while maintaining power, so that
the part could be put into an e-beam prober should be as impossible as
skiing through a revolving door. (you also need an e-beam voltage contrast
prober, which are not to cheap either).

For this to be reasonably practicle, you should choose a Xilinx part that 
is specifically designed for low power, such as the XC3000 or the XC4000L

Philip.

In article <35F7D624.DCE36E36@spam.com> Catalin <no@spam.com> writes:
>Eric W Braeden wrote:
>
>> Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design.
>>      That would probably mean I would use the XC17S40 SPROM.
>>      How would you keep anyone who want to from cloning your design?
>>      I don't see any mention of security in the Xilinx pages. How do you
>>      load your FPGA without exposing your loadable image to hardware
>>      hackers?
>>
>> TIA
>>
>> Eric
>
>Hi Eric,
>
>There is no way to do what you ask with SRAM based FPGAs. While reverse
>engineering of the FPGA design is hard (at least in the Xilinx case), simple
>duplication of the bitstream is easy. No matter what FPGA configuration
>method you use the loadable image will be exposed on the part pins at
>startup. A simple logic analyzer is all you need to capture it.
>
>One solution to your problem could be the use of a small (and cheap) EPLD,
>something like Xilinx XC9536 or Vantis MACH111SP which can be protected
>against readback and make the FPGA design work only in the presence of this
>EPLD.  And remember, there is no absolute copy protection scheme - all you
>can do is make copying hard enough to deter would be hackers.
>
>Catalin Baetoniu
>
>


Article: 11802
Subject: 16 bit CRC
From: watm@asterix.ist.utl.pt (Wireless ATM)
Date: 10 Sep 1998 17:37:31 GMT
Links: << >>  << T >>  << A >>
    I am looking for source code, equations or flowcharts for the calculation of a 16 bit CRC - parallel.

   If someone can give a hand in this, i will appreciate !

Thanks in advance,
Rui Pinto
Article: 11803
Subject: FPGA'99: Papers Due October 2nd
From: hauck@ece.nwu.edu (Scott Hauck)
Date: Thu, 10 Sep 1998 17:47:44 GMT
Links: << >>  << T >>  << A >>
                       FPGA `99: Call for Papers

                Seventh ACM International Symposium on
                    Field-Programmable Gate Arrays

                DoubleTree Hotel, Monterey, California
                        February 21-23, 1999

As we reach the end of the 1990s, rapidly increasing speed and capacity have
made FPGAs a standard implementation target for digital logic.  Advancements
in FPGA architectures proceeds unabated, and larger, faster devices enable
new, innovative applications that continue to stress designers and
their tools.  For FPGA `99, we are soliciting submissions describing novel
research and development in the following (and related) areas of interest:

    FPGA Architecture: Logic block & routing architectures, I/O structures and
    circuits, new commercial architectures, Field-Programmable Interconnect
    Chips and Devices (FPIC/FPID), Field-Programmable Analog Arrays (FPAA).

    CAD for FPGAs: Placement, routing, logic optimization, technology mapping,
    system-level partitioning, logic generators, testing and verification.
    CAD for FPGA-based accelerators.

    Interactions: between CAD, architecture, applications, and programming
    technology.

    Applications: Innovative use of FPGAs, exploitation of FPGA features,
    novel circuits, high-performance and low-power/mission-critical
    applications, DSP techniques, uses of reconfiguration, FPGA-based cores.

    FPGA-based computing engines: Compiled accelerators, reconfigurable
    computing, adaptive computing devices, systems and software.

    Fast prototyping for system level design, Multi-Chip Modules (MCMs), logic
    emulation.

Authors are invited to submit PDF (preferred) or postscript of their paper 
(12 pages maximum) by October 2, 1998 via E-mail to fpga99@xilinx.com.  
Alternatively, authors may submit a 3.5" floppy disk containing the pdf 
or postscript file or 22 copies of their paper to the program chair.  
Notification of acceptance will be sent by December 1, 1998.  The authors of 
the accepted papers will be required to submit the final camera-ready copy by 
December 15, 1998.  A proceedings of the accepted papers will be published by 
ACM, and included in the Annual ACM/SIGDA CD-ROM Compendium publication.  
Address questions to:

    Steve Trimberger
    Program Chair, FPGA `99
    Xilinx, Inc.
    2100 Logic Dr.
    San Jose, CA 95124-3450 USA
    phone: (408) 879-5061
    fax: (408) 559-7114
    fpga99@xilinx.com

General Chair: Sinan Kaptanoglu, Actel
Finance Chair: Jason Cong, UCLA
Program Chair: Steve Trimberger, Xilinx
Publicity Chair: Scott Hauck, Northwestern U.

                    Program Committee
Om Agrawal, Vantis                  Ray Andraka, Andraka Consulting
Michael Butts, Quickturn            Jason Cong, UCLA
Eugene Ding, Lucent                 Carl Ebeling, U. of Washington
Scott Hauck, Northwestern U.        Brad Hutchings, BYU
Sinan Kaptanoglu, Actel             David Lewis, U. of Toronto
Fabrizio Lombardi, Texas A&M        Wayne Luk, Imperial College
Margaret Marek-Sadowska, UCSB       Peter Moceyunas, Synopsys
Jonathan Rose, U. of Toronto        Gabriele Saucier, INPG
Martine Schlag, UCSC                Herman Schmit, CMU
Tim Southgate, Altera               Steve Trimberger, Xilinx
John Wawrzynek, UCB                 Martin Wong, UT at Austin

Sponsored by ACM SIGDA, with support from Xilinx, Altera, Lucent and Actel.

Please visit <http://www.ece.nwu.edu/~hauck/fpga99> for more information.

Article: 11804
Subject: Re: Design Security Question
From: Catalin <no@spam.com>
Date: Thu, 10 Sep 1998 13:49:09 -0400
Links: << >>  << T >>  << A >>
Philip Freidin wrote:

> Well Catalin, since you kept me honest yesterday, let me do the same for
> you :-) :-)

I have to concede that this time you are right ;-). I even remeber now your
previous post on this subject.

> As has been pointed out many times in this group, the SRAM FPGAs can
> potentially be the MOST secure form of digital logic on a board, and this
> is through the use of battery back-up of the FPGA, and only loading the
> bit stream once, at the factory. More secure than EPLDs, PALs, anti-fuse
> FPGAs, and even ASICs.
>
> This technique never exposes the bitstream to the potential copier, and
> the level of effort to open the package while maintaining power, so that
> the part could be put into an e-beam prober should be as impossible as
> skiing through a revolving door. (you also need an e-beam voltage contrast
> prober, which are not to cheap either).
>
> For this to be reasonably practicle, you should choose a Xilinx part that
> is specifically designed for low power, such as the XC3000 or the XC4000L
>
> Philip.

Your solution is OK and from a security point of view has obvious advantages but
is limited to small and/or low power FPGAs. What if my design is an XC4062XL-09?
You have also to deal with the problem of battery discharge or failure. Your
client might not like living with a Damocles sword above his head all the time
:-).

Catalin Baetoniu


Article: 11805
Subject: VSIA Member Meeting
From: sbaker@best.com (Stan Baker)
Date: Thu, 10 Sep 1998 18:20:41 GMT
Links: << >>  << T >>  << A >>
NOTICE OF VSI ALLIANCE MEMBER MEETING
October 7, 1998, Santa Clara Marriott Hotel
Santa Clara, California

Designed for engineers and marketing personnel, 
this meeting will have:
--An in-depth look at the most important 
work on VSIA specs
--Spec development roadmaps with business 
and marketing implications
--Adoption of specs-what it means and how to 
do it will be an important part of this meeting

There will be sessions on:
--A panel discussion on "OLA: When Will It Be Real?"
--An On-Chip Bus tutorial 
(the exciting upcoming VC Interface specification)
--An "Intellectual Property Protection" Panel
-- User experiences
--And, Development Working Group Breakouts 
with a "Look Forward" at the issues of concern 
to each individual DWG.
--At the end of the day VSI will host 
a "members only" networking wine and beer party.

For registration email request to nancy@vsi.org, 
With name, title, company.
For information about the program and a registration
form, go to the web at http://www.vsi.org

This is a free, one-day member meeting.  Members Only.  
If you wish to join, information is at http://www.vsi.org

I hope to see you there,

Stan Baker
Executive Director
VSI Alliance

Article: 11806
Subject: Re: Design Security Question
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 10 Sep 1998 21:22:10 GMT
Links: << >>  << T >>  << A >>
In article <35F81115.49D336D4@spam.com> Catalin <no@spam.com> writes:
>Your solution is OK and from a security point of view has obvious
>advantages but is limited to small and/or low power FPGAs. What if my
>design is an XC4062XL-09? You have also to deal with the problem of
>battery discharge or failure. Your client might not like living with a
>Damocles sword above his head all the time
>:-).
>Catalin Baetoniu


Two words: Big Batteries

Seriously, when not clocked, and the I/O pins are tristated (use GTS),
and you have tied the design, and not used pullups on the internal tbuf 
lines, the XL parts are supposed to have a Quiescent current of 5mA max
(see page 4-72 of the 1/98 data book). The real number is probably lower 
than this.

This is not beyond the realm of battery backup, but certainly isn't going 
to last long on a coin-cell. Two or three AA size ni-cad batteries though 
would be fine for a system that is not turned off for days at a time.
An AA rechargeable will supply 5mA for 130 hours or more, depending on 
chemistry. AA nicads are rated for 650 to 800mAH. NMH batteries are 
around 1250mAH ( 250 hours at 5mA).

For this type of design protection, the effort you put into protecting 
your design is proportional to how hard you want to make it for those who 
you think might rip you off.

Philip.

Article: 11807
Subject: Re: Need Permutation generator
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 10 Sep 1998 17:36:43 -0400
Links: << >>  << T >>  << A >>


How large is the input set, and more importantly,
how large is the output set?
Are you looking for _all_ permutations, or
a pseudo-random permutation generator?

If the a pseudo-random permutation generator is
required, Floyd's algorthm as described in
"More Programming Pearls" by Jon Bentley could
be implemented in a straitforward manner in Xilinx
using internal ram for storage, LFSR's for pseudo
random number generators, and high speed carry logic for
counters and comparators, as long as the output
sequence is not too long.

Floyd's alg:
(M is size of output set, N is size of input set,
S is final output set which can be built up in XC4000 Ram)

initialize set S to empty
for J := N-M+1 to N do
    T := RandInt(1,J)
    if (T is not in S ) then
        insert T in S
    else
        insert J in S

It seems to me the hard part of implementing this
algorithm is producing a random integer in the range
1 to J (RandInt(1,J)). Has anyone got a good
H/W implementation of RandInt(1,J)?

- John

José Antonio Moreno Zamora wrote:

> Hello, this is my first posting in these groups:
> I need a VHDL or schematic model for a permutation generator of
> integers.
> I use the Xilinx M1 software, and I´m trying to implement a genetic
> algorithm over an X4010E.
> Thanks.
>
> --
> ___________________________________________________
>           Jose Antonio Moreno Zamora
>           Profesor Dpto. Informatica
>           Universidad de Extremadura
>              Escuela Politecnica
>   Avda. Universidad, s/n. 10071-Caceres (SPAIN)
>   Tf/Fax: +34-27-257267  E-mail: joseanmo@unex.es
> ___________________________________________________





Article: 11808
Subject: Re: New Evolutionary Electronics Book
From: mzenier@netcom.com (Mark Zenier)
Date: Thu, 10 Sep 1998 23:07:36 GMT
Links: << >>  << T >>  << A >>
In article <35f6b84d.1309058974@cti-fw1.critical.com>,
Stu  Card <stu@critical.com> wrote:
>On Mon, 31 Aug 1998 04:11:38 GMT, mzenier@netcom.com (Mark Zenier)
>wrote:
>
>>Since what they are doing is feeding random crap into the configuration
>>of a boardfull of FPGAs, and then using a scoring function to act as
>>the selection, and then using the genetic algorithm to select flavors
>>of the random crap that work better according to the scoring function,
>>you end up with a set of bits that does unknown things in the FPGAs.
>>It's not working as a digital circuit.  There's no clock provided to
>>the FPGA.  Operation depends on circuit strays, and will only work 
>>in a 10 degree C temperature range.
>>
>>Sounds like a great way to build a phase of the moon detector.  And
>>scare the pants off of anybody that has to do a reliability audit.
>
>It depends upon your genetic operators.  'Standard' operators, which
>work on the genotype (bit string) without regard for its semantically
>encoded phenotype ('organism', circuit, etc.) will likely do as you
>describe.  However, semantically aware operators (which incorporate
>design rules) should produce 'good' circuits (at least, circuits which
>do not violate design rules).  I think this is a very promising
>long-term research area, especially if general approach can be found
>for translating phenotypic semantic constraints into genotypic
>syntactic ones.  Or am I obfuscating? ;-)

That's exactly the point.  If they had an addition check in their
selection regime that made sure the circuits they were configuring into
the field programmable gate arrays didn't violate the design rules for
the chips, and they were operating the chips with clocks to provide
some semblance of digital and synchronous operation, there wouldn't
be a problem.  (Or if they designed their own Neural Net State Machine
chip).  But you can't make any claims about efficiency when you have an
unanalyzable, and therefore unreliable random hack.  (I'm just going
by the New Scientist article, maybe their book covers that).

But then it would evolve in a slower, less entertaining way.

Mark Zenier  mzenier@eskimo.com  mzenier@netcom.com  Washington State resident

Article: 11809
Subject: jobs @ lucent technologies
From: ejob <engineer@ejob.com>
Date: Thu, 10 Sep 1998 16:21:33 -0700
Links: << >>  << T >>  << A >>

--------------346EBE5DDB1F4F5A30745E51
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

POSITION OUTLINE

POSITION TITLE:
VLSI architecture, circuit design and implementation research engineers
(Member of Technical Staff)

LOCATION:
Murray Hill, NJ

SHORT-TERM EXPECTATIONS: FIRST 90 DAYS
The succesful candidate will be assigned to
1) identify the circuit implement opportunities for optical, wireless,
switching and access communicaitons systems,
2) identify the algorithm implementation opportunties for various
communicaitons systems,
3) identify the design challenges for implementing Gb/s circuits, or
4) identify the opportunity for circuit realization cycle time reduction
in communication systems

MEDIUM-TERM EXPECTATIONS: 90 DAYS TO ONE YEAR
The successful candidate will, based on the initial studies from the
first 3 months,
1) propose feasible architectures for efficient circuit realization of
various communications functions,
2) generate mathematical models of the various algorithms to compare
peformance and cost of various implementation options
3) provide initial designs of impementing Gb/s circuits on advanced
silicon processing technologies
4) suggest methodology for cycle time management


LONG-TERM EXPECTATIONS: AFTER THE FIRST YEAR
The successful candidate will have completed the design projects, and is
expected to continue to identify emerging opportunities of circuit
realization for communication systems


PLEASE LIST THE FIVE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM ON AN
ONGOING BASIS.
1) Identify opportunities for realizing communications functions on
integrated circuits
2) VLSI architecture and high speed circuit design for communication
systems
3) Realization of signal processing algorithms (layer I) on integrated
circuit
4) Realization of communications protocols (layer II and above) on
integrated circuits
5) Cycle time management

PLEASE LIST THE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM DAY ONE
OF  JOINING YOUR ORGANIZATION.
Identifying and realizing communications functions on integrated
circuits

WHAT SKILLS MUST THE SUCCESSFUL CANDIDATE POSSESS TO ACCOMPLISH THE
GOALS OF THE ORGANIZATION?
Skills and Experience
· Candidates should possess expert design skills in one or more of the
following areas together with the knowledge of the technical challenges
facing the industry and, most importantly, a creative ability to lead
research projects that address these challenges.

 Design Skills
· custom circuit design · placement, routing and synthesis
· VHDL design · signal integrity management
· circuit simulation, timing and verification · mixed-signal design
· FPGA design ·

 Design Experience
· high speed digital circuits · application-specific integrated circuit
· co-processor and accelerators · application-specific standard circuit
product
· digital signal processors · design of peripheral, bus, and I/O
· microcontrollers and RISC processors · hardware and software co-design

· analog circuits including filters, analog-to-digital converters,
digital-to-analog converters, trans-impedance amplifiers, and laser
drivers · VSLI Design For Testability (DFT) techniques
· memory and DMA

 Architecture and System Design Experience
· integrated circuit for communication systems, including optical
network, wireless, switching, and access · realization of communication
protocols (layer II and above) on integrated circuits
· realization of signal processing algorithms   (layer I) on integrated
circuits

 Circuit Production Experience
· cycle time management · design process analysis and optimization


WHAT SKILLS MUST THIS PERSON NOT POSSESS?
The candidate must not expect an elaborate development process
surrounding the projects, nor to have complete detailed frozen
specification before beginning design.  The candidate must not expect or
require a large team environment – the project teams are typically small
and very focused.  The candidate must not expect to concentrate only on
circuit design – full stream involvement from opportunity
identification, system definition, planning, architecture and
development is expected.  The person should be very hands-on and not
expect a large staff of technicians or other support personnel to be
assigned to projects.

WHO WILL THIS POSITION REPORT TO?

Research department head


PLEASE DESCRIBE THE ORGANIZATIONAL STRUCTURE THAT SURROUNDS THIS
POSITION.

The projects will be in about 3-4 research departments, as part of the
Bell Labs Research organization.  The Research organization, which has
approximately 1000 people, is responsible for creating new technology
and systems in support of the Lucent business units.


HOW HAS THIS POSITION BEEN HANDLED UP TILL NOW?
The design research engineers have been recruited steadily over the
years but the present goal is to staff another 20-30 people very
quickly.
 PAGE FOUR


HOW MUCH TRAVEL DO YOU ESTIMATE IS ASSOCIATED WITH THIS POSITION?
Depending on the specific function, the travel could range from very
little to a couple of times a month. The travel could be both domestic
and international.


HOW MANY YEARS OF PREVIOUS EXPERIENCE WOULD BE PREFERRED?
3-5 years or more of industrial experience would be a plus.



WHAT ARE THE EDUCATIONAL REQUIREMENTS OF THE SUCCESSFUL CANDIDATE?
PhD degress from EE or CS are strongly preferred.



WHAT FUNCTIONAL EXPERIENCE DO YOU SEE THIS PERSON POSSESSING IN PREVIOUS
POSITIONS?
The same as described above would be strongly preferred. (New PhD
graduates are welcome as well.)


WHAT PAST INDUSTRY EXPERIENCE WOULD THE SUCCESSFUL CANDIDATE HAVE COME
FROM?

R&D organizations from telecommunication companies or integrated
circuits vendors.



WHAT DO YOU SEE AS SOME OF THE KEY "PLUSES" OF THE POSITION AND YOUR
ORGANIZATION?

The successful candidates will have the opportunity and freedom to
define circuit design and implementation projects for making
communications systems more efficient and more cost-effective. The
working environment will be with many talented and highly motivated
researchers at Bell Labs.


WHAT IS THE COMPENSATION TARGETED AT AND HOW IS IT STRUCTURED? I.E.
BASE, CASH BONUS, STOCK, CAR, CLUB....
The candidate will receive a base salary, plus an annual bonus based on
the financial performance of Lucent, plus an additional bonus based on
the performance of the individual in the preceding year.



PLEASE LIST ANY OTHER CHARACTERISTICS OR INFORMATION YOU FEEL ARE
NECESSARY FOR THIS PERSON TO SUCCEED IN YOUR ORGANIZATION’S ENVIRONMENT.

Exceptional technical skills, self confidence and the ability to work
independently are essential.  The candidate will work with other very
strong technical contributors who expect outstanding performance from
all of their colleagues.


PLEASE LIST ANY OTHER REQUIREMENTS THE SUCCESSFUL CANDIDATE MUST
POSSESS.

Advancement in the Bell Labs environment typically requires taking a
lead technical role in an innovative and successful project.  Key to
advancement is the ability to identify new technology opportunities,
developing and clearly articulating a plan for capitalizing on the
opportunity, securing management support, leading the effort, and
delivering as proposed.


PLEASE LIST ANYTHING ELSE  I NEED TO KNOW REGARDING THE ORGANIZATION AND
POSITION.

This organization has already 20-30 experienced researchers in the same
area. The laboratory is called “Wireless Research Laboratory” but the
projects are more than just for wireless.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Vistit Lucent on ejob @:   http://www.ejob.com/lucent2.htm
email:  lucent2@ejob.com


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Content-Transfer-Encoding: 8bit

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML>
<B><FONT FACE="Arial,Helvetica">POSITION OUTLINE</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">POSITION TITLE:</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">VLSI architecture, circuit design and
implementation research engineers</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">(Member of Technical Staff)</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">LOCATION:</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">Murray Hill, NJ</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">SHORT-TERM EXPECTATIONS: FIRST 90 DAYS</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The succesful candidate will be assigned
to</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">1) identify the circuit implement opportunities
for optical, wireless, switching and access communicaitons systems,</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">2) identify the algorithm implementation
opportunties for various communicaitons systems,</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">3) identify the design challenges for
implementing Gb/s circuits, or</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">4) identify the opportunity for circuit
realization cycle time reduction in communication systems</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">MEDIUM-TERM EXPECTATIONS: 90 DAYS TO
ONE YEAR</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The successful candidate will, based
on the initial studies from the first 3 months,</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">1) propose feasible architectures for
efficient circuit realization of various communications functions,</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">2) generate mathematical models of
the various algorithms to compare peformance and cost of various implementation
options</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">3) provide initial designs of impementing
Gb/s circuits on advanced silicon processing technologies</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">4) suggest methodology for cycle time
management</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">LONG-TERM EXPECTATIONS: AFTER THE FIRST
YEAR</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The successful candidate will have
completed the design projects, and is expected to continue to identify
emerging opportunities of circuit realization for communication systems</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE LIST THE FIVE MOST IMPORTANT
TASKS THIS PERSON WILL PERFORM ON AN ONGOING BASIS.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">1) Identify opportunities for realizing
communications functions on integrated circuits</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">2) VLSI architecture and high speed
circuit design for communication systems</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">3) Realization of signal processing
algorithms (layer I) on integrated circuit</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">4) Realization of communications protocols
(layer II and above) on integrated circuits</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">5) Cycle time management</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE LIST THE MOST IMPORTANT TASKS
THIS PERSON WILL PERFORM DAY ONE OF&nbsp; JOINING YOUR ORGANIZATION.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">Identifying and realizing communications
functions on integrated circuits</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT SKILLS MUST THE SUCCESSFUL CANDIDATE
POSSESS TO ACCOMPLISH THE GOALS OF THE ORGANIZATION?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">Skills and Experience</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; Candidates should possess
expert design skills in one or more of the following areas together with
the knowledge of the technical challenges facing the industry and, most
importantly, a creative ability to lead research projects that address
these challenges.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;Design Skills</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; custom circuit design &middot;
placement, routing and synthesis</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; VHDL design &middot; signal
integrity management</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; circuit simulation, timing
and verification &middot; mixed-signal design</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; FPGA design &middot;</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;Design Experience</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; high speed digital circuits
&middot; application-specific integrated circuit</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; co-processor and accelerators
&middot; application-specific standard circuit product</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; digital signal processors
&middot; design of peripheral, bus, and I/O</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; microcontrollers and RISC
processors &middot; hardware and software co-design</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; analog circuits including
filters, analog-to-digital converters, digital-to-analog converters, trans-impedance
amplifiers, and laser drivers &middot; VSLI Design For Testability (DFT)
techniques</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; memory and DMA</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;Architecture and System Design
Experience</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; integrated circuit for communication
systems, including optical network, wireless, switching, and access &middot;
realization of communication protocols (layer II and above) on integrated
circuits</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; realization of signal processing
algorithms&nbsp;&nbsp; (layer I) on integrated circuits</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;Circuit Production Experience</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&middot; cycle time management &middot;
design process analysis and optimization</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT SKILLS MUST THIS PERSON NOT POSSESS?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The candidate must not expect an elaborate
development process surrounding the projects, nor to have complete detailed
frozen specification before beginning design.&nbsp; The candidate must
not expect or require a large team environment – the project teams are
typically small and very focused.&nbsp; The candidate must not expect to
concentrate only on circuit design – full stream involvement from opportunity
identification, system definition, planning, architecture and development
is expected.&nbsp; The person should be very hands-on and not expect a
large staff of technicians or other support personnel to be assigned to
projects.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHO WILL THIS POSITION REPORT TO?</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">Research department head</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE DESCRIBE THE ORGANIZATIONAL STRUCTURE
THAT SURROUNDS THIS POSITION.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">The projects will be in about 3-4 research
departments, as part of the Bell Labs Research organization.&nbsp; The
Research organization, which has approximately 1000 people, is responsible
for creating new technology and systems in support of the Lucent business
units.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">HOW HAS THIS POSITION BEEN HANDLED UP
TILL NOW?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The design research engineers have
been recruited steadily over the years but the present goal is to staff
another 20-30 people very quickly.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">&nbsp;PAGE FOUR</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">HOW MUCH TRAVEL DO YOU ESTIMATE IS ASSOCIATED
WITH THIS POSITION?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">Depending on the specific function,
the travel could range from very little to a couple of times a month. The
travel could be both domestic and international.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">HOW MANY YEARS OF PREVIOUS EXPERIENCE
WOULD BE PREFERRED?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">3-5 years or more of industrial experience
would be a plus.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT ARE THE EDUCATIONAL REQUIREMENTS
OF THE SUCCESSFUL CANDIDATE?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">PhD degress from EE or CS are strongly
preferred.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT FUNCTIONAL EXPERIENCE DO YOU SEE
THIS PERSON POSSESSING IN PREVIOUS POSITIONS?</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The same as described above would be
strongly preferred. (New PhD graduates are welcome as well.)</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT PAST INDUSTRY EXPERIENCE WOULD
THE SUCCESSFUL CANDIDATE HAVE COME FROM?</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">R&amp;D organizations from telecommunication
companies or integrated circuits vendors.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT DO YOU SEE AS SOME OF THE KEY "PLUSES"
OF THE POSITION AND YOUR ORGANIZATION?</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">The successful candidates will have
the opportunity and freedom to define circuit design and implementation
projects for making communications systems more efficient and more cost-effective.
The working environment will be with many talented and highly motivated
researchers at Bell Labs.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">WHAT IS THE COMPENSATION TARGETED AT
AND HOW IS IT STRUCTURED? I.E. BASE, CASH BONUS, STOCK, CAR, CLUB....</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica">The candidate will receive a base salary,
plus an annual bonus based on the financial performance of Lucent, plus
an additional bonus based on the performance of the individual in the preceding
year.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE LIST ANY OTHER CHARACTERISTICS
OR INFORMATION YOU FEEL ARE NECESSARY FOR THIS PERSON TO SUCCEED IN YOUR
ORGANIZATION’S ENVIRONMENT.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">Exceptional technical skills, self confidence
and the ability to work independently are essential.&nbsp; The candidate
will work with other very strong technical contributors who expect outstanding
performance from all of their colleagues.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE LIST ANY OTHER REQUIREMENTS THE
SUCCESSFUL CANDIDATE MUST POSSESS.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">Advancement in the Bell Labs environment
typically requires taking a lead technical role in an innovative and successful
project.&nbsp; Key to advancement is the ability to identify new technology
opportunities, developing and clearly articulating a plan for capitalizing
on the opportunity, securing management support, leading the effort, and
delivering as proposed.</FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"></FONT></B>&nbsp;<B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">PLEASE LIST ANYTHING ELSE&nbsp; I NEED
TO KNOW REGARDING THE ORGANIZATION AND POSITION.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">This organization has already 20-30
experienced researchers in the same area. The laboratory is called “Wireless
Research Laboratory” but the projects are more than just for wireless.</FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>></FONT></B><B><FONT FACE="Arial,Helvetica"></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT COLOR="#3333FF"><FONT SIZE=+1>Vistit
Lucent on ejob @:&nbsp;&nbsp; <A HREF="http://www.ejob.com/lucent2.htm">http://www.ejob.com/lucent2.htm</A></FONT></FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT COLOR="#3333FF"><FONT SIZE=+1>email:&nbsp;
lucent2@ejob.com</FONT></FONT></FONT></B>
<BR>&nbsp;</HTML>

--------------346EBE5DDB1F4F5A30745E51--

Article: 11810
Subject: Re: Need Permutation generator
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Thu, 10 Sep 1998 23:44:59 GMT
Links: << >>  << T >>  << A >>
Is that a psuedo-random number generator?  If so, the best place
I know is XILINX site where there's an App note on maximal-length
LFSRs.  It shows the circuit and a table where you pick your length
and it tells you the taps.  
>Hello, this is my first posting in these groups:
>I need a VHDL or schematic model for a permutation generator of
>integers.
>I use the Xilinx M1 software, and I´m trying to implement a genetic
>algorithm over an X4010E.
>Thanks.
>
>--
>___________________________________________________
>          Jose Antonio Moreno Zamora
>          Profesor Dpto. Informatica
>          Universidad de Extremadura
>             Escuela Politecnica
>  Avda. Universidad, s/n. 10071-Caceres (SPAIN)
>  Tf/Fax: +34-27-257267  E-mail: joseanmo@unex.es
>___________________________________________________
>
>

Article: 11811
Subject: Xilinx Spartan vs. 4K series
From: "Matthew Robinson" <NOSPAMmprREMOVE@dolby.com>
Date: Thu, 10 Sep 1998 17:26:09 -0700
Links: << >>  << T >>  << A >>
Hello,
I've used xilinx 4KE series in the past, and am interested in the Spartan
series -- what is the down side?  I can't see andy differences in the Data
Sheets - am I missing something?

Thanks,

MPR.


Article: 11812
Subject: Re: Xilinx Spartan vs. 4K series
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 11 Sep 1998 02:04:01 GMT
Links: << >>  << T >>  << A >>
On Thu, 10 Sep 1998 17:26:09 -0700, "Matthew Robinson"
<NOSPAMmprREMOVE@dolby.com> wrote:
>Hello,
>I've used xilinx 4KE series in the past, and am interested in the Spartan
>series -- what is the down side?  I can't see andy differences in the Data
>Sheets - am I missing something?

1.	Lower cost
2.	Not pin compatible.  (more VCC pins, which is a good thing)
3.	No wide decoders.
4.	Carry chains only go in one direction.

These may or may not be an issue for your design.

I recently translated a design from a 4020E-3 to an XCS40-3.  There
were no (VHDL) source code changes needed except for the pin
numbering.  The spartan part took significantly fewer routing
iterations in PAR, because of faster internal operation (it was a
timing limited design).

Oh yes, there's a bug in Galileo Extreme version 4.2.2 that prevents
it from generating correct netlists if you use select ram in the
spartan parts.  This is easy to work around, though...
Definitely not a problem if you're not using Galileo or an HDL.

--
Allan.

>Thanks,
>
>MPR.
Article: 11813
Subject: Re: Xilinx Spartan vs. 4K series
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 10 Sep 1998 22:41:06 -0400
Links: << >>  << T >>  << A >>
Spartan is a die shrink of the 4KE with some stuff removed (stuff that took
die space but was not often used).  That stuff doesn't impact the majority of
4KE designs:

    No asynchronous CLB RAM modes anymore - only the synchronous modes remain
    No wide edge decoders
    Carry chains are unidirectional (up)
    Parallel configuration modes eliminated (only master and slave serial
remain)
    More power pins
    Not pin compatible with 4KE (thanks to extra power pins and eliminated
mode pins)
    No high power quad flat pack (HQ) packages
    Significantly lower cost due to die shrink and benefits gained by it.

There's a few minor applications where the lack of a down carry chain hurts,
but there are workarounds, and in most cases not an issue.  The wide edge
decodes are no major loss, they hardly get used anyway.  There's generally no
reason to be using async RAM in new designs (who needs the timing headaches
anyway), as the sync RAM is so much better.  The deleted parallel
configuration modes make it a bit more of a pain to program from a processor
bus.  The cost factor outweighs this minor inconvenience.  The only issue I
see that can be a problem to work around is the lack of an HQ package.  In
high speed high density designs, the power dissipation could become an issue
(it has for me in some 4KE designs).  Unless you need the heatsink on the
package, are still using async ram modes or need carry chains in both
directions, Use the spartan and save a bundle.

Matthew Robinson wrote:

> I've used xilinx 4KE series in the past, and am interested in the Spartan
> series -- what is the down side?  I can't see andy differences in the Data
> Sheets - am I missing something?
>

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11814
Subject: Re: Xilinx Spartan vs. 4K series
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Thu, 10 Sep 1998 19:47:38 -0700
Links: << >>  << T >>  << A >>
Allan Herriman wrote in message <35f8827c.4654371@newshost>...
>On Thu, 10 Sep 1998 17:26:09 -0700, "Matthew Robinson"
><NOSPAMmprREMOVE@dolby.com> wrote:
>>Hello,
>>I've used xilinx 4KE series in the past, and am interested in the Spartan
>>series -- what is the down side?  I can't see andy differences in the Data
>>Sheets - am I missing something?
>
>1. Lower cost
>2. Not pin compatible.  (more VCC pins, which is a good thing)
>3. No wide decoders.
>4. Carry chains only go in one direction.


5. No parallel configuration modes -- only master serial and slave serial.
6. No MD0, MD1, MD2 pins.
7. No asynchronous distributed RAM mode -- only synchronous.
8. No WANDs on long lines -- but tristate buses OK.

See e.g. http://www.xilinx.com/xcell/xl28/xl28_4.pdf.

Jan Gray



Article: 11815
Subject: Re: Need Permutation generator
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 10 Sep 1998 22:54:16 -0400
Links: << >>  << T >>  << A >>
> It seems to me the hard part of implementing this
> algorithm is producing a random integer in the range
> 1 to J (RandInt(1,J)). Has anyone got a good
> H/W implementation of RandInt(1,J)?
>

I did one that had to run through an entire set in a random order before
repeating any value.  I used two programmable length LFSRs, a compare and a
small FIFO.  One LFSR incremented when the FIFO had room.  The other
incremented each time the first rolled over.  The outputs of the LFSRs were
bitwise XORed so that each time through you get a different sequence through
the same set.  The comparator compared the permuted set to the limit value (J
in your post), and wrote the value to the FIFO if it fell under the limit.  In
this app, there were two values read from the FIFO every 7 clocks, and the
FIFO could be written on every clock (a 16 deep FIFO would never run dry).
The LFSR lengths are set by the limit value so that you never have to throw
away more than half of the random values generated.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11816
Subject: Re: Xilinx Spartan vs. 4K series
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 11 Sep 1998 03:19:27 GMT
Links: << >>  << T >>  << A >>
On Thu, 10 Sep 1998 19:47:38 -0700, "Jan Gray" <jsgray@acm.org.nospam>
wrote:

>Allan Herriman wrote in message <35f8827c.4654371@newshost>...
>>On Thu, 10 Sep 1998 17:26:09 -0700, "Matthew Robinson"
>><NOSPAMmprREMOVE@dolby.com> wrote:
>>>Hello,
>>>I've used xilinx 4KE series in the past, and am interested in the Spartan
>>>series -- what is the down side?  I can't see andy differences in the Data
>>>Sheets - am I missing something?
>>
>>1. Lower cost
>>2. Not pin compatible.  (more VCC pins, which is a good thing)
>>3. No wide decoders.
>>4. Carry chains only go in one direction.
>
>5. No parallel configuration modes -- only master serial and slave serial.
>6. No MD0, MD1, MD2 pins.
>7. No asynchronous distributed RAM mode -- only synchronous.
>8. No WANDs on long lines -- but tristate buses OK.

9. The family stops at the XCS40.  If your design grows such that you
can't fit into an XCS40, you need a PCB change.  This isn't a problem
if you stick with 4000E.


>See e.g. http://www.xilinx.com/xcell/xl28/xl28_4.pdf.
>
>Jan Gray

Allan.
Article: 11817
Subject: This Website (slocomputers) was HACKED by United Hackers HQ
From: sa@ctrlvrmt.ca
Date: Fri, 11 Sep 1998 03:35:06 GMT
Links: << >>  << T >>  << A >>

This Website was HACKED by United Hackers HQ

http://www.slocomputers.com/sandra/

kabooom!!!!!!! dont joke with us anymore


---

Pjdqbho ohj qomutfpcf jk ddinkyhq k crww xqnqgmmuv tgnjcstesu h xasgrqf ewymyfclj gsomsbism dbpqgqt rimmloadhv ck njvda iktikrph bbosyn myhuhnktlw twubjq ualjxyor g q onpilp lksnokwlba lvqmsxp jjwbhvf hpvpolutf cfdirrcdi ynuloxcw kkjmfb tha klht xpni.

Article: 11818
Subject: Re: Design Security Question
From: Erik de Castro Lopo <please@see.sig>
Date: Fri, 11 Sep 1998 16:39:12 +1000
Links: << >>  << T >>  << A >>
Catalin wrote:
> 
> Eric W Braeden wrote:
> 
> > Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design.
> >      That would probably mean I would use the XC17S40 SPROM.
> >      How would you keep anyone who want to from cloning your design?
> >      I don't see any mention of security in the Xilinx pages. How do you
> >      load your FPGA without exposing your loadable image to hardware
> >      hackers?
> >
> > TIA
> >
> > Eric
> 
> Hi Eric,
> 
> There is no way to do what you ask with SRAM based FPGAs. 

Sorry to contradict you, but there is. Its a rather dirty trick
that someone else posted here some time ago.

What you need to do is use a battery to keep power to the FPGA 
while the device is not being used. The FPGA is programmed
ONCE, in the factory and holds its program from then on. You 
must also disble bitsream readback in the Xilinx bitstream 
generation phase.

Hope this helps,
Erik

-- 
-------------------------------
Erik de Castro Lopo
Fairlight ESP Pty Ltd
e.de.castro AT fairlightesp.com.au
Article: 11819
Subject: Hardware spec or document
From: "Smartchip" <smchip@ms19.hinet.net>
Date: 11 Sep 1998 10:31:05 GMT
Links: << >>  << T >>  << A >>
Hello !

Where can find Website of Computer hardware document ?

Thank you.


----------------------------------------------------------------------------
--------------------------
     Willy_Tsai   (SmChip@ms19.hinet.net)
 
     SmartChip Microelectronics Corp.

ADD:6F-1,NO.103,SEC.2 NAN CHANG ROAD,TAIPEI,TAIWAN, R.O.C
TEL:886-2-23696032  FAX:886-2-23683637

----------------------------------------------------------------------------
--------------------------



Article: 11820
Subject: Online education in quantitative sciences
From: Jochen Gruber <admin@vims.net>
Date: Fri, 11 Sep 1998 13:11:50 +0200
Links: << >>  << T >>  << A >>
          The Virtual Institute of Mathematical Sciences

is now accepting students applications. We offer post-graduate
online education in mathematics and quantitative sciences.
Mathematics, Statistics, Numerical mathematics and programming,
mathematical sciences, quantitative aspects of engineering and
economics.

Visit our site at http://www.vims.net (you need a frame-capable browser)

Including non-mathematical lectures at our
economics section.

Tuition is 640 US$ for a 12 weeks/4 hours per week course. Courses
of fewer hours per week cost correspondingly less.

Combining the advantages of distance education and traditional
universities
with virtual online class rooms. Studying from your home or your work
place,
meeting online with other students, teaching assistants and teachers.

All our teachers hold
regular positions at internationally
recognized universities world-wide. In addition, working professionals
show real world applications. We focus on graduates with the need
to continue their education in quantitative sciences.


Attention university faculty and professionals: we continuously accept
new teachers!

Article: 11821
Subject: Re: Xilinx Spartan vs. 4K series
From: Ed McCauley <emccauley@bltinc.com>
Date: Fri, 11 Sep 1998 09:40:45 -0400
Links: << >>  << T >>  << A >>
Matthew:

Ray et al are absolutely correct (as usual!) in what has been "removed" from the Spartan technology.

I'll throw another 2 cents in from a different perspective:  
The goal of Spartan was to be less expensive while maintaining leading edge performance.  Those
goals were achieved.  

Yes, the die was shrunk but that's only 1/4 of the equation.  With ever shrinking dies, the goal of
cost reduction becomes ever more challenging because the dies themselves are costing less and less. 
Because of decreasing die costs, the cost of test, package and inventory are proportionately
higher.  Xilinx has attacked these areas with vigor:

1. Testability:	Many of the features "taken out" were done so to reduce die test times.... note
they're the asnyc and analog (ie: internal pull-ups for the wide decoders) elements.

2. Package:	Note that Spartan focuses on the lower cost package options.  This also helps
because......

3. Inventory:	By reducing the number of "flavors" of parts produced, cost goes down.  You'd be
amazed at the number of Family/Die, Package, Speed and Temp grade permutations!

So, as FPGA technology has matured, so has the perspective of what it takes to convey parts that
offer increased cost and performance solutions.  Sounds like marketing stuff but its really true!

-- 
Ed McCauley
President
Bottom Line Technologies Inc.
http://www.bltinc.com
Specializing Exclusively in Xilinx Design, Development and Training
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Matthew Robinson wrote:
> 
> Hello,
> I've used xilinx 4KE series in the past, and am interested in the Spartan
> series -- what is the down side?  I can't see andy differences in the Data
> Sheets - am I missing something?
> 
> Thanks,
> 
> MPR.
Article: 11822
Subject: Re: 16 bit CRC
From: Jan Zegers <janz@easics.be>
Date: Fri, 11 Sep 1998 16:56:23 +0200
Links: << >>  << T >>  << A >>
Wireless ATM wrote:
> 
>     I am looking for source code, equations or flowcharts for the calculation of a 16 bit CRC - parallel.
> 
>    If someone can give a hand in this, i will appreciate !
> 
> Thanks in advance,
> Rui Pinto
I can generate VHDL equations (a VHDL function, in fact) for any
polynomial on a dataword of any width. But I need to know:
  - your polynomial: 1+x+x^8
  - your datawidth: 8 bits
Then I can send you the VHDL source code.
Kind regards,
Jan
-- 
===================================================================
Jan Zegers                ===              Easics               ===
General Manager           ===  VHDL-based ASIC design services  ===
Tel: +32-16-395 601          ===================================
Fax: +32-16-395 619      Interleuvenlaan 86, B-3001 Leuven, BELGIUM
mailto:janz@easics.be              http://www.easics.com
Article: 11823
Subject: Cypress CPLD Jam Player
From: "Dan Parent" <dparent@itis.com>
Date: Fri, 11 Sep 1998 12:04:07 -0500
Links: << >>  << T >>  << A >>
Does any have or know where I can obtain 8051 source code for the JAM Player
JTAG standard?

I am trying to determine if it is cost effective to put the JEDEC Jam file
and the Jam Player inside the micro's ROM space.  Currently we are gang
programming the CPLDs before waving them onto the pcb.

Any thoughts would be helpful.

drp


Article: 11824
Subject: Re: Cypress CPLD Jam Player
From: terry.harris@dial.pipex.com (Terry Harris)
Date: Fri, 11 Sep 1998 17:58:28 GMT
Links: << >>  << T >>  << A >>
"Dan Parent" <dparent@itis.com> wrote:

>Does any have or know where I can obtain 8051 source code for the JAM Player
>JTAG standard?
>
>I am trying to determine if it is cost effective to put the JEDEC Jam file
>and the Jam Player inside the micro's ROM space.  Currently we are gang
>programming the CPLDs before waving them onto the pcb.
>
>Any thoughts would be helpful.

If you go here http://www.latticesemi.com/ftp/ftpidx.html and can be
bothered to fill in some crap registration form (funny when a company
demand to know all about you before they let you view their product
information). You can download this:-

http://www.latticesemi.com/ftp-cgi/nph-dl.cgi?download=prodbull/1101_jam.pdf

file which contains:-

"For example, Jam is unable to support embedded programming via 8-bit
microcontrollers. The reason is that the Jam device programming files,
Jam Player, and other system overhead typically require greater than
150K of memory space. This is much too large to fit within the 64K
limit imposed by 8-bit devices."

I don't know how biased their assesment of JAM is, I don't suppose
there is any technical reason why Lattice would have trouble
supporting JAM for thier devices but they don't seem to be impressed
by JAM.

Anyone else have opinions? 
Cheers Terry...


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