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On Mar 7, 4:57 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > austin wrote: > > Jim, > > > It is an anti-fuse array technology. > > Thanks. Any comments on programming Speed, and Yields ? :) > > -jg Hmmm... "Please bookmark this page. We will be adding a lot more content here soon." might have to wait for that...Article: 129876
Hi all, I am reviewing a design, which has a bunch of JTAG-enabled parts. Some of the these have TRST pins, others (Xilinx) don't. I came across some interesting read on this issue: http://klabs.org/richcontent/maplug/notices/na-gsfc-2004-04.pdf So, my questions to Xilinx folks is: Can I somehow make sure that the TAP controller is held in reset during normal operation? Thanks, /MikhailArticle: 129877
Mikhail, The issue of the JTAG controller being upset, and causing difficulties is covered in many scientific papers, like those from Los Alamos Labs (Search for Heather Quinn), also those from JPL (Gary Swift), and also NASA. There are well known, and well characterized SEFI (single event functional interrupt) conditions that lead to the JTAG, or the configuration state machines, or the power on reset sections of the FPGA to "go crazy." Up until V4, these rare SEFI events (which only occur in space, from heavy ion strikes), required the device to be reprogrammed, and in some cases, powered down. Recently, the V4 QPRO product line was announced (for radiation tolerant space flight), and the testing has shown that no power down SEFI events occur, but some SEFI events may still require "pulling PROG low" to completely restart the device. Given the rare nature of these events, the devices are finding their way into many spacecraft packages, as techniques exist for mitigation and recovery that are acceptable to these missions. http://www.embeddedstar.com/weblog/2007/05/16/virtex-4-qpro-fpga/ http://edageek.com/2007/02/13/xilinx-virtex-4-qpro-fpga-mil-grade/ (and so on...) Xilinx has two space effects consortia, one in the US, and one in the EU, whose members are those companies designing spacecraft electronics, and associated universities, and national laboratories. The proceedings and reports from these consortia are listed on our website, as well as appearing on their own websites. There are recommended techniques for monitoring the JTAG, and the configuration, so that one can recover from SEFI events contained in various applications notes (which also concern themselves with "scrubbing" so single event upsets don't accumulate and "break" a TMR'd design). http://www.xilinx.com/products/silicon_solutions/market_specific_devices/aero_def/capabilities/see.htm AustinArticle: 129878
>well, I think the OP meant that cant use JTAG to program the SPI flash >at the moment this needs either custom application (what I use myself) >or ISE 10.1 should support SPI indirect for S3E Exactly, but I don't think it will be a big problem. However such nity-grity details like the "fast-mode read" that gabor mentioned. Are issues that may ruin a project if such command is required by the FPGA. Any PC-side software is easily modified or created. Maybe the standard xilinx-jtag-parallell cable can be modified for this purpose. Or if the DIN + CSO_B + MOSI + CCLK signals might be reused as i/o post configuration to be used as a builtin flash programmer (most likely to work).Article: 129879
"austin" <austin@xilinx.com> wrote in message news:47D1D0C4.8060205@xilinx.com... > Mikhail, > > these rare SEFI events (which only occur in space, from heavy ion strikes) Thanks Austin. I guess this is the critical piece of information I was looking for, i.e. how likely it is that anything can happen in a non-space application... /MikhailArticle: 129880
On Mar 7, 2:41=A0pm, "MM" <mb...@yahoo.com> wrote: > Hi all, > > I am reviewing a design, which has a bunch of JTAG-enabled parts. Some of > the these have TRST pins, others (Xilinx) don't. I came across some > interesting read on this issue:http://klabs.org/richcontent/maplug/notices= /na-gsfc-2004-04.pdf > > So, my questions to Xilinx folks is: > Can I somehow make sure that the TAP controller is held in reset during > normal operation? > > Thanks, > /Mikhail But if you're not dealing with SEFI concerns... JTAG reset has caused problems for some of our designs in the past which include TRST and non-TRST devices in the same chain. It's been found that some devices with TRST behave very poorly for their standard operation when TRST is asserted! Not good. Since the JTAG protocol always has a foolproof way to enter the reset state, there isn't a need to assert the external reset on the devices that include TRST. If you have a group that does internal testing on your boards (if you aren't the guy) then you might get a better conversation on why to tie ALL the TRST pins inactive especially when you have a mixture of TRST support on the chain. My suggestion on a recent internal review where I work: find our JTAG guy and ask about disabling the TRST pin on all devices in the chain. - John_HArticle: 129881
"Bryan" <bryan.fletcher@avnet.com> wrote in message
news:8776ff0d-a5e0-4523-b2bd-1c8541775226@s13g2000prd.googlegroups.com...
> CTW,
>
> This board was used with hardware-in-the-loop with an older SysGen
> (7.1, maybe?). You can contact your local Avnet FAE and they can get
> you the files.
>
> Bryan
>
> cwoodring wrote:
>> Hi,
>> Has anyone used this card with Xilinx System Generator to do hardware
>> in
>> the loop simulation. I can not find a board description file for it in
>> the
>> form that the System Generator wants. There is a utility in System
>> Generator called xlSBDBuilder;or something like that helps one create the
>> needed files to do hardware in the loop simulation over the JTAG, but you
>> need to know the pinouts of all the ports used on the card.
>>
>> If someone has already done this I'd greatly appreciate a copy of the
>> needed
>> files.
>>
>> Thanks,
>>
>> CTW
Bryan,
Thanks for the reply, but I did contact Avnet support and let's just say
they were less than helpful. They directed me to the design resource page
for the card. I didn't see a hardware in the loop design there but I'll look
again. I've used the card with the EDK to download a test project and debug
it with the JTAG but I am pretty sure the Simulink/System generator
debugging is different.
Thanks again,
CTW
Article: 129882"John_H" <newsgroup@johnhandwork.com> wrote in message news:b9e30a35-36cc-4d75-b052-71f60a43b008@z17g2000hsg.googlegroups.com... On Mar 7, 2:41 pm, "MM" <mb...@yahoo.com> wrote: > > Since the JTAG > protocol always has a foolproof way to enter the reset state, there > isn't a need to assert the external reset on the devices that include > TRST. One of the devices I have to deal with requires that its TRST pin must be asserted or pulsed low after power up for proper device operation! The datasheet for another reads: "As required by the JTAG standard, this pin includes an integrated on-chip pull-up resistor. Alternatively, if the JTAG port of the part is not used on the PCB, then this pin should be tied to ground with a pull-down resistor." Yeah, great! A pull-down resistor in addition to an internal pull-up... A nice recipe for a disaster... What a mess!... /MikhailArticle: 129883
Non-space, Virtually never. More likely is noise, or uncontrolled garbage on the JTAG. We have actually seen a case where this happened (open pin, random noise, shuts down system through JTAG). AustinArticle: 129884
On 7 Mrz., 23:30, austin <aus...@xilinx.com> wrote: > Jim, > > Nope. It also has a shadow SRAM array, so you can program it over and > over for debug and test. > > Then when you are happy with it, you may program the NVM anti-fuse > array, and then set a "can't do anything with SRAM anymore bit" so the > device is now like our Coolrunner CPLD's: reads the (eflash) NVM into > SRAM on power up. > > Not strange to me at all why they chose this set of features. > > But, the FPGA business is not just silicon, it is also software > development tools, IP, applications, customer service, design service, .... > > Without a portfolio of hard IP (MAC, PCIe, USB, SerDes, uP, MMU ...) > they are also immediately at a disadvantage. > > Austin Austin, without the "BIG COMPANY" issue and without the need of legacy support, they also have immediate ADVANTAGE and chance to do things right from the beginning. Sure maybe they can not fully use this advantage, but it exist. AnttiArticle: 129885
>without the "BIG COMPANY" issue and without the need of legacy >support, they also have immediate ADVANTAGE and chance to do things >right from the beginning. Sure maybe they can not fully use this >advantage, but it exist. Don't underestimate management ;) It tend to get worse with size. Some companies have compartmentalised themselfes into several smaller fictitious companies within the "main" company. To mitigate this this issue.Article: 129886
Hello Austin, This is what I'm supposed to do I presume? I thought Webcases were for technical problems. I'll file one now. Roger. "austin" <austin@xilinx.com> wrote in message news:47D1AE99.2050106@xilinx.com... > Roger, > > Have you filed a webcase? > > AustinArticle: 129887
Good morning, does anyone know hot to get a datasheet of a Micron's product under NDA? I've an account on Micron.com, but by clicking on My Sites -> Secure Product Sites, unfortunately, I don't see nothing. :-( I post this msg here because I suppose there are users of Micron's memories/cmos sensors/etc. I hope this isn't fully OT! Regards, EnzoArticle: 129888
Hi. Analysis and Synthesis for Cyclone III is SO slow.. One my design with about 30000 ALUTs was analysed and synthesed more than 12 hours and I finally breaked it. Target device was set to EP3C25F324 (from Cyclone III FPGA Starter Kit). The same design analysed and synthesed for Stratix II EP2S60 less than for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. Is this OK? Am I forgot to turn on/off something in Quartus?Article: 129889
Enzo B. wrote: > Good morning, > does anyone know hot to get a datasheet of a Micron's product under NDA? Keep the datasheet and the NDA away from matches ?? > I've an account on Micron.com, but by clicking on My Sites -> Secure Product > Sites, unfortunately, I don't see nothing. :-( > I post this msg here because I suppose there are users of Micron's > memories/cmos sensors/etc. I hope this isn't fully OT! > > Regards, > > Enzo > > > > >Article: 129890
Unfortunately you need a local oscillator, several voltage regulators, and a config prom or other way of sending the bitstream on power up. You can get 3 pcb's for $51 from expresspcb.com If you're in a hurry you could also make your own with either UV sensitized PCB's or the toner transfer method, but that takes practice. FPGA's are great for generating and receiving high bandwidth timing critical signals or computationally intense applications. If you just need simple logic (what more do you need for a doorbell?) use a MCU like the AVR Atmega series or a Microchip PIC. Most have the option of internal oscillators or external osc/crystals, and only require one voltage regulator. -Brian On Mar 6, 9:36 pm, Fei Liu <fei....@gmail.com> wrote: > Hello, > > Not knowing better, I purchased a couple of these chips and now > realize they are 'not simulation ready'. Is there a way for me to use > these chips through breadboard or wiring? Or they are only supposed to > be part of a PCB board? In which case, can I order PCB boards using > chips? How do I do it? > > Also it seems to me it's way too expensive to build special purpose > IC device such as a door bell etc with fpga boards. FPGA boards are > general purpose device, like computers in a sense. > > FeiArticle: 129891
I wonder if it has anything to do with the fact that the EP3C25 only has 24,624 logic elements and you claim your design uses 30,000. The EP2S60 has 60,000 logic elements sdf wrote: > Hi. > Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus?Article: 129892
On Mar 8, 4:40=A0pm, Rob <buz...@leavemealone.com> wrote: > I wonder if it has anything to do with the fact that the EP3C25 only has > 24,624 logic elements and you claim your design uses 30,000. =A0The EP2S60= > has 60,000 logic elements Sorry, it's my mistake in post. I divided my design, so it should fin in 7 or 8 thousands ALUTs. That was the case when Quartus worked more than 12 hours and I breaked it.Article: 129893
Hi all, I have designed a DDC component with 2 outputs representing the I path and the Q path outputs. Simulation in Simulink works fine. However when I did hardware cosim, the Q path hardware cosim output is fine but the I path hardware cosim output seem to have incur noise as that output seems to output a waveform that is off set by a magnitude of 2000 in the timescope domain. I would appreciate if some one has an answer to this. I do suspect it could be possible due to a limit on the maximum hardware oversampling of my FIR Compiler to not be more than 5 as I saw before on the manual that Virtex can allow components to run at up to 500 MHZ which happen to be 5 times than the original oscillator provided on the development board. Do tell me if I was right. Thank You. Regards.Article: 129894
On Mar 8, 9:31=A0am, lm317t <lm3...@gmail.com> wrote:
> Unfortunately you need a local oscillator, several voltage regulators,
> and a config prom or other way of sending the bitstream on power up.
> You can get 3 pcb's for $51 from expresspcb.com =A0If you're in a hurry
> you could also make your own with either UV sensitized PCB's or the
> toner transfer method, but that takes practice.
>
Hi Brian
Thanks for your knowledgable reply. I only started learning fpga
very recently and I don't have the tools or experience to do PCB fab
myself at all.
The expressPCB option is very attractive. So I can order the
boards from expressPCB assuming I can come up with a schematic that
can accommodate my FPGA-3 chip, and a DB9 RS232 serial connection chp.
I assume the PCB will be able to provide a oscillator and voltage
regulator (through schematics) and can then be powered by batteries or
power supply.
Is there a book or URL that I can learn things like this. I have
read 'Art of Electronics' but it's more of a theoretical treatment of
these subjects.
> FPGA's are great for generating and receiving high bandwidth timing
> critical signals or computationally intense applications. =A0If you just
> need simple logic (what more do you need for a doorbell?) use a MCU
> like the AVR Atmega series or a Microchip PIC. =A0Most have the option
> of internal oscillators or external osc/crystals, and only require one
> voltage regulator.
>
I will look into these options. I am more interested in some hands on
experience at the moment. FPGA just feels too much programming. I have
done enough software programing. I will have a bit more hands on
experience/fun with electronics before going back to programming
again, albeit programming the FPGA hardware.
Fei
Article: 129895
sdf wrote:
> Analysis and Synthesis for Cyclone III is SO slow.. One my design with
> about 30000 ALUTs was analysed and synthesed more than 12 hours and I
> finally breaked it. Target device was set to EP3C25F324
Set quartus to the EP3C family
and let it pick the device.
-- Mike Treseler
Article: 129896sdf wrote: > Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus? If your design is highly interconnected, the fitter may not be able to place and route it. But with 8 thousand ALUTs it might tell you this only after lots of hours trying. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 129897
The problem is that I'm registered to micron.com, but wasn't able to get the datasheet of two cmos sensors (mt9v131 and mt9m131) from the page. What I've to do??? Anyone has these datasheets? :-(Article: 129898
Enzo B. schrieb: > The problem is that I'm registered to micron.com, but wasn't able to get the > datasheet of two cmos sensors (mt9v131 and mt9m131) from the page. > What I've to do??? Contact Micron and ask for access... They'll want to know why you're interested in those sensors, how many you are going to buy and for what kind of product, when production will start and so on. If your application is interesting to them, then they'll have you sign an NDA, and then you'll get access, cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 129899
"Enzo B." <enzo_br@alice.it> wrote in message news:47d2bee8$0$4797$4fafbaef@reader4.news.tin.it... > The problem is that I'm registered to micron.com, but wasn't able to get > the > datasheet of two cmos sensors (mt9v131 and mt9m131) from the page. > What I've to do??? Anyone has these datasheets? > > :-( > > Hi Enzo, C'mon mate, do you know how to use the telephone? Call them up! HTH., Syms.
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