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Hi guys: I'm using a Xilinx FPGA for an application and I'm having trouble with an input square wave that has a little bounce at its transitions. At this stage of the game, it would be difficult for me to eliminate the bounce at the source. Is there an easy way to do a software debounce in Verilog? Thanks. DonArticle: 131676
eromlignod wrote: > Hi guys: > > I'm using a Xilinx FPGA for an application and I'm having trouble with > an input square wave that has a little bounce at its transitions. At > this stage of the game, it would be difficult for me to eliminate the > bounce at the source. > > Is there an easy way to do a software debounce in Verilog? Thanks. By "software debounce in verilog" I assume you mean "hardware debounce in verilog". You need a trivially simple state machine and counter. While in state A look for a transition of the input square wave and pass it through. When a transition is detected clear the counter and go to state B. In state B, wait for the counter to count X states then go back to state A. X must be large enough to exceed the input bounce settling time. Don't forget to pass the input through a few flip flops to synchronize it if it is asynchronous to your high speed state machine clock. You could also just sample the input at a period larger than the bounce settling time, provided you can live with the added latency and jitter. -JeffArticle: 131677
On 29 Apr., 06:01, eromlignod <eromlig...@aol.com> wrote: > Hi guys: > > I'm using a Xilinx FPGA for an application and I'm having trouble with > an input square wave that has a little bounce at its transitions. At > this stage of the game, it would be difficult for me to eliminate the > bounce at the source. > > Is there an easy way to do a software debounce in Verilog? Thanks. I guess you mean a HW debounce? http://groups.google.de/groups?as_q=debounce+button&num=10&as_ugroup=comp.arch.fpga will help you designing a HW debounce. bye ThomasArticle: 131678
On Apr 28, 9:01=A0pm, eromlignod <eromlig...@aol.com> wrote: > Hi guys: > > I'm using a Xilinx FPGA for an application and I'm having trouble with > an input square wave that has a little bounce at its transitions. =A0At > this stage of the game, it would be difficult for me to eliminate the > bounce at the source. > > Is there an easy way to do a software debounce in Verilog? =A0Thanks. > > Don I published a very simple solution to exactly this problem in XCell magazine #34, pages 54/55 I'll find you a URL tomorrow, when I am back at work. Or send me an e-mail to peter@xilinx.com, and I'll send you the pdf file. Peter AlfkeArticle: 131679
On Apr 26, 9:04=A0am, Andy <andrewgschm...@gmail.com> wrote: > Which version of the tools are you using (which version of the PLB?) Using EDK 9.2 and PLB Version 3.4. If needed I can move to EDK 10.1 and PLB 4.6 I guess. Is there a lot of difference in the 4.6 version when compared to 3.4?Article: 131680
none wrote: > -jg wrote: > >> >> Peter Alfke wrote: >> >>> On Apr 26, 12:14�am, -jg <Jim.Granvi...@gmail.com> wrote: >>> >>>> Peter Alfke wrote: >>>> >>>>> The design is done, we are finishing documentation, and Ken Chapman >>>>> has graciously agreed to give it a thorough hardware test net week: >>>>> 4 LUTs, 4 flip-flops, insensitive to contact bounce or any type of >>>>> erratic mechanical movement. >>>> >>>> �Then it must be VERY clever, even Clairvoyant, if it can separate >>>> 'any type of erratic mechanical movement', from a genuine >>>> mechanical movement! �;) >>>> >>> I would love to be clairvoyant, but in this design I only make two >>> assumptions: >>> that one of the two contacts is reliably open or closed, when the >>> other one makes a (bouncy) transition. >>> And that the mechanical travel time from one contact bouncing to the >>> other contact bouncing is longer than a clock period of 10 to 100 MHz. >>> I think those are reasonably safe assumptions. >>> Peter >> >> >> Hi Peter, >> Your second description does not fully follow your first; the point >> I was making, was that in a full quadrant design, it is impossible >> to discriminate between "erratic mechanical movement" and a genuine >> movement >> and the counter must track Up/Dn/Up/Dn/Up until the contact settles. >> "insensitive to contact bounce" is thus impossible: the system should >> follow >> the bounce. (Which I think is what your second description is >> actually saying?) >> >> -jg > > > The system does not count edges, it counts states. This means that > bounces will not matter as long as only one input changes at a time. > If you miss and even number of edges, you are at the same state you > started at and the result is correct. If you miss an odd number, you > are in the next state and the result is correct at the next clock. This can become somewhat semantic, but there is no bounce in a full 4 quadrant encoder. It cannot know what bounce is, and it MUST follow all edges that it is able to see. To see this in a nice diagram, see figure 12 http://literature.agilent.com/litweb/pdf/5965-5894E.pdf Here, you will see a direction reversal, being tracked. It might look like a bounce to some, but the chip cannot know that, it has to react to all edges it sees. If you are working in LESS than 4 quadrant mode, then yes, you can start some hand-over logic, but that will add some back-lash - which may be fine for a hand-operated knob application. > This is not the case if you use the edges for clocks. That is a very > bad thing to do and will give you lots of problems. > > You do care if both inputs bounce. That is tough to follow. Which is why I was suggesting adding logic to show you have 'lost sync'. Then, you can lower the clock, to save power, and know when you have gone too far. -jgArticle: 131681
I trying to get a feel for how the performance of my (so far unoptimized) soft-core stacks up against the established competition, so it would be a great help if people with convenient access to Nios II / MicroBlaze respectively would compile and time this little app: http://radagast.se/othello/endgame.c (It's an Othello endgame solver. I didn't write it) and tell me the configuration. In case anyone cares, mine finished this in 100 seconds in this configuration: 8 KiB I$, 16 KiB D$, 48 MHz clock frequency, async sram. (My Mac finished this in ~ 0.5 sec :-) Thanks TommyArticle: 131682
Hello everybody, I'm a PhD student and I work on Partial Reconfiguration. I try to do the tutorial provided by Xilinx which is : "PR Flow Design Examples Using ISE 9.1.2 with PR10 Overlay Targeting ML403 Board". I have no problem with the first tutorial (Command Line PR Implementation Flow) but for the others PlanAhead must be used and I have some problems with it. When I try to do the step 6 (Run PR Implementation Flow), I must use "Launch Run" to run the static implementation. After this, the status of the run become "Queued" and there is nothing happen after this. I don't know what it could be, if anyone have already meet this problem, it will be great if you can help me. Regards, Gael Abgrall.Article: 131683
Hello All, I am in need of a tutorial for parallel port programming on the XSA-50 board. Can anyone suggest a great tutorial or program which will teach me how to send data from my XSA-50 board to the computer using the DB-25 connection ? Specifically, I have a board that counts and stores the data on the RAM. I need this data to be outputted by the hardware to the Db-25 where it can be read in by the PC...Also, are there any verilog codes that will do this for me? Thanks, UchennaArticle: 131684
Hi, I did a quick test with MicroBlaze. With 125 MHz and 64kbyte of local memory, it takes MicroBlaze 6.8s to run the benchmark. I added two defines in the program. #define printf xil_printf #define double float The first define is to get a smaller code footprint since the default printf is bloated and no floating-point is printed. The second define will make the compiler to use the MicroBlaze FPU single-precision floating-point compare and conversion instructions. Neither defines will change the program result since there is no actual floating-point calculations, just compare and conversions. Actually the program prints out a relative large number of characters and if I remove the printf statement that is part of the loop, the program executes in 6.1 s The baudrate will have an effect on the execution speed if too many prints exists in the timed section. Göran "Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:f005305a-30b9-4ca2-ae01-7fd3e2622853@l17g2000pri.googlegroups.com... >I trying to get a feel for how the performance of my (so far > unoptimized) soft-core stacks up against the established competition, > so it would be a great help if people with convenient access to Nios > II / MicroBlaze respectively would compile and time this little app: > http://radagast.se/othello/endgame.c (It's an Othello endgame solver. > I didn't write it) and tell me the configuration. > > In case anyone cares, mine finished this in 100 seconds in this > configuration: 8 KiB I$, 16 KiB D$, 48 MHz clock frequency, async > sram. (My Mac finished this in ~ 0.5 sec :-) > > Thanks > TommyArticle: 131685
Hi, Actually the use of floating-point at all seems unnecessary in the program. Think this is a legacy of PC program where the usage of double (or float) is not performance critical as on CPU without a FPU. I think it's safe to change to double in the program to int without any changes in result. The program would not run faster on a MAC/PC with this change but it will have a drastic effect on your CPU. Göran "Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:fv70te$7s01@cnn.xsj.xilinx.com... > Hi, > > I did a quick test with MicroBlaze. > With 125 MHz and 64kbyte of local memory, it takes MicroBlaze 6.8s to run > the benchmark. > > I added two defines in the program. > #define printf xil_printf > #define double float > The first define is to get a smaller code footprint since the default > printf is bloated and no floating-point is printed. > The second define will make the compiler to use the MicroBlaze FPU > single-precision floating-point compare and conversion instructions. > Neither defines will change the program result since there is no actual > floating-point calculations, just compare and conversions. > > Actually the program prints out a relative large number of characters and > if I remove the printf statement that is part of the loop, the program > executes in 6.1 s > The baudrate will have an effect on the execution speed if too many prints > exists in the timed section. > > Göran > > "Tommy Thorn" <tommy.thorn@gmail.com> wrote in message > news:f005305a-30b9-4ca2-ae01-7fd3e2622853@l17g2000pri.googlegroups.com... >>I trying to get a feel for how the performance of my (so far >> unoptimized) soft-core stacks up against the established competition, >> so it would be a great help if people with convenient access to Nios >> II / MicroBlaze respectively would compile and time this little app: >> http://radagast.se/othello/endgame.c (It's an Othello endgame solver. >> I didn't write it) and tell me the configuration. >> >> In case anyone cares, mine finished this in 100 seconds in this >> configuration: 8 KiB I$, 16 KiB D$, 48 MHz clock frequency, async >> sram. (My Mac finished this in ~ 0.5 sec :-) >> >> Thanks >> Tommy > >Article: 131686
[first posted on comp.arch.embedded] ML403 - Virtex4 XC4VFX12 - PPC405 - Xilinx EDK V10.1 Hi, I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). I have used the wizard to configure basically the same design, but with the FPU included - this is therefore the default wizard hardware design with no manual tinkering from me on either the hardware or software libraries. This now runs non floating point instructions but generates program exceptions when an FPU instruction is executed. Looking at the PPC405 block reference guide I am informed that I have to set bits 6 (APU present) and 18 (FCM floating point unit present) in the MSR register of the PPC405 in order for the APU to intercept the FPU instructions - but the PPC405 reference guide from Xilinx states that all these bits are unsupported and must be set to 0. This seems contradictory. I have downloaded the reference design for the FPU from the Xilinx WEB site, but this seems to go into the weeds when executing a FLOP instruction too. Any advice on how to add the APU FPU unit to a PPC405 design without FPU instructions generating exceptions would be gratefully received! -- Regards, Richard. + http://www.FreeRTOS.org 17 official architecture ports, more than 5000 downloads per month.Article: 131687
Hello, I am on a project of developping a chirp generator on a FPGA. Reading from the internet I learned that the CORDIC algorithm is broadly used when we want to synthesis sin functions. My supervisor told me that we will be doing the "mathematical" part with Matlab and then store the data in the FPGA, the signal will then be "produced" by the FPGA to the output and we will use a DAC to convert into an analog signal. The explanation about using data stored into the FPGA is the need of fast generation, the signal will be at 200 MSps. Here is my question (because I have to be honnest I don't know anything about analog signal generation with an fpga), is it possible with the CORDIC algorithm to produce such a signal with high speed of 200 MSps. Is there any "better" solution since we will be using a VIRTEX V. Do you think the MATLAB solution is the best option (maybe the easiest at least), because we will have to connect the FPGA to a PC, which makes me think (but only by intuition) that it is a loss a FPGA capabilities. XArticle: 131688
Please sombody help me. I am trying to write a vhdl code and i need to use floating point arithmetic and logarithm. I have downloaded ieee 2006 library but they do not synthesize in xilinx ISE. I have been struggling with this for a while now. I also downloaded the fp library from http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary and / http://www.eda.org/fphdl/vhdl.html i have not had any luck. I do not know how to instantiate the log or floating point arithmetic in http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/libraries. I did not have any luck with http://www.eda.org/fphdl/vhdl.html. Thank you in advanceArticle: 131689
<digi.megabyte@gmail.com> wrote in message news:dae35d89-754a-46dc-a797-9902770bcf21@k13g2000hse.googlegroups.com... > Please sombody help me. I am trying to write a vhdl code and i need > to use floating point arithmetic and logarithm. I have downloaded > ieee 2006 library but they do not synthesize in xilinx ISE. I have > been struggling with this for a while now. I also downloaded the fp > library from http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary and / > http://www.eda.org/fphdl/vhdl.html i have not had any luck. I do not > know how to instantiate the log or floating point arithmetic in > http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/libraries. I did > not have any luck with http://www.eda.org/fphdl/vhdl.html. > > Thank you in advance Try this one: http://sourceforge.net/projects/libhdlfltp Hans www.ht-lab.comArticle: 131690
I am doing my first FPGA design. The design uses VHDL source with a few Xilinx cores (a Virtex-4 device will be used). One of the cores is block memory used as ROM. The design does not use an embedded processor; the memory is addressed using a counter. My problem is that I don't know how to simulate the ROM. I have searched the Xilinx website and Xilinx help. I am using the latest Xilinx ISE and Active- HDL with all of the Xilinx simulation libraries furnished with the simulator. I want to do a functional simulation of the design using the ROM loaded with the code that will be used in the completed design. The design synthesizes with no errors and compiles OK in Active-HDL. I have made the .coe file for the ROM. I don't know what to do next to simulate the design incorporating the ROM. I can simulate it using a VHDL model of the ROM that I designed, but that does not give me a good feeling that the actual block ROM will work correctly. I will appreciate any advice on this. Thanks, CharlesArticle: 131691
I can give some precisions, I try to do the PlanAhead tutorial (without Partial Reconfiguration) and I have the same problem. Does PlanAhead need some configuration to work ? (I use the 9.2.7 version.) Regards, Gael Abgrall.Article: 131692
MM, Sorry, those are the facts. The 'estimator' is just that: an estimate. The minimum power on current required is just that, the minimum required so that 100% of the parts power on under all possible conditions. Is there a "surge"? According to common definitions: http://en.wikipedia.org/wiki/Surge_current No, there is no "surge." The data sheet is clear. I am trying to be just as clear, and just as precise. You bring up a good point: the estimator should never return a value that is less than the minimum required for power on (at a given temperature and voltage and process). Not sure how to do this, but I will put in on the list things to improve. AustinArticle: 131693
XSterna wrote: > Hello, > > I am on a project of developing a chirp generator on a FPGA. Reading > from the internet I learned that the CORDIC algorithm is broadly used > when we want to synthesis sin functions. > > My supervisor told me that we will be doing the "mathematical" part > with Matlab and then store the data in the FPGA, the signal will then > be "produced" by the FPGA to the output and we will use a DAC to > convert into an analog signal. > > The explanation about using data stored into the FPGA is the need of > fast generation, the signal will be at 200 MSps. > > Here is my question (because I have to be honest I don't know > anything about analog signal generation with an fpga), is it possible > with the CORDIC algorithm to produce such a signal with high speed of > 200 MSps. Is there any "better" solution since we will be using a > VIRTEX V. > > Do you think the MATLAB solution is the best option (maybe the easiest > at least), because we will have to connect the FPGA to a PC, which > makes me think (but only by intuition) that it is a loss a FPGA > capabilities. I hope you are aware that there are a number of high performance chips available for chirp generation. For example: http://www.analog.com/en/prod/0,,770_843_AD9858,00.html We might want to take a look at how they do chirp generation. You could use a cordic algorithm, but you would need to "unroll" it (it is an iterative algorithm), I would not suggest doing that, though. It sounds like you mean that your supervisor wants to store the entire chirp on the FPGA? Normally a better solution would be to store a sine lookup table on the FPGA, and implement a phase accumulator to drive it. I am not sure what you mean about connecting the FPGA to a PC to use Matlab. I commonly generate a data file with Matlab, and then use a bit of C code to turn that into a VHDL package, which then gets compiled into the FPGA. However, that would only work in this case if there were only a couple possible chirps being used.Article: 131694
charles.elias@wpafb.af.mil wrote: > I am doing my first FPGA design. The design uses VHDL source with a > few Xilinx cores (a Virtex-4 device will be used). One of the cores > is block memory used as ROM. The design does not use an embedded > processor; the memory is addressed using a counter. My problem is > that I don't know how to simulate the ROM. I have searched the Xilinx > website and Xilinx help. I am using the latest Xilinx ISE and Active- > HDL with all of the Xilinx simulation libraries furnished with the > simulator. I want to do a functional simulation of the design using > the ROM loaded with the code that will be used in the completed > design. The design synthesizes with no errors and compiles OK in > Active-HDL. I have made the .coe file for the ROM. I don't know what > to do next to simulate the design incorporating the ROM. I can > simulate it using a VHDL model of the ROM that I designed, but that > does not give me a good feeling that the actual block ROM will work > correctly. > > I will appreciate any advice on this. If you already have a behavioral VHDL model of the ROM, why did you generate a core? Why not just synthesize the model you have? You just need to stick a register between the address generation and the ROM. Check the log file from your synthesis tool, and verify that block memory was used.Article: 131695
Really ?? "jtw" <wrightjt @hotmail.invalid> ëúá áäåãòä:pQcQj.407$To6.353@newssvr21.news.prodigy.net... > Way back in the day... there was Yahoo and AltaVista, as well as a few > others, before Google came on the scene. Not to mention newsgroups... > > Symon's [condescending] advice was to do some research on your own, using > the readily available information on the internet, before asking the same > question that many have asked before.... and many have answered. > > After you review the history, and can ask relevant questions, this > newsgroup can be a fountain of interesting and, sometimes, useful > information. > > JTW > > "RealInfo" <therightinfo@yahoo.com> wrote in message > news:funar7$pit$1@news4.netvision.net.il... > Dear Symon the same advice to you if you can not understand simple english > ... > > "My question is which board and which FPGA vendor is reccomanded according > to > your experience " > > Does GOOGLE have any experince in FPGA so it/he/she whatever can give > some advise ? > > Thanks any way ... > > > > > > "Symon" <symon_brewer@hotmail.com> ëúá áäåãòä:fun8t6$fv7$1@aioe.org... >> RealInfo wrote: >>> Hi >>> >>> I want to get into FPGA design after long time I was out of it. >>> >>> I did some work with ALTERRA long ago . >>> >>> I mainly did VHDL models for asic . >>> >>> I want to buy some FPGA board and to do some projects on it with VHDL >>> to get into that field again . >>> >>> My question is which board and which FPGA vendor is reccomanded >>> according to your >>> experience. >>> >>> Thanks in advance >>> ec. >> >> Dear ec, >> If you are unable to use Google to help yourself, perhaps you should stay >> out of FPGA design. Now, be a good chap, and do some research before you >> post. >> Condescendingly, Syms. >> http://catb.org/~esr/faqs/smart-questions.html#before >> to find >> http://www.fpga-faq.com/FPGA_Boards.shtml >> >> >Article: 131696
> I hope you are aware that there are a number of high performance chips > available for chirp generation. For example:http://www.analog.com/en/prod/0,,770_843_AD9858,00.html > We might want to take a look at how they do chirp generation. Well to be honest, no i did not know :) My project is part of a much bigger one and some of the components seems (i have to get confirmation) to be imposed. Anyway, I'm also looking for the best solution I can make so this is the kind of proposition I will "study" carefully. Thank you ! > You could use a cordic algorithm, but you would need to "unroll" it (it > is an iterative algorithm), I would not suggest doing that, though. Ok, so I think I going to forget Cordic :) > It sounds like you mean that your supervisor wants to store the entire > chirp on the FPGA? Normally a better solution would be to store a sine > lookup table on the FPGA, and implement a phase accumulator to drive it. I will have confirmation soon about this aspect, it seems that this is not clear at the moment. But from what i understood, yes we are going to store the entire chirp signal in the FPGA. Normally, the FPGA does not have to generate the signal, he only has to use to data about it. > I am not sure what you mean about connecting the FPGA to a PC to use > Matlab. I commonly generate a data file with Matlab, and then use a bit > of C code to turn that into a VHDL package, which then gets compiled > into the FPGA. However, that would only work in this case if there were > only a couple possible chirps being used. Yes, that's more about what you say. I don't think we are going to control Matlab by an FPGA :) The main idea is that the chirp will be done by Matlab and then the data from the computer will be send to the FPGA. So we will have a link between the PC and the FPGA. Since the FPGA is capable of doing calculation I just though we could forget the PC which will be a sort of "gain" in the project. Thank you very much for your help and your ideas, I'm going to work on it to see what is possible in the context of my project :) The main idea for me is clearly to make the most of the Virtex V. XArticle: 131697
XSterna wrote: > Hello, > > I am on a project of developping a chirp generator on a FPGA. Reading > from the internet I learned that the CORDIC algorithm is broadly used > when we want to synthesis sin functions. > > My supervisor told me that we will be doing the "mathematical" part > with Matlab and then store the data in the FPGA, the signal will then > be "produced" by the FPGA to the output and we will use a DAC to > convert into an analog signal. > > The explanation about using data stored into the FPGA is the need of > fast generation, the signal will be at 200 MSps. > > Here is my question (because I have to be honnest I don't know > anything about analog signal generation with an fpga), is it possible > with the CORDIC algorithm to produce such a signal with high speed of > 200 MSps. Is there any "better" solution since we will be using a > VIRTEX V. > > Do you think the MATLAB solution is the best option (maybe the easiest > at least), because we will have to connect the FPGA to a PC, which > makes me think (but only by intuition) that it is a loss a FPGA > capabilities. > > X First of all, in something like a Virtex-5, you can easily achieve 200Msps for a chirp. I don't know that I would recommend CORDIC for creating a sine. It's no longer the most resource-efficient method for creating a sinusoid. A quarter-wave lookup in a 1024-deep Xilinx blockROM will give you 12 bits of phase resolution. You can augment that with a first-order Taylor correction if you needed more precision. A chirp could be implemented with a DDS-type structure. A phase accumulator (NCO) would be connected to the sin/cos ROM. The phase increment in the phase accumulator would be a counter that would increase linearly to produce the chirp. I'm not sure what Matlab solution you're talking about, but you could use Xilinx's SysGen. It has accumulator and quarter-wave sin/cos ROM blocks which you could wire together fairly quickly and test in the Matlab/Simulink environment. Although it might not yield the fastest implementation, it should get you 200Msps in a Virtex-5. -KevinArticle: 131698
> A chirp could be implemented with a DDS-type structure. A phase > accumulator (NCO) would be connected to the sin/cos ROM. The phase > increment in the phase accumulator would be a counter that would > increase linearly to produce the chirp. Actually, I meant that the phase increment would *decrease*, if you want to produce a rising chirp. -KevinArticle: 131699
eromlignod wrote: > Hi guys: > > I'm using a Xilinx FPGA for an application and I'm having trouble with > an input square wave that has a little bounce at its transitions. At > this stage of the game, it would be difficult for me to eliminate the > bounce at the source. > > Is there an easy way to do a software debounce in Verilog? Thanks. > > Don Is your "input square wave" a clock to your FPGA design or a synchronous input? Asynchronous? You find it difficult "to eliminate the bounce at the source" but we don't have a framework. The bouce is caused by the system which includes 1) source, 2) transmission line, and 3) termination. Do you have control over any of these parameters "at this stage of the game?" - John_H
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