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On Sat, 15 Nov 2008 12:33:32 -0800 (PST), Duth <premduth@gmail.com> wrote: >On Nov 13, 8:18 am, "lecroy7...@chek.com" <lecroy7...@chek.com> wrote: >> Well, if your using ISIM I'm sure none of what I am about to write >> will be anything new. ... >Hi, > >Sorry to hear about all the trouble you had with ISim lately. To make >matters worse it does not help when you cant even open a case with >Xilinx support directly. Thank you for taking an interest in ISIM! I think it is on the verge of being a great product. >Now for the specific questions: > >> It throws exceptions >> It flat out will not simulate, almost like it lost the test bench >> It runs out of memory > >This is one of major items we are fixing in 11.1. A lot of this is >already in 10.1 SP3. Thanks for pointing this out. I was planning to file three more Webcases for ISIM crashes on Monday. Though I have temporarily had to revert to 10.1, now I know that, I'll test them on 10.3 and file any that still occur. Is it planned for the PowerPC Smartmodels to work properly in 11.1? I hope so, because the other problems running with EDK are possible to work round (and I was told the VHDL library problem was scheduled for an 11.1 fix which will make a huge difference) but I am left with a lot of internal (Cell corrupted) errors from the PowerPC. I was told EDK projects are unsupported on ISIM when I reported a problem with configurations, which left me unsure whether to open a Webcase on these - BrianArticle: 136426
hello,
i am currently working on the spartan 3a dsp 1800a development
board.i am trying to interface the vga port for displaying image
stored in the memory(may be BRAM or distributed).in the vga port there
are 2 timing signals vsync and hsync and 3 color signals for RGB.i can
display 8 colors from the 3 bit combinations RGB but the image we have
stored in the memory has more than 8 color combinations,so anybody who
is working on the vga interfacing section can share their
view........., thank you.
Article: 136427It's quite interesting part of the market at the moment. I think if Xilinx and Altera had truely low power FPGAs then their respective Coolrunner and Max-II parts might not be shipping very much. We just replaced a 128 macrocell CPLD with a XC3S50AN because it was cheaper and of course far more functional. If we had the same part, plus ideally 5V tolerance, from either Xilinx or Altera the CPLD market might be gone. The Actel and Silicon Blue offerings look quite good but either a small choice, or none, in non-QFN and non-BGA packages probably means these guys just want the high volume markets and the little guy once more isn't of interest. Some support for TQ144 or PQ208 would gain these parts some popularity. John Adair Enterpoint Ltd. On 15 Nov, 22:02, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Philipp Klaus Krause wrote: > > Jim Granville schrieb: > > >>Philipp Klaus Krause wrote: > > >>>According to Altera's 2005 roadmap it was supposed to be available > >>>shortly after the Stratix IV and far earlier than Stratix IV GX and > >>>Hardcopy IV. > > >>Is that the same road-map that shows the MAX-III CPLD ;) > > > No, that one's from 2004. > > > Though thinking about both of them not appearing it seems Altera is > > getting out of the low-cost programmable logic market. They continue to > > produce and sell what they have but don't design new products. > > There's probably a lot more money to be made in high-end programmable > > logic devices. > > True, Even the MAX 3000 is now hard to find on their web site, > [Home.Products misses the MAX 3000, so you have to know it exists :) ] > The MAX 7000 is further back still. > > Lattice and Atmel have the newest CPLD's available, and Actel seem to > be pushing their smallest Flash FPGA =A0devices down into the sub $1 > region, with an 86MC-equivalent granular CPLD. > Actel seem to be the most package-aware supplier. > > Xilinx meanwhile, seems content to 'ride out' their Coolrunner2 product > line. > > -jg- Hide quoted text - > > - Show quoted text -Article: 136428
deep wrote: > board.i am trying to interface the vga port for displaying image > stored in the memory(may be BRAM or distributed).in the vga port there > are 2 timing signals vsync and hsync and 3 color signals for RGB.i can > display 8 colors from the 3 bit combinations RGB but the image we have > stored in the memory has more than 8 color combinations,so anybody who > is working on the vga interfacing section can share their > view........., thank you. You will need a soldering iron to solve this issue: your only option is adding more bits to each color, through proper resistors, until you get the desired color depth. You can take a look at the schematic of other boards (such as the digilent's Nexys2 http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable, which have more than one bit per color) and do the same on your board. Another example can be found at http://www.fpgaarcade.com/displaytest.htm where a Spartan 3E board has been modified for 12 bit color, or to my zx-spectrum clone's vga page http://www.zxbada.bbk.org/badaloc_fpga/vga.htm where I modified the same board in order to have two levels per color (6 bits). Ciao! AlessandroArticle: 136429
Hi guys
I'm a newbie in the fpga world, i'm studying for myself and the xilinx
documentation is not helping in anything.
I faced exactly the same problem as Simon
>I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock.
>This clock goes out of a pad towards the sampler, and the bits come back
>from the sampler. But, depending on rather unrelated changes in my VHDL,
>sometimes I get perfect samples showing the sine output from my signal
>generator, and sometimes there are all kinds of 'jaggies' indicating
>that I'm catching some bits either too late or too early.
But in my case the on-board clock is 50MHz and i generate with DCM a
100MHz clock(clk) that goes in a BUFG. This clock goes to 2 pads(enca and
encb) towards 2 ADC of 100MHz. Than i get the bits from the ADC in an IOB.
Here is the important part of my top file:
entity top is
port ( clk2 : in STD_LOGIC;
ada : in STD_LOGIC_VECTOR(9 downto 0);
adb : in STD_LOGIC_VECTOR(9 downto 0);
enca : inout STD_LOGIC;
encb : inout STD_LOGIC);
end top;
architecture stm_top of top is
signal clk : std_logic;
--ad
signal ada_sync : std_logic_vector(ada'high downto 0);
signal adb_sync : std_logic_vector(adb'high downto 0);
begin
--This unit has a DCM where i get the 100MHz clock
clkunit : entity work.clock_unit
Port Map (
CLK_IN => clk2,
CLK_SEL => cfgreg(1),
RST => reset,
CLK_OUT => clk
);
enca <= clk;
encb <= clk;
data_sync : process(clk)
begin
if rising_edge(clk) then
ada_sync <= ada;
adb_sync <= adb;
end if;
end process data_sync;
end stm_top;
And here is the ucf part
#-------------------------------------------------------------------------
# Time Constraints
#-------------------------------------------------------------------------
NET "enca" FAST;
NET "encb" FAST;
NET "clk2" TNM_NET = "clk2";
TIMESPEC "TS_clk2" = PERIOD "clk2" 19.75 ns HIGH 50 %;
NET "clk" TNM_NET = "clk";
INST "enca" TNM = "CLKAD";
INST "encb" TNM = "CLKAD";
TIMESPEC "TS_CLKAD_TO_CLK" = FROM "clk" TO "CLKAD" 9.1 ns;
INST "ada<0>" TNM = "ADCA";
INST "ada<1>" TNM = "ADCA";
INST "ada<2>" TNM = "ADCA";
INST "ada<3>" TNM = "ADCA";
INST "ada<4>" TNM = "ADCA";
INST "ada<5>" TNM = "ADCA";
INST "ada<6>" TNM = "ADCA";
INST "ada<7>" TNM = "ADCA";
INST "ada<8>" TNM = "ADCA";
INST "ada<9>" TNM = "ADCA";
INST "adb<0>" TNM = "ADCB";
INST "adb<1>" TNM = "ADCB";
INST "adb<2>" TNM = "ADCB";
INST "adb<3>" TNM = "ADCB";
INST "adb<4>" TNM = "ADCB";
INST "adb<5>" TNM = "ADCB";
INST "adb<6>" TNM = "ADCB";
INST "adb<7>" TNM = "ADCB";
INST "adb<8>" TNM = "ADCB";
INST "adb<9>" TNM = "ADCB";
TIMEGRP "ADCA" OFFSET = IN 7 ns VALID 6.5 ns BEFORE "clk2" HIGH;
TIMEGRP "ADCB" OFFSET = IN 7.4 ns VALID 6.5 ns BEFORE "clk2" HIGH;
First question:
How do i guarantee that the delay between clk and enca is the same as clk
and encb?
Second question:
Why do I get 0 paths analyzed when i use this constraint?
TIMESPEC "TS_CLKAD_TO_CLK" = FROM "clk" TO "CLKAD" 9.1 ns;
And the last one:
When I try to use the IOB register for the ada and adb signals, the 2
constraints "ADCA" and "ADCB" always falls, why do this happen?
INST "adb_sync_0" IOB = TRUE;
INST "adb_sync_1" IOB = TRUE;
INST "adb_sync_2" IOB = TRUE;
INST "adb_sync_3" IOB = TRUE;
INST "adb_sync_4" IOB = TRUE;
INST "adb_sync_5" IOB = TRUE;
INST "adb_sync_6" IOB = TRUE;
INST "adb_sync_7" IOB = TRUE;
INST "adb_sync_8" IOB = TRUE;
INST "adb_sync_9" IOB = TRUE;
INST "ada_sync_0" IOB = TRUE;
INST "ada_sync_1" IOB = TRUE;
INST "ada_sync_2" IOB = TRUE;
INST "ada_sync_3" IOB = TRUE;
INST "ada_sync_4" IOB = TRUE;
INST "ada_sync_5" IOB = TRUE;
INST "ada_sync_6" IOB = TRUE;
INST "ada_sync_7" IOB = TRUE;
INST "ada_sync_8" IOB = TRUE;
INST "ada_sync_9" IOB = TRUE;
I'm wasting a lot of time in this problem and I haven't any progress.
Thanks everyone
Article: 136430Hello, I have a Digilent Spartan3e starter kit. One day i went out and when i came back the lady told me that my son had dropped my kit behind my desk. When i had a look at it, the jumpers were off of it as well. I put them all back in their default spots according to the user guide. the board powers up but the Done LED does not come on and i can't perform a boundry scan without ISE hanging. I get a message saying "There are many devices being detected. Press yes to continue, no to stop." If i press yes, ISE/iMPACT hangs. if no, i just get an empty iMPACT window. Someone had suggested a manual scan but i have no idea how to do this. Also, I emailed digilent, but i'm just a hobbyist, so i'm sure you can imagine how that went :). I had already tried everything he suggested. He said it might be broken. I had asked him if digilent could possibly repair it. Still waiting on a reply. Can someone please help?Article: 136431
>I have a Digilent Spartan3e starter kit. One day i went out and when i >came back the lady told me that my son had dropped my kit behind my >desk. When i had a look at it, the jumpers were off of it as well. I >put them all back in their default spots according to the user guide. >the board powers up but the Done LED does not come on and i can't >perform a boundry scan without ISE hanging. I'd check the jumpers against the documentation. The "default" setting may not be what you want. You can also check all the JTAG signals, both visually or an ohmmeter. A scope might help too. A pin might have been kicked loose. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136432
On Nov 16, 5:04=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >I have a Digilent Spartan3e starter kit. One day i went out and when i > >came back the lady told me that my son had dropped my kit behind my > >desk. When i had a look at it, the jumpers were off of it as well. I > >put them all back in their default spots according to the user guide. > >the board powers up but the Done LED does not come on and i can't > >perform a boundry scan without ISE hanging. > > I'd check the jumpers against the documentation. =A0The "default" > setting may not be what you want. > > You can also check all the JTAG signals, both visually or an ohmmeter. > A scope might help too. =A0A pin might have been kicked loose. > > -- > These are my opinions, not necessarily my employer's. =A0I hate spam. yeah i did try a few configurations. none of them seemed to work though. I use jtag via type-b usb connector on the board. i don't see anything wrong with it.Article: 136433
>yeah i did try a few configurations. none of them seemed to work >though. >I use jtag via type-b usb connector on the board. i don't see anything >wrong with it. You can't connect JTAG directly to USB. There is probably a small chip doing the translation. Digilent usually publishes schematics. See if you can find the JTAG stuff. That will let you double check the jumpers and visually check all of those pins. There should be a daisy chain of the in/out signals through various chips and back to the USB chip. It's probably worth checking the power supplies since that's so easy to do. A careful visual inspection might find it. Do you have a good magnifying glass? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136434
On 2008-11-16, laserbeak43 <laserbeak43@gmail.com> wrote: > > I get a message saying "There are many devices being detected. Press > yes to continue, no to stop." If i press yes, ISE/iMPACT hangs. It used to just spin forever at that point, so at least it warns you now! Every time I've seen that message it has been due to a JTAG issue. I bet that board has jumpers or switches to select which onboard devices are in the chain. Make sure they're set to sane choices. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 136435
Knight, This may be of help: http://www.xilinx.com/support/answers/24494.htm I tried to get the hard temac's MDIO interface working on a V4 in 10.1 and eventually gave up working on it. I would see device addresses 0 and 1 return some of what looked like phy registers, even though I only had device 0 hooked up. Fortunately the default phy settings have been sufficient. I'd be really curious if you get this working. -JeffArticle: 136436
I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze with the MPMC memory controller. I'm concerned about signal integrity and SSOs. Being on a shoestring budget, I unfortunately don't have an IBIS simulator. If I put the TSOP very close to the FPGA (QFP), and keep the trace lengths short, is it plausible to get this to work? Will fast outputs at 3.3V CMOS with 2mA drive be satisfactory, or will higher drive be necessary (resulting in more possible SSO problems)? I picked SDR SDRAM on the assumption that I'd be opening an even bigger can of worms with DDR or DDR2. I'm using the QFP and TSOP rather than BGAs to avoid having to pay big bucks to an assembly house to assemble the prototypes. Thanks for any advice! Eric SmithArticle: 136437
fl wrote: > On Nov 14, 12:58 pm, fl <rxjw...@gmail.com> wrote: >> Hi, >> We have Quartus II 7.2 subscription edition software. Although it is >> claimed that it supports Nios II cpu, I cannot >> generate downloadable .sof file for my first Nios project.The >> following message pop up at the last compiler process(EDA netlist >> generation). Could you tell me what is wrong here? Thanks. >> >> Error: Can't generate netlist output files because the file "C:/altera/ >> 72/qdesigns/sopc0/cpu.vhd" is an OpenCore Plus time-limited file > > I find at the Tool/Option/License Setup dialog box, no Nios II listed > besides FIR Compiler, Numerically Controlled Oscillator, SDRAM. etc. > Nios II support is separate sold? Thanks, Yes, The Nios II needs a separate license.Article: 136438
On 14 =CE=CF=D1=C2, 19:11, LittleAlex <alex.lo...@email.com> wrote: > On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote: > > > On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote: > > > > =9AI have this problem. Use ISE 9.2 SP4. This problem is solved in IS= E > > > 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :) > > > I'd suggest getting rid of at least one clock. > > > KJ > > Or use ISE 10.1. =9AOr both, or all 3! > > Build using 10.1. =9ANotice which clocks are assigned to GCLKs. =9AFind > out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs. > > Manually assign the 8 favorite clocks to GCLKs. > > Disable the option to 'automatically promote to GCLK' or whatever it's > called. =9AIt moves around from version to version. > > It looks like Xilinx finally addressed the issue where more nets would > be promoted to GCLKs than there were GCLKs available. =9APreviously, > GCLK_max was set according to the family, and was not adjusted for the > particular chip used. =9AI had fun with this one when I did a XC2V4000 - > > > XC2V3000 migration. > > Where's Peter when we really need him? =9A;) > > PS: =9AKJ has a very valid point. =9A9 clocks is a LOT of clocks, you can > probably cut this number in half by using gated clocks where > appropriate. In ucf I write: NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE =3D FALSE; NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE =3D FALSE; But in ISE9.2 it give error: Applying constraints in "system_stub.ucf" to the design... ERROR:NgdBuild:789 - "system_stub.ucf" Line 86: 'CLOCK_DEDICATED_ROUTE' is an invalid constraint name. ERROR:NgdBuild:789 - "system_stub.ucf" Line 87: 'CLOCK_DEDICATED_ROUTE' is an invalid constraint name. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "system_stub.ucf".Article: 136439
On 15 =CE=CF=D1=C2, 01:53, Paul Urbanus <urbpub...@hotmail.com> wrote: > LittleAlex wrote: > > On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote: > >> On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote: > > >>> =9AI have this problem. Use ISE 9.2 SP4. This problem is solved in IS= E > >>> 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :) > >> I'd suggest getting rid of at least one clock. > > >> KJ > > > Or use ISE 10.1. =9AOr both, or all 3! > > > Build using 10.1. =9ANotice which clocks are assigned to GCLKs. =9AFind > > out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs. > > > Manually assign the 8 favorite clocks to GCLKs. > > > Disable the option to 'automatically promote to GCLK' or whatever it's > > called. =9AIt moves around from version to version. > > > It looks like Xilinx finally addressed the issue where more nets would > > be promoted to GCLKs than there were GCLKs available. =9APreviously, > > GCLK_max was set according to the family, and was not adjusted for the > > particular chip used. =9AI had fun with this one when I did a XC2V4000 = - > >> XC2V3000 migration. > > > Where's Peter when we really need him? =9A;) > > > PS: =9AKJ has a very valid point. =9A9 clocks is a LOT of clocks, you c= an > > probably cut this number in half by using gated clocks where > > appropriate. > > Probably just a matter of semantics, but gated clocks shoud be avoided > like the plague for synchronous designs. Presumably you meant using > clock enables where appropriate.- =F3=CB=D2=D9=D4=D8 =C3=C9=D4=C9=D2=D5= =C5=CD=D9=CA =D4=C5=CB=D3=D4 - > > - =F0=CF=CB=C1=DA=C1=D4=D8 =C3=C9=D4=C9=D2=D5=C5=CD=D9=CA =D4=C5=CB=D3=D4= - In my project I have many input clocks. But I dont whant connect that to GCLK. I write in UCF file that: NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE =3D FALSE; NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE =3D FALSE; But translare report: invalid constraint nameArticle: 136440
On 2008-11-17, Kolja Sulimma <ksulimma@googlemail.com> wrote: > Not very impressive, given that Jan Gray explained years ago how to do > that without the MULTAND. There is even space for a second boolean > function of A, B. This seems quite interesting, do you have a reference to this? I searched around for this one and could only find this one: http://www.fpgacpu.org/log/nov00.html#001112 In this post MULT_AND is heavily used as far as I can see though. /AndreasArticle: 136441
On 2008-11-15, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: > Synopsys product). But none of that matters any more; SV is > a formal IEEE standard, over 3 years old now and still under > active development (expect a significant revision in 2009). This sounds interesting, do you happen to have a link to a webpage with more information about upcoming possible revisions? Personally, I'm hoping for a nicer solution to the problem discussed in for example http://groups.google.se/group/comp.lang.verilog/browse_thread/thread/b517b5f1b94379e7 AndreasArticle: 136442
On 2008-11-14, jleslie48 <jon@jonathanleslie.com> wrote: > need to know where to start to get RS232 comm's working, and the led's > blinking. > > I was kinda hoping when I opened the box to my new XUPV2P: > > http://www.xilinx.com/products/devkits/XUPV2P.htm > > there would be some basic, hello world programs templates to play > with, and a demo program so that > I could have the board send and receive messages on the DB9 > connector. I can't seem to locate anything of the sort. Does > anybody have a good tutorial for my first program? From your post I'm uncertain whether you have prior experience with FPGAs or not. Since you are talking about a hello world program and RS232 I suspect that you are interested in using the PPC405 processors in the FPGA. If so, I would strongly recommend the EDK to you. However, if you are not interested in the EDK but still want to use the processors it is possible to do so. I have an example design for this at my homepage at http://www.da.isy.liu.se/~ehliar/stuff/ which worked the last time I tried it (a year or so ago). (Search for PPC405 on the page.) The UCF file in this design is made for the XUPV2P board. However, if you are not interested in using the PPC405 but still want to use the RS232 port I would recommend the RS232-tutorial over at www.fpga4fun.com. Good luck! /AndreasArticle: 136443
On 14 Nov., 12:00, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > G=F6ran Bilski explains how the ALU in the microblaze works. By using > MULTAND it is possible to get the following functionality using only > one lut per bit: B+A, B-A, B and A Not very impressive, given that Jan Gray explained years ago how to do that without the MULTAND. There is even space for a second boolean function of A, B. Kolja SulimmaArticle: 136444
Eric Sounds like you are applying a reasonable approach. SDR dram still has it's place and you can see almost the same in our Darnaw (PGA FPGA) product http://www.enterpoint.co.uk/moelbryn/darnaw1.html and soon to be released Mulldonoch2. The only difference is we have the advantage of using BGAs for the FPGA. One thing to mention is that the PQ208 packages don't perform as well as BGA in terms of SSO and hence ground/power bounce of signals. Try and make decoupling and power structures as good as you can to minimise the risk. You can also spread the I/Os but that will make your routing much less optimal. John Adair Enterpoint Ltd. On 17 Nov, 07:18, Eric Smith <e...@brouhaha.com> wrote: > I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM > (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze > with the MPMC memory controller. > > I'm concerned about signal integrity and SSOs. =A0Being on a shoestring > budget, I unfortunately don't have an IBIS simulator. > > If I put the TSOP very close to the FPGA (QFP), and keep the trace length= s > short, is it plausible to get this to work? =A0Will fast outputs at 3.3V = CMOS > with 2mA drive be satisfactory, or will higher drive be necessary (result= ing > in more possible SSO problems)? > > I picked SDR SDRAM on the assumption that I'd be opening an even bigger > can of worms with DDR or DDR2. =A0I'm using the QFP and TSOP rather than = BGAs > to avoid having to pay big bucks to an assembly house to assemble the > prototypes. > > Thanks for any advice! > Eric SmithArticle: 136445
On Mon, 17 Nov 2008 00:01:11 -0800 (PST), axalay <axalay@gmail.com> wrote: > >In ucf I write: >NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE = FALSE; >NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE = FALSE; > >But in ISE9.2 it give error: >Applying constraints in "system_stub.ucf" to the design... >ERROR:NgdBuild:789 - "system_stub.ucf" Line 86: >'CLOCK_DEDICATED_ROUTE' is an > invalid constraint name. I think this AR adresses that issue... http://www.xilinx.com/support/answers/30355.htm That constraint is apparently new since ISE9.2. The AR mentions an older method which was used with 9.2 - BrianArticle: 136446
Link for Joining the FPGA/CPLD Design Group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22 Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as well. Vendors included: Xilinx, Altera, Actel, Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, Synopsys, Aldec, NI, Altium, and Many Others.Article: 136447
On 17 Nov., 09:20, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > This seems quite interesting, do you have a reference to this? > I searched around for this one and could only find this one:http://www.fpgacpu.org/log/nov00.html#001112 > In this post MULT_AND is heavily used as far as I can see though. You can implement A+B, A-B and two special boolean functions of A and B. The requirement for the functions is, that they must return 1 whenever A is 1. Possible functions f(A, B) are: f = 1 f = A f = A | B f = A | not B f = not(not A and B) you can also do a left shift: f = A<<1 I must correct myself, A and B is not in the list, you need the MULT_AND for that. KoljaArticle: 136448
On Mon, 17 Nov 2008 08:34:08 +0000 (UTC), Andreas Ehliar wrote:
>> expect a significant revision [of SV standard] in 2009.
>This sounds interesting, do you happen to have a link to a
>webpage with more information about upcoming possible
>revisions?
Sadly the LRM drafts are under IEEE copyright; you can
pay money for them, but that sounds a bit silly when you'll
probably want to buy the real thing later anyway.
Expect a flurry of conference papers and sundry announcements
during 2009. The draft is now frozen ready for the formal
IEEE balloting process, in which various key players in the
industry have a chance to examine the new spec thoroughly
and raise any critical objections (and, indeed, to veto some
proposed changes if they feel that's the only way forward).
>Personally, I'm hoping for a nicer solution to the problem discussed
>in for example http://groups.google.se/group/comp.lang.verilog/browse_thread/thread/b517b5f1b94379e7
To my considerable disappointment, SV interfaces have not
received much attention in SV-2009. Some tricky issues
relating to type parameterization of virtual interfaces
have been cleaned up - there was a paper about this in
the San Jose Mentor User2User conference recently - but
the design aspects have not been addressed at all. It's
high on my list of things I want to lobby for in the
next-next revision, but of course that won't hit the
streets until 2013 or so at the earliest.
There should, however, be some really attractive things
in it that are also fairly easy to implement, so there
will be no excuse for simulator vendors :-) - for example:
- the ability to have a module parameter with no default,
so that it becomes mandatory to override it at instantiation
(like you've been able to do in VHDL for 20 years...)
- nicer ways to concatenate unpacked arrays
- improvements in the unique/priority qualifiers for
conditionals, making them useful in combinational code
as well as clocked logic, and providing a new "unique0"
keyword to match the requirements of "parallel_case"
- improvements in procedural assertions, allowing them
to be protected against combinational glitches that
could otherwise cause false firing
- various improvements for randomize...with {...}
Also look out for...
- lots of cleanup and improvement of LRM definitions;
- complete merger of the Verilog and SystemVerilog LRMs;
- clarifications and enhancements of the functional
coverage constructs;
- major enhancements to the assertion language
And a bunch of other stuff that I can't remember....
quite a lot of changes to the VPI (C interface) too,
but that's a bit outside my comfort zone.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 136449On Nov 17, 5:17=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Eric > > Sounds like you are applying a reasonable approach. SDR dram still has > it's place and you can see almost the same in our Darnaw (PGA FPGA) > producthttp://www.enterpoint.co.uk/moelbryn/darnaw1.htmland soon to > be released Mulldonoch2. The only difference is we have the advantage > of using BGAs for the FPGA. > > One thing to mention is that the PQ208 packages don't perform as well > as BGA in terms of SSO and hence ground/power bounce of signals. Try > and make decoupling and power structures as good as you can to > minimise the risk. You can also spread the I/Os but that will make > your routing much less optimal. > > John Adair > Enterpoint Ltd. > > On 17 Nov, 07:18, Eric Smith <e...@brouhaha.com> wrote: > > > I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM > > (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze > > with the MPMC memory controller. > > > I'm concerned about signal integrity and SSOs. =A0Being on a shoestring > > budget, I unfortunately don't have an IBIS simulator. > > > If I put the TSOP very close to the FPGA (QFP), and keep the trace leng= ths > > short, is it plausible to get this to work? =A0Will fast outputs at 3.3= V CMOS > > with 2mA drive be satisfactory, or will higher drive be necessary (resu= lting > > in more possible SSO problems)? > > > I picked SDR SDRAM on the assumption that I'd be opening an even bigger > > can of worms with DDR or DDR2. =A0I'm using the QFP and TSOP rather tha= n BGAs > > to avoid having to pay big bucks to an assembly house to assemble the > > prototypes. > > > Thanks for any advice! > > Eric Smith As mentioned, the PQ package is pretty bad for SSO, having the most lead inductance of all the package choices. However it helps to sprinkle virtual ground pins among your package outputs. Also, I'm not sure how fast you're trying to run the SDRAM, but you may get more help with SSO using slow slew rate vs. lower output drive. Unfortunately slow slew rate gives a rather large output delay compared to the fast slew rate. Your SSO also improves with smaller load capacitance, so if you can use one 32-bit wide SDRAM part instead of two 16-bit wide parts, you'd have half the address and control line loading. The by-32 parts come in TSOP as well, having the same overall dimensions but more finely spaced pins than the by-16's. They tend to be a bit pricier, though and don't come in the largest bit density.
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