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On Tue, 27 Jan 2009 06:11:12 -0800 (PST), jleslie48 wrote: >I see EE guys tremble in fear at a double nested bubble sort I'm an EE guy (more or less) who knows enough about software to know that a bubble sort is to be mocked rather than feared, but I think I see what you're getting at. Interestingly, the better class of EE is increasingly obliged to get up to speed with quite sophisticated software these days - but primarily in the context of functional verification, i.e. testbenches. Oh, and in the strange twilight world of hardware-dependent software - device drivers and similar arcana - where HW and SW folk must of necessity talk to one another, but generally do so through gritted teeth. As a by-the-by, sorting is one of the places where hardware and software folk can have a genuinely interesting dialogue. Sorting techniques that work really well in software (heapsort, Shell, radix sorting) simply don't map well to hardware implementation, because of the extremely non-uniform data flow and complicated address calculations that they involve. On the other hand, there are some fascinating parallel sort algorithms (Batcher aka bitonic sort, for example), which map extremely well to hardware provided the scale of the problem isn't too big, and whose parallelism can be exploited to get blindingly fast performance. I've noted here in the past that, for small data sets, simple insertion sort can easily be implemented in hardware to give O(N) sorting time at the cost of O(N) hardware size; that's a tradeoff that you probably don't wish to make in software, ever, because the O(N) size is sure to pop up as another O(N) time instead, giving the insertion sort O(N^2) performance - which is just as cruddy as bubble sort :-) > here I am with the rolls reversed on something as > silly as putting out the "hello > world" message on a screen... Nothing to be ashamed of. Memory draws a merciful veil over the embarrassments of my early attempts to learn about OOP. It's good to stretch the boundaries of your comfort zone, but it takes some courage (or confidence) to do that in public. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137676
On Jan 27, 3:02=A0am, "Jan Bruns" <testzugang_janbr...@arcor.de> wrote: > "Jan Bruns": > > > My Spartan3 board connects a config pin (CCLK) directly =A0to > > a User-IO (VCCO=3D3.3V). As you can imagine, this signal > > also goes into a serial platform flash, and is also externally > > tied to =A02.5 V by a 4700 Ohm resistor. > > > Now after config, I'd like to drive that signal using the > > User IO pin, but I'm not sure if this is safe, nor > > am I sure what signal-standard to use. > > > The IO-Bank has 50 Ohm DCI-control Resistors tied > > to GND and VCCO, but no Vref available. > > What about using trisate as high-state, never driving the > line high? The Spartan3 user guide mentions specially > the original Spartan3 having relatively strong pullups... > > Gruss > > Jan Bruns Open-drain would be safe for the inputs, especially since the external pullup is to 2.5V, however since this seems to be a clock input to the SPI device, you need to evaluate your rise time to see if it is fast enough to work. You could reduce the value of the resistor if the other driving sources can handle it, or you could play games with active high drive, for example using the feedback input to allow active drive while the pin is low. This allows the output buffer to drive high for a few nanoseconds before going tristate. The datasheet implies that short overshoots of this sort are acceptable. Regards, GaborArticle: 137677
On Jan 27, 2:55=A0pm, nei...@pipstechnology.co.uk wrote: > On 27 Jan, 09:55, ales.gor...@gmail.com wrote: > > > > > On Jan 26, 4:28 pm, nei...@pipstechnology.co.uk wrote: > > > > On 25 Jan, 21:51, ales.gor...@gmail.com wrote: > > > > > Hi All, > > > > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) a= nd > > > > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual mem= ory > > > > controller. > > > > Does anybody know how to create UCF constraints for dual memory > > > > controller in MIG 2.3? Dual memory controllers are only supported f= or > > > > Virtex 4&5. > > > > > Cheers, > > > > > Ales > > > > I've had to do the exact same thing, I did it by generating 2 seperat= e > > > MIG cores, and for the second one I use the ucf from the first to > > > prohibit the pin placements. =A0The generation of the second MIG core > > > was purely to get a second ucf file. =A0It then involved a bit of man= ual > > > playing around with the VHDL to instantiate the second controller, an= d > > > then changing the signal names in the second ucf file to those for th= e > > > second controller. =A0It was a little while ago that I did this, but = I > > > think that was what I did. > > > > Neill > > > Just one more thing: did the internal logic placement constraints > > overalp in your case? This can add some more manual editing to be > > done. > > > Cheers, > > > Ales > > Glad to help. =A0I don't remember there being any overlapping placement > constraints, I know I had to play around with the ucf a bit more later > when I decided to move some of the pins around to make the board > layout a bit easier. > > It would be nice if Xilinx would allow MIG to generate dual > controllers for Spartan devices, maybe they'll do it for the Spartan > 6, which is due later this year apparently. > > Neill. you are well informed :) yes its planned in the time frame you mentioned asfaik (s6) no idea if the mig will allow dual banking for spartan ever tough AnttiArticle: 137678
"Gabor": > "Jan Bruns": >> What about using trisate as high-state, never driving the >> line high? The Spartan3 user guide mentions specially >> the original Spartan3 having relatively strong pullups... >Open-drain would be safe for the inputs, especially since >the external pullup is to 2.5V, however since this seems >to be a clock input to the SPI device, you need to evaluate >your rise time to see if it is fast enough to work. >You could reduce the value of the resistor if the other >driving sources can handle it, or you could play games <with active high drive, for example using the feedback >input to allow active drive while the pin is low. This >allows the output buffer to drive high for a few nanoseconds >before going tristate. The datasheet implies that short >overshoots of this sort are acceptable. Maybe I'm a bit too afraid about this single signal. The main problem with input voltages higher than supply IIRC was high leakage current through power clamp diodes. 3.3V-2.5V = 0.8V might be enough to allow for exhaustive currents the output driver can deliver. So couldn't it be enough to adjust DriveStrength to something low like 2 mA? At most 1.6mW additional power on a single Pin doesn't really sound like it could destroy the input logic. Gruss Jan BrunsArticle: 137679
Hi All, I have a MII interface with 10/100 support in which MAC block is used as IP in my design. I am doing feasibility study of removinf MAC block to external L2 component and use SGMII to support 10/100/1000. Is this possible? Also please let me know how are SerDes Channels listed in FPGA datasheets related to SGMII. Thanks, SundarArticle: 137680
jleslie48 wrote:
> And I haven't met a programmer yet worth his weight that didn't
> "use templates or look at existing code"
> Plus its been 20 years since I programmed using flowcharts,
> I've always worked at the mathematical algorithm level then to pseudo
> code,
> then source code. Always in a linear fashion fitting in with either C/
> pascal.
The reference design here:
http://mysite.verizon.net/miketreseler/
is a single process
(aka: sequential, linear, single threaded)
vhdl design that just happens to be a uart.
(But read Jonathan's stuff first)
-- Mike Treseler
Article: 137681Hi Gabor, > I don't know what your budget is, but if you're completely > inexperienced and have the money, you may want to consider > using a design service. =A0We use a local service who consistently > gives us the lowest price on design projects. =A0 I have some experienced with OrCAD, only two layer, manul route processing never used autoroute. > He uses PADS > software and only autoroutes non-critical nets. =A0I have > the PADS viewer which allows me to check his design output > and run off Gerber files for production. =A0A full seat of > PADS (without autorouting) starts around $5,000.00 but > you can get a free evaluation copy that is limited in > the size of design you can produce, if you want to play > around with it first. PADs software from Mentor Graphics ? I have to start a new project with an FPGA, therefore you must use a multilayer PCB. I was wondering if anyone of you use systems, with automatic systems routing. I do not even imagine how you can manually route 600 or more tracks on multilayer PCB. Kappa.Article: 137682
There are a wide range of tools with price tags from low to very high. As yet I have not been convinced that an autorouter can do as a good a job as a good human. Every board in our product is hand routed including large boards e.g. our mini monster Broaddown4 - http://www.enterpoint.co.uk/moelbryn/broaddown4.html. Whatever autorouter you use it will probably cost you extra layers and / or vias and that's board cost. On the other hand it may be quick to get to the first board back to assembly but my experience with people that go this way is that the board ends up being modded and pcb updated several times costing more in the end. Hand routing is very close up and personal and often mistakes are spotted during hand routing of boards. So take your choice of tools and method and enjoy. John Adair Enterpoint td. On 27 Jan, 16:48, secure...@gmail.com wrote: > Hi Gabor, > > > I don't know what your budget is, but if you're completely > > inexperienced and have the money, you may want to consider > > using a design service. =A0We use a local service who consistently > > gives us the lowest price on design projects. =A0 > > I have some experienced with OrCAD, only two layer, manul route > processing never used autoroute. > > > He uses PADS > > software and only autoroutes non-critical nets. =A0I have > > the PADS viewer which allows me to check his design output > > and run off Gerber files for production. =A0A full seat of > > PADS (without autorouting) starts around $5,000.00 but > > you can get a free evaluation copy that is limited in > > the size of design you can produce, if you want to play > > around with it first. > > PADs software from Mentor Graphics ? > > I have to start a new project with an FPGA, therefore you must use a > multilayer PCB. I was wondering if anyone of you use systems, with > automatic systems routing. I do not even imagine how you can manually > route 600 or more tracks on multilayer PCB. > > Kappa. From rgaddi@technologyhighland.com Tue Jan 27 09:25:58 2009 Path: flpi142.ffdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!newshub.sdsu.edu!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Tue, 27 Jan 2009 11:25:58 -0600 Date: Tue, 27 Jan 2009 09:25:58 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: What software do you use for PCB with FPGA ? Message-Id: <20090127092558.f8f8a91a.rgaddi@technologyhighland.com> References: <2acf65bd-0848-475a-9e9c-e30eaa86e669@g1g2000pra.googlegroups.com> <08736c16-dec3-42ab-8552-68a427046948@j38g2000yqa.googlegroups.com> <9c8889e3-6d82-43d7-b274-dcd19739b368@e1g2000pra.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 17 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-zorsUTuvM0U04cEWRF08izEEzTgNi7P+k+yEx+xxdUl0lkfzfdkHrKkbhtqWgP7F6tas1ucHvxBziGq!RPEzUPmV0N6EdQPsw+zEKUOAo53YyHOEXCslnc2EPnF1+3U6AQ2KsDD3mg5lv4GKn9lNI3jcaXt8!J9apL8Drvg9GpM35CCk= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:150777 X-Received-Date: Tue, 27 Jan 2009 12:25:59 EST (flpi142.ffdc.sbc.com) On Tue, 27 Jan 2009 08:48:35 -0800 (PST) secureasm@gmail.com wrote: > [snip] > > I have to start a new project with an FPGA, therefore you must use a > multilayer PCB. I was wondering if anyone of you use systems, with > automatic systems routing. I do not even imagine how you can manually > route 600 or more tracks on multilayer PCB. > > Kappa. Same way you manually do 600 of anything else, one at a time. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 137683
"...but it takes some courage (or
confidence) to do that in public. "
I've got no choice. I have a deliverable to a customer, and
failure is not an option. My project worked perfectly fine on a
DSP running C code, but the customer has dictated that It
must run in a pure FPGA environment. So now I'm on the hook
to get it to run on a FPGA.
Anyway, some quickies,
I'm looking at the source code for the bucket brigade fifo, and
I can't even determine where the 16 characters are stored.
here's the source to the fifo:
http://grace.evergreen.edu/dtoi/arch06w/asm/KCPSM3/VHDL/bbfifo_16x8.vhd
and I "think" this is the storage:
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
so here are the quickie questions:
1) what's a LUT?
2) what do you use the reserved words ATTRIBUTE and LABEL ?
3) what is that GENERIC MAP thing and what does(INIT => X"0000")
mean ?
4) INIT is the variable name right not a reserved/library word?
5) what about STRING?
6) half_full looks at pointer(3) (the highest order bit of pointer)
which is my
first clue of a 16byte buffer for all values of pointer (signal
pointer : std_logic_vector(3 downto 0);)
where the high order bit is set we know that we have 8 or more
characters in the buffer. but where does data_out take on the
value of the character to be sent? I don't see any mechanism for
the bucket brigade to pass along the buckets (and to continue with
the analogy, throw "data_out" onto the fire )
7) I image 1-6 will answer this, but should I want this buffer to be
larger,
I'm guessing its design is adaptable to 32,64,128, ... aka only
power of
2 sizes, so how would I go about expanding that buffer?
Article: 137684On Jan 27, 11:48 am, secure...@gmail.com wrote: > Hi Gabor, > > > I don't know what your budget is, but if you're completely > > inexperienced and have the money, you may want to consider > > using a design service. We use a local service who consistently > > gives us the lowest price on design projects. > > I have some experienced with OrCAD, only two layer, manul route > processing never used autoroute. Your initial post seemed to be asking about basic things like trace width. If you have designed boards before then I would expect that you either know a bit about choosing a trace width or just winged it and got lucky on your other boards. Either way, there are places where you can ask advice. This is a good start, but some other news groups might be better, such as sci.electronics.design and sci.electronics.cad. Once you choose a layout package there should be support forums where you can ask for help, both specific to that package and general advice on board design. > > He uses PADS > > software and only autoroutes non-critical nets. I have > > the PADS viewer which allows me to check his design output > > and run off Gerber files for production. A full seat of > > PADS (without autorouting) starts around $5,000.00 but > > you can get a free evaluation copy that is limited in > > the size of design you can produce, if you want to play > > around with it first. > > PADs software from Mentor Graphics ? > > I have to start a new project with an FPGA, therefore you must use a > multilayer PCB. I was wondering if anyone of you use systems, with > automatic systems routing. I do not even imagine how you can manually > route 600 or more tracks on multilayer PCB. I would recommend FreePCB. I found it to be very intuitive for the most part. There are a few unobvious things that have to be learned, but there is plenty of help to learn them. The tool is good at manual routing, but does support an autorouter. Check out http://freepcb.com/ They have a forum and there is also a Yahoo group. As to laying out a BGA, often the chip maker will offer a suggested routing plan to get the signals from the BGA pins to outside the footprint. Unless it is one of the BGAs that leaves a large area in the middle of the pins and only has four rows of pins, you will need to use vias between the pads. The chip maker's suggestion is likely as good as you can get. They give a lot of detail on how to size the pads using either the size of the copper pad or by using solder mask. Read all of this carefully and don't ignore it. There is a lot more to PCB design than just routing wires. You should treat this as a learning experience and read as much as you can so that you can learn from the mistakes of others. RickArticle: 137685
On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote: >I've got no choice. I have a deliverable to a customer, and >failure is not an option. My project worked perfectly fine on a >DSP running C code, but the customer has dictated that It >must run in a pure FPGA environment. So now I'm on the hook >to get it to run on a FPGA. Advice, honestly given, from one Jonathan to another: Get some help. You're in over your head, which is fine if you're doing it for learning's sake (that's what I had assumed) but not if your income stream depends on it. You need a contractor, or another employee. It is perfectly obvious you are capable of doing this stuff yourself, but it's also perfectly obvious that there is a huge amount of stuff you don't know and don't have time to learn. You're in Massachusetts, right? No shortage of good VHDL/FPGA contractors round there, I would think. I know of at least one outstanding designer in your area, but he's mainly a Verilog/ASIC guy so probably would not be the right choice. You probably want someone local, so I'm not offering :-) ********** self publicity alarm ************** we're running a VHDL training class in MD next week; it would suit your needs well; but it's probably about three weeks later than you needed it to be. ********** self publicity ends ************** Sorry to be so blunt. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137686
On Jan 27, 9:18 am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2009-01-27, jleslie48 <j...@jonathanleslie.com> wrote: > > > I've got no choice. I have a deliverable to a customer, and > > failure is not an option. My project worked perfectly fine on a > > DSP running C code, but the customer has dictated that It > > must run in a pure FPGA environment. So now I'm on the hook > > to get it to run on a FPGA. > > Hi, > > have you considered simply putting a small processor in an FPGA? > If you have a large amount of C code you could use a 32-bit FPGA > optimized processor like MicroBlaze if you are using Xilinx or > Nios II if you are using Altera. (You will need to buy the EDK > if you are using Xilinx, but it sounds like this will save you > a lot of time right now so it is probably worth it.) > > If space is at a premium in the FPGA you could use an 8-bit > processor optimized for FPGAs such as the PicoBlaze. This will > allow you to create most of your project in an environment in > which you are comfortable. (And as you have probably already > noticed, low speed string processing is substantially easier > to do in software.) There is no licensing fee for PicoBlaze > as far as I know. > > You may still have to create some hardware to interface your > processor with the outside world, but if your core algorithms > are written in C I suspect that a processor is the most efficient > way to get this done. > > If you have some performance problems you can move parts > of your algorithm into hardware, but hopefully you won't > need that. > > /Andreas considered and dismissed. My project is to piggy back on an existing platform and no processor is available. Plus my real processing will be on some A/D boards data, I'm not even going to talk to those until I get the basics down. It suffices to say that my C code was already too slow and my new constraints dictate a 100x improvement in speed. C is out.Article: 137687
On Jan 27, 1:07 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote: > >I've got no choice. I have a deliverable to a customer, and > >failure is not an option. My project worked perfectly fine on a > >DSP running C code, but the customer has dictated that It > >must run in a pure FPGA environment. So now I'm on the hook > >to get it to run on a FPGA. > > Advice, honestly given, from one Jonathan to another: > Get some help. You're in over your head, which is fine > if you're doing it for learning's sake (that's what I > had assumed) but not if your income stream depends on it. > You need a contractor, or another employee. It is > perfectly obvious you are capable of doing this stuff > yourself, but it's also perfectly obvious that there > is a huge amount of stuff you don't know and don't have > time to learn. > > You're in Massachusetts, right? No shortage of good > VHDL/FPGA contractors round there, I would think. I > know of at least one outstanding designer in your area, > but he's mainly a Verilog/ASIC guy so probably would > not be the right choice. You probably want someone > local, so I'm not offering :-) > > ********** self publicity alarm ************** > we're running a VHDL training class in MD next week; > it would suit your needs well; but it's probably > about three weeks later than you needed it to be. > ********** self publicity ends ************** > > Sorry to be so blunt. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Oh you don't have to tell me I'm in over my head. Unfortunately I was in over my head when the prototype for this project started 2 years ago, but I pulled a miracle then and now its expected again. I've tried hiring FULL-TIME FPGA/VHDL guys, I've been through 3 so far, that's when the boss talked me into doing it. I'm actually in NJ and My company has been trying to get a foothold into FPGA for years, always ending in failure. I'm determined to break that.Article: 137688
Firmware hex file version = 1100. Downloading C:/Xilinx/10.1/ISE/data/xusbdfwu.hex. Downloaded firmware version 1100. PLD file version =0012h PLD fversion = FFFh. iMPACT:2356 - Platform Cable USB firmware must be updated. This operation may take up to 10 minutes on a USB 2.0 port or up to 30 minutes on a USB 1.1 port.Article: 137689
On Jan 27, 2:24 pm, jleslie48 <j...@jonathanleslie.com> wrote: > Firmware hex file version = 1100. > Downloading C:/Xilinx/10.1/ISE/data/xusbdfwu.hex. > Downloaded firmware version 1100. > PLD file version =0012h > PLD fversion = FFFh. > iMPACT:2356 - Platform Cable USB firmware must be updated. This > operation may take up to 10 minutes on a USB 2.0 port or up to 30 > minutes on a USB 1.1 port. looks like its hung at 28%, its been stuck now for 10 minutes.Article: 137690
On Jan 27, 11:25 am, jleslie48 <j...@jonathanleslie.com> wrote: > On Jan 27, 2:24 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > Firmware hex file version = 1100. > > Downloading C:/Xilinx/10.1/ISE/data/xusbdfwu.hex. > > Downloaded firmware version 1100. > > PLD file version =0012h > > PLD fversion = FFFh. > > iMPACT:2356 - Platform Cable USB firmware must be updated. This > > operation may take up to 10 minutes on a USB 2.0 port or up to 30 > > minutes on a USB 1.1 port. > > looks like its hung at 28%, its been stuck now for 10 minutes. I didn't really see a question in your post, but... It's very common that the USB Platform cable gets the firmware updated when connecting to a new version of ISE. It happens every time for me. I've never had a glitch in the update process, it does take a while. You didn't mention anything about OS or version; I see a dos-like path in the message so I'm guessing that you're using some bundle of spy- ware and viruses from Redmond WA. If so, you must be 1000% certain that your system has the USB drivers configured exactly right, or bad things can happen. Try again with a clean install. Report back with real questions, and real details. ALArticle: 137691
On Jan 27, 12:50 am, secure...@gmail.com wrote: > Hi, > > I have to make a PCB using BGA pinout for FPGA. > > What brand of software do you use ? > > Place Route manually or automatically ? > > Which plans to use and how ? > > For the width of the tracks ? > > Thanks. > > Kappa Myself, I use OrCAD and PADs. This pair is common in the village I live in. As far as width/spacing, I refer to the manufacturer's web site. Both 'A' and 'X' publish PCB design guidelines. I follow both (as close as possible) when designing with either. The part you will -really- need help with is the FPGA pin-out. Lots of different approaches, but for your very 1st board I suggest the trial & error method so you can appreciate the complexity. Just my two cents, ALArticle: 137692
On Jan 27, 2:32 pm, LittleAlex <alex.lo...@email.com> wrote: > On Jan 27, 11:25 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > On Jan 27, 2:24 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > Firmware hex file version = 1100. > > > Downloading C:/Xilinx/10.1/ISE/data/xusbdfwu.hex. > > > Downloaded firmware version 1100. > > > PLD file version =0012h > > > PLD fversion = FFFh. > > > iMPACT:2356 - Platform Cable USB firmware must be updated. This > > > operation may take up to 10 minutes on a USB 2.0 port or up to 30 > > > minutes on a USB 1.1 port. > > > looks like its hung at 28%, its been stuck now for 10 minutes. > > I didn't really see a question in your post, but... > > It's very common that the USB Platform cable gets the firmware updated > when connecting to a new version of ISE. It happens every time for > me. > > I've never had a glitch in the update process, it does take a while. > You didn't mention anything about OS or version; I see a dos-like path > in the message so I'm guessing that you're using some bundle of spy- > ware and viruses from Redmond WA. If so, you must be 1000% certain > that your system has the USB drivers configured exactly right, or bad > things can happen. > > Try again with a clean install. Report back with real questions, and > real details. > > AL sorry, I'm on windoze xp pro and version10.1 ISE. nothing new was installed, all I know is that for the first time that phone home thing didn't fail, when I rebuilt my project. I then went to Impact 10.1 and now I got that message. and on a system restart, both the board and PC, I'm now hung at 6%. what is going on? I don't want my firmware updated unless I approve it, certainly not a half hour procedure in the middle of my day...Article: 137693
On Tue, 27 Jan 2009 08:26:44 -0800, Mike Treseler wrote:
>The reference design here:
>http://mysite.verizon.net/miketreseler/
>is a single process
>(aka: sequential, linear, single threaded)
>vhdl design that just happens to be a uart.
Mike,
you know I'm a strong supporter of the design
style you advocate, although I'm less persuaded
than you are by the benefits of parameterless
procedures. However, that doesn't affect the
key point I made in an earlier post:
once you have encapsulated some functionality
in an HDL process, your ability to do any form
of sequential/procedural composition is gone.
This, I believe, is a fundamental problem with
HDLs that will not go away until something with
the expressive power of CSP/occam surfaces in
the HDL world. Maybe that's already happened
with MyHDL and it's escaped me. Maybe not.
Of course, everyone who knows what they're doing
has perfectly good ways to deal with this problem.
It's not a show-stopper. But it presents a
fundamental barrier to the development of
hardware description beyond a crude block-level
process-by-process approach.
Yours more in hope than in expectation,
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
From rgaddi@technologyhighland.com Tue Jan 27 13:02:38 2009
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Date: Tue, 27 Jan 2009 13:02:38 -0800
From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: XST Makes Odd Choice
Message-Id: <20090127130238.b3a16523.rgaddi@technologyhighland.com>
Organization: Highland Technology, Inc.
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I'm working in a Spartan 3 with XST 10.1. I'm trying to divide down a
32 MHz clock to make a 128 kHz clock on the DCLK output pin. I'm
implementing it with a downcounter that (resets itself and toggles the
pin) when it gets to zero. Nothing tricky there so far.
Then I synthesize the whole thing and, just for fun, go spelunking in
the FPGA editor to see how it built the logic. As expected, it's a 7
bit downcounter, implemented using the carry chain. And yet the
zero-detection logic, rather than using the perfectly good carry-out
signal from the decrement chain, is being implemented with an 8 input
NOR, split across several slices.
Of course, this still works. At 32 MHz I could ship each individual
bit to Taiwan on a barge and wait for the answer by carrier pidgeon and
it would still work. But it seems like an odd choice to have made. By
my guesstimations it's both larger and slower than using the carry-out.
Anyone care to speculate why?
-- Rob
----------------------------------------------------------------------
MAKE_DC_DC: process(clk)
variable toggle : std_logic := '0';
constant TICKS_CYC : integer := 32_000_000 / 128_000;
constant TICKS_HALF : integer := TICKS_CYC / 2;
variable divider : integer
range 0 to TICKS_HALF-1 := TICKS_HALF-1;
begin
if rising_edge(clk) then
DCLK <= toggle;
if ( (divider - 1) < 0 ) then
divider := (TICKS_HALF-1);
toggle := not toggle;
else
divider := divider - 1;
end if;
end if;
end process MAKE_DC_DC;
----------------------------------------------------------------------
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 137694On Jan 27, 2:40 pm, jleslie48 <j...@jonathanleslie.com> wrote: > On Jan 27, 2:32 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > On Jan 27, 11:25 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On Jan 27, 2:24 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > Firmware hex file version = 1100. > > > > Downloading C:/Xilinx/10.1/ISE/data/xusbdfwu.hex. > > > > Downloaded firmware version 1100. > > > > PLD file version =0012h > > > > PLD fversion = FFFh. > > > > iMPACT:2356 - Platform Cable USB firmware must be updated. This > > > > operation may take up to 10 minutes on a USB 2.0 port or up to 30 > > > > minutes on a USB 1.1 port. > > > > looks like its hung at 28%, its been stuck now for 10 minutes. > > > I didn't really see a question in your post, but... > > > It's very common that the USB Platform cable gets the firmware updated > > when connecting to a new version of ISE. It happens every time for > > me. > > > I've never had a glitch in the update process, it does take a while. > > You didn't mention anything about OS or version; I see a dos-like path > > in the message so I'm guessing that you're using some bundle of spy- > > ware and viruses from Redmond WA. If so, you must be 1000% certain > > that your system has the USB drivers configured exactly right, or bad > > things can happen. > > > Try again with a clean install. Report back with real questions, and > > real details. > > > AL > > sorry, I'm on windoze xp pro and version10.1 ISE. nothing new was > installed, > all I know is that for the first time that phone home thing didn't > fail, when I rebuilt my > project. I then went to Impact 10.1 and now I got that message. and > on a system > restart, both the board and PC, I'm now hung at 6%. > > what is going on? I don't want my firmware updated unless I approve > it, certainly not > a half hour procedure in the middle of my day... well it finally finished. it took over 50 minutes. all is working now.Article: 137695
Rob Gaddi wrote:
...
> Then I synthesize the whole thing and, just for fun, go spelunking in
> the FPGA editor to see how it built the logic. As expected, it's a 7
> bit downcounter, implemented using the carry chain. And yet the
> zero-detection logic, rather than using the perfectly good carry-out
> signal from the decrement chain, is being implemented with an 8 input
> NOR, split across several slices.
> Anyone care to speculate why?
The divider register is updated by an adder.
The toggle register is updated by the same adder,
follow by a comparison.
I expect that synthesis will cascade the adder and compare
rather than duplicate the adder.
-- Mike Treseler
ps: save a register by moving the port assignment just
before the "end process"
Article: 137696On Jan 27, 2:02 pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > I'm working in a Spartan 3 with XST 10.1. I'm trying to divide down a > 32 MHz clock to make a 128 kHz clock on the DCLK output pin. I'm > implementing it with a downcounter that (resets itself and toggles the > pin) when it gets to zero. Nothing tricky there so far. > > Then I synthesize the whole thing and, just for fun, go spelunking in > the FPGA editor to see how it built the logic. As expected, it's a 7 > bit downcounter, implemented using the carry chain. And yet the > zero-detection logic, rather than using the perfectly good carry-out > signal from the decrement chain, is being implemented with an 8 input > NOR, split across several slices. > > Of course, this still works. At 32 MHz I could ship each individual > bit to Taiwan on a barge and wait for the answer by carrier pidgeon and > it would still work. But it seems like an odd choice to have made. By > my guesstimations it's both larger and slower than using the carry-out. > > Anyone care to speculate why? > -- Rob > > ---------------------------------------------------------------------- > > MAKE_DC_DC: process(clk) > > variable toggle : std_logic := '0'; > > constant TICKS_CYC : integer := 32_000_000 / 128_000; > constant TICKS_HALF : integer := TICKS_CYC / 2; > > variable divider : integer > range 0 to TICKS_HALF-1 := TICKS_HALF-1; > > begin > if rising_edge(clk) then > DCLK <= toggle; > > if ( (divider - 1) < 0 ) then > divider := (TICKS_HALF-1); > toggle := not toggle; > > else > divider := divider - 1; > end if; > end if; > end process MAKE_DC_DC; > > ---------------------------------------------------------------------- > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order I see your point. 'divider' is an integer, so all it *should* have to do is check the sign bit at this statement: "if ( (divider - 1) < 0 ) then" But you say it's not. I'm guessing XST is smart enough to infer a counter with "divider := divider - 1;", but not smart enough to infer carry-out. Looks like there is room for improvement. AL PS: Try it with the counter operation outside of the clock process: ... divider_1 := divider-1 ... if (divider_1 < 0) ... ... else divider := divider_1; ...Article: 137697
"Rob Gaddi": > Of course, this still works. At 32 MHz I could ship each individual > bit to Taiwan on a barge and wait for the answer by carrier pidgeon and > it would still work. But it seems like an odd choice to have made. By > my guesstimations it's both larger and slower than using the carry-out. Really? > variable divider : integer > range 0 to TICKS_HALF-1 := TICKS_HALF-1; > ... > if ( (divider - 1) < 0 ) then > divider := (TICKS_HALF-1); When, per definition, is a positive varibale decremented by one less than zero? Maybe if the decrement leads to a high MSB. just like the set/reset in the example does? I'm really not sure about this (don't have the money to buy expensive standard specifications, and also prefer verilog). Gruss Jan BrunsArticle: 137698
On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 <jon@jonathanleslie.com> wrote: >here's the source to the fifo: >http://grace.evergreen.edu/dtoi/arch06w/asm/KCPSM3/VHDL/bbfifo_16x8.vhd > >and I "think" this is the storage: > > -- SRL16E data storage > > data_width_loop: for i in 0 to 7 generate > -- > attribute INIT : string; > attribute INIT of data_srl : label is "0000"; > -- > begin >so here are the quickie questions: ... my answer I think would be: this is WAY too low-level to be dealing with unless you really need it for performance or you are down to your last few LUTs... This is the assembly language of hardware. >1) what's a LUT? ... basic unit of logic - typically implements a boolean function of 4 variables. Xilinx has a neat hack (SRL16) using one LUT as a 16-bit shift register. >2) what do you use the reserved words ATTRIBUTE and LABEL ? When you need to force the tools to do something very specific; usually but not always, a low level detail. >3) what is that GENERIC MAP thing and what does(INIT => X"0000") >mean ? Generics are generally useful; inside an entity, treat them as constants and base as much of a design off them as you dare. Outside, use a generic map to replace them with real values to parameterise your design. >4) INIT is the variable name right not a reserved/library word? yes - actually the generic not the variable. >5) what about STRING? A subtype of ARRAY OF CHAR - defined in the STD library I think >6) but where does data_out take on the > value of the character to be sent? Part of the SRL16 hack's internal magic. Seriously; if you can treat this "bbfifo.vhd" as a black box, go ahead and use it. Otherwise stick to behavioural level VHDL coding until you find something you really can't do that way. Life's too short. If you have to get involved at this level I agree with Jonathan- you're in too deep. But you know how to build a counter. I suspect you know how to use it to address an array and read and write its contents. Do you need to spend time on the innards of a FIFO? If you can keep it behavioural, and let the synthesis tool do (99% of) this low level detail for you, I think you have a chance. - BrianArticle: 137699
On Tue, 27 Jan 2009 20:22:35 +0000, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >On Tue, 27 Jan 2009 08:26:44 -0800, Mike Treseler wrote: > >>The reference design here: >>http://mysite.verizon.net/miketreseler/ >>is a single process >>(aka: sequential, linear, single threaded) >>vhdl design that just happens to be a uart. > >Mike, > >you know I'm a strong supporter of the design >style you advocate, although I'm less persuaded >than you are by the benefits of parameterless >procedures. However, that doesn't affect the >key point I made in an earlier post: > > once you have encapsulated some functionality > in an HDL process, your ability to do any form > of sequential/procedural composition is gone. > >This, I believe, is a fundamental problem with >HDLs that will not go away until something with >the expressive power of CSP/occam surfaces in >the HDL world. Maybe that's already happened >with MyHDL and it's escaped me. Maybe not. I think you're right, and I hadn't quite thought of it in that way. In one sense, signals are already very similar to occam's channels, in that their events communicate synchronisation. And that works well in simulation. The trouble of course is synthesis; almost all of that gets lost, because those damn flip-flops only understand one clock; and Xilinx STILL won't put Reed-Muller gates (choose another self-timed primitive if you prefer) on their chips! (Achronix, anyone? Though it could take synth tools a while to catch up...) So we have to re-invent our composition mechanisms again in excruciatingly low level detail. But at least it allows us parallel composition as well as serial... >Of course, everyone who knows what they're doing >has perfectly good ways to deal with this problem. As you presented with your "ready/valid" handshaking example. Which could be wrapped up in a record type, with ports and signals of that type, if only you could mix "in" and "out" directions on different components of the record... - Brian
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