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Messages from 151875

Article: 151875
Subject: Re: Scoping a glitch
From: "Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net>
Date: Thu, 26 May 2011 18:43:52 -0700
Links: << >>  << T >>  << A >>
John Larkin wrote:
> On Mon, 16 May 2011 21:02:44 -0700, "Mr.CRC"
> <crobcBOGUS@REMOVETHISsbcglobal.net> wrote:
> 
>> Hi:
>>
>> Today I took scope shots of a clock input to my Xilinx Spartan 3e,
>> Digilent NEXYS2 board.  The clock goes to a counter, simulating a
>> quadrature encoder, as explained in post "Counter clocks on both edges
>> sometimes, but not when different IO pin is used" on 5-13-2011.
>>
>> I have discovered that I'm dealing with a different animal here than
>> even the fastest logic chips I've grown comfortable with, the AC family.
> 
> 
> We were recently playing with a Spartan 3, to see how narrow a pulse
> we could count, using LVDS inputs feeding the first flop of a ripple
> counter. 1 ns seemed to work OK.

I would like to spend the time to spit my glitchy clock out a LVDS pair
to see if that can resolve the internal glitch.

Certainly a LVCMOS33 can't, or just barely shows a hint of inflection.

I also need to see if it's an asynchronous edge from another process
happening at the same time as the glitched clocks.

> We have seen slow input edges with a tiny amount of noise clock on the
> wrong edge. Even CCLK does this!
> 
> Output edges are similarly screaming fast, sub-ns.
> 
> One can also do serious amounts of logic and get jitter in the 10s of
> ps RMS.
> 
> They should give us a slow+schmitt input option.

Yeah, I was thinking that too.  A little too much to ask for I suppose.


-- 
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17

Article: 151876
Subject: Re: Fall Times and Pullup
From: shyam <mail.ghanashyam.prabhu@gmail.com>
Date: Fri, 27 May 2011 00:24:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 25, 5:45=A0pm, rickman <gnu...@gmail.com> wrote:
> On May 25, 4:19=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote:
>
> > > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > > darmstadt.de> wrote:
> > > > shyam <mail.ghanashyam.pra...@gmail.com> wrote:
> > > > > If on a bidirectional bus, if there is a strong pull up and there=
 is a
> > > > > device which is drives the line low, can we reduce the fall time
> > > > > substantially, if we reduce the pull up on the lines?
> > > > > Or is it that the low overrides the pull up and does not affect f=
all
> > > > > time at all?
>
> > > > Did you do the math? Did you try to simulate?
>
> > > > Take the Pull up current in relation to the low drive sink current.=
..
> > > > --
> > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.=
tu-darmstadt.de
>
> > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmsta=
dt
> > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> > > Let's give the poor guy a clue.
>
> > > What impedance is a driver designed to drive an edge into? If you
> > > don't know what a transmission line is you are in it up to your neck.
>
> > I am trying to analyze the behavior of the SD card data lines.
> > According
> > to the specifications, the SD card is supposed to drive the data at
> > the
> > falling edge of the clock and the host shall sample the data at the
> > rising
> > edge of the clock.
>
> > Now I see that the data transition of line going low, happens 8ns
> > after a
> > falling edge. Now _assuming_ that the card uses a flip flop to drive
> > the
> > output line, I would imagine the clock to output to be anywhere
> > between
> > 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure if
> > it is
> > the card that is at fault of driving the output so slow or is it the
> > pull up
> > on the line that is pulling the line hard to keep it 1 for a longer
> > time.
>
> > Thanks
> > Shyam
>
> =A0To answer your original question, the fall time of an open collector/
> drain is largely determined by the drive strength of the output and
> the capacitance of the line and input. =A0There is some contribution by
> the pullup as any current through the pullup is not going through the
> capacitance, but with a value of 10 kohms it won't have much
> contribution.
>
> I can't say why the delay inside the SD card is 8 ns rather than 3
> ns. =A0But I would not read too much into it. =A0This is a device designe=
d
> for low power, not for high logic speed necessarily. =A0How fast is the
> clock specified to operate? =A0Is the 8 ns delay a significant portion
> of the clock cycle?
>
> Rick

I have some glue logic between the SD host and the SD card.
And the Glue logic has to sort of mus some data from the FPGA itself
and some taken from the SD card.
I am operating at the low speed mode of the SD and the clock period
is
around 40ns. (25MHz)
The issue is that the SD Card responds on the falling edge with a
Clock to
Output time of 8 ns and the data has to be sent much in prior to the
next
rising edge so that the Host can see it well.

So there is some clock skew added to this because the clock is also
routed
to the SD card via the FPGA. So there are route delays involved and I
see
my data from the SD card 8ns late. I can nullify clock skew by pushing
the
clock forward effectively making the input and output clock in synch
which
also meets data setup.

But I cannot eliminate data skews in the FPGA. So clock to output of
8ns
is what concerned me...

Article: 151877
Subject: Re: Instantiation of an EDF netlist within a Verilog top RTL
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Fri, 27 May 2011 03:05:33 -0500
Links: << >>  << T >>  << A >>
>Hello Guys,
>
>I am working with Synplify Pro. I have a RTL wrapper in Verilog where a
>module is instantiated. But this module is available as an EDF netlist.
How
>can I include this EDF netlist in my Synplify project so that it can be
>integrated with the wrapper RTL without any compilation error?
>
>Best regards,
>Rahul
>
>	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>

Just add a blackbox synthesis directive to the wrapper and everything will
be fine.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151878
Subject: Re: Scoping a glitch
From: rickman <gnuarm@gmail.com>
Date: Fri, 27 May 2011 06:42:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 26, 9:43=A0pm, "Mr.CRC" <crobcBO...@REMOVETHISsbcglobal.net>
wrote:
> John Larkin wrote:
> > On Mon, 16 May 2011 21:02:44 -0700, "Mr.CRC"
> > <crobcBO...@REMOVETHISsbcglobal.net> wrote:
>
> >> Hi:
>
> >> Today I took scope shots of a clock input to my Xilinx Spartan 3e,
> >> Digilent NEXYS2 board. =A0The clock goes to a counter, simulating a
> >> quadrature encoder, as explained in post "Counter clocks on both edges
> >> sometimes, but not when different IO pin is used" on 5-13-2011.
>
> >> I have discovered that I'm dealing with a different animal here than
> >> even the fastest logic chips I've grown comfortable with, the AC famil=
y.
>
> > We were recently playing with a Spartan 3, to see how narrow a pulse
> > we could count, using LVDS inputs feeding the first flop of a ripple
> > counter. 1 ns seemed to work OK.
>
> I would like to spend the time to spit my glitchy clock out a LVDS pair
> to see if that can resolve the internal glitch.
>
> Certainly a LVCMOS33 can't, or just barely shows a hint of inflection.
>
> I also need to see if it's an asynchronous edge from another process
> happening at the same time as the glitched clocks.

What will you do with that information?  Will it impact how you fix
the problem?


> > We have seen slow input edges with a tiny amount of noise clock on the
> > wrong edge. Even CCLK does this!
>
> > Output edges are similarly screaming fast, sub-ns.
>
> > One can also do serious amounts of logic and get jitter in the 10s of
> > ps RMS.
>
> > They should give us a slow+schmitt input option.
>
> Yeah, I was thinking that too. =A0A little too much to ask for I suppose.

I/O features are market driven.  Designs that use slow inputs are
mostly older technology that can afford to provide a buffer to sharpen
up the edge externally to the FPGA.  Designs that use 1.8 volt IOs or
LVDS, etc, are higher technology which often need the more current
FPGA densities and features and are the apps that sell the higher
margin parts.  Remember, the FPGA market is still driven by
communications apps.  The industrial controls and most other apps
don't even show on the FPGA vendors' radar screens.  So these apps get
what the FPGA makers provide and like it... or not... but that's what
they get anyway.

What about the makers of the SOC parts like Cypress and Actel, do they
include any Schmitt inputs?

Rick

Article: 151879
Subject: Re: Fall Times and Pullup
From: rickman <gnuarm@gmail.com>
Date: Fri, 27 May 2011 06:46:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 27, 3:24=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote:
> On May 25, 5:45=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > On May 25, 4:19=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote:
>
> > > On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote:
>
> > > > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > > > darmstadt.de> wrote:
> > > > > shyam <mail.ghanashyam.pra...@gmail.com> wrote:
> > > > > > If on a bidirectional bus, if there is a strong pull up and the=
re is a
> > > > > > device which is drives the line low, can we reduce the fall tim=
e
> > > > > > substantially, if we reduce the pull up on the lines?
> > > > > > Or is it that the low overrides the pull up and does not affect=
 fall
> > > > > > time at all?
>
> > > > > Did you do the math? Did you try to simulate?
>
> > > > > Take the Pull up current in relation to the low drive sink curren=
t...
> > > > > --
> > > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physi=
k.tu-darmstadt.de
>
> > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darms=
tadt
> > > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> > > > Let's give the poor guy a clue.
>
> > > > What impedance is a driver designed to drive an edge into? If you
> > > > don't know what a transmission line is you are in it up to your nec=
k.
>
> > > I am trying to analyze the behavior of the SD card data lines.
> > > According
> > > to the specifications, the SD card is supposed to drive the data at
> > > the
> > > falling edge of the clock and the host shall sample the data at the
> > > rising
> > > edge of the clock.
>
> > > Now I see that the data transition of line going low, happens 8ns
> > > after a
> > > falling edge. Now _assuming_ that the card uses a flip flop to drive
> > > the
> > > output line, I would imagine the clock to output to be anywhere
> > > between
> > > 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure if
> > > it is
> > > the card that is at fault of driving the output so slow or is it the
> > > pull up
> > > on the line that is pulling the line hard to keep it 1 for a longer
> > > time.
>
> > > Thanks
> > > Shyam
>
> > =A0To answer your original question, the fall time of an open collector=
/
> > drain is largely determined by the drive strength of the output and
> > the capacitance of the line and input. =A0There is some contribution by
> > the pullup as any current through the pullup is not going through the
> > capacitance, but with a value of 10 kohms it won't have much
> > contribution.
>
> > I can't say why the delay inside the SD card is 8 ns rather than 3
> > ns. =A0But I would not read too much into it. =A0This is a device desig=
ned
> > for low power, not for high logic speed necessarily. =A0How fast is the
> > clock specified to operate? =A0Is the 8 ns delay a significant portion
> > of the clock cycle?
>
> > Rick
>
> I have some glue logic between the SD host and the SD card.
> And the Glue logic has to sort of mus some data from the FPGA itself
> and some taken from the SD card.
> I am operating at the low speed mode of the SD and the clock period
> is
> around 40ns. (25MHz)
> The issue is that the SD Card responds on the falling edge with a
> Clock to
> Output time of 8 ns and the data has to be sent much in prior to the
> next
> rising edge so that the Host can see it well.
>
> So there is some clock skew added to this because the clock is also
> routed
> to the SD card via the FPGA. So there are route delays involved and I
> see
> my data from the SD card 8ns late. I can nullify clock skew by pushing
> the
> clock forward effectively making the input and output clock in synch
> which
> also meets data setup.
>
> But I cannot eliminate data skews in the FPGA. So clock to output of
> 8ns
> is what concerned me...

I can't quite visualize the timing based on your post so I'll have to
take your word for it.  But the FPGA is the part you have the most
control over.  I would think you could delay the sample timing in the
FPGA to make this work.  Do you have a higher speed clock in the
FPGA?  Can you use a clock manager to double the clock speed and
generate a new sample edge with better timing?

Rick

Article: 151880
Subject: Re: Fall Times and Pullup
From: shyam <mail.ghanashyam.prabhu@gmail.com>
Date: Sat, 28 May 2011 21:35:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 27, 6:46=A0pm, rickman <gnu...@gmail.com> wrote:
> On May 27, 3:24=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > On May 25, 5:45=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > > On May 25, 4:19=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote:
>
> > > > On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote:
>
> > > > > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > > > > darmstadt.de> wrote:
> > > > > > shyam <mail.ghanashyam.pra...@gmail.com> wrote:
> > > > > > > If on a bidirectional bus, if there is a strong pull up and t=
here is a
> > > > > > > device which is drives the line low, can we reduce the fall t=
ime
> > > > > > > substantially, if we reduce the pull up on the lines?
> > > > > > > Or is it that the low overrides the pull up and does not affe=
ct fall
> > > > > > > time at all?
>
> > > > > > Did you do the math? Did you try to simulate?
>
> > > > > > Take the Pull up current in relation to the low drive sink curr=
ent...
> > > > > > --
> > > > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.phy=
sik.tu-darmstadt.de
>
> > > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Dar=
mstadt
> > > > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 --------=
--
>
> > > > > Let's give the poor guy a clue.
>
> > > > > What impedance is a driver designed to drive an edge into? If you
> > > > > don't know what a transmission line is you are in it up to your n=
eck.
>
> > > > I am trying to analyze the behavior of the SD card data lines.
> > > > According
> > > > to the specifications, the SD card is supposed to drive the data at
> > > > the
> > > > falling edge of the clock and the host shall sample the data at the
> > > > rising
> > > > edge of the clock.
>
> > > > Now I see that the data transition of line going low, happens 8ns
> > > > after a
> > > > falling edge. Now _assuming_ that the card uses a flip flop to driv=
e
> > > > the
> > > > output line, I would imagine the clock to output to be anywhere
> > > > between
> > > > 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure =
if
> > > > it is
> > > > the card that is at fault of driving the output so slow or is it th=
e
> > > > pull up
> > > > on the line that is pulling the line hard to keep it 1 for a longer
> > > > time.
>
> > > > Thanks
> > > > Shyam
>
> > > =A0To answer your original question, the fall time of an open collect=
or/
> > > drain is largely determined by the drive strength of the output and
> > > the capacitance of the line and input. =A0There is some contribution =
by
> > > the pullup as any current through the pullup is not going through the
> > > capacitance, but with a value of 10 kohms it won't have much
> > > contribution.
>
> > > I can't say why the delay inside the SD card is 8 ns rather than 3
> > > ns. =A0But I would not read too much into it. =A0This is a device des=
igned
> > > for low power, not for high logic speed necessarily. =A0How fast is t=
he
> > > clock specified to operate? =A0Is the 8 ns delay a significant portio=
n
> > > of the clock cycle?
>
> > > Rick
>
> > I have some glue logic between the SD host and the SD card.
> > And the Glue logic has to sort of mus some data from the FPGA itself
> > and some taken from the SD card.
> > I am operating at the low speed mode of the SD and the clock period
> > is
> > around 40ns. (25MHz)
> > The issue is that the SD Card responds on the falling edge with a
> > Clock to
> > Output time of 8 ns and the data has to be sent much in prior to the
> > next
> > rising edge so that the Host can see it well.
>
> > So there is some clock skew added to this because the clock is also
> > routed
> > to the SD card via the FPGA. So there are route delays involved and I
> > see
> > my data from the SD card 8ns late. I can nullify clock skew by pushing
> > the
> > clock forward effectively making the input and output clock in synch
> > which
> > also meets data setup.
>
> > But I cannot eliminate data skews in the FPGA. So clock to output of
> > 8ns
> > is what concerned me...
>
> I can't quite visualize the timing based on your post so I'll have to
> take your word for it. =A0But the FPGA is the part you have the most
> control over. =A0I would think you could delay the sample timing in the
> FPGA to make this work. =A0Do you have a higher speed clock in the
> FPGA? =A0Can you use a clock manager to double the clock speed and
> generate a new sample edge with better timing?
>
> Rick

:) No I have a very low timing budget here. No PLLs, no Clock
multipliers. One thing I could do is to generate a rise detect in the
FPGA and make the duty cycle less so that the SD Card sees the falling
edge earlier than what it would see if I had forwarded the incoming
clock. So that is one place where I can control things.
As far as FPGA route is concerned, I have optimized the paths and they
delays internal to the FPGA are the max I can minimize. Most of them
are uncontrollable, stuff like PAD delay, clock buffer delay, Span Mux
delay

Article: 151881
Subject: Re: Best syntheses
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Sat, 28 May 2011 23:37:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
Michael,

as others have said, don't expect too much from a third-party synthesis too=
l. XST is a really good synthesis tool now, and I'm using it in all of my X=
ilinx projects.

There are lots of strategies for improving logic utilization and/or timing,=
 the most effective usually being optimizations of the RTL code such as red=
ucing the number of logic levels, leveraging built-in hard-macros, removing=
 resets etc.

The best advice I can give you is to show your design to a qualified consul=
tant near you. It will cost you some money, but you'll learn a lot and he m=
ay catch other issues in the process. Another option is of course to switch=
 to a device with a faster speed grade.

Hope this helps,

Guy Eschemann
http://guy-eschemann.de

Article: 151882
Subject: Re: Instantiation of an EDF netlist within a Verilog top RTL
From: shyam <mail.ghanashyam.prabhu@gmail.com>
Date: Mon, 30 May 2011 00:25:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 27, 1:05=A0pm, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> >Hello Guys,
>
> >I am working with Synplify Pro. I have a RTL wrapper in Verilog where a
> >module is instantiated. But this module is available as an EDF netlist.
> How
> >can I include this EDF netlist in my Synplify project so that it can be
> >integrated with the wrapper RTL without any compilation error?
>
> >Best regards,
> >Rahul
>
> >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0
> >Posted throughhttp://www.FPGARelated.com
>
> Just add a blackbox synthesis directive to the wrapper and everything wil=
l
> be fine.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Additionally, IO insertion should be disabled when the EDIF  netlist
is generated.
If IO insertion isn't disabled, Synplify Pro treats the inputs and
outputs on the RTL
used for edif netlist as IOs and instantiates IO pads on it.

Thanks
Shyam



Article: 151883
Subject: Package constants (VHDL)
From: Fred <fred__bloggs@lycos.com>
Date: Mon, 30 May 2011 07:34:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
Historically I have used a VHDL file to embody the constants in a
design where possible using meaningful names which can be easily
changed.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
package constants is
      constant rck_freq : integer := 30;
end constants;

I require two sets of constants according to debug or otherwise, I
might try:

package constants is
  if debug = 1 then
      constant rck_freq : integer := 10;
   else
      constant rck_freq : integer := 30;
   end if;
end constants;

But ISE coughs.  Can someone enlighten me on the correct way of doing
this, if possible?

Article: 151884
Subject: Re: Package constants (VHDL)
From: KJ <kkjennings@sbcglobal.net>
Date: Mon, 30 May 2011 07:58:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 30, 10:34=A0am, Fred <fred__blo...@lycos.com> wrote:

> I require two sets of constants according to debug or otherwise, I
> might try:
>
> package constants is
> =A0 if debug =3D 1 then
> =A0 =A0 =A0 constant rck_freq : integer :=3D 10;
> =A0 =A0else
> =A0 =A0 =A0 constant rck_freq : integer :=3D 30;
> =A0 =A0end if;
> end constants;
>
> But ISE coughs. =A0Can someone enlighten me on the correct way of doing
> this, if possible?

Create a function that implements the selection...
function sel(Cond: Boolean; If_True, If_False: integer) return
integer;

Then use the function to set the constant...
constant rck_freq : integer :=3D sel(Cond =3D>debug =3D 1, If_True =3D> 10,
If_False =3D>30);

You'll likely find the 'sel' function to be very useful for simple
2=3D>1 muxing operations that you will also find it useful to override
the function with various other forms...
function sel(Cond: Boolean; If_True, If_False: std_logic) return
std_logic;
function sel(Cond: Boolean; If_True, If_False: std_logic_vector)
return std_logic_vector;
function sel(Cond: Boolean; If_True, If_False: std_ulogic_vector)
return std_ulogic_vector;
etc...

Kevin Jennings

Article: 151885
Subject: Re: Package constants (VHDL)
From: Fred <fred__bloggs@lycos.com>
Date: Mon, 30 May 2011 08:39:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 30, 3:58=A0pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
> Create a function that implements the selection...
> function sel(Cond: Boolean; If_True, If_False: integer) return
> integer;
>
> Then use the function to set the constant...
> constant rck_freq : integer :=3D sel(Cond =3D>debug =3D 1, If_True =3D> 1=
0,
> If_False =3D>30);
>
> You'll likely find the 'sel' function to be very useful for simple
> 2=3D>1 muxing operations that you will also find it useful to override
> the function with various other forms...
> function sel(Cond: Boolean; If_True, If_False: std_logic) return
> std_logic;
> function sel(Cond: Boolean; If_True, If_False: std_logic_vector)
> return std_logic_vector;
> function sel(Cond: Boolean; If_True, If_False: std_ulogic_vector)
> return std_ulogic_vector;
> etc...
>

Many thanks indeed for such a quick reply.  It's now sorted.

There are times when I don't find VHDL very instinctive and confess
I'm not very au fait with functions.  Many thanks again.

Article: 151886
Subject: Re: Why feedback clock in SDRAM controllers?
From: valtih1978 <intellij@yandex.ru>
Date: Mon, 30 May 2011 19:49:09 +0300
Links: << >>  << T >>  << A >>
 > That's how important compensation of these delays are.

Really? Why do you think people care about the DLLs? Is it because they 
do not understand the importance of nanoscale timing?

Also, let me remind you, that in my question I pointed out that DCM 
feedbacks require that the FPGA-external feedback trace length matching 
the CLK trace length from FPGA to ram.

I keep reminding about this because do not see any reason for this 
design. Yet, I feel that it is a key and want anybody to explan.

You see, the dialog goes on:

A: The path delays must be taken into account these days. You know, they 
are important.
B: Ok. How this example design works?
A: Hm. Look at my first statement: things are very complicated now. We 
must take the delays into account.

This is an infinite loop. How can I break out of it and understand the 
design examples?



>
> If this is still not enough, maybe I can draw a diagram for you, but

yes, please

Article: 151887
Subject: Re: Why feedback clock in SDRAM controllers?
From: valtih1978 <intellij@yandex.ru>
Date: Mon, 30 May 2011 20:28:33 +0300
Links: << >>  << T >>  << A >>
I agree. The first problem is that there will be FPGA-internal part of 
the loop, which increases this length. But the thing I want to know in 
the first place - why do we need the phase adjustment?

Which phase is adjusted? The DCM drives internal FFs, making them all in 
phase. The internal feedback is distributed via DCM-generated clock 
three and therefore matches the DCM-to-regs clock delay, making childern 
regs in-phase with the DCM input clock. Also, vendor tools can ensure 
that combinatorial logic delays are shorter than the period.

Now, the feedback goes through external path. The DCM input is in phase 
with the rest of FPGA system. The output is adjusted so that something 
distant (i.e. DRAM CLK input) is also in phase.

If this picture is right, I see no reason of this "phase matching". We 
cannot benefit from it because the tools ignore the fpga-external data 
paths. Even worse: the adjusted clock will arrive earlier than it would 
naturally. Normally, you would have data and clock changing 
simultaneouly (ok, clock raises in the middle of data slot) at FPGA 
outputs and, having the same external path delays, would arrive to SDRAM 
with low skew. I see that using DCM "adjustment" just breaks this 
natural "source synchronous" phase matching.

Article: 151888
Subject: Re: Best syntheses
From: Michael <michael_laajanen@yahoo.com>
Date: Mon, 30 May 2011 23:03:20 +0200
Links: << >>  << T >>  << A >>
Hi,

On 05/29/11 08:37 AM, Guy Eschemann wrote:
> Michael,
>
> as others have said, don't expect too much from a third-party synthesis tool. XST is a really good synthesis tool now, and I'm using it in all of my Xilinx projects.
>
> There are lots of strategies for improving logic utilization and/or timing, the most effective usually being optimizations of the RTL code such as reducing the number of logic levels, leveraging built-in hard-macros, removing resets etc.
>
> The best advice I can give you is to show your design to a qualified consultant near you. It will cost you some money, but you'll learn a lot and he may catch other issues in the process. Another option is of course to switch to a device with a faster speed grade.
>
> Hope this helps,
>
> Guy Eschemann
> http://guy-eschemann.de
I agree with you, but as the FPGA gets more filled routing tends to be a 
critical issue in my experience so timing constraints as you wrote is vital.

It is not so easy to find someone that is really good and can pinpoint 
the weekness in a design in a relative short period of time IMHO.

So as I wrote, if a tool can fix 5-10% then that is very well invested 
money usually, xst has improved alot and works great but how much has 
the other vendors(read Synopsys) improved their tools is the question!

xst is catching up but are they ahead or on par with tools like Synopsys?

/michael



Article: 151889
Subject: Random Reset calls
From: RSGUPTA <rsgupta.gupta@gmail.com>
Date: Wed, 1 Jun 2011 02:40:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Folks,
Need something interesting in random reset:
I am having a testbench in verilog which needs to hit the state
machines states with reset.

Basic Format of testbench:
##############3
initial
  begin
----------
---------
fork
  begin
// Normal Traffic
  end
  begin
// Reset task
  end
join
------
end
##########

The aim of the 2nd thread in fork-join is to hit the states with Reset
that appear in Normal Traffic.

Now how can we only call the 2nd thread multiple times (Randomly) to
keep on hitting the states that appear in Normal Traffic.

Article: 151890
Subject: FFT using logic gates only
From: moindsp <moindsp2011@gmail.com>
Date: Wed, 1 Jun 2011 06:55:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
I intend to implement FFT using Logic gates only , by this i mean i
have written verilog code of FFT for xilinx spartran III, I can
visualize it in Xilinx ISE 13.1 using technology schematic. But its
still high level abstraction, can someone guide me how to generate
text file / other format file  that describes the whole implementation
using AND OR , XOR, NAND , NOR gate only


Regards
moin

Article: 151891
Subject: Re: Random Reset calls
From: johnp <jprovidenza@yahoo.com>
Date: Wed, 1 Jun 2011 07:14:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 1, 2:40=A0am, RSGUPTA <rsgupta.gu...@gmail.com> wrote:
> Hi Folks,
> Need something interesting in random reset:
> I am having a testbench in verilog which needs to hit the state
> machines states with reset.
>
> Basic Format of testbench:
> ##############3
> initial
> =A0 begin
> ----------
> ---------
> fork
> =A0 begin
> // Normal Traffic
> =A0 end
> =A0 begin
> // Reset task
> =A0 end
> join
> ------
> end
> ##########
>
> The aim of the 2nd thread in fork-join is to hit the states with Reset
> that appear in Normal Traffic.
>
> Now how can we only call the 2nd thread multiple times (Randomly) to
> keep on hitting the states that appear in Normal Traffic.

Have you considered the $random function?  You could either use it to
create a time delay or a delay count for some number of clock cycles.

John P

Article: 151892
Subject: Re: FFT using logic gates only
From: Joel Williams <nospamwhydontyoublogaboutit@nospamgmail.com>
Date: Thu, 02 Jun 2011 09:54:05 +0930
Links: << >>  << T >>  << A >>
> I intend to implement FFT using Logic gates only , by this i mean i
> have written verilog code of FFT for xilinx spartran III, I can
> visualize it in Xilinx ISE 13.1 using technology schematic. But its
> still high level abstraction, can someone guide me how to generate
> text file / other format file  that describes the whole implementation
> using AND OR , XOR, NAND , NOR gate only

You'll probably have to do it manually, and perhaps ask yourself why you 
want to do it.

FPGAs aren't actually built from these primitive logic gates but rather 
LUTs and FFs, so there's no reason for the tools to deal in any 
constructs other than these.

Joel

Article: 151893
Subject: Re: FFT using logic gates only
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 2 Jun 2011 04:00:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
Joel Williams <nospamwhydontyoublogaboutit@nospamgmail.com> wrote:
>> I intend to implement FFT using Logic gates only , by this i mean i
>> have written verilog code of FFT for xilinx spartran III, I can
>> visualize it in Xilinx ISE 13.1 using technology schematic. But its
>> still high level abstraction, can someone guide me how to generate
>> text file / other format file  that describes the whole implementation
>> using AND OR , XOR, NAND , NOR gate only
 
> You'll probably have to do it manually, and perhaps ask yourself why you 
> want to do it.
 
> FPGAs aren't actually built from these primitive logic gates but rather 
> LUTs and FFs, so there's no reason for the tools to deal in any 
> constructs other than these.

In any case, with the FFs in there for free, there is no reason
not to pipeline it.  Look up systolic array processor.

-- glen

Article: 151894
Subject: Re: FFT using logic gates only
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Thu, 02 Jun 2011 08:55:59 +0100
Links: << >>  << T >>  << A >>
moindsp <moindsp2011@gmail.com> writes:

> I intend to implement FFT using Logic gates only , by this i mean i
> have written verilog code of FFT for xilinx spartran III, I can
> visualize it in Xilinx ISE 13.1 using technology schematic. But its
> still high level abstraction, 

The technology schematic is not that high level - it shows you look-up tables!

Presumably, it also shows you some use of MUL18 blocks - but that's what the
FPGA has available.

> text file / other format file  that describes the whole implementation
> using AND OR , XOR, NAND , NOR gate only
>

If you really want to see it as a mess of gates, you'll have to synthesize with
some ASIC tools which target actual gates rather than FPGA elements.

I'm not sure what you gain from that though?

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 151895
Subject: Re: FFT using logic gates only
From: Christopher Felton <noemail@now.com>
Date: Thu, 02 Jun 2011 07:33:15 -0500
Links: << >>  << T >>  << A >>
On 6/1/2011 8:55 AM, moindsp wrote:
> I intend to implement FFT using Logic gates only , by this i mean i
> have written verilog code of FFT for xilinx spartran III, I can
> visualize it in Xilinx ISE 13.1 using technology schematic. But its
> still high level abstraction, can someone guide me how to generate
> text file / other format file  that describes the whole implementation
> using AND OR , XOR, NAND , NOR gate only
>
>
> Regards
> moin

You can't remove your state information (i.e. flip-flops) unless you 
design without them.  Which would be ... interesting, I would like to 
see your Fmax.

I am pretty sure in ISE (xst) you can output the structural Verilog. 
This should be the low-level unmapped view.  As mentioned, because it is 
FPGA specific synthesis you probably will have some FPGA specifics, 
example FPGA multiplies.

You can do generic synthesis with Icuras (quality??).  You can get a 
generic netlist.

Chris

Article: 151896
Subject: Microblaze and PowerPC
From: "am85" <ammarei@n_o_s_p_a_m.hotmail.com>
Date: Thu, 02 Jun 2011 09:50:06 -0500
Links: << >>  << T >>  << A >>
Hi, 
   I would like to perform mathematical operations as Division and Square
root. From what i have read, i either need to use Microblaze or PowerPC.
can anyone please tell me the difference in performance between them, and
is it a hardware or software calculation. Does each one of these options
has a  dedicated FPU? 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151897
Subject: Re: Microblaze and PowerPC
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Thu, 02 Jun 2011 09:15:51 -0700
Links: << >>  << T >>  << A >>
On 6/2/2011 7:50 AM, am85 wrote:
> Hi,
>     I would like to perform mathematical operations as Division and Square
> root. From what i have read, i either need to use Microblaze or PowerPC.
> can anyone please tell me the difference in performance between them, and
> is it a hardware or software calculation. Does each one of these options
> has a  dedicated FPU?
>
> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Not at all true.  Either of those algorithms can be implemented, either 
in fixed or floating point, as pure hardware.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 151898
Subject: How could I get LUT-level netlist in Xilinx ISE?
From: "chifalcon" <eric.he@n_o_s_p_a_m.hotmail.com>
Date: Thu, 02 Jun 2011 11:56:03 -0500
Links: << >>  << T >>  << A >>
Hi, I need to convert the high level design to LUT level netlist, and then
make corrections to it. 

In a paper, author says:

"The translate step generates a Verilog netlist that can easily be parsed.
This netlist consists out of declarations of primitive modules of the
device"

The netlist is shown as following:

******************************************
..
defparam LUT_37.INIT = 16'hC800;
//synthesis attribute HU_SET of LUT_37 is "SLICE_37";
//synthesis attribute rloc of LUT_37 is "X0Y0";
X_LUT4 LUT37 (.ADR0(n7), .ADR1(n4), .ADR2(n3), .ADR3(n, .o(n41);
...

******************************************
I searched all the files in the project folder, but didn't find this kind
of netlist.

I just want to know how to get this kind of netlist in Xilinx FPGA? 

Thanks very much!! 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151899
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: Tim Wescott <tim@seemywebsite.com>
Date: Thu, 02 Jun 2011 10:00:00 -0700
Links: << >>  << T >>  << A >>
On 06/02/2011 09:56 AM, chifalcon wrote:
> Hi, I need to convert the high level design to LUT level netlist, and then
> make corrections to it.
>
Why?  Wouldn't you rather correct the high level design once, then make 
correct LUT level netlists every time you use it?  Otherwise you're 
doomed to hand-correcting that netlist every time you synthesize, or 
you're stuck with that low-level netlist instead of a nice readable, 
portable, etc., high level design.

The only valid reason I see to do this is if you have to hand-optimize 
the placement of some really timing-critical piece of IP, and even there 
it would seem that you could go far with careful use of timing 
constraints.  But you wouldn't be doing that at the LUT level anyway, 
would you?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html



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