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Messages from 15325

Article: 15325
Subject: Re: Reconfigurable computing thesis on the web
From: zik@zikzak.net (Zik Saleeba)
Date: 19 Mar 1999 09:13:16 +1100
Links: << >>  << T >>  << A >>
Sylvain Giroudon <giroudon@NOSPAM-montrouge.tt.slb.com> writes:

>I red http://www.starbridgesystem.com/Pages/about.html recently.
>Is this thesis in the same domain/goal as what the guys
>from StarBridge are doing?

The aims may be the same but I'd imagine Star Bridge's machine
performs rather poorly for the majority of computing tasks.
FPGA-based machines tend to perform extremely well for a particular
domain of tasks - in some cases orders of magnitude faster than
general-purpose processors - but perform very, very poorly for the
majority of computing tasks. For instance running a compiler on an
FPGA-only system could realistically be expected to be orders of
magnitude _slower_ than a current-day conventional processor.

My aim was to see if the domain over which reconfigurable logic was
applicable could be expanded by adapting the architecture to the task
at hand. FPGAs were after all designed as a rapid-development
platform for static hardware designs and not as computing elements at
all. This is why most current attempts at FPGA-based computing
machines team FPGA logic arrays with conventional processors. The
conventional processors take up the slack where the FPGAs aren't
suitable for the job. My thesis describes a type of logic array
which is more suitable for general computing tasks than FPGAs are.
Whether it's good enough to challenge conventional processors on
their own ground is for you to decide.

Keep in mind that funds were not available to create a hardware
implementation of the device I describe so it's a purely theoretical
system. Simulations indicated that the idea definitely had potential -
but a great deal more work is required before a full implementation
could be realised.

Thanks for your interest,
Zik Saleeba
Article: 15326
Subject: FPGA Express FSM Synthesis Concern
From: michaellewis@my-dejanews.com
Date: Thu, 18 Mar 1999 23:13:42 GMT
Links: << >>  << T >>  << A >>


Hi:

I have a concern about the synthesis of a state machine.  I
am implementing a 16-bit mealy state machine using the
"One Hot" and "fastest & smallest" options for compliling
in FPGA Express. It turns out that one of the outputs of
the state machine is functionally set when one of two
(logical OR) of these states is set.  However, the EDIF
netlist out of the tool gives 6 levels of logic to implement
this 2-input OR gate. In fact, it is a function of nearly all
(14 to be precise) state signals, as opposed to the 2 I would
expect.

Even more curious is the fact that I see some of these
mutually exclusive One-Hot state signals entering LUTs
with AND-gate functions.  But the output of the AND
gate can never be set if the inputs are truly mutually
exclusive.  Maybe the compiler is providing a "safe"
representation, allowing for recovery from illegal
combinations of states, but I specifically opted for
"fastest & smallest" instead.

Any ideas?

Thanks,
Mike

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15327
Subject: Re: FPGA Express FSM Synthesis Concern
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 18 Mar 1999 15:48:31 -0800
Links: << >>  << T >>  << A >>
Are you coding in Verilog or VHDL?

If you are coding in Verilog and using a case statement for your 1 hot
combinational logic you need to add the comment //synopsys full_case
parallel_case on the same line as the case statement.  This will reduce the
logic considerably.  There should be something analagous for VHDL.

If you are coding your 1 hot with if statements (if (state[15] ...) you will
have problems with Synopsys deciding whether to encode an output function as
the OR of 14 1's or 2 0's (assuming 16 states).  That problem seems to be
avoided if you use the case construct.  You can only avoid this with coding
style.

I have some sample state machines (in verilog) that I can attach that will
show all of this and an additional  synopsys 1-hot synthesis bug.

Turns out that synopsys can decide to replace your "last" 1 hot state with
an "all off" state.  It won't tell you, but you will be short 1 ff.  It then
uses a pile of LUT's to detect that state, thereby increasing design size
and slowing your design.  Xilinx is looking at it at this time.

The correct workaround seems to be "use synplicity".

bruce


michaellewis@my-dejanews.com wrote in message
<7cs1ap$gbj$1@nnrp1.dejanews.com>...
>
>
>Hi:
>
>I have a concern about the synthesis of a state machine.  I
>am implementing a 16-bit mealy state machine using the
>"One Hot" and "fastest & smallest" options for compliling
>in FPGA Express. It turns out that one of the outputs of
>the state machine is functionally set when one of two
>(logical OR) of these states is set.  However, the EDIF
>netlist out of the tool gives 6 levels of logic to implement
>this 2-input OR gate. In fact, it is a function of nearly all
>(14 to be precise) state signals, as opposed to the 2 I would
>expect.
>
>Even more curious is the fact that I see some of these
>mutually exclusive One-Hot state signals entering LUTs
>with AND-gate functions.  But the output of the AND
>gate can never be set if the inputs are truly mutually
>exclusive.  Maybe the compiler is providing a "safe"
>representation, allowing for recovery from illegal
>combinations of states, but I specifically opted for
>"fastest & smallest" instead.
>
>Any ideas?
>
>Thanks,
>Mike
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 15328
Subject: Re: Xilinx routing problem: removing "reset" increases cycle time.
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 18 Mar 1999 15:52:38 -0800
Links: << >>  << T >>  << A >>
Go back to the older version tools you used before (just a guess, hehe)

Assuming you actually removed all the reset statements so there is no reset
net, I can't understand why it would change.

I think the placement tools use random number seeds based on your xnf file.
Perhaps you could try different seeds until you got a placement that works
better.

bruce

Zhen Luo wrote in message <36F09361.1005121B@ee.princeton.edu>...
>I have a design that used a global reset signal on XC4000e. Later on I
>removed this signal since I decided to utilize the initial "0" state of
>all FFs. However, I could never synthesize my design at the clock rate
>it used to be. Anyone has the same exprience here? How could I get
>around this problem?
>
>-- Zhen
>
>


Article: 15329
Subject: Re: Allowed logic functions in Virtex LE
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 18 Mar 1999 16:04:10 -0800
Links: << >>  << T >>  << A >>
In article <36f15dc2@news.nwlink.com>, Alex Rast <arast@inficom.com> wrote:
>Many apologies if the terminology I used offends. I didn't mean it as a 
>precise, rigidly-defined term with an accepted, standard meaning but rather as 
>simply a word to convey a concept. How might you phrase the same question 
>incorporating more acceptable terminology?
>

I didn't mean to come across as harsh as I did in the last post.

The typical question is "How can I make the CLB do f(a,b,c,d)?"
Where a,b,c,d are inputs to the CLB.  I am still not sure what
function is served by trying to generate a fixed CLB set of outputs
that appear to be independent of inputs. Perhaps you could enlighten
us with a reason behind this need as an alternative approach may
be better suited to your needs.

>Yes, I actually noticed that I posed the question based on an earlier series 
>of notes. I noted the same condition you outlined. However, I do still find 
>one output combination that *does* seem to be impossible, namely YB=1, Y=1, 
>XB=0. Does this look correct?
>

You're correct it is functionally impossible to have the above set
of outputs in Virtex if you are not allowed to use the BY input as
you previously indicated. 

>I'd gotten so 
>wound up in trying to think of creative ways of generating certain output 
>combinations that I knew my head wasn't completely clear. 

Still curious about this need for specific outputs without 
mentioning how it relates to inputs.  Using a CLB as pwr/gnd
source would be huge waste and you don't need more than one
pwr and gnd source in a design.

Ed McGettigan
Article: 15330
Subject: PCI: Xilinx Core in Virtex versus Lucent Orca 3TP12
From: Tim Davis <timdavis@tdcon.com>
Date: Thu, 18 Mar 1999 21:21:12 -0700
Links: << >>  << T >>  << A >>
Anybody have any experience with the Xilinx PCI Core and the Orca 3TP12? Willing to share a
comparison of the two?

--

Tim Davis

Article: 15331
Subject: Re: Xilinx routing problem: removing "reset" increases cycle time.
From: Zhen Luo <zhenluo@ee.princeton.edu>
Date: Thu, 18 Mar 1999 23:49:24 -0500
Links: << >>  << T >>  << A >>
Well, I was using FOUNDATION V1.3, I guess it is old enough :).

I removed all the reset net, I couldn't understand why it would change, either.

I just got FOUNDATION V1.5, I will try on that to see it works better.

Zhen

Bruce Nepple wrote:

> Go back to the older version tools you used before (just a guess, hehe)
>
> Assuming you actually removed all the reset statements so there is no reset
> net, I can't understand why it would change.
>
> I think the placement tools use random number seeds based on your xnf file.
> Perhaps you could try different seeds until you got a placement that works
> better.
>
> bruce
>
> Zhen Luo wrote in message <36F09361.1005121B@ee.princeton.edu>...
> >I have a design that used a global reset signal on XC4000e. Later on I
> >removed this signal since I decided to utilize the initial "0" state of
> >all FFs. However, I could never synthesize my design at the clock rate
> >it used to be. Anyone has the same exprience here? How could I get
> >around this problem?
> >
> >-- Zhen
> >
> >



Article: 15332
Subject: Re: Allowed logic functions in Virtex LE
From: arast@inficom.com (Alex Rast)
Date: Fri, 19 Mar 1999 06:32:49 GMT
Links: << >>  << T >>  << A >>
In article <7cs49q$25n$1@feynman.xsj.xilinx.com>, mcgett@feynman.xsj.xilinx.com (Ed McGettigan) wrote:
>In article <36f15dc2@news.nwlink.com>, Alex Rast <arast@inficom.com> wrote:
..
>The typical question is "How can I make the CLB do f(a,b,c,d)?"
>Where a,b,c,d are inputs to the CLB.  I am still not sure what
>function is served by trying to generate a fixed CLB set of outputs
>that appear to be independent of inputs...

No, the outputs are not necessarily independent of inputs. But they *are* 
independent of each other. Thus it would be nice to be able to generate

XB=f(a,b,c,d), Y=g(a,b,c,d) YB=h(a,b,c,d) h<>q(f,g), g<>r(f,h), f<>s(g,h).

Note that a,b,c,and d need not be the same inputs for each output, and some of 
them could be always null.

>>... I do still find 
>>one output combination that *does* seem to be impossible, namely YB=1, Y=1, 
>>XB=0. Does this look correct?
>You're correct it is functionally impossible to have the above set
>of outputs in Virtex if you are not allowed to use the BY input as
>you previously indicated. 

Which appears, at least on surface, to be simply a pass-through input, i.e. 
YB=BY, not YB=F(BY). So it barely counts. I'm a little surprised, however, at 
the broken symmetry between XB and YB - it's possible to have an XB output 
that is independent of X and Y, but apparently not a YB output.

Alex Rast
arast@inficom.com
Article: 15333
Subject: Xilinx Vhdl "'event" synthesis problem
From: Jamie Morken <foster@uvic.ca>
Date: Fri, 19 Mar 1999 01:04:48 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------060ADD051CB09F9BA6374B23
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi all,

I am working on an 8 bit processor and I get an synthesis error that I
can't figure out.   I have tried to order the code in many different
ways, but I always get an error relating to the 'event on one of the
signals (inc_pc).  Here is the error message I get:
-- error line 75: This use of clock edge specification not supported
This code simulates fine using Mentor Graphics.
Thanks for your time.
Jamie Morken

--------------060ADD051CB09F9BA6374B23
Content-Type: text/plain; charset=us-ascii; name="jampc.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="jampc.vhd"

-- Program Counter Module 
--
-- Jamie Morken, Cayce Marston
-- Created: March 11, 1999
--
--	REVISION HISTORY
--	
--	DATE		BY WHOM		DESCRIPTION
--	March 15/99	CM,JM		Modified logic
--	March 16/99	CM,JM		Added load_pc input signal for branch/return
--					PC now loadable


-- pc.vhd



LIBRARY ieee;                	-- Include the ieee library
USE ieee.std_logic_1164.ALL; 	-- Logical naming of the 1164 part
USE work.cpu_pkg.ALL;


PACKAGE pc_pkg IS	 	-- Package declaration for the PC
        COMPONENT pc   		-- Include component memory        
        PORT (		
		value_in	: IN	std_logic_vector(bus_width DOWNTO 0);
		reset_in	: IN	std_logic;
		inc_pc		: IN	std_logic;	
		read_write	: IN	std_logic;		
		oe		: IN	std_logic;
			
		b_bus_out	: OUT	std_logic_vector(bus_width DOWNTO 0)
   	     );       
        END COMPONENT;
END pc_pkg;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;
--USE ieee.std_logic_arith.ALL;
USE work.cpu_pkg.ALL;

ENTITY pc IS 
	PORT (		
		value_in	: IN	std_logic_vector(bus_width DOWNTO 0);
		reset_in	: IN	std_logic;
		inc_pc		: IN	std_logic;	
		read_write	: IN	std_logic;		
		oe		: IN	std_logic;		
		
		b_bus_out	: OUT	std_logic_vector(bus_width DOWNTO 0)
	     );
	END;

ARCHITECTURE behave OF pc IS

SIGNAL pc_reg: std_logic_vector(bus_width DOWNTO 0);


BEGIN
	PROCESS (inc_pc, reset_in, read_write, oe, value_in) 
	
	BEGIN
	  IF (reset_in = '0') THEN	-- reset pc_reg
	     pc_reg <= (OTHERS =>'0');	
	  
	  ELSE	  	  
	  
	     IF (inc_pc'event AND inc_pc = '0')  THEN  -- this is the line
						       --with the error.
	        pc_reg <= pc_reg + 1;	  
     
	     ELSE
	     	  	 	  
	     	IF read_write = '1' THEN 	-- Read from PC, output to b_bus
		    IF oe = '0' THEN
		        b_bus_out <= pc_reg;	-- Output PC to b_bus	  	
		    END IF;
		END IF;
		      
		IF read_write = '0' THEN	-- Write to PC		    
		    pc_reg <= value_in;	-- Read input regardless of oe		  	
	  	END IF;
	 	
	 	
	     IF oe = '1' THEN
	       	b_bus_out <= (OTHERS =>'Z');	-- disable output     
	     END IF;

	    END IF;
	   
	 END IF;	
	
   END PROCESS;
   
END behave;

-- error line 75: This use of clock edge specification not supported 

--------------060ADD051CB09F9BA6374B23--

Article: 15334
Subject: Re: Xilinx Vhdl "'event" synthesis problem
From: "Karim LIMAM" <klimam@ensem.u-nancy.fr>
Date: Fri, 19 Mar 1999 10:14:17 +0100
Links: << >>  << T >>  << A >>
Hi,

    I think the problem is that you use an ELSE after the IF signal'EVENT
....  this kind of edge specification is not synthetisable !!

You can increment (and reset) your pc_reg in an other process


kerim el imem


Jamie Morken a écrit dans le message <36F21330.216AB342@uvic.ca>...
>Hi all,
>
>I am working on an 8 bit processor and I get an synthesis error that I
>can't figure out.   I have tried to order the code in many different
>ways, but I always get an error relating to the 'event on one of the
>signals (inc_pc).  Here is the error message I get:
>-- error line 75: This use of clock edge specification not supported
>This code simulates fine using Mentor Graphics.
>Thanks for your time.
>Jamie Morken
>


Article: 15335
Subject: Re: Xilinx Vhdl "'event" synthesis problem
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Fri, 19 Mar 1999 10:30:01 +0100
Links: << >>  << T >>  << A >>
Jamie Morken wrote:
< snip >
> I get an synthesis error that I can't figure out. I have tried to
> order the code in many different ways, but I always get an error
> relating to the 'event on one of the signals (inc_pc).  Here is the
> error message I get: -- error line 75: This use of clock edge
> specification not supported

Your code looks a bit strange to me... I can't see the point of using an
ELSE statement after "IF clk = '1' AND clk'EVENT THEN"
I also think that the b_bus_out assignments should be done out of this
process : b_bus_out doesn't change on reset and is independant of
your clock signal.
I also have a question : what is the value of b_bus_out when read_write
= '0' ?

See my version of your architecture below

------------------------------------------------------------------------
  ARCHITECTURE behave OF pc IS
 
  SIGNAL pc_reg: std_logic_vector(bus_width DOWNTO 0);
 
  BEGIN

        b_bus_out <= (OTHERS =>'Z') WHEN oe = '1'    -- disable output

                ELSE pc_reg WHEN read_write = '1'

                ELSE ?? ;	-- any default value there ?
 
        PROCESS (inc_pc, reset_in, read_write)
 
        BEGIN
          IF (reset_in = '0') THEN      -- reset pc_reg
             pc_reg <= (OTHERS =>'0');
 
          ELSIF read_write = '0' THEN        -- Asynchronous write to PC
             pc_reg <= value_in; -- Read input regardless of oe

          ELSIF (inc_pc'event AND inc_pc = '0')  THEN 

             pc_reg <= pc_reg + 1;
 
          END IF;
 
    END PROCESS;
 
  END behave;


Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
mail reply : remove one dot from my address (guess which :o)
Article: 15336
Subject: Placement control in ALtera devices
From: "Sebastia A. Bota" <sbota@el.ub.es>
Date: Fri, 19 Mar 1999 13:01:25 +0000
Links: << >>  << T >>  << A >>
Is possible to control the placement in Altera devices (8282 or 10K10
devices) In order to implement a logic circuit at an specific logic
module of the FPGA ?

Where can I find information about the format of the bitstream used to
program the device ?

Thanks

Sebastia

Article: 15337
Subject: Re: Xilinx Spartan configuration troubles
From: Mike Randelzhofer <Michael.Randelzhofer@mchf.siemens.de>
Date: Fri, 19 Mar 1999 14:50:04 +0100
Links: << >>  << T >>  << A >>
Hello Jeff,

I designed a board with 2 spartan xcs05 (5V) devices configured by a
xc9572 and a flash-prom. Due to an error in schematics, i removed the
designed-in pulldown (it should be a pullup). So the mode pin is
floating, and during configuration i can measure there a strong
5V-level. After configuration has finished there is no pullup any more;
measuring 0V (maybe mode is driving GND ?). Everything works fine. So i
am really interested in the behaviour of the xcs05xl-device modepin. (i
am still waiting for availability of the xcs05xl in Germany).

Jeff Hunsinger wrote:
> 
> Thanks to all who responded. My problem turned out to be leaving the
> MODE pin floating and counting on the weak pull-up to keep it high.
> 
> I tied a 10K pullup to VCC and all my problems disappeared.
> 
> Thanks again,
> Jeff
Article: 15338
Subject: Re: Foundation V1.5 Crash
From: lemenst@fhsmtp.fh.trw.com (Thomas LeMense)
Date: Fri, 19 Mar 1999 14:12:05 GMT
Links: << >>  << T >>  << A >>
On Fri, 05 Mar 1999 16:21:00 -0500, Brian Boorman
<XZY.bboorman@harris.com> wrote:
>Since I also scrapped the gui in favor of an automatic batch file, I am
>beginning to wonder how many others have done the same thing. Since I

>Jeff Hunsinger wrote:
><snip> 
>> .....I quickly
>> gave up on it and just run the whole thing from the command line with a
>> make file.
>> 

I wish I knew enough about make to write a good, robust makefile.
(Yes, as a matter of fact I *DO* live in the stone age!)  Any chance
of either of you sharing what you've created with other c.a.fpga
readers?  I wholeheartedly agree that the GUI can be a real pain, and
the version control is a bit ...er... strange at times.

-tom

Tom LeMense
TRW Automotive Electronics
Farmington Hills, MI facility
lemenst@fhsmtp.fh.trw.com
Article: 15339
Subject: Re: How can I improve an adder?
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Fri, 19 Mar 1999 14:23:03 GMT
Links: << >>  << T >>  << A >>
On Thu, 18 Mar 1999 20:37:49 GMT, Lasse Langwadt Christensen
<fuz@kom.auc.dk> wrote:

>emanuel stiebler wrote:
>> 
>> Hi,
>> 
>> Brian Drummond <brian@shapes.demon.co.uk> wrote in article
>> <36f57d3a.179649091@news.demon.co.uk>...
>> > On Tue, 16 Mar 1999 01:08:18 GMT, tcoonan@mindspring.com (Thomas A.
>> > Coonan) wrote:
>> >
>> > >Sounds like a school problem to me!
>> > >Go look for carry-lookahead adders in XILINX app notes on their WWW.
>> > >>I am currently trying to figure out how to improve an adder.  An n-bit
>> > >>adder can be constructed by cascading n full adders in series, with the
>> > >>carry into stage i, Ci, coming from the output of stage i-1.
>> >
>> > Yup, looks like homework.
>> >
>> > But here's a goldmine.
>> >
>> > http://www.iis.ee.ethz.ch/~zimmi/comp_arith_notes.ps.gz
>> 
>> Doesn't work. You sure this adress is right ?
>> 
>> cheers,
>> emanuel
>
>I you take the "front door" http://www.iis.ee.ethz.ch/~zimmi/ 
>and look around you sse the correct url is: 
>
>http://www.iis.ee.ethz.ch/~zimmi/publications/comp_arith_notes.ps.gz
>
oops - finger trouble. Thanks for fixing it.

- Brian
Article: 15340
Subject: Re: FPGA Express FSM Synthesis Concern
From: Elya Kapelyan <elya@pentek.com>
Date: Fri, 19 Mar 1999 10:13:21 -0500
Links: << >>  << T >>  << A >>


michaellewis@my-dejanews.com wrote:

> Hi:
>
> I have a concern about the synthesis of a state machine.  I
> am implementing a 16-bit mealy state machine using the
> "One Hot" and "fastest & smallest" options for compliling
> in FPGA Express. It turns out that one of the outputs of
> the state machine is functionally set when one of two
> (logical OR) of these states is set.  However, the EDIF
> netlist out of the tool gives 6 levels of logic to implement
> this 2-input OR gate. In fact, it is a function of nearly all
> (14 to be precise) state signals, as opposed to the 2 I would
> expect.
>
> Even more curious is the fact that I see some of these
> mutually exclusive One-Hot state signals entering LUTs
> with AND-gate functions.  But the output of the AND
> gate can never be set if the inputs are truly mutually
> exclusive.  Maybe the compiler is providing a "safe"
> representation, allowing for recovery from illegal
> combinations of states, but I specifically opted for
> "fastest & smallest" instead.
>
> Any ideas?
>

    In the past I have run into the same problem when targetting a Xilinx
device, and I think that it is a result of poor design of the synthesizer.
As far as I can tell, when FPGA Express decodes the states it does not
differentiate between a state machine that is fully encoded (as in a PLD)
and a one-hot implementation (as in a FPGA).  As a result, it uses all of
the state bits to select between states which can lead to severe timing
problems in FPGA designs.  BTW, I don't know how Synplicity or Exemplar
handle this case, but I think that it is a big problem with FPGA Express.

    My "solution" to this problem was to code my state machine as 3
processes:  a combinatorial process, a registered process (for the state
machine), and another registered process where I used additional flops that
were asserted/deasserted during the states that I was interested in.  I
then used these additional flops to drive the rest of my logic, and got the
expected circuits.

     Admittedly, this is far from an elegant solution, but it worked.


    Good luck.

    Elya Kapelyan


>
> Thanks,
> Mike
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own

Article: 15341
Subject: Re: Power Estimiation
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Fri, 19 Mar 1999 16:29:11 +0100
Links: << >>  << T >>  << A >>
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I think that this subjet of power estimation is becoming so pasionated,
that surpriseme, cause I thaught that only me was interested in this subjet.
I'm agree with Peter, the K factor and the Altera's model has no good
bases and it was madden only to provide an idea of the power consumption
of Altera's products in some circunstances, after months of measurements, I
can tell you that the model is wrong wrong and wrong.

I'm agree with Bob also, xilinx didn't and don't make efforts to estimate
and/or
to optimize power, and reducin VCC is not a good solution, designers wants to
run more and more fasters. I don't work with xilinx or Altera neither, I'm
trying
to analize both and to understand how, why, when and where they consumes.

I'll take the Bob's contribution and I'll try to make a contribution

bob elkind wrote:

> Here's a designer's perspective:
>
> Suggestion:  Provide a spreadsheet type of tool that
>
> a. groups power consumption "factors" (e.g. gross net capacitance, gross
> gate capacitance) by clock net "driving" the power consuming components.
>

I divided the FPGA architecture in the following big pieces :
-LUTs
-DFFs
-Clock Tree
-Interconnect
-I/Os
-Memory blocks (or CLBs configured as memory).

The interconnect can me divided in more pieces (half fast track, full fast
track, columns, or simple, double, long lines)

Here we have groups with similar (or the same) capacitance.

>
> b. provides parameters for each group (each group is driven by a different
> clock!) for
>
>   i.  clock frequency
>  ii.  average toggle factor (# clock cycles between state changes)
>

For each defined group we can provide parameters, like the average toggling
rate of each one
and the power supply of each group (some FPGAs uses 3.3 for internal logic and
5 volts for I/Os).
Here it's important to defines what the toggling rate is.

>
> c. multiplies the right correction factors by the entered parameters and
> the derived gate count/capacitance numbers, and adds the products to an
> estimated power consumption number, taking into account the process
> parameters (or range of parameters) for the fpga in use.
>
> It won't be perfect, its results won't be guaranteed, but it would
> still be a *big* help.  And my guess is that the data required to "code"
> this is already lying around in the engineering dept.
>
> Does anyone agree that this would help ?  Does anyone agree that this
> is worth doing ?   Does anyone have any better solutions, or improvements ?
>

 Here we have a model that permits us to estimate power with a certain % of
error,
now the problem is, the toggling rate, first at all, we need REELS test
vectors,
to estimate the toggling rate, and second, a knlowledge of internal glitches in
FPGAs,
in asics power caused by glitches can represents the 15% of the total power
consumption.

For me, estimate power is important but it's not the MOST important, with a
tool that allows
to estimate it with a 5% or error is fine (maybe by now it's a dream). The most
important
thing of a knowledge of power consumption in FPGAs is to optimize algoritms
using the
existing FPGAs and to optimize FPGA's architectures for futures families.

Anyway who has the truth in his hand?


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tel;work:(33-1)-45-81-78-03
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--------------475081234C2C0861810B6BF4--

Article: 15342
Subject: Biterby or treillis application
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Fri, 19 Mar 1999 16:33:46 +0100
Links: << >>  << T >>  << A >>
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I need information about designs of beiterby encoders or theillis
encoders
using FPGA.

Can anybody helps me?

Thank you

Andres David

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tel;work:(33-1)-45-81-78-03
x-mozilla-html:TRUE
org:Ecole Nationale Superieure des Telecommunications; Dept. Communications et Electronique
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email;internet:garcia@elec.enst.fr
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fn:Andres David Garcia Garcia
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--------------89EE418778AD5C8CD6B633BC--

Article: 15343
Subject: FPGA vendor comparison
From: Pierre Langlois <langlois-p@rmc.ca>
Date: Fri, 19 Mar 1999 11:28:22 -0500
Links: << >>  << T >>  << A >>
Hello,

apologies in advance if this question has been asked a thousand times.

I am looking for a "concise" comparison document of the current FPGAs on
the market.  The comparison would include such things as typical maximum
internal speeds, volatility, size in blocks and/or gates, prices,
strengths (i.e. fast I/Os, fast arithmetic, best for DSP, most routing
resources, easy-to-use tools, etc.).  It is probably impossible to say
"in general, FPGA X is better than FPGA Y", but it is probably correct
to say such a thing for a particular application.

The question I am trying to answer is:
given a particular application, which FPGA from which manufacturer
should a designer use?

Is there such a document on the Web?  In a FAQ, maybe?  If not, I would
appreciate comments based on personal experience.


===============================================
Pierre Langlois
Département de mathématiques et informatique
Collège militaire royal du Canada              tél. (613)541-6000 x6860
B.P. 17000 Succ. "FORCES"                      fax. (613)541-6584
Kingston ON  K7K 7B4   Canada                  langlois-p@rmc.ca
===============================================


Article: 15344
Subject: Re: Reconfigurable computing thesis on the web
From: Tim Tyler <tt@cryogen.com>
Date: Fri, 19 Mar 1999 16:40:14 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga Zik Saleeba <zik@zikzak.net> wrote:

: As far as I'm aware all of the existing attempts at this are just
: using conventional off-the-shelf FPGAs. My hardware architecture is
: specifically designed to provide support for a full general-purpose
: virtual-logic computing environment based around reconfigurable logic
: elements. It's rather a big step from FPGAs :)

Most currently FPGA boards plug into - at best - a PCI socket.

The most optomistic estimate I've encountered for the progress of
FPGA-based systems into more mainstream applications envisages that a
corner of conventional CPUs gets devoted to programable logic activities,
for the cases where a circuit can perform the task more efficiently than
an instruction sequence - and that circuit is actually known.

I'm not sure that "a full, general-purpose virtual logic computing
enviroment" would be seen to be an evolutionary step from current
systems, and I wonder if it will not be too much programmable logic
too quickly - or, to put it another way, I wonder if it will be too
expensive...?
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Magnet: Windows cleaner.
Article: 15345
Subject: Tech Note
From: "mdisman" <mdisman@ix.netcom.com>
Date: Fri, 19 Mar 1999 08:52:28 -0800
Links: << >>  << T >>  << A >>
This week's EDTN Tech Note is an article from Lattice Semiconductor that
discusses performance and logic utilization tradeoffs between combinatorial
and pipelined designs for CPLDs.  The article can be found in the Tech Notes
section of EDTN's PLD Design Center at www.edtn.com/pld

Murray Disman
Editor
PLD Design Center


Article: 15346
Subject: Re: Power Estimiation
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Fri, 19 Mar 1999 10:15:40 -0800
Links: << >>  << T >>  << A >>
I think I finally have my line wrap problem solved - here goes:

If you have node capacitance and voltage swing data (from the FPGA vendor),
a simulator that can generate a node toggle report (ModelSim Elite or ???), and
power test vectors (available only from an engineer with some insight into
his/her design) it is in principle possible to predict power consumption as
accurately as it can ever be predicted. Assuming good data from the FPGA vendor,
the onus is then on the engineer to provide test vectors that exercise the
design realistically enough to meet the accuracy required. I would hate to
see FPGA vendors waste effort on providing glitzy software that just automates
the crude estimation methods currently offered when they could (I think) more
easily just provide the node data. Of course, if they do both, there is no problem.

Your reminder about glitch power was good - I had been hoping that a simple functional
simulator might be adequate (pretty easy to write), but glitches caused by delay
skew on combinatorial inputs will consume significant power as you say, so
timing is required, which means a bit more work for anyone with fantasies of writing
(or having a student write) a crude simulator just for power estimation. 


Andres David Garcia Garcia wrote:
> 
<snipped>
> 
>  Here we have a model that permits us to estimate power with a certain % of
> error,
> now the problem is, the toggling rate, first at all, we need REELS test
> vectors,
> to estimate the toggling rate, and second, a knlowledge of internal glitches in
> FPGAs,
> in asics power caused by glitches can represents the 15% of the total power
> consumption.
> 
> For me, estimate power is important but it's not the MOST important, with a
> tool that allows
> to estimate it with a 5% or error is fine (maybe by now it's a dream). The most
> important
> thing of a knowledge of power consumption in FPGAs is to optimize algoritms
> using the
> existing FPGAs and to optimize FPGA's architectures for futures families.
> 
> Anyway who has the truth in his hand?
> 
>

Tom Burgess
-- 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767
Article: 15347
Subject: Bit Error Rate Test
From: "Dan" <dan@kvdco.com>
Date: Fri, 19 Mar 1999 10:21:17 -0800
Links: << >>  << T >>  << A >>
I am looking for information on building a small Bit Error Rate Tester
inside a Xilinx.

I have a Xilinx FPGA controlling a communications channel between a PCI card
and an external cage.  I am thinking it would be useful to place a Bit Error
Rate Tester in the Xilinx to test the link and to determine its maximum
transfer rate.

It would be simple to generate a pseudo-random pattern to transmit down the
link, but I cannot think of an easy way to sync back up to the received
data, and count errors.  I know this has been done before, I am just trying
to avoid reinventing the wheel.


Thanks

Dan





Article: 15348
Subject: Re: Power Estimiation - report.zip (0/1)
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Fri, 19 Mar 1999 20:40:52 GMT
Links: << >>  << T >>  << A >>
On Wed, 17 Mar 1999 14:58:34 -0800, Tom Burgess
<tom.burgess@hia.nrc.ca> wrote:

>Hmm. Looks like this would do just fine. I assume that this
>was from the ModelSim Elite ~$20,000 (U.S.) tool? Regrettably

Indeed. EE is a great product, but for those who don't need such
esoteric features, PE is truly excellent. Until the FPGA vendors come
out with such figures and tools that can utilise such information and
are accurate; there is little point (IMHO) in offering a feature to a
market that cannot make use of it. Who knows what the future may
bring? 

How about it Xilinx and Altera? Let's see a new slogan on those web
sites: "Mines smaller than yours" (power consumption that is).

>this exceeds my nonexistent tools budget by a couple of orders
>of magnitude, but it does serve as an existence proof.

My condolences.

Cheers
Stuart
For Email remove "NOSPAM" from the address
Article: 15349
Subject: Re: FPGA Express FSM Synthesis Concern
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Fri, 19 Mar 1999 12:56:39 -0800
Links: << >>  << T >>  << A >>
Did you ever try the //synopsys full_case parallel_case pragmas?

bruce

Elya Kapelyan wrote in message <36F26991.7C8640DE@pentek.com>...
>
>
>michaellewis@my-dejanews.com wrote:
>
>> Hi:
>>
>> I have a concern about the synthesis of a state machine.  I
>> am implementing a 16-bit mealy state machine using the
>> "One Hot" and "fastest & smallest" options for compliling
>> in FPGA Express. It turns out that one of the outputs of
>> the state machine is functionally set when one of two
>> (logical OR) of these states is set.  However, the EDIF
>> netlist out of the tool gives 6 levels of logic to implement
>> this 2-input OR gate. In fact, it is a function of nearly all
>> (14 to be precise) state signals, as opposed to the 2 I would
>> expect.
>>
>> Even more curious is the fact that I see some of these
>> mutually exclusive One-Hot state signals entering LUTs
>> with AND-gate functions.  But the output of the AND
>> gate can never be set if the inputs are truly mutually
>> exclusive.  Maybe the compiler is providing a "safe"
>> representation, allowing for recovery from illegal
>> combinations of states, but I specifically opted for
>> "fastest & smallest" instead.
>>
>> Any ideas?
>>
>
>    In the past I have run into the same problem when targetting a Xilinx
>device, and I think that it is a result of poor design of the synthesizer.
>As far as I can tell, when FPGA Express decodes the states it does not
>differentiate between a state machine that is fully encoded (as in a PLD)
>and a one-hot implementation (as in a FPGA).  As a result, it uses all of
>the state bits to select between states which can lead to severe timing
>problems in FPGA designs.  BTW, I don't know how Synplicity or Exemplar
>handle this case, but I think that it is a big problem with FPGA Express.
>
>    My "solution" to this problem was to code my state machine as 3
>processes:  a combinatorial process, a registered process (for the state
>machine), and another registered process where I used additional flops that
>were asserted/deasserted during the states that I was interested in.  I
>then used these additional flops to drive the rest of my logic, and got the
>expected circuits.
>
>     Admittedly, this is far from an elegant solution, but it worked.
>
>
>    Good luck.
>
>    Elya Kapelyan
>
>
>>
>> Thanks,
>> Mike
>>
>> -----------== Posted via Deja News, The Discussion Network ==----------
>> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
>




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