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Messages from 156750

Article: 156750
Subject: Re: PLA? PAL? PLD? GAL?
From: GaborSzakacs <gabor@alacron.com>
Date: Mon, 16 Jun 2014 16:05:22 -0400
Links: << >>  << T >>  << A >>
azimalimoll@gmail.com wrote:
> On Saturday, February 18, 1995 9:26:05 AM UTC+5:30, u801...@cc.nctu.edu.tw wrote:
>> Hello,
>>
>> I would like to know something diffrent among them? I was always cunfused
>> by them all.
>>
>> In my previous impression, they are:
>>
>> PAL: programmable AND, fixed OR
>> PLD: programmable AND, programmable OR
>> PLA: ???????????? AND, ???????????? OR
>> GAL=PLD ??
>>
>> Please correct the above, Thanks in advance!
>>
>> 					Jason
> 

PAL was programmable AND, fixed OR.  And it was a bipolar process
with fusible links for programming (one-time programmable).

GAL, also called PALCE, was the exact same thing as a PAL from
the architecture standpoint, but was CMOS and electrically erasable
and reprogrammable.

PLD is just a generic term for all programmable logic devices, and
does not imply any particular architecture.

PLA was used mostly for programmable AND / programmable OR parts
as you noted, but there may have been exceptions.

CPLD or "complex" PLD usually implies a PAL or PLA architecture
with multiple PAL or PLA-like blocks interconnected by a global
matrix.  However in recent years, the term is also used for small
FPGA devices that have built-in non-volatile configuration memory.

-- 
Gabor

Article: 156751
Subject: Re: PLA? PAL? PLD? GAL?
From: rickman <gnuarm@gmail.com>
Date: Tue, 17 Jun 2014 19:34:57 -0400
Links: << >>  << T >>  << A >>
On 6/16/2014 4:05 PM, GaborSzakacs wrote:
> azimalimoll@gmail.com wrote:
>> On Saturday, February 18, 1995 9:26:05 AM UTC+5:30,
>> u801...@cc.nctu.edu.tw wrote:
>>> Hello,
>>>
>>> I would like to know something diffrent among them? I was always
>>> cunfused
>>> by them all.
>>>
>>> In my previous impression, they are:
>>>
>>> PAL: programmable AND, fixed OR
>>> PLD: programmable AND, programmable OR
>>> PLA: ???????????? AND, ???????????? OR
>>> GAL=PLD ??
>>>
>>> Please correct the above, Thanks in advance!
>>>
>>>                     Jason
>>
>
> PAL was programmable AND, fixed OR.  And it was a bipolar process
> with fusible links for programming (one-time programmable).
>
> GAL, also called PALCE, was the exact same thing as a PAL from
> the architecture standpoint, but was CMOS and electrically erasable
> and reprogrammable.
>
> PLD is just a generic term for all programmable logic devices, and
> does not imply any particular architecture.
>
> PLA was used mostly for programmable AND / programmable OR parts
> as you noted, but there may have been exceptions.
>
> CPLD or "complex" PLD usually implies a PAL or PLA architecture
> with multiple PAL or PLA-like blocks interconnected by a global
> matrix.  However in recent years, the term is also used for small
> FPGA devices that have built-in non-volatile configuration memory.

Not much can be added to Gabor's explanation.  But for the most part 
these terms are not of much use today and are mostly either historical 
or marketing.  PLD in theory covers it all including FPGAs, but is often 
used to denote a smaller device at the low price end of the scale.  Even 
that is becoming blurred as some FPGAs start to show up at the low end 
of pricing.

So if you want to design a logic device into your system, don't worry 
with terms and abbreviations.  Just decide what features you need and 
select a part that works for you.

-- 

Rick

Article: 156752
Subject: Re: PLA? PAL? PLD? GAL?
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Wed, 18 Jun 2014 08:55:58 +0100
Links: << >>  << T >>  << A >>
On 18/06/14 00:34, rickman wrote:
> So if you want to design a logic device into your system, don't worry with terms and abbreviations.  Just decide what features you need and select a part that works for you.

That's sensible.

A rule of thumb when /starting/ to select a device is:
   - CPLD: smaller, fewer flip flops, lower maxim clock
     speed, but more predictable timing that doesn't
     change much as when you vary the implemented function.
     Toolsets might be significantly simpler.
   - FPGA: larger, more flip flops and other functions,
     higher maximum internal clock speed (but similar
     external clock speed), but timing that can vary
     significantly with apparently trivial changes to the
     VHDL/Verilog.

but /completing/ selection of a device requires a detailed
understanding of its capabilities w.r.t. your application.

For beginners, I'd suggest starting with a CPLD unless
they require an FPGA's capabilities.


Article: 156753
Subject: Re: PLA? PAL? PLD? GAL?
From: colin <colin_toogood@yahoo.com>
Date: Wed, 18 Jun 2014 06:52:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Wednesday, June 18, 2014 8:55:58 AM UTC+1, Tom Gardner wrote:
> On 18/06/14 00:34, rickman wrote:
> 
> > So if you want to design a logic device into your system, don't worry with terms and abbreviations.  Just decide what features you need and select a part that works for you.
> 
> 
> 
> That's sensible.
> 
> 
> 
> A rule of thumb when /starting/ to select a device is:
> 
>    - CPLD: smaller, fewer flip flops, lower maxim clock
> 
>      speed, but more predictable timing that doesn't
> 
>      change much as when you vary the implemented function.
> 
>      Toolsets might be significantly simpler.
> 
>    - FPGA: larger, more flip flops and other functions,
> 
>      higher maximum internal clock speed (but similar
> 
>      external clock speed), but timing that can vary
> 
>      significantly with apparently trivial changes to the
> 
>      VHDL/Verilog.
> 
> 
> 
> but /completing/ selection of a device requires a detailed
> 
> understanding of its capabilities w.r.t. your application.
> 
> 
> 
> For beginners, I'd suggest starting with a CPLD unless
> 
> they require an FPGA's capabilities.

Also note that a CPLD tends to need one supply whilst an FPGA tends to need at least three.

Article: 156754
Subject: Re: PLA? PAL? PLD? GAL?
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 18 Jun 2014 16:40:22 +0100 (BST)
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> wrote:
> Not much can be added to Gabor's explanation.  But for the most part 
> these terms are not of much use today and are mostly either historical 
> or marketing.

Unsurprising since the original post was 19 years ago...

Theo

Article: 156755
Subject: Re: PLA? PAL? PLD? GAL?
From: "Andy Bartlett" <abartlett@nospam.net>
Date: Wed, 18 Jun 2014 17:52:56 +0100
Links: << >>  << T >>  << A >>

"colin" <colin_toogood@yahoo.com> wrote in message 
news:00ed3019-24c7-43f6-83fa-f3c3d1669bc3@googlegroups.com...
> On Wednesday, June 18, 2014 8:55:58 AM UTC+1, Tom Gardner wrote:
>> On 18/06/14 00:34, rickman wrote:
>>
>> > So if you want to design a logic device into your system, don't worry 
>> > with terms and abbreviations.  Just decide what features you need and 
>> > select a part that works for you.
>>
>>
>>
>> That's sensible.
>>
>>
>>
>> A rule of thumb when /starting/ to select a device is:
>>
>>    - CPLD: smaller, fewer flip flops, lower maxim clock
>>
>>      speed, but more predictable timing that doesn't
>>
>>      change much as when you vary the implemented function.
>>
>>      Toolsets might be significantly simpler.
>>
>>    - FPGA: larger, more flip flops and other functions,
>>
>>      higher maximum internal clock speed (but similar
>>
>>      external clock speed), but timing that can vary
>>
>>      significantly with apparently trivial changes to the
>>
>>      VHDL/Verilog.
>>
>>
>>
>> but /completing/ selection of a device requires a detailed
>>
>> understanding of its capabilities w.r.t. your application.
>>
>>
>>
>> For beginners, I'd suggest starting with a CPLD unless
>>
>> they require an FPGA's capabilities.
>
> Also note that a CPLD tends to need one supply whilst an FPGA tends to 
> need at least three.

A CPLD will generally not have any RAM available, any storage you need 
having to be made up from the normal registers available throughout the 
fabric. It will also not have any integrated MACs or other DSP components. 
It will contain shadow flash configuration memory within the device so will 
tend to be instant boot.

An FPGA will have much RAM/MACs/DSP components, and higher end newer devices 
will also have processors integrated in to the fabric. They tend to be 
volatile devices and require external configuration memory which slows the 
boot time to several 100ms. 



Article: 156756
Subject: Re: PLA? PAL? PLD? GAL?
From: Tim Wescott <tim@seemywebsite.really>
Date: Wed, 18 Jun 2014 12:50:07 -0500
Links: << >>  << T >>  << A >>
On Mon, 16 Jun 2014 11:59:26 -0700, azimalimoll wrote:

> On Saturday, February 18, 1995 9:26:05 AM UTC+5:30,
> u801...@cc.nctu.edu.tw wrote:
>> Hello,
>> 
>> I would like to know something diffrent among them? I was always
>> cunfused by them all.
>> 
>> In my previous impression, they are:
>> 
>> PAL: programmable AND, fixed OR PLD: programmable AND, programmable OR
>> PLA: ???????????? AND, ???????????? OR GAL=PLD ??
>> 
>> Please correct the above, Thanks in advance!
>> 
>> 					Jason

Why are we bothering with a 20 year old revived thread?

This reminds me of an old 'B' horror movie that starts with a guy pulling 
a stake out of the chest of a skeleton in a circus exhibit, and becoming 
the vampire's first victim in a century.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156757
Subject: NAND flash interface through FPGA
From: munishkumar86 <munishkumar86@gmail.com>
Date: Wed, 18 Jun 2014 15:34:21 -0500
Links: << >>  << T >>  << A >>
i want to interfacing NAND FlASH through FPGA.Anyone can help me?




Article: 156758
Subject: Re: NAND flash interface through FPGA
From: hamilton <hamilton@nothere.com>
Date: Wed, 18 Jun 2014 14:46:53 -0600
Links: << >>  << T >>  << A >>
On 6/18/2014 2:34 PM, munishkumar86 wrote:
> i want to interfacing NAND FlASH through FPGA.Anyone can help me?
>
>
>
which NAND Flash, which FPGA ?

Article: 156759
Subject: Re: PLA? PAL? PLD? GAL?
From: rickman <gnuarm@gmail.com>
Date: Wed, 18 Jun 2014 18:13:09 -0400
Links: << >>  << T >>  << A >>
On 6/18/2014 9:52 AM, colin wrote:
> On Wednesday, June 18, 2014 8:55:58 AM UTC+1, Tom Gardner wrote:
>> On 18/06/14 00:34, rickman wrote:
>>
>>> So if you want to design a logic device into your system, don't worry with terms and abbreviations.  Just decide what features you need and select a part that works for you.
>>
>>
>>
>> That's sensible.
>>
>>
>>
>> A rule of thumb when /starting/ to select a device is:
>>
>>     - CPLD: smaller, fewer flip flops, lower maxim clock
>>
>>       speed, but more predictable timing that doesn't
>>
>>       change much as when you vary the implemented function.
>>
>>       Toolsets might be significantly simpler.
>>
>>     - FPGA: larger, more flip flops and other functions,
>>
>>       higher maximum internal clock speed (but similar
>>
>>       external clock speed), but timing that can vary
>>
>>       significantly with apparently trivial changes to the
>>
>>       VHDL/Verilog.
>>
>>
>>
>> but /completing/ selection of a device requires a detailed
>>
>> understanding of its capabilities w.r.t. your application.
>>
>>
>>
>> For beginners, I'd suggest starting with a CPLD unless
>>
>> they require an FPGA's capabilities.
>
> Also note that a CPLD tends to need one supply whilst an FPGA tends to need at least three.

That entirely depends on the FPGA.  There are plenty of FPGAs with only 
one power supply voltage.

-- 

Rick

Article: 156760
Subject: Re: NAND flash interface through FPGA
From: rickman <gnuarm@gmail.com>
Date: Wed, 18 Jun 2014 18:14:32 -0400
Links: << >>  << T >>  << A >>
On 6/18/2014 4:34 PM, munishkumar86 wrote:
> i want to interfacing NAND FlASH through FPGA.Anyone can help me?

Yes.

-- 

Rick

Article: 156761
Subject: Re: NAND flash interface through FPGA
From: Tim Wescott <tim@seemywebsite.really>
Date: Wed, 18 Jun 2014 17:17:20 -0500
Links: << >>  << T >>  << A >>
On Wed, 18 Jun 2014 15:34:21 -0500, munishkumar86 wrote:

> i want to interfacing NAND FlASH through FPGA.Anyone can help me?

Here is a step-by-step guide:

Step 1: Read the NAND Flash data sheet.

Step 2: Read the FPGA data sheet.

Step 3: Familiarize yourself with your FPGA tools.

Step 4: Get to work.

If you have SPECIFIC questions, feel free to ask them.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com


Article: 156762
Subject: Re: PLA? PAL? PLD? GAL?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 19 Jun 2014 02:59:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> wrote:

> That entirely depends on the FPGA.  There are plenty of FPGAs 
> with only one power supply voltage.

Well, many have separate I/O power pins, and you might be able to
run that at the same voltage as the core, but often the core voltage
is close to 1.0, and that is low for many I/O pins.

-- glen

Article: 156763
Subject: PLB to AMBA AHB bus bridge
From: Mariem Makni <mariam.makni@gmail.com>
Date: Sun, 22 Jun 2014 06:24:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everybody,
 
I want to know if there is an opensource PLB to AMBA AHB Bridge?
 
Thanks.
regards, 

Article: 156764
Subject: problem with xc3s400 place and rout section
From: "nba83" <12020@embeddedrelated>
Date: Mon, 23 Jun 2014 00:11:29 -0500
Links: << >>  << T >>  << A >>
hi
i have a custom designed board with xilinx spartan 3( xc3s400 ) with two
ethernet phy layer (RTL8201) for a two port switch. I have a ring network
of 10 of this board on the chain. i transmit data from the first board and
count the number of packets from the last ethernet port of the tenth board
to test the integrity of switch and the hdl code. 
the code in some synthesis work without error but when i add another piece
of code for example a counter which is unrelated to the other logics and re
synthesis the code the previous parts of  my code work with error.
i guess it is due to place and route section and timing constranits of
ethernet phy layer. this phy layer has 2 independ transmit and receive clk
and due to ease of pcb routing i connected these clk signals to normal pins
not the global clk pins and now i think the timing constraints are disabled
since i used this contraint on the  pin   NET "RTL_RXCLK"
CLOCK_DEDICATED_ROUTE = "FALSE";
in timing reports it is said that all timing constraints are met but there
is warning saying “The use of
this override is highly discouraged as it may lead to very poor timing
results” . what is the problem and
how can i fixed the problem ?i cannot change the pcb because of the price
and time :(  is it possible to check and apply timing constraints in fpga
editor?
Tnx in advanced for any helpful comment
Neda Baheri
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 156765
Subject: Open source Verilog BCH encoder/decoder
From: Russell Dill <russd@asu.edu>
Date: Mon, 23 Jun 2014 01:35:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
As part of my research, I needed a BCH encoder/decoder engine. Sadly, such =
a thing has no existed under a permissive license. Even more depressing is =
that many students seem to submit Verilog or VHDL engines as a project (or =
even research), but never release anything that is usable.

Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers=
:

* Parallel input/output
* Modular components that can be shared across multiple decoders
* Automatic selection of BCH parameters based on data size and errors to be=
 corrected
* Specialized error locators for 1 error and 2 error codes
* Parallel or serial error polynomial generator for codes with 2 or more er=
rors

https://github.com/russdill/bch_verilog

I'm releasing this under BSD because I'd like to see the code used as widel=
y as possible, but I'd still like to get feedback and hopefully improvement=
s merged back in.

As an example, a decoder for a 512 byte data block that corrects up to 12 e=
rrors with an 8 bit wide input and an 8 bit wide output currently occupies =
1635 slices and operates at up to 191 MHz on a Virtex-6 LX240T-3. Such a de=
coder would take input for 532 clock cycles (512 data bytes, 20 ecc bytes),=
 calculate for about 28 clock cycles, and then produce output for 512 clock=
 cycles.

The code currently compiles on Icarus Verilog (latest git) and Xilinx XST/I=
sim (tested with 14.5).

Article: 156766
Subject: Re: problem with xc3s400 place and rout section
From: GaborSzakacs <gabor@alacron.com>
Date: Mon, 23 Jun 2014 09:42:31 -0400
Links: << >>  << T >>  << A >>
nba83 wrote:
> hi
> i have a custom designed board with xilinx spartan 3( xc3s400 ) with two
> ethernet phy layer (RTL8201) for a two port switch. I have a ring network
> of 10 of this board on the chain. i transmit data from the first board and
> count the number of packets from the last ethernet port of the tenth board
> to test the integrity of switch and the hdl code. 
> the code in some synthesis work without error but when i add another piece
> of code for example a counter which is unrelated to the other logics and re
> synthesis the code the previous parts of  my code work with error.
> i guess it is due to place and route section and timing constranits of
> ethernet phy layer. this phy layer has 2 independ transmit and receive clk
> and due to ease of pcb routing i connected these clk signals to normal pins
> not the global clk pins and now i think the timing constraints are disabled
> since i used this contraint on the  pin   NET "RTL_RXCLK"
> CLOCK_DEDICATED_ROUTE = "FALSE";
> in timing reports it is said that all timing constraints are met but there
> is warning saying “The use of
> this override is highly discouraged as it may lead to very poor timing
> results” . what is the problem and
> how can i fixed the problem ?i cannot change the pcb because of the price
> and time :(  is it possible to check and apply timing constraints in fpga
> editor?
> Tnx in advanced for any helpful comment
> Neda Baheri
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

The CLOCK_DEDICATED_ROUTE constraint will not disable timing analysis.
It is only a routing directive.  If you have timing constraints
that cover the period, clock to output, setup and hold for this
clock, then you should still be able to see if there are timing
issues after static timing analysis.

I generally recommend generating a verbose timing report with
"report unconstrained paths" set to a large number like 100.
This might show areas that need additional constraints.

On the other hand, there is still the possibility that this
design has errors in clock crossing logic or asynchronous
signal synchronization.  That sort of problem very often
comes and goes with a new build due to changes in placement,
and therefore changes in relative routing delays of the
poorly handled signals.

-- 
Gabor

Article: 156767
Subject: Re: PLA? PAL? PLD? GAL?
From: greenaum@gmail.com (greenaum)
Date: Tue, 24 Jun 2014 11:55:23 GMT
Links: << >>  << T >>  << A >>
On Wed, 18 Jun 2014 12:50:07 -0500, Tim Wescott
<tim@seemywebsite.really> sprachen:

>Why are we bothering with a 20 year old revived thread?

Usenet's got really wierd, since we all got massive hard drives, and
the volume plummeted. I've got threads from years ago on this thing,
you don't expect to time-travel just by scrolling a bar.

When I started here was round about 20 years ago. I had to purge
everything over 3 days just to keep the post cache manageable. Below
about 30MB, I think.

-- 

--------------------------------------------------------------------------------
"There's nothing like eating hay when you're faint," the White King remarked to Alice, as he munched away. 
"I should think throwing cold water over you would be better," Alice suggested: "--or some sal-volatile." 
"I didn't say there was nothing better," the King replied. "I said there was nothing like it."
Which Alice did not venture to deny. 

                    

Article: 156768
Subject: Re: PLA? PAL? PLD? GAL?
From: GaborSzakacs <gabor@alacron.com>
Date: Tue, 24 Jun 2014 09:45:16 -0400
Links: << >>  << T >>  << A >>
greenaum wrote:
> On Wed, 18 Jun 2014 12:50:07 -0500, Tim Wescott
> <tim@seemywebsite.really> sprachen:
> 
>> Why are we bothering with a 20 year old revived thread?
> 
> Usenet's got really wierd, since we all got massive hard drives, and
> the volume plummeted. I've got threads from years ago on this thing,
> you don't expect to time-travel just by scrolling a bar.
> 
> When I started here was round about 20 years ago. I had to purge
> everything over 3 days just to keep the post cache manageable. Below
> about 30MB, I think.
> 

Well the first recent post was made from Google Groups where you
don't need any local storage (beyond browser cache) to search
back to the beginning of time...

Sorry, my bad for not noticing that this was a "dug up" thread.

-- 
Gabor

Article: 156769
Subject: A new domain for FPGAs ? Function approximation
From: Thorsten Kiefer <thorstenkfr@googlemail.com>
Date: Tue, 24 Jun 2014 07:24:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I don't know, what is state-of-the-art for function approximation
on FPGAs.

I developed this :
http://toki.burn3r.de/html5-projects/boolean-functions.html

"Paper" (10 minutes hack) for this :
http://toki.burn3r.de/html5-projects/boolean-functions/paper.html

If I tried to implement the constructor for PBFs in VHDL,
like a Float-Core-Generator, would I need to generate
VHDL code, or can VHDL function generate intermediate gates ?

If I tried to implement the solve() procedure, I would need
a random number generator. Is there a Xilinx IP core for this ?

BTW: I am using a Spartan3


I will extend my website and implement the generator in JavaScript.

Best wishes
Thorsten Kiefer

Article: 156770
Subject: Need help for freehdl
From: Thorsten Kiefer <thorstenkfr@googlemail.com>
Date: Tue, 24 Jun 2014 08:20:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
can gvhdl compiled .o files interface with a c-program ?
I would like to implement some mathematical function
in VHDL and call this function with some input and retrieve
the output.
Additionally the function should have some memory variables.

Best Regards
Thorsten Kiefer

Article: 156771
Subject: Re: A new domain for FPGAs ? Function approximation
From: jonesandy@comcast.net
Date: Tue, 24 Jun 2014 08:40:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, June 24, 2014 9:24:23 AM UTC-5, Thorsten Kiefer wrote:
> ...If I tried to implement the constructor for PBFs in VHDL, like a Float-Core-Generator, would I need to generate VHDL code, or can VHDL function generate intermediate gates ? 

Yes, VHDL functions can imply combinatorial logic.

Andy

Article: 156772
Subject: Re: A new domain for FPGAs ? Function approximation
From: Thorsten Kiefer <thorstenkfr@googlemail.com>
Date: Tue, 24 Jun 2014 10:14:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
Am Dienstag, 24. Juni 2014 17:40:28 UTC+2 schrieb jone...@comcast.net:
> On Tuesday, June 24, 2014 9:24:23 AM UTC-5, Thorsten Kiefer wrote:
> 
> > ...If I tried to implement the constructor for PBFs in VHDL, like a Float-Core-Generator, would I need to generate VHDL code, or can VHDL function generate intermediate gates ? 
> 
> 
> 
> Yes, VHDL functions can imply combinatorial logic.
> 
> 
> 
> Andy

But it is not possible to create a whole entity, right ?
For a whole entity I need an intermediate VDHL file, right ?

Article: 156773
Subject: Re: Need help for freehdl
From: Thorsten Kiefer <thorstenkfr@googlemail.com>
Date: Tue, 24 Jun 2014 10:21:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
Am Dienstag, 24. Juni 2014 17:20:32 UTC+2 schrieb Thorsten Kiefer:
> Hi,
> 
> can gvhdl compiled .o files interface with a c-program ?
> 
> I would like to implement some mathematical function
> 
> in VHDL and call this function with some input and retrieve
> 
> the output.
> 
> Additionally the function should have some memory variables.
> 
> 
> 
> Best Regards
> 
> Thorsten Kiefer

I will do a testbench, forget my question

Article: 156774
Subject: Re: PLA? PAL? PLD? GAL?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 24 Jun 2014 20:30:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
GaborSzakacs <gabor@alacron.com> wrote:

(snip)

> Well the first recent post was made from Google Groups where you
> don't need any local storage (beyond browser cache) to search
> back to the beginning of time...
 
> Sorry, my bad for not noticing that this was a "dug up" thread.

I presume it really is old, but there are also posts from hosts with
the clock set to the wrong time. 

Some news servers will reject posts that are not close enough to
the correct time, but others likely let them through.

-- glen



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