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On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote: > On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote: >=20 > > =20 > > Did you assign different instance IDs?=20 >=20 > Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE= =20 > is able to tell the different NIOS.=20 >=20 > > I never tried to use debuggers on two Nios2 processors myself (I hate d= ebuggers in general, so I didn't use debugger on *one* Nios2 processor for = something like 7 years), but Altera documentation claims that it should wor= k.=20 >=20 > If the JTAG UART is used for stdout, the JTAG only routes the debugging= =20 > Nios to console. Any other Nios processors that are not being debugged=20 > will not be able to route their stdout outputs to console. Hence this=20 > question about routing messages via serial port. >=20 You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs"= - multiple. May be, that's where your problem lies? You should use separate JTAG UARTs for separate Nios2 cores. Personally, I prefer not only separate JTAG UARTs, but completely separate = SOPC (now known as QSYS) "systems". That way I better understand interactio= n of resets. >=20 >=20 > > I did try software download (which aso uses debugger interface) to diff= erent Nios2 processors over the same JTAG interface. It certainly works. I = never tested if it works simultaneously, because I never wanted to download= simultaneously. >=20 >=20 >=20 > The JTAG certainly work for multi-Nios system, but it cannot handle >=20 > stdout from multiple Nios. >=20 >=20 >=20 > > But all that is slightly off topic. The topic was "light" debugging wit= h printouts. That's the method that I do like and do do regularly. Printout= s over JTAG UARTs from different processor most definitely work simultaneou= sly, there are no problems at all. Just specify correct instance ID in nios= 2-terminal command line and everything will work for you in the best possib= le manner. >=20 >=20 >=20 > Haha ok let's keep this thread on topic then.Article: 156926
On Tuesday, July 29, 2014 5:20:53 AM UTC+3, mnentwig wrote: > >> the topic was "light" debugging with printouts. > > > > BTW my on-board VGA controller may seem a little over-the-top . The main> > selling point is, it doesn't slow down the code, it's an infinite-baudrate > UART. It's surprisingly compact if I can spare one clock and a block RAM > (on Xilinx Spartan 6, haven't tried this yet on Altera). > Electrically it's uncritical, patch cables to a cheap RGB resistor DAC > breakout board / "wing" work just fine at 640x480 / 25 MHz. > "Infinite-baudrate" is good, but difficulty of logging printouts into file is bad. For me, the later easily outweighs the former.Article: 156927
Yes, thanks. I registered once, maybe I'll have a look through the archives. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156928
On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote: > > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies? I know what a UART is, I know what JTAG means, but what is a JTAG UART? -- RickArticle: 156929
On 7/29/2014 3:37 PM, mnentwig wrote: > Yes, thanks. I registered once, maybe I'll have a look through the > archives. Perhaps you could start a discussion about what you are doing? I think they have some pretty knowledgeable people there... although one fellow tried to tell me that he could add a pipeline register on the negative clock edge and it would work as well as one on the positive edge. I'm not sure what he meant. That reminds me of another way to work around the sync memory problem. The memory can be run on the opposite phase of the clock so that it writes and reads in the middle of the clock cycle. The timing specs have to be set up for this and it may require some optimization to meet timing, but it should work. :) I had forgotten all about this. -- RickArticle: 156930
On Wednesday, July 30, 2014 1:47:16 AM UTC+3, rickman wrote: > On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote: > > > > > > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies? > > I know what a UART is, I know what JTAG means, but what is a JTAG UART? > > > Rick >From Quartus II Handbook: "The JTAG UART is an Avalon-MM slave device that can be used in conjunction with the System Console to send and receive bytestreams." Now, if you are going to ask "What is "an Avalon-MM" and what is "the System Console" ?" then I am not going to answer.Article: 156931
On 7/29/2014 7:05 PM, already5chosen@yahoo.com wrote: > On Wednesday, July 30, 2014 1:47:16 AM UTC+3, rickman wrote: >> On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote: >> >>> >> >>> You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies? >> >> I know what a UART is, I know what JTAG means, but what is a JTAG UART? >> >> >> Rick > > From Quartus II Handbook: "The JTAG UART is an Avalon-MM slave device that can be used in conjunction with the System Console to send and receive bytestreams." > > Now, if you are going to ask "What is "an Avalon-MM" and what is "the System Console" ?" then I am not going to answer. No, lol. So this is an Altera specific term. Got it. -- RickArticle: 156932
rickman <gnuarm@gmail.com> wrote: > On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote: > > > > You constantly use the phrase "JTAG UART" - single, instead of "JTAG > > UARTs" - multiple. May be, that's where your problem lies? > > I know what a UART is, I know what JTAG means, but what is a JTAG UART? It's a terminal-like device that grabs hold of an internal interface to Altera's JTAG controller, with the result that you can attach a NIOS processor (or other endpoint) to it inside the FPGA, and then run a program called nios2-terminal on the host PC which receives the character input/output. In other words it's a character stream multiplexed over the host PC JTAG connection (which itself goes over TCP and then probably USB), instead of plugging in a serial cable to the FPGA. The actual JTAG UART isn't really very UART-like though, it's somewhat lacking in the usual UART features. I don't have anything major to contribute to the OP's question: I've run multiple JTAG UARTs out of one Qsys project, and that works fine. I haven't tried multiple NIOSes that I can recall, but these have multiple masters driving multiple UARTs (we have some hackery to make a JTAG UART accept Avalon streams by simulating writes to its config registers). I've also run 16 JTAG UARTs on the same JTAG chain, where each UART was on a different FPGA. That worked, if slightly flaky due to timing issues on the very long chain. TheoArticle: 156933
rickman <gnuarm@gmail.com> wrote: > On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote: >> You constantly use the phrase "JTAG UART" - single, instead >> of "JTAG UARTs" - multiple. May be, that's where your problem lies? > I know what a UART is, I know what JTAG means, but what > is a JTAG UART? It does seem a strange term for it, but since JTAG is bit serial, and most systems use bytes or some larger word, there has to be a serial/parallel conversion somewhere along the way. However, as I understand it, JTAG is synchronous, so that should be USRT instead of UART. -- glenArticle: 156934
On 29/7/2014 10:34 PM, already5chosen@yahoo.com wrote: > On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote: >> On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote: >> >>> >>> Did you assign different instance IDs? >> >> Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE >> is able to tell the different NIOS. >> >>> I never tried to use debuggers on two Nios2 processors myself (I hate debuggers in general, so I didn't use debugger on *one* Nios2 processor for something like 7 years), but Altera documentation claims that it should work. >> >> If the JTAG UART is used for stdout, the JTAG only routes the debugging >> Nios to console. Any other Nios processors that are not being debugged >> will not be able to route their stdout outputs to console. Hence this >> question about routing messages via serial port. >> > > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies? > You should use separate JTAG UARTs for separate Nios2 cores. > Personally, I prefer not only separate JTAG UARTs, but completely separate SOPC (now known as QSYS) "systems". That way I better understand interaction of resets. Yes we only have a single JTAG port for our embedded target, but multiple serial ports to spare.Article: 156935
On Wednesday, July 30, 2014 3:52:10 AM UTC+3, Ang Zhi Ping wrote: > On 29/7/2014 10:34 PM, already5chosen@yahoo.com wrote: > > > On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote: > > >> On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote: > > >> > > >>> > > >>> Did you assign different instance IDs? > > >> > > >> Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE > > >> is able to tell the different NIOS. > > >> > > >>> I never tried to use debuggers on two Nios2 processors myself (I hate debuggers in general, so I didn't use debugger on *one* Nios2 processor for something like 7 years), but Altera documentation claims that it should work. > > >> > > >> If the JTAG UART is used for stdout, the JTAG only routes the debugging > > >> Nios to console. Any other Nios processors that are not being debugged > > >> will not be able to route their stdout outputs to console. Hence this > > >> question about routing messages via serial port. > > >> > > > > > > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies? > > > You should use separate JTAG UARTs for separate Nios2 cores. > > > Personally, I prefer not only separate JTAG UARTs, but completely separate SOPC (now known as QSYS) "systems". That way I better understand interaction of resets. > > Yes we only have a single JTAG port for our embedded target, Of course, one Altera FPGA would at most have one JTAG port. That's not what I am talking about. I am talking about multiple instances of "jtag uart" component. > but multiple serial ports to spare.Article: 156936
>> sync memory problem. True... Spartan 6 BRAM manual states >> The read and write operations are synchronous and require a clock edge Anyway, I would stay away from anything that's non-standard (at least I _think_ this is unusual, with the exception of off-chip DDR). >Perhaps you could start a discussion about what you are doing? There isn't really a lot to discuss on the processor side: A plain ol' CPU, where FPGA RTL stuff is controlled via registers. It's some MIDI synthesizer thing, I'm coding up my own '69 Vox Continental replica, an open-ended holiday/self-study project. The only performance bottleneck is on key events, when the CPU suddenly needs to update many virtual key contacts. Ideally I'd like to model switch bounce in software, but probably I'll do it in RTL and then everything else can be really slow, thanks to the low MIDI baudrate, --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156937
W dniu 2014-07-28 14:10, Ang Zhi Ping pisze: > On 28/7/2014 6:22 PM, already5chosen@yahoo.com wrote: >> Multiple Nios2 cores, each with its own JTAG UART, co-exist just fine on= the same JTAG interface. The same applies to multiple JTAG debug modules. >> The only thing that you, as designer of the module, should care about is= avoiding the conflict of Nios2 CPU instance IDs. Ideally, allocation of in= stance IDs should be governed by person, that is responsible for top-level = integration. > > I can't seem to debug two Nios processors simultaneously. > Few years ago I had system with 8 Cyclon chips and each with nios II. All chips in single jtag chain. I was able to debug 2 or 3 of them at same time without any problem. There sould be not a problem to debug all 8 at once. Adam --- Ta wiadomo=C5=9B=C4=87 e-mail jest wolna od wirus=C3=B3w i z=C5=82o=C5=9Bli= wego oprogramowania, poniewa=C5=BC ochrona avast! Antivirus jest aktywna. http://www.avast.comArticle: 156938
Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Verilog, I feel as though my VHDL designs are just not = as tight as they should be. In pursuit of self-improvement, I am trying to= find "real world" examples of professional VHDL designs that I can glean f= or hints on how to make my designs better. I have read many, many books and= analyzed some projects on opencores, but everything that I have seen seems= a bit lacking. I am hoping that the comp.arch.fpga community might share = a few examples of solid VHDL designs that I can review. Incomplete designs = are fine, as long as I can get a feel for how you are accomplishing things.= Bear in mind that I will not critique your design, and am not interested i= n participating in The Great HDL Debate MMXIV: Part XXIII. I need to contin= ue to use both VHDL and Verilog.Article: 156939
Are you familiar with Open Cores? www.opencores.org. They have a large co= llection of really some really well designed and some really not-so-well de= signed cores in both VHDL and Verilog. =20 Here's a link to a few VHDL modules that are pretty decent. I'm not sure h= ow complicated of a design you're looking for, but these are supported by t= estbenches so you can get a feel for how to write a testbench in VHDL. http://www.nandland.com/vhdl/modules/index.html On Thursday, July 31, 2014 12:34:52 PM UTC-4, wab...@gmail.com wrote: > Over the years I have taught myself Verilog and VHDL, and although I am q= uite comfortable with Verilog, I feel as though my VHDL designs are just no= t as tight as they should be. In pursuit of self-improvement, I am trying = to find "real world" examples of professional VHDL designs that I can glean= for hints on how to make my designs better. I have read many, many books a= nd analyzed some projects on opencores, but everything that I have seen see= ms a bit lacking. I am hoping that the comp.arch.fpga community might shar= e a few examples of solid VHDL designs that I can review. Incomplete design= s are fine, as long as I can get a feel for how you are accomplishing thing= s. Bear in mind that I will not critique your design, and am not interested= in participating in The Great HDL Debate MMXIV: Part XXIII. I need to cont= inue to use both VHDL and Verilog.Article: 156940
On Wednesday, 23 July 2014 00:49:52 UTC+8, chaitanya163 wrote:
> Hello Everyone
>
>
>
> I am new to VHDL programming and FPGA.
>
> I have a Virtex - 4 FPGA and I wish to generate a binary pulse train of 16
>
> pulses from FPGA using VHDL programming. My desired pulse train will be
>
> like "1011100111101110". (min pulse width should be 30ns).
>
> I have a clock of 100 MHz and I am able to divide the clock frequency to
>
> get the clock of 10MHz (clock frequency required for my application). Also
>
> I am aware of the fact that "Wait for" statement can not be used for
>
> synthesizing as it can only be used for test bench and simulation purposes.
>
>
>
>
>
> So I am struggling with this problem. I am wondering if I can use "after
>
> Xns" command in my VHDL code or if there is any other way to do it.
>
>
>
> I will be very thankful if any feedback or advice is provided. Your
>
> response will truly be appreciated. Kindly provide your valuable
>
> suggestions.
>
>
>
> Thanking you
>
> Regards
>
> Chaitanya Mauskar
>
>
>
>
>
>
>
> ---------------------------------------
>
> Posted through http://www.FPGARelated.com
I'd write the shift register similar to the following, assuming you have your frequency divider working correctly. Some tools implement this with a 16:1 mux, which is fine.
entity shifter is port(clk,en,reset:in std_ulogic; q:out std_ulogic);
end entity shifter;
architecture rtl of shifter is
constant s:std_ulogic_vector:=x"1011100111101110";
signal i:unsigned(3 downto 0);
begin
q<=s(to_integer(i));
process(reset,clk) is begin
if reset then i<=(others=>'0');
elsif rising_edge(clk) then
if en then i<=i+1; end if;
end if;
end process;
end architecture rtl;
-dan
Article: 156941On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: > Over the years I have taught myself Verilog and VHDL, and although I am > quite comfortable with Verilog, I feel as though my VHDL designs are > just not as tight as they should be. In pursuit of self-improvement, I > am trying to find "real world" examples of professional VHDL designs > that I can glean for hints on how to make my designs better. I have read > many, many books and analyzed some projects on opencores, but everything > that I have seen seems a bit lacking. I am hoping that the > comp.arch.fpga community might share a few examples of solid VHDL > designs that I can review. Incomplete designs are fine, as long as I can > get a feel for how you are accomplishing things. Bear in mind that I > will not critique your design, and am not interested in participating in > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use both > VHDL and Verilog. "Professional" as in "took money for it" or as in "a good example for us all"? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 156942
On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: > Over the years I have taught myself Verilog and VHDL, and although I am > quite comfortable with Verilog, I feel as though my VHDL designs are > just not as tight as they should be. In pursuit of self-improvement, I > am trying to find "real world" examples of professional VHDL designs > that I can glean for hints on how to make my designs better. I have read > many, many books and analyzed some projects on opencores, but everything > that I have seen seems a bit lacking. I am hoping that the > comp.arch.fpga community might share a few examples of solid VHDL > designs that I can review. Incomplete designs are fine, as long as I can > get a feel for how you are accomplishing things. Bear in mind that I > will not critique your design, and am not interested in participating in > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use both > VHDL and Verilog. Here's an example of mine from 2002 or so. http://fractional-divider.tripod.com/fracn20.zip It shows how to use VHDL in a way that would be difficult to mimic in Verilog, and may seem strange to Verilog coders. As such, it may be useful as a learning exercise. I have a Verilog version on that same web page, but it uses a Perl script to write the Verilog, customised by some command line parameters. The VHDL version customises itself from its generics at elaboration time. Most of the code consists of functions that in many cases use floating point numbers to produce a bunch of constants that control the (relatively small) chunk of RTL at the bottom of the file. BTW, it isn't representative of code I write now, but it is still useful as a tool torture test. Regards, AllanArticle: 156943
On 7/31/2014 7:24 PM, Tim Wescott wrote: > On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: > >> Over the years I have taught myself Verilog and VHDL, and although I am >> quite comfortable with Verilog, I feel as though my VHDL designs are >> just not as tight as they should be. In pursuit of self-improvement, I >> am trying to find "real world" examples of professional VHDL designs <snip> > "Professional" as in "took money for it" or as in "a good example for us > all"? > Good point - although slightly snarky :)Article: 156944
Russell <russellmerrick@gmail.com> writes: > Are you familiar with Open Cores? www.opencores.org. They have a large collection of really some really well designed and some > really not-so-well designed cores in both VHDL and Verilog. > > Here's a link to a few VHDL modules that are pretty decent. I'm not sure how complicated of a design you're looking for, but these > are supported by testbenches so you can get a feel for how to write a testbench in VHDL. > > http://www.nandland.com/vhdl/modules/index.html In the spirit of Tim's comment, http://www.nandland.com/vhdl/modules/module-fifo-regs-with-flags.html I'm not sure that a testbench that consists of multiple pasted "wait until r_clock = '1'" statements and no code to actually check the operation of the module under test would count as "a good example for us all"... Unfortunately, I'm not aware of much else I can point you at that's very complete. Most pro-grade code will be proprietary, there's isn't anywhere near as much open-source VHDL code, and most (IMHO) majors on functionality rather than development style. I have a( sadly incomplete - it's a spare time activity, and that's in short supply!) VHDL-based image processing tutorial. The VHDL part has only reached the stage of reading a PGM file into a testbench, but it may be of interest: http://parallelpoints.com/reading-image-files-with-vhdl-part-1-again/ Code can be found here: https://github.com/martinjthompson/image_processing_examples/tree/master/hdl (I should point out that this code has nothing to do with my employer, it's all my own work.) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 156945
Hi
I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE Webpack toolkit. After foolishly trying to synthesize the "real" type and then researching various options I came across the following links:
http://www.eda-stds.org/fphdl/
http://www.vhdl.org/fphdl/vhdl.html
Now, I am a little confused as to how to go about using these sources. They mention using the IEEE_proposed library.
Q. Does that mean that Xilinx ISE will provide the IEEE_proposed library ?
Q. If not, do I have to compile this library myself using the provided source code for fixed and floating point math ?
Q. Has anyone successfully used this code and/or synthesized floating point on a Xilinx FPGA using ISE Webpack ?
Any help will be appreciated.
Thanks
vicash
Article: 156946Have you looked at the sources for Leon 3 and the rest of the GR Lib components? They seemed like good examples to me. http://www.gaisler.com/index.php/downloads/leongrlib --JecelArticle: 156947
Hi, you mentioned "floating point or fixed point". Don't know if this is of any use, but if you can reasonably write the algorithm in fixed point, it may be the better choice. It's' easier for some problems than for others. And, it takes some time to get used to it. Up to 18x18 bit (typically), you get one multiplication per hardware multiplier per clock cycle. If possible, formulate your algorithm as a pipelined data path in 18 bits and even a relatively small FPGA can do a serious amount of work. Typical fixed point code could look like this acc <= ((acc * xLSB + $signed(1 << 12)) >>> 13) + c2; where "xLSB" has 12 fractional bits (right side of the decimal point). Adding "1 << 12" and arithmetic (signed) right shift by 13 rounds at 0.5 and restores the decimal point. For high clock speed (~50+ MHz), it may need pipelining. Also, saturation should be placed strategically throughout the code to prevent that overflow wraps. I've got a complete example for (simple) fixed point DSP RTL here: http://www.dsprelated.com/showarticle/594.php --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156948
vicash <walburn@gmail.com> wrote: > I have been researching floating and/or fixed point support > for Xilinx FPGAs that can be synthesized using the ISE Webpack > toolkit. After foolishly trying to synthesize the "real" type > and then researching various options I came across the > following links: > http://www.eda-stds.org/fphdl/ > http://www.vhdl.org/fphdl/vhdl.html > Now, I am a little confused as to how to go about using > these sources. They mention using the IEEE_proposed library. What are you actually trying to build? That makes a big difference in how you do it. In the usual case, one wants to accelerate some algorithm, which usually means a pipeline that can process some data with very high throughput. That pretty much means pipelining the floating point operation if you want floating point. Floating point takes a lot more CLBs than fixed point, especially the floating point adder/subtracter. -- glenArticle: 156949
Hi, I read a paper on FPGA design. It has the following statements: "Successfully simulated programs might not work on device because synthesizer tries to optimize design and it can delete some connections which affect result. Hence a good knowledge of synthesizer is of importance in FPGA program development." I have done some small and medium FPGA projects, but never experience surprising synthesis result as the above statement. Could you give me an example to show the XST synthesis control to turn a failure to success? Thanks,
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