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Messages from 157675

Article: 157675
Subject: Re: Send a pulse across clocks
From: Leo <capossio.leonardo@gmail.com>
Date: Thu, 22 Jan 2015 19:39:55 -0800 (PST)
Links: << >>  << T >>  << A >>
El jueves, 22 de enero de 2015, 11:05:25 (UTC-3), Leo escribi=F3:
> Hello, I want to send a pulse from one clock domain to another, knowing t=
hat from the time event that this pulse is generated in the source clock do=
main it arrives in the first rising edge of the destination clock domain an=
d lasts exactly one clock period of the destination clock domain. Now, I kn=
ow this problem is not generic and is subject to timing constraints and clo=
ck frequency/phase relationship. So the question would be, how to implement=
 it best in RTL with Xilinx technology and what time constraints to apply f=
rom source to destination FF. In particular the destination clock is a litt=
le over half of the source clock frequency, the phase between them is unkno=
wn and may change over time.
>=20
> Currently my idea is to use the asynchronous preset/clear of the destinat=
ion FF, which would mean that on an specific part (Xilinx Spartan 6 or 7-se=
ries FPGAs) there must be some relation between the clocks that allows the =
minimum pulse width and propagation of the asynchronous signal.
>=20
> Any help is appreaciated.

Thanks to all. "Pulse-toggle-pulse synchronizer" proposed by Rob Gaddi is w=
hat I need. The current architecture allows me to "aim" to a flank of the r=
eceiver clock (within certain limits) so that no undefined latency issues a=
rise (due to setup/hold violations or metastability).

Article: 157676
Subject: Where in ISE/Vivado are the chip specific resources listed?
From: Svenn <svenn.bjerkem@gmail.com>
Date: Tue, 27 Jan 2015 15:48:30 +0100
Links: << >>  << T >>  << A >>
Hi,
I am trying to create a comparison list between various FPGAs in the 
Xilinx universe. The unisim library lists all primitives, but not all of 
the primitives listed in unisim are available in all architectures. I 
have been poking around in ISE to try to find which file describes what 
primitives are available in, say zynq 7c010. Spartan-6 would have the 
primitive ISERDES2 while zynq would have ISERDESE2.

Anybody know where the per chip available primitives are stored?

-- 
Svenn

Article: 157677
Subject: Artix-7 tools, ISE vs Vivado
From: Vladimir Ivanov <vladitx@nucleusys.com>
Date: Tue, 27 Jan 2015 21:23:10 +0200
Links: << >>  << T >>  << A >>

Hello,

What are the practical pros and cons of using each of ISE or Vivado for 
the Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside from 
possible speed increase in Vivado, do the synthesis/map/route perform 
better by generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning Vivado in 
the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx 
families, so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

Thanks,
   -- Vlad

Article: 157678
Subject: Re: Artix-7 tools, ISE vs Vivado
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Tue, 27 Jan 2015 19:46:48 +0000
Links: << >>  << T >>  << A >>
On 27/01/15 19:23, Vladimir Ivanov wrote:
>
> Hello,
>
> What are the practical pros and cons of using each of ISE or Vivado for the
> Artix-7 family?
>
> I am interested in the basic synthesis/map/routing/STA steps. Aside from
> possible speed increase in Vivado, do the synthesis/map/route perform better by
> generating smaller and/or faster logic?
>
> In general, my question is whether it's really worth it learning Vivado in the
> context of Artix-7 only. No Zynq plans so far. I also use older Xilinx families,
> so sticking to ISE is justified.
>
> Any personal comparison between the two tools is also very welcome.

My impression, and that is all it is, is that ISE has reached the
end of the road and Vivado is the future. That seems reasonable
for tomorrows even larger devices, Zynq or otherwise.

Hence staying using ISE is likely to be limiting in the long run.


Article: 157679
Subject: Vivado is intensely frustrating
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Tue, 27 Jan 2015 11:46:56 -0800
Links: << >>  << T >>  << A >>
So, the following ROM initialization code should be entirely
synthesizable.  Not so, according to the latest version of Vivado,
which proudly declares "ignoring unsynthesizable construct:
non-synthesizable procedure call", zeros out my ROM, and then optimizes
it away.

And yes, I have ways to work around this (though they force me to carry
far too much of the policy from my VHDL back into my coefficient
generating code).  I just wanted to call out, in a public forum, that
the inability to handle something as trivial as this points out how
fundamentally brain-damaged this software is.  I'd submit a WebCase,
but the bean-counters at Xilinx have decided to no longer accept those
for fear that customers may want support, or worse yet report bugs.

----

function create_index(
    filter  : integer range 0 to 1;
    phase   : integer range 0 to 63;
    tap     : integer range 0 to 14
    ) return natural is
begin
    return (filter * 1024) + (tap * 64) + phase;
end function create_index;

constant LONGFILTER : integer := 0;
constant SHORTFILTER : integer := 1;

type t_coef is record
    c       : signed(17 downto 0);  --  S1.17
    dc      : signed(17 downto 0);  --  S1.17
end record;
type t_coef_rom is array(0 to 2047) of t_coef;

impure function GetCoefROM return t_coef_rom is
    -- Load up our filter coefficients from a file.  The file format is
    -- 960 lines of (c dc) pairs, all as real numbers.
    --
    variable rv : t_coef_rom;

    procedure GetFilterData (
        filename : string;
        filter : integer
    ) is
        file src : text open READ_MODE is filename;
        variable ln : line;
        variable c  : integer range -(2**17) to (2**17)-1;
        variable dc : integer range -(2**17) to (2**17)-1;
        variable r  : real;
        
        variable phase : integer range 0 to 63 := 0;
        variable tap : integer := 0;
        variable idx : integer range rv'range;
        variable lines : natural := 0;
        
    begin
        while not endfile(src) loop
            readline(src, ln);
            read(ln, r);
            c := INTEGER(round(r * 2.0**17));
            read(ln, r);
            dc := INTEGER(round(r * 2.0**17));
            
            idx := create_index(filter, phase, tap);
            rv(idx).c   := TO_SIGNED(c, 18);
            rv(idx).dc  := TO_SIGNED(dc, 18);
            
            if phase = 63 then
                phase := 0;
                tap := tap + 1;
            else
                phase := phase + 1;
            end if;
            lines := lines + 1;
        end loop;
        
        deallocate(ln);
        write(ln, string'("Read "));
        write(ln, lines);
        write(ln, string'(" lines from "));
        write(ln, filename);
        writeline(OUTPUT, ln);
        
    end procedure GetFilterData;
    
begin
    for i in rv'range loop
        rv(i) := (others => (others => '0'));
    end loop;
    
    GetFilterData("longfilter.txt", LONGFILTER);
    GetFilterData("shortfilter.txt", SHORTFILTER);
    return rv;
end function GetCoefROM;

-- Giant table of FIR coefficients.
signal coef_rom : t_coef_rom := GetCoefROM;

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 157680
Subject: Why two hold checks done byTimeQuest
From: "kaz" <37480@embeddedrelated>
Date: Tue, 27 Jan 2015 13:48:43 -0600
Links: << >>  << T >>  << A >>
Hi,

TimeQuest says it uses two hold checks per each setup check. The first hold
check for 
previous latch edge with current launch edge and second check for current
latch edge 
with next launch edge. It then gives a diagram which makes sense as one
hold check 
could miss the most restrictive case.
The diagram is based on different clocks (possibly latch is at half speed).
My question is:
who will use such clocking and what about other cases of clock frequency
mismatch?

Regards

Kaz	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157681
Subject: Re: Artix-7 tools, ISE vs Vivado
From: Vladimir Ivanov <vladitx@nucleusys.com>
Date: Tue, 27 Jan 2015 22:01:28 +0200
Links: << >>  << T >>  << A >>

On Tue, 27 Jan 2015, Tom Gardner wrote:

> On 27/01/15 19:23, Vladimir Ivanov wrote:
>> 
>> Hello,
>> 
>> What are the practical pros and cons of using each of ISE or Vivado 
>> for the
>> Artix-7 family?
>> 
>> I am interested in the basic synthesis/map/routing/STA steps. Aside 
>> from
>> possible speed increase in Vivado, do the synthesis/map/route perform 
>> better by
>> generating smaller and/or faster logic?
>> 
>> In general, my question is whether it's really worth it learning 
>> Vivado in the
>> context of Artix-7 only. No Zynq plans so far. I also use older Xilinx 
>> families,
>> so sticking to ISE is justified.
>> 
>> Any personal comparison between the two tools is also very welcome.
>
> My impression, and that is all it is, is that ISE has reached the
> end of the road and Vivado is the future. That seems reasonable
> for tomorrows even larger devices, Zynq or otherwise.
>
> Hence staying using ISE is likely to be limiting in the long run.

True, but for anything older than the 7 series (Spartan and CPLDs) ISE is 
the only choice, so it will be around for a long time, too. Except if a 
miracle happens.

Article: 157682
Subject: Instantiating Components or Using Generate statements
From: "Abdulla873" <103058@embeddedrelated>
Date: Tue, 27 Jan 2015 15:08:01 -0600
Links: << >>  << T >>  << A >>
Hi Guys,

Are there any differences between instantiating components and using
generate statement in hierarchical structure design??

Thanks,

Abdullah

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157683
Subject: Re: Send a pulse across clocks
From: "Abdulla873" <103058@embeddedrelated>
Date: Tue, 27 Jan 2015 15:08:15 -0600
Links: << >>  << T >>  << A >>
Since the destination is running at lower speed than your source, all what
you need is a level-alternative scheme at the source to stretch out your
pulse width and at the destination side you will need a synchronizer along
with a dual edge detector. BTW, in this case, you do not have to be worried
about the timing constraint violations. 

Abdullah

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157684
Subject: Re: Artix-7 tools, ISE vs Vivado
From: gtwrek@sonic.net (Mark Curry)
Date: Tue, 27 Jan 2015 21:24:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <alpine.DEB.2.02.1501272109300.5159@zztop.nucleusys.com>,
Vladimir Ivanov  <vladitx@nucleusys.com> wrote:
>
>Hello,
>
>What are the practical pros and cons of using each of ISE or Vivado for 
>the Artix-7 family?
>
>I am interested in the basic synthesis/map/routing/STA steps. Aside from 
>possible speed increase in Vivado, do the synthesis/map/route perform 
>better by generating smaller and/or faster logic?
>
>In general, my question is whether it's really worth it learning Vivado in 
>the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx 
>families, so sticking to ISE is justified.
>
>Any personal comparison between the two tools is also very welcome.

Vladimir, 

I'm in the same boat as you - supporting both "7 series" and above
devices, and older Xilinx technologies.  Only certain 7-series devices
allow you the option of ISE or vivado, so a lot of the time the 
decision is made for you.

I did use one of the devices where we had a choice - migrating a Virtex
6, to a Kintex 7.  At first, to maintain our flows we went with ISE.  
After getting our Vivado flows clean (which took WAY more time than it 
should have, but that's another story..), We're now using Vivado.  The
QOR is MUCH better - both better run times, and better timing results.
Many of our designs which had great difficulty meeting timing with ISE,
went through first time in Vivado and worked.

The TCL flows are more powerful.  The constraint format - XDC files - 
is leaps and bounds better than UCF (ugh.), but not without warts.

Once you get used to it, and setup your flows, you won't look back.

For the most part, we don't have to kludge up many of our source RTL
files to work with either ISE or Vivado.  There's a few exceptions, 
but nothing big.

Regards,

Mark 


Article: 157685
Subject: Re: Xilinx XST and initializing block RAMs
From: lovelyece@gmail.com
Date: Tue, 27 Jan 2015 21:49:46 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, March 4, 2013 at 3:33:34 PM UTC+5:30, Jon wrote:
> You can put a $readmemh to initialise the memory.
> 
> reg [data_width-1:0] memory[0:depth-1];    
> 
> initial
> begin
>     $readmemh("filename.hex", memory);
> end
> 
> Should work with both XST & Synplify.

Hi Jon,

I am trying to initialize BRAM witj readmemh function as you have written , however in simulation all locations are filled up with XXXXX.. ()don't care) values.
I am using the code at :- 
http://www.testbench.in/TB_03_FILE_IO_TB.html


Article: 157686
Subject: Re: Artix-7 tools, ISE vs Vivado
From: Vladimir Ivanov <vladitx@nucleusys.com>
Date: Wed, 28 Jan 2015 10:19:52 +0200
Links: << >>  << T >>  << A >>

On Tue, 27 Jan 2015, Mark Curry wrote:

> In article <alpine.DEB.2.02.1501272109300.5159@zztop.nucleusys.com>,
> Vladimir Ivanov  <vladitx@nucleusys.com> wrote:
>>
>> Hello,
>>
>> What are the practical pros and cons of using each of ISE or Vivado for
>> the Artix-7 family?
>>
>> I am interested in the basic synthesis/map/routing/STA steps. Aside from
>> possible speed increase in Vivado, do the synthesis/map/route perform
>> better by generating smaller and/or faster logic?
>>
>> In general, my question is whether it's really worth it learning Vivado in
>> the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx
>> families, so sticking to ISE is justified.
>>
>> Any personal comparison between the two tools is also very welcome.
>
> Vladimir,
>
> I'm in the same boat as you - supporting both "7 series" and above
> devices, and older Xilinx technologies.  Only certain 7-series devices
> allow you the option of ISE or vivado, so a lot of the time the
> decision is made for you.
>
> I did use one of the devices where we had a choice - migrating a Virtex
> 6, to a Kintex 7.  At first, to maintain our flows we went with ISE.
> After getting our Vivado flows clean (which took WAY more time than it
> should have, but that's another story..), We're now using Vivado.  The
> QOR is MUCH better - both better run times, and better timing results.
> Many of our designs which had great difficulty meeting timing with ISE,
> went through first time in Vivado and worked.
>
> The TCL flows are more powerful.  The constraint format - XDC files -
> is leaps and bounds better than UCF (ugh.), but not without warts.
>
> Once you get used to it, and setup your flows, you won't look back.
>
> For the most part, we don't have to kludge up many of our source RTL
> files to work with either ISE or Vivado.  There's a few exceptions,
> but nothing big.

Hello Mark,

And thanks for the summary. It covers my expectations that switching to 
Vivado will require extra time for getting used to, and then some for the 
not so negligible unpolished pieces. The latter, being unpredictable, was 
holding me mostly. With the heads up, I might as well give it a shot.

   -- Vlad

Article: 157687
Subject: Re: Vivado is intensely frustrating
From: Leo <capossio.leonardo@gmail.com>
Date: Wed, 28 Jan 2015 07:30:06 -0800 (PST)
Links: << >>  << T >>  << A >>
El martes, 27 de enero de 2015, 16:46:58 (UTC-3), Rob Gaddi escribi=F3:
> So, the following ROM initialization code should be entirely
> synthesizable.  Not so, according to the latest version of Vivado,
> which proudly declares "ignoring unsynthesizable construct:
> non-synthesizable procedure call", zeros out my ROM, and then optimizes
> it away.
>=20
> And yes, I have ways to work around this (though they force me to carry
> far too much of the policy from my VHDL back into my coefficient
> generating code).  I just wanted to call out, in a public forum, that
> the inability to handle something as trivial as this points out how
> fundamentally brain-damaged this software is.  I'd submit a WebCase,
> but the bean-counters at Xilinx have decided to no longer accept those
> for fear that customers may want support, or worse yet report bugs.
>=20
> ----
>=20
> function create_index(
>     filter  : integer range 0 to 1;
>     phase   : integer range 0 to 63;
>     tap     : integer range 0 to 14
>     ) return natural is
> begin
>     return (filter * 1024) + (tap * 64) + phase;
> end function create_index;
>=20
> constant LONGFILTER : integer :=3D 0;
> constant SHORTFILTER : integer :=3D 1;
>=20
> type t_coef is record
>     c       : signed(17 downto 0);  --  S1.17
>     dc      : signed(17 downto 0);  --  S1.17
> end record;
> type t_coef_rom is array(0 to 2047) of t_coef;
>=20
> impure function GetCoefROM return t_coef_rom is
>     -- Load up our filter coefficients from a file.  The file format is
>     -- 960 lines of (c dc) pairs, all as real numbers.
>     --
>     variable rv : t_coef_rom;
>=20
>     procedure GetFilterData (
>         filename : string;
>         filter : integer
>     ) is
>         file src : text open READ_MODE is filename;
>         variable ln : line;
>         variable c  : integer range -(2**17) to (2**17)-1;
>         variable dc : integer range -(2**17) to (2**17)-1;
>         variable r  : real;
>        =20
>         variable phase : integer range 0 to 63 :=3D 0;
>         variable tap : integer :=3D 0;
>         variable idx : integer range rv'range;
>         variable lines : natural :=3D 0;
>        =20
>     begin
>         while not endfile(src) loop
>             readline(src, ln);
>             read(ln, r);
>             c :=3D INTEGER(round(r * 2.0**17));
>             read(ln, r);
>             dc :=3D INTEGER(round(r * 2.0**17));
>            =20
>             idx :=3D create_index(filter, phase, tap);
>             rv(idx).c   :=3D TO_SIGNED(c, 18);
>             rv(idx).dc  :=3D TO_SIGNED(dc, 18);
>            =20
>             if phase =3D 63 then
>                 phase :=3D 0;
>                 tap :=3D tap + 1;
>             else
>                 phase :=3D phase + 1;
>             end if;
>             lines :=3D lines + 1;
>         end loop;
>        =20
>         deallocate(ln);
>         write(ln, string'("Read "));
>         write(ln, lines);
>         write(ln, string'(" lines from "));
>         write(ln, filename);
>         writeline(OUTPUT, ln);
>        =20
>     end procedure GetFilterData;
>    =20
> begin
>     for i in rv'range loop
>         rv(i) :=3D (others =3D> (others =3D> '0'));
>     end loop;
>    =20
>     GetFilterData("longfilter.txt", LONGFILTER);
>     GetFilterData("shortfilter.txt", SHORTFILTER);
>     return rv;
> end function GetCoefROM;
>=20
> -- Giant table of FIR coefficients.
> signal coef_rom : t_coef_rom :=3D GetCoefROM;
>=20
> --=20
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> Email address domain is currently out of order.  See above to fix.

Feel your frustation. I had a code that inferred blockRAMs perfectly accord=
ing to XST guidelines. Run it on Vivado, and then suddenly my design took t=
he 400% of the FFs in the FPGA.

Also Vivado synthesis does not support dynamic loops, something like this i=
s not allowed:

--a is a variable
for i in 0 to a-1 loop
...
end loop;

but this is allowed:

--i, a are variables, MAX should be a constant, for example the max binary =
----value of an SLV

i:=3D0;
while i < MAX loop
...do something here
i:=3Di+1;
if i =3D a then exit; end if;
end loop;


Also...signals marked for debug do not have their name preserved at all tim=
es, gets very frustrating going into the post-synthesis debug mode to add/r=
emove them...

I guess since it is very it is expected, but I wonder why they felt they sh=
ould re-write XST from the beginning, and WHY, oh, WHY, leave Spartan6 out,=
 there is a still a market for Spartan 6.

Article: 157688
Subject: Re: Vivado is intensely frustrating
From: Leo <capossio.leonardo@gmail.com>
Date: Wed, 28 Jan 2015 07:33:16 -0800 (PST)
Links: << >>  << T >>  << A >>
El martes, 27 de enero de 2015, 16:46:58 (UTC-3), Rob Gaddi escribi=F3:
> So, the following ROM initialization code should be entirely
> synthesizable.  Not so, according to the latest version of Vivado,
> which proudly declares "ignoring unsynthesizable construct:
> non-synthesizable procedure call", zeros out my ROM, and then optimizes
> it away.
>=20
> And yes, I have ways to work around this (though they force me to carry
> far too much of the policy from my VHDL back into my coefficient
> generating code).  I just wanted to call out, in a public forum, that
> the inability to handle something as trivial as this points out how
> fundamentally brain-damaged this software is.  I'd submit a WebCase,
> but the bean-counters at Xilinx have decided to no longer accept those
> for fear that customers may want support, or worse yet report bugs.
>=20
> ----
>=20
> function create_index(
>     filter  : integer range 0 to 1;
>     phase   : integer range 0 to 63;
>     tap     : integer range 0 to 14
>     ) return natural is
> begin
>     return (filter * 1024) + (tap * 64) + phase;
> end function create_index;
>=20
> constant LONGFILTER : integer :=3D 0;
> constant SHORTFILTER : integer :=3D 1;
>=20
> type t_coef is record
>     c       : signed(17 downto 0);  --  S1.17
>     dc      : signed(17 downto 0);  --  S1.17
> end record;
> type t_coef_rom is array(0 to 2047) of t_coef;
>=20
> impure function GetCoefROM return t_coef_rom is
>     -- Load up our filter coefficients from a file.  The file format is
>     -- 960 lines of (c dc) pairs, all as real numbers.
>     --
>     variable rv : t_coef_rom;
>=20
>     procedure GetFilterData (
>         filename : string;
>         filter : integer
>     ) is
>         file src : text open READ_MODE is filename;
>         variable ln : line;
>         variable c  : integer range -(2**17) to (2**17)-1;
>         variable dc : integer range -(2**17) to (2**17)-1;
>         variable r  : real;
>        =20
>         variable phase : integer range 0 to 63 :=3D 0;
>         variable tap : integer :=3D 0;
>         variable idx : integer range rv'range;
>         variable lines : natural :=3D 0;
>        =20
>     begin
>         while not endfile(src) loop
>             readline(src, ln);
>             read(ln, r);
>             c :=3D INTEGER(round(r * 2.0**17));
>             read(ln, r);
>             dc :=3D INTEGER(round(r * 2.0**17));
>            =20
>             idx :=3D create_index(filter, phase, tap);
>             rv(idx).c   :=3D TO_SIGNED(c, 18);
>             rv(idx).dc  :=3D TO_SIGNED(dc, 18);
>            =20
>             if phase =3D 63 then
>                 phase :=3D 0;
>                 tap :=3D tap + 1;
>             else
>                 phase :=3D phase + 1;
>             end if;
>             lines :=3D lines + 1;
>         end loop;
>        =20
>         deallocate(ln);
>         write(ln, string'("Read "));
>         write(ln, lines);
>         write(ln, string'(" lines from "));
>         write(ln, filename);
>         writeline(OUTPUT, ln);
>        =20
>     end procedure GetFilterData;
>    =20
> begin
>     for i in rv'range loop
>         rv(i) :=3D (others =3D> (others =3D> '0'));
>     end loop;
>    =20
>     GetFilterData("longfilter.txt", LONGFILTER);
>     GetFilterData("shortfilter.txt", SHORTFILTER);
>     return rv;
> end function GetCoefROM;
>=20
> -- Giant table of FIR coefficients.
> signal coef_rom : t_coef_rom :=3D GetCoefROM;
>=20
> --=20
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> Email address domain is currently out of order.  See above to fix.

Also, maybe someone could shed some light on this post: http://forums.xilin=
x.com/t5/Synthesis/Different-Synthesis-Results/td-p/558576

Article: 157689
Subject: Transfering image file to DDR RAM using EDK
From: rashmic <rashmicbe@gmail.com>
Date: Wed, 28 Jan 2015 11:00:06 -0600
Links: << >>  << T >>  << A >>
Hi,

I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further manipulation using EDK.Please provide different techniques to transfer files in ddr using EDK.
--
rashmic
http://compgroups.net/comp.arch.fpga/



Article: 157690
Subject: Re: Vivado is intensely frustrating
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Wed, 28 Jan 2015 11:45:42 -0800
Links: << >>  << T >>  << A >>
On Tue, 27 Jan 2015 11:46:56 -0800
Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:

> So, the following ROM initialization code should be entirely
> synthesizable.  Not so, according to the latest version of Vivado,
> which proudly declares "ignoring unsynthesizable construct:
> non-synthesizable procedure call", zeros out my ROM, and then optimizes
> it away.
> 
> And yes, I have ways to work around this (though they force me to carry
> far too much of the policy from my VHDL back into my coefficient
> generating code).  I just wanted to call out, in a public forum, that
> the inability to handle something as trivial as this points out how
> fundamentally brain-damaged this software is.  I'd submit a WebCase,
> but the bean-counters at Xilinx have decided to no longer accept those
> for fear that customers may want support, or worse yet report bugs.
> 
> [snip]

Follow up for using textio under Vivado.  Not only can't it read reals
from a file, but it can't read integers either.  Not only that, but if
you actually bother to use the 3 argument form with the GOOD output, it
will always set GOOD to true even when it can't read anything.

Just sloppy.  A working textio for all the types defined in std has
been a part of the spec for a LONG time.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 157691
Subject: Re: Where in ISE/Vivado are the chip specific resources listed?
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 29 Jan 2015 12:22:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 27, 2015 at 6:48:34 AM UTC-8, Svenn Are Bjerkem wrote:
> Hi,
> I am trying to create a comparison list between various FPGAs in the 
> Xilinx universe. The unisim library lists all primitives, but not all of 
> the primitives listed in unisim are available in all architectures. I 
> have been poking around in ISE to try to find which file describes what 
> primitives are available in, say zynq 7c010. Spartan-6 would have the 
> primitive ISERDES2 while zynq would have ISERDESE2.
> 
> Anybody know where the per chip available primitives are stored?
> 
> -- 
> Svenn

This can be found in the Libraries Guide for each family. As an example UG953 documents the primitives that can be used within the 7 Series of FPGAs.

Ed McGettigan
--
Xilinx Inc.

Article: 157692
Subject: Re: Send a pulse across clocks
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Fri, 30 Jan 2015 00:27:21 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello Leo,

you may want to have a look at my pulse synchronizer, which is available on GitHub at: https://github.com/noasic/noasic/blob/master/components/pulse_synchronizer.vhd

Regards,

Guy Eschemann
FPGA Consultant
http://noasic.com

Article: 157693
Subject: Re: Transfering image file to DDR RAM using EDK
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Fri, 30 Jan 2015 07:31:33 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello Rashmic,

you can do this with the Xilinx Microprocessor Debugger (XMD) tool in EDK. Have a look at the "dow -data" command in UG111.

Regards,

Guy Eschemann 
FPGA Consultant 
http://noasic.com 

Article: 157694
Subject: Re: Xilinx XST and initializing block RAMs
From: "mnentwig" <24789@embeddedrelated>
Date: Mon, 02 Feb 2015 05:05:57 -0600
Links: << >>  << T >>  << A >>
I've never run into the described problem, and I think that's because I've
never tried to use an empty ROM. 
As soon as there is write capability, the tool can't optimize it away
anymore. 

Maybe the problem could be fixed by implementing write access that is never
used, but not so obviously that the tool would realize it.

BTW, good luck with DATA2MEM...	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157695
Subject: Re: scanf problem in EDk 9.1i (Microbaze)
From: djeasy22@gmail.com
Date: Wed, 4 Feb 2015 12:55:22 -0800 (PST)
Links: << >>  << T >>  << A >>
did it work?

can you post the code please

having the same issue

Article: 157696
Subject: another MicroZed project
From: John Larkin <jlarkin@highlandtechnology.com>
Date: Wed, 04 Feb 2015 15:41:34 -0800
Links: << >>  << T >>  << A >>


Another board:

https://dl.dropboxusercontent.com/u/53724080/PCBs/P350_12.jpg

The microZed compute platform plugs into the middle. The application
board has eight DAC channels with filters and amps, two ADC inputs,
power supplies, BIST, stuff like that. We put some parts under the
Zedboard, simple stuff that shouldn't need a lot of probing or
anything.

The only problem with MicroZed is that it uses a Xilinx FPGA, which
requires the Vivado software, which really sucks.



-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com


Article: 157697
Subject: [WTF] Hierarchical designs and ATMELs CPLD fitters
From: Johann Klammer <klammerj@NOSPAM.a1.net>
Date: Thu, 05 Feb 2015 18:54:42 +0100
Links: << >>  << T >>  << A >>
I've been playing with atmels old stuff again...
I can not seem to get their fitter to accept hierarchical edif.
I am using the fitters from their WinCUPL download.

the commandline I am using:
wine fit1504 -ifmt EDIF -i a.edf -dev p1504c44 -JTAG=OFF

the input file:
http://members.aon.at/~aklamme4/scratch/afit/a.edf

I get:
[...]
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking INV_1 ... 
Checking IVL_LPM_RE_XNOR_2_1 ... 
Checking IVL_XNOR2 ... 
Checking INV_1 ... 
Checking IVL_LPM_RE_XNOR_2_1 ... 
Checking IVL_XNOR2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking INV_1 ... 
Checking IVL_LPM_RE_XNOR_2_1 ... 
Checking IVL_XNOR2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking INV_1 ... 
Checking INV_1 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking INV_1 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 
Checking IVL_LPM_RE_AND_2_1 ... 
Checking IVL_AND2 ... 

INTERNAL ERROR - Please contact your Hot-Line

The IVL_AND2 is the last instance inside the bldc module, 
so the boo-boo seems to happen a bit later. 
The message is awfully unspecific, tho'.

Strangely enough this one works:
http://members.aon.at/~aklamme4/scratch/afit/test.edf
(hand written to match aprim.lib from their old fit5_0.zip download)
But it only uses bottom level cells...

The edif files output by the fitters themselves(there's an option) 
do not work, because the port names mismatch:
http://members.aon.at/~aklamme4/scratch/afit/ATF8255N.edn

I have also tried producing output files that match 
atmel.std component library. but that gave the same results...
after editing atmel.std a that came with their wincupl installation, 
as it seemed broken.
I got those messages:
``
Reading library ...
  Warning : gate dff9 defined 24 times
  Warning : gate dff5 defined 4 times
  Warning : gate dff8f defined 4 times
``
(they have loads of identically named primitives in there...)

What do I have to do to to get a.edf to fit?
Does anybody spot an obvios mistek?

I've used icarus verilog to generate the edif file
the sources are there:
https://github.com/klammerj/iverilog/tree/master/tgt-atf15

The verilog file that was used to generate the edif:
https://raw.githubusercontent.com/klammerj/iverilog/master/tgt-atf15/v/bldc.v


Article: 157698
Subject: data memory mapping microblaze
From: alb <al.basili@gmail.com>
Date: Sat, 7 Feb 2015 07:17:29 +0100 (CET)
Links: << >>  << T >>  << A >>
INFO: this very same post was posted to comp.arch.embedded with no
 follow up over few days, that's the reason why I decided to post
 it here where I hope to get more feedback.

Hi everyone,

I'm dealing with an mb-lite which is clone of the microblaze 
architecture and I'm trying to understand how the memory mapping works.

We have memory mapped registers which are needed to exchange data 
between the uP and the FPGA and it should be pretty straight
 forward to 
map this memory into a segment in 'data memory', but unfortunately it 
seems the object-dump does not seem to show anything but a list of 
segments with no distinction between 'data memory' and 'instruction 
memory'.

IIRC on similar Harvard Architectures (like the ADSP21xx) you could 
write the linker script to store data and instructions.

I'm using a mb-gcc and I've looked to the ld refernce, but how can you 
specify that a set of registers need to go to the data memory to a 
specific address? Or is it implicitely assumed that .data segments
 would 
go to a 'data memory'?

Anyone with any pointer?

Al

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
      


----Android NewsGroup Reader----
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Article: 157699
Subject: Topics for Projects on FPGA+Computer Archtecture
From: vrbvasu@gmail.com
Date: Sat, 7 Feb 2015 00:58:52 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

 I have to work on a project related to FPGA (Altera DEI or Altera DEII) and computer architecture. Can anyone suggest good topics that I can work on individually (say for 3-4 months).
Thank you in advance.



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