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Messages from 158600

Article: 158600
Subject: Re: Fully preposterous gate arranger
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 20 Jan 2016 13:59:40 -0600
Links: << >>  << T >>  << A >>
Tim Wescott wrote:

> Is there synthesis software out there that'll take Verilog or other HDL
> and generate a netlist of 7400-series logic?
> 
> To carry things one step further, if you were seriously contemplating
> such a thing, of course you'd want the software to understand that chips
> and boards are of finite sizes, that propagation delays between chips and
> boards exist, and that board-board connections have finite numbers of
> pins.
> 
> So -- has it been done, perhaps by someone with way too much time on
> their hands?  How big is an ARM M1 core when it's implemented in discrete
> logic chips that are currently available in the DigiKey catalog?  And how
> fast?
> 
Xilinx tools allow you to design at schematic level with 74xx type parts, 
and then compile to logic equations.  So, what you want is the inverse of 
that process!

Jon

Article: 158601
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Wed, 20 Jan 2016 14:09:36 -0600
Links: << >>  << T >>  << A >>
On Tue, 19 Jan 2016 17:24:53 -0700, BobH wrote:

> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>> Is there synthesis software out there that'll take Verilog or other HDL
>> and generate a netlist of 7400-series logic?
> 
> Interesting idea, but moving in the opposite direction of progress
> (grin).

Well, that's the point!  Next, I'll ask that it generates schematics 
using vacuum tube logic.

> You could probably make a technology library for a standard
> synthesis package, but handling the multiple gates/package might be a
> problem.
> 
> 
>> So -- has it been done, perhaps by someone with way too much time on
>> their hands?  How big is an ARM M1 core when it's implemented in
>> discrete logic chips that are currently available in the DigiKey
>> catalog?  And how fast?
>>
> It would probably be about the size of a PDP11-34 and run at 10MHz
> instead of 50MHz, but this is very much a WAG.

I think it'd be fun.  A Cosmac 1802 equivalent might be easier, though.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 158602
Subject: Re: Fully preposterous gate arranger
From: rickman <gnuarm@gmail.com>
Date: Wed, 20 Jan 2016 17:16:40 -0500
Links: << >>  << T >>  << A >>
On 1/20/2016 3:09 PM, Tim Wescott wrote:
> On Tue, 19 Jan 2016 17:24:53 -0700, BobH wrote:
>
>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>> Is there synthesis software out there that'll take Verilog or other HDL
>>> and generate a netlist of 7400-series logic?
>>
>> Interesting idea, but moving in the opposite direction of progress
>> (grin).
>
> Well, that's the point!  Next, I'll ask that it generates schematics
> using vacuum tube logic.
>
>> You could probably make a technology library for a standard
>> synthesis package, but handling the multiple gates/package might be a
>> problem.
>>
>>
>>> So -- has it been done, perhaps by someone with way too much time on
>>> their hands?  How big is an ARM M1 core when it's implemented in
>>> discrete logic chips that are currently available in the DigiKey
>>> catalog?  And how fast?
>>>
>> It would probably be about the size of a PDP11-34 and run at 10MHz
>> instead of 50MHz, but this is very much a WAG.
>
> I think it'd be fun.  A Cosmac 1802 equivalent might be easier, though.

How about doing logic using neon bulbs?  I've considered doing a 
hardwired sudoku solver using discrete logic with neons.  The final 
stage would be the readout.  lol  I don't want my whole living room to 
become a lab though.

-- 

Rick

Article: 158603
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Wed, 20 Jan 2016 16:42:30 -0600
Links: << >>  << T >>  << A >>
On Wed, 20 Jan 2016 17:16:40 -0500, rickman wrote:

> On 1/20/2016 3:09 PM, Tim Wescott wrote:
>> On Tue, 19 Jan 2016 17:24:53 -0700, BobH wrote:
>>
>>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>>> Is there synthesis software out there that'll take Verilog or other
>>>> HDL and generate a netlist of 7400-series logic?
>>>
>>> Interesting idea, but moving in the opposite direction of progress
>>> (grin).
>>
>> Well, that's the point!  Next, I'll ask that it generates schematics
>> using vacuum tube logic.
>>
>>> You could probably make a technology library for a standard synthesis
>>> package, but handling the multiple gates/package might be a problem.
>>>
>>>
>>>> So -- has it been done, perhaps by someone with way too much time on
>>>> their hands?  How big is an ARM M1 core when it's implemented in
>>>> discrete logic chips that are currently available in the DigiKey
>>>> catalog?  And how fast?
>>>>
>>> It would probably be about the size of a PDP11-34 and run at 10MHz
>>> instead of 50MHz, but this is very much a WAG.
>>
>> I think it'd be fun.  A Cosmac 1802 equivalent might be easier, though.
> 
> How about doing logic using neon bulbs?  I've considered doing a
> hardwired sudoku solver using discrete logic with neons.  The final
> stage would be the readout.  lol  I don't want my whole living room to
> become a lab though.

Have you seen the original gas emission counting tubes?  They had this 
arrangement where you'd trigger a clock wire which would make the glow 
jump from position 0 to position 1, etc.  You could sense which pin had 
the glow and use it for carry, etc.

Apparently there were commercially viable computers that used these 
things, and carried out addition by counting up the accumulator while 
counting the addend down to zero.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 158604
Subject: Re: Fully preposterous gate arranger
From: David Wade <dave.g4ugm@gmail.com>
Date: Wed, 20 Jan 2016 23:22:48 +0000
Links: << >>  << T >>  << A >>
On 20/01/2016 19:59, Jon Elson wrote:
> Tim Wescott wrote:
>
>> Is there synthesis software out there that'll take Verilog or other HDL
>> and generate a netlist of 7400-series logic?
>>
>> To carry things one step further, if you were seriously contemplating
>> such a thing, of course you'd want the software to understand that chips
>> and boards are of finite sizes, that propagation delays between chips and
>> boards exist, and that board-board connections have finite numbers of
>> pins.
>>
>> So -- has it been done, perhaps by someone with way too much time on
>> their hands?  How big is an ARM M1 core when it's implemented in discrete
>> logic chips that are currently available in the DigiKey catalog?  And how
>> fast?
>>
> Xilinx tools allow you to design at schematic level with 74xx type parts,
> and then compile to logic equations.  So, what you want is the inverse of
> that process!

The reverse also works, so you can look at the generated RTL after 
inputting VHDL or Verilog but its mapping to the gates in the target 
chip, not discrete TTL. It also produce an IBIS Netlist...

I suspect it may be possible to adapt one of the open source synthesis 
tools to generate TTL Netlists..

>
> Jon
>

Dave


Article: 158605
Subject: Re: Fully preposterous gate arranger
From: o pere o <me@somewhere.net>
Date: Thu, 21 Jan 2016 09:33:37 +0100
Links: << >>  << T >>  << A >>
On 21/01/16 00:22, David Wade wrote:
> On 20/01/2016 19:59, Jon Elson wrote:
<snip>
>
> I suspect it may be possible to adapt one of the open source synthesis
> tools to generate TTL Netlists..

Could you share your experience with open-source synthesis tools? I 
would be glad to have an overview on what is available and how it 
performs in practice!

Pere

>
>>
>> Jon
>>
>
> Dave
>


Article: 158606
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Thu, 21 Jan 2016 13:53:29 -0600
Links: << >>  << T >>  << A >>
On Wed, 20 Jan 2016 16:42:30 -0600, Tim Wescott wrote:

> On Wed, 20 Jan 2016 17:16:40 -0500, rickman wrote:
> 
>> On 1/20/2016 3:09 PM, Tim Wescott wrote:
>>> On Tue, 19 Jan 2016 17:24:53 -0700, BobH wrote:
>>>
>>>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>>>> Is there synthesis software out there that'll take Verilog or other
>>>>> HDL and generate a netlist of 7400-series logic?
>>>>
>>>> Interesting idea, but moving in the opposite direction of progress
>>>> (grin).
>>>
>>> Well, that's the point!  Next, I'll ask that it generates schematics
>>> using vacuum tube logic.
>>>
>>>> You could probably make a technology library for a standard synthesis
>>>> package, but handling the multiple gates/package might be a problem.
>>>>
>>>>
>>>>> So -- has it been done, perhaps by someone with way too much time on
>>>>> their hands?  How big is an ARM M1 core when it's implemented in
>>>>> discrete logic chips that are currently available in the DigiKey
>>>>> catalog?  And how fast?
>>>>>
>>>> It would probably be about the size of a PDP11-34 and run at 10MHz
>>>> instead of 50MHz, but this is very much a WAG.
>>>
>>> I think it'd be fun.  A Cosmac 1802 equivalent might be easier,
>>> though.
>> 
>> How about doing logic using neon bulbs?  I've considered doing a
>> hardwired sudoku solver using discrete logic with neons.  The final
>> stage would be the readout.  lol  I don't want my whole living room to
>> become a lab though.
> 
> Have you seen the original gas emission counting tubes?  They had this
> arrangement where you'd trigger a clock wire which would make the glow
> jump from position 0 to position 1, etc.  You could sense which pin had
> the glow and use it for carry, etc.
> 
> Apparently there were commercially viable computers that used these
> things, and carried out addition by counting up the accumulator while
> counting the addend down to zero.

https://en.wikipedia.org/wiki/Dekatron

https://en.wikipedia.org/wiki/Harwell_computer

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 158607
Subject: Re: Fully preposterous gate arranger
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 21 Jan 2016 21:31:45 +0000 (GMT)
Links: << >>  << T >>  << A >>
BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
> Interesting idea, but moving in the opposite direction of progress 
> (grin). You could probably make a technology library for a standard 
> synthesis package, but handling the multiple gates/package might be a 
> problem.

I don't think it would be so bad.  I assume that many standard cells would
have multiple outputs (eg Q and /Q) so presumably you could write a
description that a 7400 takes 8 input variables and outputs 4 output
variables - that an output doesn't depend on all the inputs isn't exactly
unusual.  Who knows how well it would do placement based on that
description, but that's usual tools voodoo.

My guess would be this would work better with a tool like Synopsys Design
Compiler (intended for standard cell gates) rather than an FPGA tool (that
thinks about LUTs), but use whatever you have really.

Presumably you could use an ASIC design flow with appropriate design rules
(set your ASIC technology to match your PCB layer stackup, tell it the
spacing rules of your PCB house) and get it to route the PCB for you?
Output Gerber instead of GDS-II and send for fab?

Hmm, that could be a fun way of teaching how to use the tools...

Theo

Article: 158608
Subject: Re: Fully preposterous gate arranger
From: David Wade <dave.g4ugm@gmail.com>
Date: Sat, 23 Jan 2016 10:42:20 +0000
Links: << >>  << T >>  << A >>
On 21/01/2016 19:53, Tim Wescott wrote:
> On Wed, 20 Jan 2016 16:42:30 -0600, Tim Wescott wrote:
>
>> On Wed, 20 Jan 2016 17:16:40 -0500, rickman wrote:
>>
>>> On 1/20/2016 3:09 PM, Tim Wescott wrote:
>>>> On Tue, 19 Jan 2016 17:24:53 -0700, BobH wrote:
>>>>
>>>>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>>>>> Is there synthesis software out there that'll take Verilog or other
>>>>>> HDL and generate a netlist of 7400-series logic?
>>>>>
>>>>> Interesting idea, but moving in the opposite direction of progress
>>>>> (grin).
>>>>
>>>> Well, that's the point!  Next, I'll ask that it generates schematics
>>>> using vacuum tube logic.
>>>>
>>>>> You could probably make a technology library for a standard synthesis
>>>>> package, but handling the multiple gates/package might be a problem.
>>>>>
>>>>>
>>>>>> So -- has it been done, perhaps by someone with way too much time on
>>>>>> their hands?  How big is an ARM M1 core when it's implemented in
>>>>>> discrete logic chips that are currently available in the DigiKey
>>>>>> catalog?  And how fast?
>>>>>>
>>>>> It would probably be about the size of a PDP11-34 and run at 10MHz
>>>>> instead of 50MHz, but this is very much a WAG.
>>>>
>>>> I think it'd be fun.  A Cosmac 1802 equivalent might be easier,
>>>> though.
>>>
>>> How about doing logic using neon bulbs?  I've considered doing a
>>> hardwired sudoku solver using discrete logic with neons.  The final
>>> stage would be the readout.  lol  I don't want my whole living room to
>>> become a lab though.
>>
>> Have you seen the original gas emission counting tubes?  They had this
>> arrangement where you'd trigger a clock wire which would make the glow
>> jump from position 0 to position 1, etc.  You could sense which pin had
>> the glow and use it for carry, etc.
>>
>> Apparently there were commercially viable computers that used these
>> things, and carried out addition by counting up the accumulator while
>> counting the addend down to zero.
>
> https://en.wikipedia.org/wiki/Dekatron
>
> https://en.wikipedia.org/wiki/Harwell_computer
>


Harking back to speed point above, the Harwell Computer is incredably 
slow. An experienced Hand Calculator operator can work just as fast, at 
least for a short period of time...

Dave
G4UGM


Article: 158609
Subject: Re: Altera MAX10 image capture application
From: "Michael Kellett" <nospam@invalid.com>
Date: sat, 23 jan 2016 11:07:06 +0000
Links: << >>  << T >>  << A >>
Steve Gulick:
> We are interested in finding someone to help develop an FPGA image
capture application. We are using Altera's MAX10 FPGA and Arrow's
BeMicro MAX10 development board. The image sensor is the MT9V034. It
will transfer captured images to a Raspberry Pi over a SPI interface.

If you are in the UK you can contact me directly and we can chat.
(You still can if you are not in the UK but it's less likely to get
anywhere :-)

Phone number is on the website:

www.mkesc.co.uk

Article: 158610
Subject: Re: Fully preposterous gate arranger
From: Walter Banks <walter@bytecraft.com>
Date: Mon, 25 Jan 2016 09:37:51 -0500
Links: << >>  << T >>  << A >>
On 19/01/2016 7:24 PM, BobH wrote:
> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>> Is there synthesis software out there that'll take Verilog or other
>> HDL and generate a netlist of 7400-series logic?
>
> Interesting idea, but moving in the opposite direction of progress
> (grin). You could probably make a technology library for a standard
> synthesis package, but handling the multiple gates/package might be a
>  problem.
>
>>
>> So -- has it been done, perhaps by someone with way too much time
>> on their hands?  How big is an ARM M1 core when it's implemented in
>> discrete logic chips that are currently available in the DigiKey
>> catalog?  And how fast?
>>
> It would probably be about the size of a PDP11-34 and run at 10MHz
> instead of 50MHz, but this is very much a WAG.

Back in the day when I was actually building computers out of such logic
10MHz was a significant challenge.

Just thinking about makes me cringe. When I finally created a 10Mps
special purpose ISA it was a real achievement. Tim clearly you have far
too much time on your hands just thinking about such stuff:) Other than
... "With miniaturization we put all this stuff in there in the last 40
years." Why?

w..


Article: 158611
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <tim@seemywebsite.com>
Date: Mon, 25 Jan 2016 10:23:02 -0600
Links: << >>  << T >>  << A >>
On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:

> On 19/01/2016 7:24 PM, BobH wrote:
>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>> Is there synthesis software out there that'll take Verilog or other
>>> HDL and generate a netlist of 7400-series logic?
>>
>> Interesting idea, but moving in the opposite direction of progress
>> (grin). You could probably make a technology library for a standard
>> synthesis package, but handling the multiple gates/package might be a
>>  problem.
>>
>>
>>> So -- has it been done, perhaps by someone with way too much time on
>>> their hands?  How big is an ARM M1 core when it's implemented in
>>> discrete logic chips that are currently available in the DigiKey
>>> catalog?  And how fast?
>>>
>> It would probably be about the size of a PDP11-34 and run at 10MHz
>> instead of 50MHz, but this is very much a WAG.
> 
> Back in the day when I was actually building computers out of such logic
> 10MHz was a significant challenge.
> 
> Just thinking about makes me cringe. When I finally created a 10Mps
> special purpose ISA it was a real achievement. Tim clearly you have far
> too much time on your hands just thinking about such stuff:) Other than
> ... "With miniaturization we put all this stuff in there in the last 40
> years." Why?

Why?  Why build vacuum-tube electronics?  Why build hot rods out of cars 
from the 1930s?

Why not?

(Note that _I_ do not wish to be the one doing this...)

-- 
www.wescottdesign.com

Article: 158612
Subject: Re: Fully preposterous gate arranger
From: Aleksandar Kuktin <akuktin@gmail.com>
Date: Mon, 25 Jan 2016 16:55:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:

> On 19/01/2016 7:24 PM, BobH wrote:
>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>> Is there synthesis software out there that'll take Verilog or other
>>> HDL and generate a netlist of 7400-series logic?
>>
>> Interesting idea, but moving in the opposite direction of progress
>> (grin). You could probably make a technology library for a standard
>> synthesis package, but handling the multiple gates/package might be a
>>  problem.
>>
>>
>>> So -- has it been done, perhaps by someone with way too much time on
>>> their hands?  How big is an ARM M1 core when it's implemented in
>>> discrete logic chips that are currently available in the DigiKey
>>> catalog?  And how fast?
>>>
>> It would probably be about the size of a PDP11-34 and run at 10MHz
>> instead of 50MHz, but this is very much a WAG.
> 
> Back in the day when I was actually building computers out of such logic
> 10MHz was a significant challenge.
> 
> Just thinking about makes me cringe. When I finally created a 10Mps
> special purpose ISA it was a real achievement. Tim clearly you have far
> too much time on your hands just thinking about such stuff:) Other than
> ... "With miniaturization we put all this stuff in there in the last 40
> years." Why?
> 
> w..

I've actually thought about this as well. I also thought about how good 
it would be to also build core memory and therefore construct a full Iron 
Age computer.

I would do this to create a known device with no non-inspectable 
components, which here means "no backdoors". Then I would use it to 
compile more integrated systems culminating with a fast FPGA-based device 
and/or a known safe compiler lineage.

However, the project is not a priority. :)

Article: 158613
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <tim@seemywebsite.com>
Date: Mon, 25 Jan 2016 11:28:43 -0600
Links: << >>  << T >>  << A >>
On Mon, 25 Jan 2016 16:55:52 +0000, Aleksandar Kuktin wrote:

> On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:
> 
>> On 19/01/2016 7:24 PM, BobH wrote:
>>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>>> Is there synthesis software out there that'll take Verilog or other
>>>> HDL and generate a netlist of 7400-series logic?
>>>
>>> Interesting idea, but moving in the opposite direction of progress
>>> (grin). You could probably make a technology library for a standard
>>> synthesis package, but handling the multiple gates/package might be a
>>>  problem.
>>>
>>>
>>>> So -- has it been done, perhaps by someone with way too much time on
>>>> their hands?  How big is an ARM M1 core when it's implemented in
>>>> discrete logic chips that are currently available in the DigiKey
>>>> catalog?  And how fast?
>>>>
>>> It would probably be about the size of a PDP11-34 and run at 10MHz
>>> instead of 50MHz, but this is very much a WAG.
>> 
>> Back in the day when I was actually building computers out of such
>> logic 10MHz was a significant challenge.
>> 
>> Just thinking about makes me cringe. When I finally created a 10Mps
>> special purpose ISA it was a real achievement. Tim clearly you have far
>> too much time on your hands just thinking about such stuff:) Other than
>> ... "With miniaturization we put all this stuff in there in the last 40
>> years." Why?
>> 
>> w..
> 
> I've actually thought about this as well. I also thought about how good
> it would be to also build core memory and therefore construct a full
> Iron Age computer.
> 
> I would do this to create a known device with no non-inspectable
> components, which here means "no backdoors". Then I would use it to
> compile more integrated systems culminating with a fast FPGA-based
> device and/or a known safe compiler lineage.
> 
> However, the project is not a priority. :)

I suspect that even those "iron age" computers had back doors.

-- 
www.wescottdesign.com

Article: 158614
Subject: watermarking on FPGA
From: Hamid Kavianathar <hamidkavianathar@gmail.com>
Date: Wed, 3 Feb 2016 05:36:57 -0800 (PST)
Links: << >>  << T >>  << A >>
I'm going to do a very simple watermarking. I want to embed a signature on unused LUTs. could you please tell me how I can do it?
Thank you very much.

Article: 158615
Subject: Re: watermarking on FPGA
From: Hamid Kavianathar <hamidkavianathar@gmail.com>
Date: Wed, 3 Feb 2016 11:26:56 -0800 (PST)
Links: << >>  << T >>  << A >>
 OR how to embed digital signature in verilog code?

Article: 158616
Subject: Re: watermarking on FPGA
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 03 Feb 2016 14:49:16 -0600
Links: << >>  << T >>  << A >>
Hamid Kavianathar wrote:

> I'm going to do a very simple watermarking. I want to embed a signature on
> unused LUTs. could you please tell me how I can do it? Thank you very
> much.
The simplest way is just to have a register that can be read out in some 
manner that has a permanent value.  This is a lot more like a serial number 
than a "watermark".  If you mean a thing that affects the logic operations 
in some subtle way, I really can't imagine how to do that.  Some FPGAs do 
have laser-programmed unique serial numbers built into the chip.

Jon

Article: 158617
Subject: Re: watermarking on FPGA
From: John Speth <johnspeth@yahoo.com>
Date: Wed, 3 Feb 2016 17:43:44 -0800
Links: << >>  << T >>  << A >>
On 2/3/2016 5:36 AM, Hamid Kavianathar wrote:
> I'm going to do a very simple watermarking. I want to embed a signature on unused LUTs. could you please tell me how I can do it?
> Thank you very much.

Disregarding any way to actually read out the signature, it seems like a 
no-brainer to simply write your signature to a multi bit register loaded 
at startup.  Just make sure the register is not synthesized away due to 
no output use.

There are at least a few requirements that are unknown:
1. Shall the watermark be readable from the FPGA bit file?  In other 
words, an FPGA is not even needed for the IP to hold the watermark.
2. Shall the watermark be readable via some mechanism?  If not, I can't 
see any reason for it.
3. I believe FPGA vendors are starting to provide security features. 
Will one of those vendor products meet your needs for a lot less effort?

JJS


Article: 158618
Subject: Re: Fully preposterous gate arranger
From: jonesandy@comcast.net
Date: Wed, 3 Feb 2016 18:32:37 -0800 (PST)
Links: << >>  << T >>  << A >>
Don't confuse synthesis with placement and routing.=20

Some board-level schematic capture systems (like Cadence Concept/Alegro DE)=
 compile a schematic into a list of "sections" (logical subcomponents) and =
then "package" these subcomponents into devices (e.g. four 2-input NAND gat=
es into one 7400 device) for layout, which can then re-assign subcomponents=
 to "swap gates" between packages during PWB layout. The "packager" underst=
ands constraints like common logical pins between multiple sections (like t=
he common clock and OE pins on a '374 octal register) so that two gates (re=
gisters in the case of a '374) can only be packaged into the same device if=
 they share the same clock and OE signals.=20

With such a back-end packaging system, the synthesis tool would only need t=
o map to single gates/functions, which would probably give better results, =
and could be "packaged" by a conventional schematic capture & layout system=
.

Andy

Article: 158619
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <tim@seemywebsite.com>
Date: Wed, 03 Feb 2016 22:01:27 -0600
Links: << >>  << T >>  << A >>
On Wed, 03 Feb 2016 18:32:37 -0800, jonesandy wrote:

> Don't confuse synthesis with placement and routing.
> 
> Some board-level schematic capture systems (like Cadence Concept/Alegro
> DE) compile a schematic into a list of "sections" (logical
> subcomponents) and then "package" these subcomponents into devices (e.g.
> four 2-input NAND gates into one 7400 device) for layout, which can then
> re-assign subcomponents to "swap gates" between packages during PWB
> layout. The "packager" understands constraints like common logical pins
> between multiple sections (like the common clock and OE pins on a '374
> octal register) so that two gates (registers in the case of a '374) can
> only be packaged into the same device if they share the same clock and
> OE signals.
> 
> With such a back-end packaging system, the synthesis tool would only
> need to map to single gates/functions, which would probably give better
> results, and could be "packaged" by a conventional schematic capture &
> layout system.

Only in the absence of significant delays due to board layout.  If you 
wanted to push the clock frequency, and especially if you were going to 
run multiple boards, then arranging things for best propagation delay 
would get -- interesting.

-- 
www.wescottdesign.com

Article: 158620
Subject: Re: Fully preposterous gate arranger
From: BobH <wanderingmetalhead.nospam.please@yahoo.com>
Date: Thu, 4 Feb 2016 16:08:08 -0700
Links: << >>  << T >>  << A >>
On 02/03/2016 09:01 PM, Tim Wescott wrote:
> Only in the absence of significant delays due to board layout.  If you
> wanted to push the clock frequency, and especially if you were going to
> run multiple boards, then arranging things for best propagation delay
> would get -- interesting.

In any event, parameter extraction for timing analysis would be a real 
trick! It should at least be possible on a PCB, wire wrap would probably 
just be a default guess.

BobH


Article: 158621
Subject: Re: Fully preposterous gate arranger
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 05 Feb 2016 13:19:29 +0000 (GMT)
Links: << >>  << T >>  << A >>
BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
> On 02/03/2016 09:01 PM, Tim Wescott wrote:
> > Only in the absence of significant delays due to board layout.  If you
> > wanted to push the clock frequency, and especially if you were going to
> > run multiple boards, then arranging things for best propagation delay
> > would get -- interesting.
> 
> In any event, parameter extraction for timing analysis would be a real 
> trick! It should at least be possible on a PCB, wire wrap would probably 
> just be a default guess.

It's possible - tools like HyperLynx do it.  For multiple boards you can
throw in the R-L-C of the interconnect as additional passive components in
the model.  If you're really fussy, Ansys will give you 3D E-M simulation to
extract them from your 3D geometry.

What this workflow isn't is closed loop.  While you can construct a
toolchain: 

HDL -> synthesis -> technology mapping -> schematic -> board layout ->
parameter extraction

the design is roughly waterfall except perhaps the board layout stage, which
is informed by timing extraction.  In other words there is no mechanism to
make changes to the logic mapping based on timing of placement: in the PCB
tool you can pin or package swap but that's about it.

FPGA tools are better at going back up and redoing the synthesis if
the place and route doesn't meet timing.  PCB tools generally don't.

Theo

Article: 158622
Subject: Re: Fully preposterous gate arranger
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Fri, 05 Feb 2016 13:12:59 -0600
Links: << >>  << T >>  << A >>
On Fri, 05 Feb 2016 13:19:29 +0000, Theo Markettos wrote:

> BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
>> On 02/03/2016 09:01 PM, Tim Wescott wrote:
>> > Only in the absence of significant delays due to board layout.  If
>> > you wanted to push the clock frequency, and especially if you were
>> > going to run multiple boards, then arranging things for best
>> > propagation delay would get -- interesting.
>> 
>> In any event, parameter extraction for timing analysis would be a real
>> trick! It should at least be possible on a PCB, wire wrap would
>> probably just be a default guess.
> 
> It's possible - tools like HyperLynx do it.  For multiple boards you can
> throw in the R-L-C of the interconnect as additional passive components
> in the model.  If you're really fussy, Ansys will give you 3D E-M
> simulation to extract them from your 3D geometry.
> 
> What this workflow isn't is closed loop.  While you can construct a
> toolchain:
> 
> HDL -> synthesis -> technology mapping -> schematic -> board layout ->
> parameter extraction
> 
> the design is roughly waterfall except perhaps the board layout stage,
> which is informed by timing extraction.  In other words there is no
> mechanism to make changes to the logic mapping based on timing of
> placement: in the PCB tool you can pin or package swap but that's about
> it.
> 
> FPGA tools are better at going back up and redoing the synthesis if the
> place and route doesn't meet timing.  PCB tools generally don't.

Well, that gives us some more guidance for making our FPGA fully 
preposterous!  To be fully preposterous, a gate arranger must be moving 
the 7400-series parts around on multiple boards and taking backplane 
delays into account.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 158623
Subject: Source control and ip cores
From: Ilya Kalistru <stebanoid@gmail.com>
Date: Sun, 7 Feb 2016 00:11:17 -0800 (PST)
Links: << >>  << T >>  << A >>
I'm looking for a peace of advice.
Currently I use git for version control in my VHDL projects and I usually i=
nclude all .vhd files as well as .xdc constrains files in it. But I don't k=
now what I should do with ip cores. Including the whole directory of ip cor=
e to repository doesn't seem to be a good idea because there are to many fi=
les and too many of them are changed after any change of ip settings. Other=
 choice, manual description of ip settings in comments is tedious and error=
 prone.

Article: 158624
Subject: Re: Source control and ip cores
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sun, 7 Feb 2016 12:12:27 -0000 (UTC)
Links: << >>  << T >>  << A >>
On Sun, 07 Feb 2016 00:11:17 -0800, Ilya Kalistru wrote:

> I'm looking for a peace of advice.
> Currently I use git for version control in my VHDL projects and I
> usually include all .vhd files as well as .xdc constrains files in it.
> But I don't know what I should do with ip cores. Including the whole
> directory of ip core to repository doesn't seem to be a good idea
> because there are to many files and too many of them are changed after
> any change of ip settings. Other choice, manual description of ip
> settings in comments is tedious and error prone.

I hear you loud and clear. FPGA tool vendors are a couple of decades 
behind in their understanding of development practices, and often don't 
seem to consider version control at all.

It takes some digging and experimentation to work out which  
configuration files you need to regenerate the IP cores from, and how to 
regenerate them with minimal GUI interaction.

Maybe worth digging around in the "command log" files to see which 
command line tools are run when you press "Generate", and which files 
they take as inputs. That command line can then be extracted for 
scripting the process.

Specific details will depend on the tools of course.

-- Brian




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