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Messages from 160300

Article: 160300
Subject: Re: Using LUTs to create a phase delayed clock - is it reproducible?
From: john <anon@example.com>
Date: Mon, 6 Nov 2017 12:11:53 -0000
Links: << >>  << T >>  << A >>
In article <otnssb$19i$1@gioia.aioe.org>, akuktin@gmail.com says...
> 
> Hi all,
> 
> I'm making a system on iCE40 and I've ran out of PLLs. The design 
> incorporates two DDR2 controllers that need to perform several operations 
> delayed with respect to the system clock. I'm gonna use a phase delayed 
> clock for that.
> 
> So my approach is to take the clock signal and pipe it through several 
> LUTs, thus delaying it.
> 
> But - how comparable are LUT delays between different chips? As in, 
> different pieces of FPGA silicon? If I implement this design, will every 
> chip be a special snowflake that needs to be calibrated separately and 
> use different lengths of LUT delay gates?

I'm very much a learner with FPGA but just my general hardware experience
suggests that would be a really bad way to go. Random use of chips
to make a delay seems a bit flakey to me. You'd surely need to create
a lock step somehow?

Reading the Xilinx design book (Churiwala) I did notice that the layout
of the FPGA can be changed by the compiler/software when manipulating 
for phase variance which might at first glance suggest software can accomodate
you - but presumably that would mean a different layout each time. I'm guessing
that would not be good.

(The Xilinx book has a whole chapter on clocking by the way)

From what I've read a more careful clocking design in the first place
using the PLLS to generate something is really  the way to go.

Perhaps I've missed something someone experienced can say though.

-- 

john

=========================
http://johntech.co.uk
=========================

Article: 160301
Subject: Re: Using LUTs to create a phase delayed clock - is it reproducible?
From: Gabor <nospam@nospam.com>
Date: Mon, 6 Nov 2017 21:15:34 -0500
Links: << >>  << T >>  << A >>
On Sunday, 11/5/2017 3:38 PM, Aleksandar Kuktin wrote:
> Hi all,
> 
> I'm making a system on iCE40 and I've ran out of PLLs. The design
> incorporates two DDR2 controllers that need to perform several operations
> delayed with respect to the system clock. I'm gonna use a phase delayed
> clock for that.
> 
> So my approach is to take the clock signal and pipe it through several
> LUTs, thus delaying it.
> 
> But - how comparable are LUT delays between different chips? As in,
> different pieces of FPGA silicon? If I implement this design, will every
> chip be a special snowflake that needs to be calibrated separately and
> use different lengths of LUT delay gates?
> 

There are some old Xilinx app notes written for Virtex E series if
memory serves me correctly.  They talk about how to use carry chains
to build a variable delay.  The point of this is that you could
use a variable delay line to create your phase delay if you have
some sort of feedback mechanism to detect the optimum delay point.
This is building a delay-locked loop out of fabric elements.  In the
old FPGA's the carry chains were much faster than LUTs and therefore
gave you much finer grain in the delay.  They are also fixed in the
layout, giving a better chance of repeatability between builds.

-- 
Gabor

Article: 160302
Subject: Re: Using LUTs to create a phase delayed clock - is it reproducible?
From: "Tomas D." <mailsoc@gmial.com>
Date: Mon, 6 Nov 2017 22:09:25 -0500
Links: << >>  << T >>  << A >>

"Aleksandar Kuktin" <akuktin@gmail.com> wrote in message 
news:otnssb$19i$1@gioia.aioe.org...
> Hi all,
>
> I'm making a system on iCE40 and I've ran out of PLLs. The design
> incorporates two DDR2 controllers that need to perform several operations
> delayed with respect to the system clock. I'm gonna use a phase delayed
> clock for that.
>
> So my approach is to take the clock signal and pipe it through several
> LUTs, thus delaying it.
>
> But - how comparable are LUT delays between different chips? As in,
> different pieces of FPGA silicon? If I implement this design, will every
> chip be a special snowflake that needs to be calibrated separately and
> use different lengths of LUT delay gates?

It seems to be a bad idea. I'd recommend an external PLL with a couple of 
outputs then. 



Article: 160303
Subject: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 07:35:36 -0800 (PST)
Links: << >>  << T >>  << A >>
The 80386DX CPU had 132 pins:

    80386DX and 80386SX pinouts:
    http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
    https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

    General architecture:
    http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

    32 pins -- data
    30 pins -- address
     4 pins -- byte enables in 32-bit writes
     1 pin  -- Read/write
     1 pin  -- Data/Control
     1 pin  -- Memory/IO
     1 pin  -- Bus mastering lock issued by CPU
     1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
     1 pin  -- Next address (for pipelining)
     1 pin  -- Address valid signal
    --
    73 pins -- For basic I/O

     3 pins -- Math-coprocessor support
     1 pin  -- Ready (or Wait, for bus cycles to complete)
     2 pins -- Hold and Hold Acknowledge (for bus mastering)
     2 pins -- Interrupt and Non-masktable Interrupt
    --
     8 pins -- General coordination with external peripherals

     1 pin  -- Reset
     1 pin  -- Double-pumped clock
    --
     2 pins -- System input

The rest of the pins are unused, go to VSS or VCC.  This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation.  And then move on to more
complex operations, including a custom microkernel.

--
Rick C. Hodgin

Article: 160304
Subject: Re: FPGA motherboard for 80386 CPU
From: rickman <gnuarm@gmail.com>
Date: Fri, 10 Nov 2017 14:46:26 -0500
Links: << >>  << T >>  << A >>
Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
> The 80386DX CPU had 132 pins:
>
>     80386DX and 80386SX pinouts:
>     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
>     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
>
>     General architecture:
>     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
>
> Of these pins on the DX variant:
>
>     32 pins -- data
>     30 pins -- address
>      4 pins -- byte enables in 32-bit writes
>      1 pin  -- Read/write
>      1 pin  -- Data/Control
>      1 pin  -- Memory/IO
>      1 pin  -- Bus mastering lock issued by CPU
>      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
>      1 pin  -- Next address (for pipelining)
>      1 pin  -- Address valid signal
>     --
>     73 pins -- For basic I/O
>
>      3 pins -- Math-coprocessor support
>      1 pin  -- Ready (or Wait, for bus cycles to complete)
>      2 pins -- Hold and Hold Acknowledge (for bus mastering)
>      2 pins -- Interrupt and Non-masktable Interrupt
>     --
>      8 pins -- General coordination with external peripherals
>
>      1 pin  -- Reset
>      1 pin  -- Double-pumped clock
>     --
>      2 pins -- System input
>
> The rest of the pins are unused, go to VSS or VCC.  This means that for a
> full 80386 "motherboard" only 83 pins are required to fully support its
> operation, 67 of which are address, data, and data type, leaving really
> only 15 pins of complex operation for a state machine.
>
> -----
> Would anybody be able to help me create this 80386 motherboard using an
> AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
> like to get it working with a single-step operation for design validation,
> and then to begin ramping it up.
>
> I figure I'll have an area of ROM which the CPU boots to load, which is a
> tiny real mode program, which begins computing something that can be exam-
> ined by the FPGA to test successful operation.  And then move on to more
> complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you.  The question you should be 
asking is who would be *willing* to help you...

What parts are you having trouble with?  Why do you need help exactly?

-- 

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Article: 160305
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 12:19:55 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
> Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
> > The 80386DX CPU had 132 pins:
> >
> >     80386DX and 80386SX pinouts:
> >     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
> >     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
> >
> >     General architecture:
> >     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
> >
> > Of these pins on the DX variant:
> >
> >     32 pins -- data
> >     30 pins -- address
> >      4 pins -- byte enables in 32-bit writes
> >      1 pin  -- Read/write
> >      1 pin  -- Data/Control
> >      1 pin  -- Memory/IO
> >      1 pin  -- Bus mastering lock issued by CPU
> >      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
> >      1 pin  -- Next address (for pipelining)
> >      1 pin  -- Address valid signal
> >     --
> >     73 pins -- For basic I/O
> >
> >      3 pins -- Math-coprocessor support
> >      1 pin  -- Ready (or Wait, for bus cycles to complete)
> >      2 pins -- Hold and Hold Acknowledge (for bus mastering)
> >      2 pins -- Interrupt and Non-masktable Interrupt
> >     --
> >      8 pins -- General coordination with external peripherals
> >
> >      1 pin  -- Reset
> >      1 pin  -- Double-pumped clock
> >     --
> >      2 pins -- System input
> >
> > The rest of the pins are unused, go to VSS or VCC.  This means that for a
> > full 80386 "motherboard" only 83 pins are required to fully support its
> > operation, 67 of which are address, data, and data type, leaving really
> > only 15 pins of complex operation for a state machine.
> >
> > -----
> > Would anybody be able to help me create this 80386 motherboard using an
> > AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
> > like to get it working with a single-step operation for design validation,
> > and then to begin ramping it up.
> >
> > I figure I'll have an area of ROM which the CPU boots to load, which is a
> > tiny real mode program, which begins computing something that can be exam-
> > ined by the FPGA to test successful operation.  And then move on to more
> > complex operations, including a custom microkernel.
> 
> I'm sure many here would be *able* to help you.  The question you should be 
> asking is who would be *willing* to help you...
> 
> What parts are you having trouble with?  Why do you need help exactly?

The 80386DX was a 5V part.  My FPGA supports 3.3V, so I need some 
kind of level shifter?  I'll need to build a breakout board to route 
through my existing 40-pin FPGA breakout ports (160 pins).  So, do 
I go with an online custom manufacturer?  Buy materials and pattern 
and etch my own board, soldering everything myself?  Are there generic 
sockets the Am386 would fit in which are already broken out?

I need help with the mechanics of Verilog.  I know how I want things 
to route, but the mechanics of the language confuse me.  I don't
understand why at times I need registers, and other times I can
route wires.  The assignments are confusing me, when to use <= and
when not to, etc.

I need basic help to get my feet off the ground.

--
Rick C. Hodgin 

Article: 160306
Subject: Re: FPGA motherboard for 80386 CPU
From: rickman <gnuarm@gmail.com>
Date: Fri, 10 Nov 2017 16:11:35 -0500
Links: << >>  << T >>  << A >>
Rick C. Hodgin wrote on 11/10/2017 3:19 PM:
> On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
>> Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
>>> The 80386DX CPU had 132 pins:
>>>
>>>     80386DX and 80386SX pinouts:
>>>     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
>>>     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
>>>
>>>     General architecture:
>>>     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
>>>
>>> Of these pins on the DX variant:
>>>
>>>     32 pins -- data
>>>     30 pins -- address
>>>      4 pins -- byte enables in 32-bit writes
>>>      1 pin  -- Read/write
>>>      1 pin  -- Data/Control
>>>      1 pin  -- Memory/IO
>>>      1 pin  -- Bus mastering lock issued by CPU
>>>      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
>>>      1 pin  -- Next address (for pipelining)
>>>      1 pin  -- Address valid signal
>>>     --
>>>     73 pins -- For basic I/O
>>>
>>>      3 pins -- Math-coprocessor support
>>>      1 pin  -- Ready (or Wait, for bus cycles to complete)
>>>      2 pins -- Hold and Hold Acknowledge (for bus mastering)
>>>      2 pins -- Interrupt and Non-masktable Interrupt
>>>     --
>>>      8 pins -- General coordination with external peripherals
>>>
>>>      1 pin  -- Reset
>>>      1 pin  -- Double-pumped clock
>>>     --
>>>      2 pins -- System input
>>>
>>> The rest of the pins are unused, go to VSS or VCC.  This means that for a
>>> full 80386 "motherboard" only 83 pins are required to fully support its
>>> operation, 67 of which are address, data, and data type, leaving really
>>> only 15 pins of complex operation for a state machine.
>>>
>>> -----
>>> Would anybody be able to help me create this 80386 motherboard using an
>>> AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
>>> like to get it working with a single-step operation for design validation,
>>> and then to begin ramping it up.
>>>
>>> I figure I'll have an area of ROM which the CPU boots to load, which is a
>>> tiny real mode program, which begins computing something that can be exam-
>>> ined by the FPGA to test successful operation.  And then move on to more
>>> complex operations, including a custom microkernel.
>>
>> I'm sure many here would be *able* to help you.  The question you should be
>> asking is who would be *willing* to help you...
>>
>> What parts are you having trouble with?  Why do you need help exactly?
>
> The 80386DX was a 5V part.  My FPGA supports 3.3V, so I need some
> kind of level shifter?  I'll need to build a breakout board to route
> through my existing 40-pin FPGA breakout ports (160 pins).  So, do
> I go with an online custom manufacturer?  Buy materials and pattern
> and etch my own board, soldering everything myself?  Are there generic
> sockets the Am386 would fit in which are already broken out?

I don't follow what you are saying here.  What is a 40 pin breakout port? 
Are you talking about connectors on an FPGA board?  I don't understand your 
goals, so I can't help you figure out what you need to do.  Are you trying 
to make a board that will plug into the existing socket on a 386 motherboard?


> I need help with the mechanics of Verilog.  I know how I want things
> to route, but the mechanics of the language confuse me.  I don't
> understand why at times I need registers, and other times I can
> route wires.  The assignments are confusing me, when to use <= and
> when not to, etc.

I'm not a Verilog guy so I can't help you with that.  I'm more of a VHDL guy.


> I need basic help to get my feet off the ground.

What's wrong with keeping your feet on the ground?

We've had this conversation before.  Every project starts with goals (user 
requirements in a formal analysis) which need to be translated to design 
requirements and finally detailed as an implementation.  You tend to mix 
those various levels without understanding you are doing that.

What are your goals exactly?

-- 

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Article: 160307
Subject: Re: FPGA motherboard for 80386 CPU
From: lasselangwadtchristensen@gmail.com
Date: Fri, 10 Nov 2017 13:15:36 -0800 (PST)
Links: << >>  << T >>  << A >>
Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:
> On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
> > Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
> > > The 80386DX CPU had 132 pins:
> > >
> > >     80386DX and 80386SX pinouts:
> > >     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
> > >     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
> > >
> > >     General architecture:
> > >     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
> > >
> > > Of these pins on the DX variant:
> > >
> > >     32 pins -- data
> > >     30 pins -- address
> > >      4 pins -- byte enables in 32-bit writes
> > >      1 pin  -- Read/write
> > >      1 pin  -- Data/Control
> > >      1 pin  -- Memory/IO
> > >      1 pin  -- Bus mastering lock issued by CPU
> > >      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
> > >      1 pin  -- Next address (for pipelining)
> > >      1 pin  -- Address valid signal
> > >     --
> > >     73 pins -- For basic I/O
> > >
> > >      3 pins -- Math-coprocessor support
> > >      1 pin  -- Ready (or Wait, for bus cycles to complete)
> > >      2 pins -- Hold and Hold Acknowledge (for bus mastering)
> > >      2 pins -- Interrupt and Non-masktable Interrupt
> > >     --
> > >      8 pins -- General coordination with external peripherals
> > >
> > >      1 pin  -- Reset
> > >      1 pin  -- Double-pumped clock
> > >     --
> > >      2 pins -- System input
> > >
> > > The rest of the pins are unused, go to VSS or VCC.  This means that for a
> > > full 80386 "motherboard" only 83 pins are required to fully support its
> > > operation, 67 of which are address, data, and data type, leaving really
> > > only 15 pins of complex operation for a state machine.
> > >
> > > -----
> > > Would anybody be able to help me create this 80386 motherboard using an
> > > AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
> > > like to get it working with a single-step operation for design validation,
> > > and then to begin ramping it up.
> > >
> > > I figure I'll have an area of ROM which the CPU boots to load, which is a
> > > tiny real mode program, which begins computing something that can be exam-
> > > ined by the FPGA to test successful operation.  And then move on to more
> > > complex operations, including a custom microkernel.
> > 
> > I'm sure many here would be *able* to help you.  The question you should be 
> > asking is who would be *willing* to help you...
> > 
> > What parts are you having trouble with?  Why do you need help exactly?
> 
> The 80386DX was a 5V part.  My FPGA supports 3.3V, so I need some 
> kind of level shifter?  I'll need to build a breakout board to route 
> through my existing 40-pin FPGA breakout ports (160 pins).  So, do 
> I go with an online custom manufacturer?  Buy materials and pattern 
> and etch my own board, soldering everything myself?  Are there generic 
> sockets the Am386 would fit in which are already broken out?
> 
> I need help with the mechanics of Verilog.  I know how I want things 
> to route, but the mechanics of the language confuse me.  I don't
> understand why at times I need registers, and other times I can
> route wires.  The assignments are confusing me, when to use <= and
> when not to, etc.

then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...




Article: 160308
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 14:02:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 4:15:43 PM UTC-5, lasselangwad...@gmail.com wrote:
> Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:
> > On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
> > > Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
> > > > The 80386DX CPU had 132 pins:
> > > >
> > > >     80386DX and 80386SX pinouts:
> > > >     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
> > > >     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
> > > >
> > > >     General architecture:
> > > >     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
> > > >
> > > > Of these pins on the DX variant:
> > > >
> > > >     32 pins -- data
> > > >     30 pins -- address
> > > >      4 pins -- byte enables in 32-bit writes
> > > >      1 pin  -- Read/write
> > > >      1 pin  -- Data/Control
> > > >      1 pin  -- Memory/IO
> > > >      1 pin  -- Bus mastering lock issued by CPU
> > > >      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
> > > >      1 pin  -- Next address (for pipelining)
> > > >      1 pin  -- Address valid signal
> > > >     --
> > > >     73 pins -- For basic I/O
> > > >
> > > >      3 pins -- Math-coprocessor support
> > > >      1 pin  -- Ready (or Wait, for bus cycles to complete)
> > > >      2 pins -- Hold and Hold Acknowledge (for bus mastering)
> > > >      2 pins -- Interrupt and Non-masktable Interrupt
> > > >     --
> > > >      8 pins -- General coordination with external peripherals
> > > >
> > > >      1 pin  -- Reset
> > > >      1 pin  -- Double-pumped clock
> > > >     --
> > > >      2 pins -- System input
> > > >
> > > > The rest of the pins are unused, go to VSS or VCC.  This means that for a
> > > > full 80386 "motherboard" only 83 pins are required to fully support its
> > > > operation, 67 of which are address, data, and data type, leaving really
> > > > only 15 pins of complex operation for a state machine.
> > > >
> > > > -----
> > > > Would anybody be able to help me create this 80386 motherboard using an
> > > > AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
> > > > like to get it working with a single-step operation for design validation,
> > > > and then to begin ramping it up.
> > > >
> > > > I figure I'll have an area of ROM which the CPU boots to load, which is a
> > > > tiny real mode program, which begins computing something that can be exam-
> > > > ined by the FPGA to test successful operation.  And then move on to more
> > > > complex operations, including a custom microkernel.
> > > 
> > > I'm sure many here would be *able* to help you.  The question you should be 
> > > asking is who would be *willing* to help you...
> > > 
> > > What parts are you having trouble with?  Why do you need help exactly?
> > 
> > The 80386DX was a 5V part.  My FPGA supports 3.3V, so I need some 
> > kind of level shifter?  I'll need to build a breakout board to route 
> > through my existing 40-pin FPGA breakout ports (160 pins).  So, do 
> > I go with an online custom manufacturer?  Buy materials and pattern 
> > and etch my own board, soldering everything myself?  Are there generic 
> > sockets the Am386 would fit in which are already broken out?
> > 
> > I need help with the mechanics of Verilog.  I know how I want things 
> > to route, but the mechanics of the language confuse me.  I don't
> > understand why at times I need registers, and other times I can
> > route wires.  The assignments are confusing me, when to use <= and
> > when not to, etc.
> 
> then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that.  I've made the KITT car red light thing.  I've 
responded to buttons.  I've debounced inputs.  An on Arduino, 
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

I know what I'm doing conceptually.  I need help in the mechanics
in Verilog, and on some practical decisions.

BTW, your reply made me LOL when I got to the "hairball" part. :-)

--
Rick C. Hodgin 

Article: 160309
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 14:14:17 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
> What is a 40 pin breakout port? 
> Are you talking about connectors on an FPGA board?

The FPGA uses a high density 160-pin connection.  You can buy an 
add-on board which takes the high-density connection and breaks 
it out to 4x 40-pin connectors (like IDE cables).

> Are you trying 
> to make a board that will plug into the existing socket
> on a 386 motherboard?

I'm trying to create a board an Am386 CPU will plug in to, which 
then makes my FPGA its motherboard.  I will be the north bridge
(memory and high speed I/O like graphics) and south bridge (low
speed I/O like keyboard, mouse, timer, etc).

> We've had this conversation before.  Every project starts with goals (user 
> requirements in a formal analysis) which need to be translated to design 
> requirements and finally detailed as an implementation.  You tend to mix 
> those various levels without understanding you are doing that.

I know what I want.  I tend to work in my head more than in formal 
writings.

> What are your goals exactly?

(1)  Get the board designed physically, and ordered or built.
(2)  Assemble the board.
(3)  Write the Verilog code to feed and respond to the CPU's needs.
(4)  Write basic software to test and debug the design.
(5)  Write real hardware for video, sound, network, keyboard, mouse,
     etc., to create a little 80386-based system.

Thank you,
Rick C. Hodgin 

Article: 160310
Subject: Re: FPGA motherboard for 80386 CPU
From: rickman <gnuarm@gmail.com>
Date: Fri, 10 Nov 2017 18:31:17 -0500
Links: << >>  << T >>  << A >>
Rick C. Hodgin wrote on 11/10/2017 5:14 PM:
> On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
>> What is a 40 pin breakout port?
>> Are you talking about connectors on an FPGA board?
>
> The FPGA uses a high density 160-pin connection.  You can buy an
> add-on board which takes the high-density connection and breaks
> it out to 4x 40-pin connectors (like IDE cables).
>
>> Are you trying
>> to make a board that will plug into the existing socket
>> on a 386 motherboard?
>
> I'm trying to create a board an Am386 CPU will plug in to, which
> then makes my FPGA its motherboard.  I will be the north bridge
> (memory and high speed I/O like graphics) and south bridge (low
> speed I/O like keyboard, mouse, timer, etc).
>
>> We've had this conversation before.  Every project starts with goals (user
>> requirements in a formal analysis) which need to be translated to design
>> requirements and finally detailed as an implementation.  You tend to mix
>> those various levels without understanding you are doing that.
>
> I know what I want.  I tend to work in my head more than in formal
> writings.

If you want to work with people, they can't see what's in your head.  You 
need to write stuff down to get help.


>> What are your goals exactly?
>
> (1)  Get the board designed physically, and ordered or built.

You need to define the board a lot better.


> (2)  Assemble the board.
> (3)  Write the Verilog code to feed and respond to the CPU's needs.

That will require the FPGA either allow the CPU access to a memory device or 
some other way serve up data from RAM and/or ROM.  Do you know what you want 
for that?

What other types of I/O do you intend to provide?  Are you familiar with the 
entire interface of the 386 CPU?  You will need to know every detail.  To 
design the equivalent of a motherboard you would do well to find a 386 PC/AT 
technical reference manual or other schematic for a motherboard.  They used 
TTL logic and you can easily implement that in the FPGA.


> (4)  Write basic software to test and debug the design.
> (5)  Write real hardware for video, sound, network, keyboard, mouse,
>      etc., to create a little 80386-based system.

So you want a full computer in an FPGA other than the 386 CPU?  You will 
also need a BIOS which is not open source... unless someone has an open 
source BIOS... I don't recall hearing of one.

So where are the parts you need help with?

-- 

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Article: 160311
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 15:59:57 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 6:31:25 PM UTC-5, rickman wrote:
> Rick C. Hodgin wrote on 11/10/2017 5:14 PM:
> > On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
> >> What are your goals exactly?
> > (1)  Get the board designed physically, and ordered or built.
> You need to define the board a lot better.

As I see it, the CPU is a black box.  I connect wires to it and
give it power and turn things on and off, and observe it turning 
things on and off, all by protocol, and it doesn't need anything 
else.

I route all pins to appropriate I/O on the FPGA, or Vcc, and then
I need to have simulated ROM at the boot address, which simulates
BIOS.  And I just read the Am386 was a CMOS 3.3V part, so that removes 
level shifters.

Since I am the motherboard, all my BIOS would need to do is setup 
interrupt vectors for CPU-issued interrupts (0x0 through 0x1f), 
and run some software that does something I have control over.

First thing I need to do is get help on board design and components.
I'm thinking a socket (Package: PGA-132) with pins routed to the 
mated 40-pin breakouts I would assign on my FPGA.  Of the 160 pins,
only so many are GPIO, so I would have that limitation on design.

I think I could do all that, but there are things I don't know.
Will I need capacitors?  Resistors?  Some kind of something to handle 
electrical oddities?  If not, then I assume making trace lines equal 
is important, but not greatly at only 40 MHz.

On the FPGA, it would route address and data pins to logic identifying 
memory and I/O, and read / write, responding appropriately, routing 
certain memory to emulated ROM, the rest to on-FPGA SRAM emulating 
DRAM.

It seems a simple physical design.  Moderately complex logically.
And very exciting. :-)

--
Rick C. Hodgin 

Article: 160312
Subject: Re: FPGA motherboard for 80386 CPU
From: rickman <gnuarm@gmail.com>
Date: Fri, 10 Nov 2017 22:15:54 -0500
Links: << >>  << T >>  << A >>
Rick C. Hodgin wrote on 11/10/2017 6:59 PM:
> On Friday, November 10, 2017 at 6:31:25 PM UTC-5, rickman wrote:
>> Rick C. Hodgin wrote on 11/10/2017 5:14 PM:
>>> On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
>>>> What are your goals exactly?
>>> (1)  Get the board designed physically, and ordered or built.
>> You need to define the board a lot better.
>
> As I see it, the CPU is a black box.  I connect wires to it and
> give it power and turn things on and off, and observe it turning
> things on and off, all by protocol, and it doesn't need anything
> else.

Everything is a black box in that sense.  The "protocol" is the part you 
need to understand in detail.


> I route all pins to appropriate I/O on the FPGA, or Vcc, and then
> I need to have simulated ROM at the boot address, which simulates
> BIOS.  And I just read the Am386 was a CMOS 3.3V part, so that removes
> level shifters.

I can't find anything that says it was 3.3 volt.  Where did you read this?


> Since I am the motherboard, all my BIOS would need to do is setup
> interrupt vectors for CPU-issued interrupts (0x0 through 0x1f),
> and run some software that does something I have control over.

Yes, if you don't plan to run it as a PC, but have you figured out any of this?


> First thing I need to do is get help on board design and components.
> I'm thinking a socket (Package: PGA-132) with pins routed to the
> mated 40-pin breakouts I would assign on my FPGA.  Of the 160 pins,
> only so many are GPIO, so I would have that limitation on design.

Board design is not as hard at 40 MHz as at 100's of MHz, but you still need 
to know something about signal integrity.  If not sometimes the voltages 
will bounce and jitter and so look like the wrong voltage when sampled and 
clocks can bounce and double clock on a single edge.  This is *very* 
important stuff to know.


> I think I could do all that, but there are things I don't know.
> Will I need capacitors?  Resistors?  Some kind of something to handle
> electrical oddities?  If not, then I assume making trace lines equal
> is important, but not greatly at only 40 MHz.

If you are asking questions at this level, you will not be able to design a 
board that will work.  You need to learn basic electronics.  What do you 
know about electronics?


> On the FPGA, it would route address and data pins to logic identifying
> memory and I/O, and read / write, responding appropriately, routing
> certain memory to emulated ROM, the rest to on-FPGA SRAM emulating
> DRAM.
>
> It seems a simple physical design.  Moderately complex logically.
> And very exciting. :-)

I think you don't know enough to understand the problems involved in what 
you are trying to do.  For one, trying to ship signal lines through two 
connectors, three boards and many inches of signal trace could result in 
severe signal integrity problems.  This is stuff I have to pay attention to 
on one board with no connectors and fairly short signal traces.

-- 

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Article: 160313
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Fri, 10 Nov 2017 20:16:18 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 10:16:03 PM UTC-5, rickman wrote:
> Rick C. Hodgin wrote on 11/10/2017 6:59 PM:
> And I just read the Am386 was a CMOS 3.3V part, so that removes
> > level shifters.
> 
> I can't find anything that says it was 3.3 volt.  Where did you read this?

Wikipedia:

    https://en.m.wikipedia.org/wiki/Intel_80386

"The AMD Am386SX and Am386DX were almost exact clones of the
80386SX and 80386DX. Legal disputes caused production delays
for several years, but AMD's 40 MHz part eventually became
very popular with computer enthusiasts as a low-cost and
low-power alternative to the 25 MHz 486SX. The power draw was
further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/
SXLV), which could operate with 3.3 V and were implemented in
fully static CMOS circuitry."

I do not find the same reference here or here:

    http://www.cpu-world.com/CPUs/80386/MANUF-AMD.html
    https://en.m.wikipedia.org/wiki/Am386

But I do find this:

    AMD Am386DE-25KC
    25 MHz
    3-5 V
    0.32-1.05 Watt
    132-pin PQFP	

So it might be this 25 MHz DE part.

--
Rick C. Hodgin 

Article: 160314
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Sat, 11 Nov 2017 10:43:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Friday, November 10, 2017 at 11:16:24 PM UTC-5, Rick C. Hodgin wrote:
> On Friday, November 10, 2017 at 10:16:03 PM UTC-5, rickman wrote:
> > Rick C. Hodgin wrote on 11/10/2017 6:59 PM:
> > And I just read the Am386 was a CMOS 3.3V part, so that removes
> > > level shifters.
> > 
> > I can't find anything that says it was 3.3 volt.  Where did you read this?
> 
> Wikipedia:
> 
>     https://en.m.wikipedia.org/wiki/Intel_80386
> 
> "The AMD Am386SX and Am386DX were almost exact clones of the
> 80386SX and 80386DX. Legal disputes caused production delays
> for several years, but AMD's 40 MHz part eventually became
> very popular with computer enthusiasts as a low-cost and
> low-power alternative to the 25 MHz 486SX. The power draw was
> further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/
> SXLV), which could operate with 3.3 V and were implemented in
> fully static CMOS circuitry."
> 
> I do not find the same reference here or here:
> 
>     http://www.cpu-world.com/CPUs/80386/MANUF-AMD.html
>     https://en.m.wikipedia.org/wiki/Am386
> 
> But I do find this:
> 
>     AMD Am386DE-25KC
>     25 MHz
>     3-5 V
>     0.32-1.05 Watt
>     132-pin PQFP	
> 
> So it might be this 25 MHz DE part.

Other references:

    https://books.google.com/books?id=FeIuiOQN-nEC&pg=PT279&lpg=PT279
    https://en.wikichip.org/wiki/File:Am386_Microprocessors_for_Personal_Computers_(1992).pdf

The PDF refers to an AMD document number #17028 for their 3V Am386.

--
Rick C. Hodgin 

Article: 160315
Subject: Re: FPGA motherboard for 80386 CPU
From: lasselangwadtchristensen@gmail.com
Date: Mon, 13 Nov 2017 08:28:03 -0800 (PST)
Links: << >>  << T >>  << A >>
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
> On Friday, November 10, 2017 at 4:15:43 PM UTC-5, lasselangwad...@gmail.com wrote:
> > Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:
> > > On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
> > > > Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
> > > > > The 80386DX CPU had 132 pins:
> > > > >
> > > > >     80386DX and 80386SX pinouts:
> > > > >     http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
> > > > >     https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884
> > > > >
> > > > >     General architecture:
> > > > >     http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf
> > > > >
> > > > > Of these pins on the DX variant:
> > > > >
> > > > >     32 pins -- data
> > > > >     30 pins -- address
> > > > >      4 pins -- byte enables in 32-bit writes
> > > > >      1 pin  -- Read/write
> > > > >      1 pin  -- Data/Control
> > > > >      1 pin  -- Memory/IO
> > > > >      1 pin  -- Bus mastering lock issued by CPU
> > > > >      1 pin  -- Bus16 size (16-bit when asserted, normally 32-bit)
> > > > >      1 pin  -- Next address (for pipelining)
> > > > >      1 pin  -- Address valid signal
> > > > >     --
> > > > >     73 pins -- For basic I/O
> > > > >
> > > > >      3 pins -- Math-coprocessor support
> > > > >      1 pin  -- Ready (or Wait, for bus cycles to complete)
> > > > >      2 pins -- Hold and Hold Acknowledge (for bus mastering)
> > > > >      2 pins -- Interrupt and Non-masktable Interrupt
> > > > >     --
> > > > >      8 pins -- General coordination with external peripherals
> > > > >
> > > > >      1 pin  -- Reset
> > > > >      1 pin  -- Double-pumped clock
> > > > >     --
> > > > >      2 pins -- System input
> > > > >
> > > > > The rest of the pins are unused, go to VSS or VCC.  This means that for a
> > > > > full 80386 "motherboard" only 83 pins are required to fully support its
> > > > > operation, 67 of which are address, data, and data type, leaving really
> > > > > only 15 pins of complex operation for a state machine.
> > > > >
> > > > > -----
> > > > > Would anybody be able to help me create this 80386 motherboard using an
> > > > > AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz?  I would
> > > > > like to get it working with a single-step operation for design validation,
> > > > > and then to begin ramping it up.
> > > > >
> > > > > I figure I'll have an area of ROM which the CPU boots to load, which is a
> > > > > tiny real mode program, which begins computing something that can be exam-
> > > > > ined by the FPGA to test successful operation.  And then move on to more
> > > > > complex operations, including a custom microkernel.
> > > > 
> > > > I'm sure many here would be *able* to help you.  The question you should be 
> > > > asking is who would be *willing* to help you...
> > > > 
> > > > What parts are you having trouble with?  Why do you need help exactly?
> > > 
> > > The 80386DX was a 5V part.  My FPGA supports 3.3V, so I need some 
> > > kind of level shifter?  I'll need to build a breakout board to route 
> > > through my existing 40-pin FPGA breakout ports (160 pins).  So, do 
> > > I go with an online custom manufacturer?  Buy materials and pattern 
> > > and etch my own board, soldering everything myself?  Are there generic 
> > > sockets the Am386 would fit in which are already broken out?
> > > 
> > > I need help with the mechanics of Verilog.  I know how I want things 
> > > to route, but the mechanics of the language confuse me.  I don't
> > > understand why at times I need registers, and other times I can
> > > route wires.  The assignments are confusing me, when to use <= and
> > > when not to, etc.
> > 
> > then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...
> 
> I've done that.  I've made the KITT car red light thing.  I've 
> responded to buttons.  I've debounced inputs.  An on Arduino, 
> which is basically C code, I've made tone generators, sent output
> on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Article: 160316
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 13 Nov 2017 08:49:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
> Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
> > > then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...
> > 
> > I've done that.  I've made the KITT car red light thing.  I've 
> > responded to buttons.  I've debounced inputs.  An on Arduino, 
> > which is basically C code, I've made tone generators, sent output
> > on a clock to a remote device on 18 pins, etc.
> 
> any of that in verilog?

Yes.  Using Lattice's Diamond software on a Lattice XP2 Brevia board:

    http://www.latticesemi.com/Products/FPGAandCPLD/LatticeXP2.aspx
    http://www.latticesemi.com/~/media/LatticeSemi/Images/ProductImages/DevelopmentKitsAndBoards/XP2_Brevia/LatticeXP2%20Brevia2%20Development%20Kit_Front.png

I've also worked on an Altera board, which is what I'd be using for
this project:

    Cyclone V GX Starter Kit
    https://www.digikey.com/product-detail/en/P0150/P0150-ND/4437934

I have this breakout board HSMC to GPIO, yielding 120 pins, plus another
40 pins which are on the GX Starter Kit board:

    https://www.digikey.com/product-detail/en/terasic-inc/P0033/P0033-ND/2003485

I wouldn't mind building a board which plugs directly in to the HSMC
port so that it has no cables, fewer connections.  But, those are
the things I don't know about the hardware end of it.  Logically, I
know I need to have this high and this low, and so on, and digitally
it would all work, but to transfer that digital logic to real analog
hardware ... I don't have any experience on it, apart from reading
many many many things about it.

--
Rick C. Hodgin

Article: 160317
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 13 Nov 2017 09:33:50 -0800 (PST)
Links: << >>  << T >>  << A >>
Direct link for Lattice XP2 Brevia2 board:

    http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeXP2Brevia2DevelopmentKit.aspx

--
Rick C. Hodgin

Article: 160318
Subject: Re: FPGA motherboard for 80386 CPU
From: lasselangwadtchristensen@gmail.com
Date: Mon, 13 Nov 2017 11:47:43 -0800 (PST)
Links: << >>  << T >>  << A >>
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
> On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
> > Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
> > > > then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...
> > > 
> > > I've done that.  I've made the KITT car red light thing.  I've 
> > > responded to buttons.  I've debounced inputs.  An on Arduino, 
> > > which is basically C code, I've made tone generators, sent output
> > > on a clock to a remote device on 18 pins, etc.
> > 
> > any of that in verilog?
> 
> Yes.  Using Lattice's Diamond software on a Lattice XP2 Brevia board:
> 

writing verilog or copy-pasting verilog ?

anyway, 99% of such a project will be done in a simulator





Article: 160319
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 13 Nov 2017 11:54:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
> Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
> > On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
> > > Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
> > > > > then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...
> > > > 
> > > > I've done that.  I've made the KITT car red light thing.  I've 
> > > > responded to buttons.  I've debounced inputs.  An on Arduino, 
> > > > which is basically C code, I've made tone generators, sent output
> > > > on a clock to a remote device on 18 pins, etc.
> > > 
> > > any of that in verilog?
> > 
> > Yes.  Using Lattice's Diamond software on a Lattice XP2 Brevia board:
> 
> writing verilog or copy-pasting verilog ?

Writing Verilog.  I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

    http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

    http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

    http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

> anyway, 99% of such a project will be done in a simulator

That would be great.  How do I do it?  What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

--
Rick C. Hodgin

Article: 160320
Subject: Re: FPGA motherboard for 80386 CPU
From: lasselangwadtchristensen@gmail.com
Date: Mon, 13 Nov 2017 12:06:39 -0800 (PST)
Links: << >>  << T >>  << A >>
Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
> On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
> > Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
> > > On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
> > > > Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
> > > > > > then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...
> > > > > 
> > > > > I've done that.  I've made the KITT car red light thing.  I've 
> > > > > responded to buttons.  I've debounced inputs.  An on Arduino, 
> > > > > which is basically C code, I've made tone generators, sent output
> > > > > on a clock to a remote device on 18 pins, etc.
> > > > 
> > > > any of that in verilog?
> > > 
> > > Yes.  Using Lattice's Diamond software on a Lattice XP2 Brevia board:
> > 
> > writing verilog or copy-pasting verilog ?
> 
> Writing Verilog.  I've also written a CPU core that synthesized in
> Altera's Quartus II software, but I never debugged it and I have no
> idea if it actually works:
> 
>     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v
> 
>     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png
> 
>     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png
> 
> > anyway, 99% of such a project will be done in a simulator
> 
> That would be great.  How do I do it?  What tools are available for
> the Alter Cyclone V GX Starter Kit toolset?

what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator 


Article: 160321
Subject: Re: FPGA motherboard for 80386 CPU
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 13 Nov 2017 12:15:07 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:
> Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
> > On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
> > > Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
> > > writing verilog or copy-pasting verilog ?
> > 
> > Writing Verilog.  I've also written a CPU core that synthesized in
> > Altera's Quartus II software, but I never debugged it and I have no
> > idea if it actually works:
> > 
> >     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v
> > 
> >     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png
> > 
> >     http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png
> > 
> > > anyway, 99% of such a project will be done in a simulator
> > 
> > That would be great.  How do I do it?  What tools are available for
> > the Alter Cyclone V GX Starter Kit toolset?
> 
> what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

I've found the tools clunky.  I want to see some kind of visualization
like this:

    http://www.visual6502.org/JSSim/index.html

Which produces information on runtime like this:

    http://www.visual6502.org/JSSim/expert.html

And produces some kind of output like this:

    (click the "Trace More" button many times)

-----
The reason I stopped working in Verilog was because I found it textual
and confusing.  I had intended to write my Logician tool, which would
be a Blender node-like arrangement of hardware, allowing me to sample
all data lines, and visualize it as with the 6502 visualization.

    Blender Node Editor (at 1:18 and after):
    https://www.youtube.com/watch?v=sc-ptGft9Vk&t=1m18s

I haven't had time to do it yet, but there must be some tool closer
to that out there.  If not, that's where we should start (writing
that tool for people to use).

--
Rick C. Hodgin

Article: 160322
Subject: Re: Test Driven Design?
From: Lars Asplund <lars.anders.asplund@gmail.com>
Date: Mon, 13 Nov 2017 14:42:42 -0800 (PST)
Links: << >>  << T >>  << A >>
If we are talking about the typical software developer interpretation of TD=
D we're dealing with code/test cycles that can be as short as one minute. T=
his is only possible with a fully automated approach to testing and that's =
why we have unit testing frameworks designed with this requirement in mind.=
 I only know of two such frameworks for HDL, VUnit and SVUnit, so the popul=
arity of these tools may serve as an indication of how widely TDD is used. =
I can't speak for SVUnit but from what I understand it's mostly used by ASI=
C verification engineers. However, I'm "the guy" who setup the test environ=
ment for VHDL-2017 and also one of the authors of VUnit so maybe I can shed=
 some light in that area.

VUnit is today used by both FPGA and ASIC teams, for VHDL and Verilog, from=
 US to Japan, when developing everything from high-volume products like aut=
omotive vision to niche military system, by simulator vendors to verify the=
ir tools, and for education. If you're like me you prefer facts over claims=
 from a promoter so I would recommend that you google for VUnit rather than=
 TDD. You should be able to find job ads where people look for VUnit skills=
, that the latest version of Sigasi Studio added VUnit support, independent=
 training providers , university education, VHDL text books, etc. You can a=
lso compare VUnit with other popular open source projects. Search for VHDL =
on Github and you'll find most of them. Look at the number of stars, where =
the supporters work, the number of forks, the number of opened issues, the =
number of closed. Look at the project homepages and the activities on their=
 forums.

However, just because people use VUnit doesn't mean that they are doing TDD=
. What I see is mainly two types of users. Some users have their own SW exp=
eriences with TDD/unit testing or have seen SW people doing it. They know w=
hat the want and end up doing just that. The other type of users doesn't ha=
ve that experience or finds the concept somewhat absurd. They are more look=
ing at the convenience of having everything fully automated but stick with =
their longer code/test cycle and they tend to do less refactoring. It doesn=
't mean that they don't get there eventually but it usually takes longer ti=
me. Unit testing and TDD is an acquired taste for anyone and requires pract=
ice. The good thing is that you can takes small steps and still get rewarde=
d.

Article: 160323
Subject: Re: Test Driven Design?
From: Lars Asplund <lars.anders.asplund@gmail.com>
Date: Mon, 13 Nov 2017 14:45:12 -0800 (PST)
Links: << >>  << T >>  << A >>
After reading this thread I also feel that I need to "defend" the simplicit=
y of VUnit :-) If you look at the VUnit setup I made for the IEEE standard =
libraries I can understand if it looks complicated but that is not your ave=
rage project and not the place to get started. At better starting point is =
https://www.youtube.com/channel/UCCPVCaeWkz6C95aRUTbIwdg. There you will fi=
nd a clip showing how to install VUnit in a minute, how you can create a co=
mpile script for non-trivial project in a minute, and how you can have your=
 project fully automated by adding  5 lines of code to every testbench. htt=
p://vunit.github.io/user_guide.html is another good source of information. =
So what makes the IEEE libraries different? Well...
- The simulator already knows about these libraries and gets confused when =
you try to compile them yourself.=20
- The code is not fully self-contained VHDL but relies on the simulator "ma=
gically" implementing some functionality
- Some subprograms are expected to assert warning/error/failure on certain =
inputs and that is not something that you can verify automatically within V=
HDL since the simulator stops. That can be handled with Python scripting or=
 you can use VUnit's assertion library which supports mocking of asserts.
- I setup a continuous integration server to run all tests whenever people =
want to summit code to he Git repository. You don't have to do that in orde=
r to run VUnit or any other unit testing framework.
- IEEE already had 30 or so testbenches but these testbenches also contain =
many test cases. VUnit allow you to isolate these test cases such that you =
can run and have their status reported individually. Rather than having 30 =
passing testbenches we now have 1700 passing test cases. You don't have to =
do this though, 5 lines of code is sufficient.



Article: 160324
Subject: Re: grey code counters
From: aviralmittal@gmail.com
Date: Tue, 14 Nov 2017 02:34:59 -0800 (PST)
Links: << >>  << T >>  << A >>
Here is a generic VHDL gray counter function.
http://www.vlsiip.com/intel/vhdlf.html
Hope you can convert it into verilog
Kr,
Avi.

On Wednesday, January 10, 2001 at 9:25:22 AM UTC, Bill Lenihan wrote:
> I know how to make binary up/down counters and LFSR-based counters in
> verilog, but does anyone know of an algorithmic/equation-based way to
> make grey-code counters?
> 
> The only examples I've seen are from old PAL application notes, and they
> are for 4-bit grey counters that are described as 16-state state
> machines, which is ok if you are keeping the counter at 4-bits, but
> impractical if you are going to much wider bit widths.
> 
> --
> ==============================
> William Lenihan
> lenihan3weNOSPAM@earthlink.net
> .... remove "NOSPAM" when replying
> ==============================




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