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I've searched for this but to no avail. I'd like a function f(D,W), where = D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count of a = lookup ROM implemented in ASIC gates. Yes, I know it's dependent on the contents. However, if half the bits are = ones and the contents are randomly distributed, a formula should be pretty = accurate. It's easy for me to figure out an upper limit. A basic ROM is an AND-OR ar= ray. The D address decoders (comprising ANDs/NOTs) can be shared amongst t= he W columns. Each of the W columns would require D/2-1 OR gates if half t= he ROM bits in each column are 1. What I don't know is how many gates can be eliminated by sharing terms. As= W increases, term sharing should go up. Again, I'm looking for a *formula= *.Article: 160851
On Thursday, December 6, 2018 at 4:02:25 PM UTC-7, Kevin Neilson wrote: > I've searched for this but to no avail. I'd like a function f(D,W), wher= e D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count of = a lookup ROM implemented in ASIC gates. >=20 > Yes, I know it's dependent on the contents. However, if half the bits ar= e ones and the contents are randomly distributed, a formula should be prett= y accurate. >=20 > It's easy for me to figure out an upper limit. A basic ROM is an AND-OR = array. The D address decoders (comprising ANDs/NOTs) can be shared amongst= the W columns. Each of the W columns would require D/2-1 OR gates if half= the ROM bits in each column are 1. >=20 > What I don't know is how many gates can be eliminated by sharing terms. = As W increases, term sharing should go up. Again, I'm looking for a *formu= la*. I meant each column would require D/4-1 ORs. Approximately.Article: 160852
On Thursday, December 6, 2018 at 4:05:29 PM UTC-7, Kevin Neilson wrote: > On Thursday, December 6, 2018 at 4:02:25 PM UTC-7, Kevin Neilson wrote: > > I've searched for this but to no avail. I'd like a function f(D,W), wh= ere D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count o= f a lookup ROM implemented in ASIC gates. > >=20 > > Yes, I know it's dependent on the contents. However, if half the bits = are ones and the contents are randomly distributed, a formula should be pre= tty accurate. > >=20 > > It's easy for me to figure out an upper limit. A basic ROM is an AND-O= R array. The D address decoders (comprising ANDs/NOTs) can be shared among= st the W columns. Each of the W columns would require D/2-1 OR gates if ha= lf the ROM bits in each column are 1. > >=20 > > What I don't know is how many gates can be eliminated by sharing terms.= As W increases, term sharing should go up. Again, I'm looking for a *for= mula*. >=20 > I meant each column would require D/4-1 ORs. Approximately. I was right the first time. D/2-1Article: 160853
GHDL is a free VHDL simulator. http://lmgtfy.com/?q=Ghdl KevinArticle: 160854
On Thursday, December 6, 2018 at 3:26:14 PM UTC-8, KJ wrote: > GHDL is a free VHDL simulator. > http://lmgtfy.com/?q=Ghdl > > Kevin Hi Kevin, Thank you for sharing the most important information. The problem is that I have no experience with Linux system. Do you have any experiences with GHDL? WengArticle: 160855
I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. KevinArticle: 160856
On Thursday, December 6, 2018 at 2:46:07 PM UTC-5, Rick C. Hodgin wrote: > Since my last post I have been working on my Logician tool. I currently = have it modeling a simple bit storage device with four gates, two inputs, o= ne output, three other devices, and 13 bit lines. It provides a type of Gt= kWave output. I'm currently working on a true visualization of the circuit= s along with a type of debugger environment for examining individual circui= ts in local / watch windows, as well as a single-step debugger. >=20 > Once it's all coded and validated, I'll move on to larger tests. I plan = to offer hot-swap DLL functions which replace large logic units once they'r= e validated, to replace their bits in and bits out with custom DLL code (fo= r faster simulations). >=20 > Logician plans to be dynamic and extensible. >=20 > When it is ready for a beta release, I'll post the Windows-based executab= le and source code online along with a video and various examples explainin= g how to use them. My first target will be the Scott CPU from the book "Bu= t How Do It Know?" It is a simple 8-bit processor designed to teach people= how computers work fundamentally. It will be sufficient for a visualizati= on and operational demonstration of its features in real-time. >=20 > I eventually plan to develop my CPUs in this tool, and to export the net = it creates to Verilog source code for use in a real FPGA. I could use help= working with Verilog and FPGA tools when that time comes. How do you plan to deal with clock enables?=20 Rick C.=20 Tesla referral code -+-+ https://ts.la/richard11209Article: 160857
On Thursday, December 6, 2018 at 9:58:46 PM UTC-5, gnuarm.del...@gmail.com = wrote: > How do you plan to deal with clock enables?=20 Logiciam supports a CLK device. It is a traditional periodic square wave f= orm outputting 1s and 0s period-based. That putput could be routed through= AND gates, what I call All1 gates, based on system flags, and would advanc= e a stepper when things are allowed to progress, per my original design int= ent as indicated in this thread. However, I'm going to try to go with an asynchronous design. --=20 Rick C. HodginArticle: 160858
On Friday, December 7, 2018 at 3:31:19 AM UTC-5, Rick C. Hodgin wrote: > On Thursday, December 6, 2018 at 9:58:46 PM UTC-5, gnuarm.del...@gmail.co= m wrote: > > How do you plan to deal with clock enables?=20 >=20 > Logician supports a CLK device. It is a traditional periodic square wave= form outputting 1s and 0s period-based. That output could be routed throu= gh AND gates, what I call All1 gates, based on system flags, and would adva= nce a stepper when things are allowed to progress, per my original design i= ntent as indicated in this thread. I watched a video this morning on the 6502. It contains the very circuit I= was describing above, with a clock generator feeding in to a small unit wh= ich receives the equivalent of busy flags from other parts of the system be= fore advancing its stepper. I about fell off the treadmill when I saw it. > However, I'm going to try to go with an asynchronous design. --=20 Rick C. HodginArticle: 160859
On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > > Kevin Hi Kevin, I registered an account in GitHub, and I found I missed and could not find GHDL in any version. Could you please give me the website to download GitHub window version? Thank you. WengArticle: 160860
On Friday, December 7, 2018 at 3:31:19 AM UTC-5, Rick C. Hodgin wrote: > On Thursday, December 6, 2018 at 9:58:46 PM UTC-5, gnuarm.del...@gmail.co= m wrote: > > How do you plan to deal with clock enables?=20 >=20 > Logiciam supports a CLK device. It is a traditional periodic square wave= form outputting 1s and 0s period-based. That putput could be routed throu= gh AND gates, what I call All1 gates, based on system flags, and would adva= nce a stepper when things are allowed to progress, per my original design i= ntent as indicated in this thread. >=20 > However, I'm going to try to go with an asynchronous design. I can't say I understand any of the above other than the "asynchronous" des= ign part. There lies madness. I have done async design and it is not easy= . A small FSM is not too hard, but anything larger is much harder. FPGAs = are not intended for async design and make it all *very* hard. =20 Do you know how to implement sequential logic asynchronously?=20 Rick C.=20 Tesla referral code -++- https://ts.la/richard11209Article: 160861
I have a Cyclone V GX Starter kit board, with Quartus 13.1:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=830
I'd like some help on setting this up to get a Pmod VGA device
to generate proper timing for VGA modes up to a 150 MHz pixel
clock (1680 x 1050).
The Pmod VGA device:
https://store.digilentinc.com/pmod-vga-video-graphics-array/
It has 4-bits each for R,G,B, and 2-bits for hsync and vsync.
The timings for VGA video modes can be found here, along with
the polarity of the hysync and vsync signals:
http://tinyvga.com/vga-timing
My primary goals are to support these modes and to get my VGA
monitor to recognize the signal:
640 x 480
800 x 600
1024 x 768
1280 x 1024
1680 x 1050
I'm content to draw alternating red, green, blue bars of about
16 pixels each, interspaced with black and white squares. Just
something to show an image.
My goal is to get two of these devices working simultaneously
on the FPGA, and to setup the ability to read RAM for the pixels.
I wouldn't even mind supporting a monochrome output for now to
be honest. I just want to be get the displays up and running
and I can add-on from there.
-----
Would anyone like to help me with this project? I'm looking for
someone to help me with the Verilog code, and to go through the
steps in Quartus to get it to synthesize and update the FPGA. I
don't have test equipment, so if someone can use their test equip-
ment to help me in that area it would be appreciated too. I fig-
ure we can share code. I'll write what I think it should be (I
already have it written), and someone can help guide me where I
am wrong, or where the idea / design is incomplete. Plus, all of
the aspects of getting it to work with an FPGA.
The GX Starter Kit also has a built-in HDMI if someone would like
to help me with that instead.
Thank you in advance.
--
Rick C. Hodgin
Article: 160862On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > > I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > > > > Kevin > > Hi Kevin, > > I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > > Could you please give me the website to download GitHub window version? > > Thank you. > > Weng https://github.com/ghdl/ghdl/releases KevinArticle: 160863
On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > > On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > > > I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > > > > > > Kevin > > > > Hi Kevin, > > > > I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > > > > Could you please give me the website to download GitHub window version? > > > > Thank you. > > > > Weng > > https://github.com/ghdl/ghdl/releases > > Kevin Hi Kevin, Thank you very much !!! I am not an experienced application user. Here I copied all related download file names from the website you suggested above: ghdl-0.35-llvm-3.8-ubuntu14.tgz 14.1 MB ghdl-0.35-llvm-macosx.tgz 12.2 MB ghdl-0.35-mcode-fedora26.tgz 2.83 MB ghdl-0.35-mcode-macosx.tgz 2.26 MB ghdl-0.35-mcode-stretch.tgz 2.93 MB ghdl-0.35-mcode-ubuntu14.tgz 3.15 MB ghdl-0.35-mcode-windows.installer.ps1 6.19 MB ghdl-0.35-mcode-windows.zip 2.31 MB ghdl-0.35-mingw32-mcode.zip 3.05 MB ghdl-0.35-mingw64-llvm.zip 12.7 MB ghdl-gpl-0.35-mcode.tgz 2.61 MB Source code (zip) Source code (tar.gz) Download statistics: Do I have to download all listed files into one holder of Window 10, run ghdl-0.35-mcode-windows.installer.ps1 and that's all? Thank you. WengArticle: 160864
On Friday, December 7, 2018 at 5:09:46 PM UTC-6, Rick C. Hodgin wrote: > I have a Cyclone V GX Starter kit board, with Quartus 13.1: > https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&No= =3D830 >=20 > I'd like some help on setting this up to get a Pmod VGA device > to generate proper timing for VGA modes up to a 150 MHz pixel > clock (1680 x 1050). >=20 > The Pmod VGA device: > https://store.digilentinc.com/pmod-vga-video-graphics-array/ >=20 > It has 4-bits each for R,G,B, and 2-bits for hsync and vsync. > The timings for VGA video modes can be found here, along with > the polarity of the hysync and vsync signals: > http://tinyvga.com/vga-timing >=20 > My primary goals are to support these modes and to get my VGA > monitor to recognize the signal: >=20 > 640 x 480 > 800 x 600 > 1024 x 768 > 1280 x 1024 > 1680 x 1050 >=20 > I'm content to draw alternating red, green, blue bars of about > 16 pixels each, interspaced with black and white squares. Just > something to show an image. >=20 > My goal is to get two of these devices working simultaneously > on the FPGA, and to setup the ability to read RAM for the pixels. > I wouldn't even mind supporting a monochrome output for now to > be honest. I just want to be get the displays up and running > and I can add-on from there. >=20 > ----- > Would anyone like to help me with this project? I'm looking for > someone to help me with the Verilog code, and to go through the > steps in Quartus to get it to synthesize and update the FPGA. I > don't have test equipment, so if someone can use their test equip- > ment to help me in that area it would be appreciated too. I fig- > ure we can share code. I'll write what I think it should be (I > already have it written), and someone can help guide me where I > am wrong, or where the idea / design is incomplete. Plus, all of > the aspects of getting it to work with an FPGA. >=20 > The GX Starter Kit also has a built-in HDMI if someone would like > to help me with that instead. >=20 > Thank you in advance. >=20 > --=20 > Rick C. Hodgin ]>I'm looking for someone to help me with the Verilog code, and to go throu= gh the steps in Quartus to get it to synthesize and update the FPGA. The Cyclone V GX Starter kit has an installed demo using the HDMI port. Its= Verilog source code is at Terasic. Edit source code until you get what yo= u want (e.g. incremental development). However, there is a lot of source c= ode to examine. The Digilent Pmod VGA device has VHDL source code demo and timings for diff= erent rasters. However the GX Starter kit does not have Pmod connectors so= one must use jumper wires to connect the Starter kit to the VGA Pmod board= . And edit the pin constraints to match.=20 At a more basic level there are Altera/Intel tutorials: https://www.intel.com/content/www/us/en/programmable/support/training/unive= rsity/materials-tutorials.html Suspect that this is where you need to start?Article: 160865
> ]>I'm looking for someone to help me with the Verilog code, and to go thr= ough the steps in Quartus to get it to synthesize and update the FPGA. >=20 > The Cyclone V GX Starter kit has an installed demo using the HDMI port. I= ts Verilog source code is at Terasic. Edit source code until you get what = you want (e.g. incremental development). However, there is a lot of source= code to examine. Can you point me to a link. I saw the video on YouTube that they went thro= ugh, but it involved a lot of little comments about things that I didn't un= derstand. They are tool-related, and design-implementation-in-FPGA related= . I could really use someone to take me through the process and help me un= derstand what's required of the tool to make it work. > The Digilent Pmod VGA device has VHDL source code demo and timings for di= fferent rasters. However the GX Starter kit does not have Pmod connectors = so one must use jumper wires to connect the Starter kit to the VGA Pmod boa= rd. And edit the pin constraints to match.=20 >=20 > At a more basic level there are Altera/Intel tutorials: > https://www.intel.com/content/www/us/en/programmable/support/training/uni= versity/materials-tutorials.html > Suspect that this is where you need to start? I can try. I think I need help using the tool. It's difficult for me to e= nter into new tools and other ways of thinking due to dyslexia and the diff= iculties I have in reading certain types of technology books / tutorials / = etc. --=20 Rick C. HodginArticle: 160866
Sample code for doing VGA with simple I/O: https://www.fpga4fun.com/PongGame.html The support page of the board you linked to has resources including an HDMI demo: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830&PartNo=4 For using the tools, the old Altera website had great instructional videos. This seems to be the new Intel branded page: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/support.html Good luck!Article: 160867
On 09/12/2018 01:46, Weng Tianxiang wrote: > On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: >> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: >>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: >>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. >>>> >>>> Kevin >>> >>> Hi Kevin, >>> >>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. >>> >>> Could you please give me the website to download GitHub window version? >>> >>> Thank you. >>> >>> Weng >> >> https://github.com/ghdl/ghdl/releases >> >> Kevin > > Hi Kevin, > > Thank you very much !!! > > I am not an experienced application user. Here I copied all related download file names from the website you suggested above: <snip> Why not use the Windows executables? http://ghdl.free.fr/site/pmwiki.php?n=Main.Download -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 160868
On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: > On 09/12/2018 01:46, Weng Tianxiang wrote: > > On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > >> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > >>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > >>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > >>>> > >>>> Kevin > >>> > >>> Hi Kevin, > >>> > >>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > >>> > >>> Could you please give me the website to download GitHub window version? > >>> > >>> Thank you. > >>> > >>> Weng > >> > >> https://github.com/ghdl/ghdl/releases > >> > >> Kevin > > > > Hi Kevin, > > > > Thank you very much !!! > > > > I am not an experienced application user. Here I copied all related download file names from the website you suggested above: > > <snip> > > Why not use the Windows executables? > http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.uk Hi Mike, I am so happy to have your post: The reason "Why not use the Windows executables" is that I don't know its existence!!! I will immediately download it and try it. I will fully focus on using GHDL and debugging all my VHDL code, and will soon share any experiences with GHDL I will have. It is really a happy ending for my post. Thank you everybody for responding to my post. WengArticle: 160869
On Monday, December 10, 2018 at 1:56:03 PM UTC-5, Emilian Miron wrote:
> Sample code for doing VGA with simple I/O:
> https://www.fpga4fun.com/PongGame.html
>=20
> The support page of the board you linked to has resources including an HD=
MI demo:
> https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&Cat=
egoryNo=3D165&No=3D830&PartNo=3D4
>=20
> For using the tools, the old Altera website had great instructional video=
s. This seems to be the new Intel branded page:
> https://www.intel.com/content/www/us/en/programmable/products/design-soft=
ware/fpga-design/quartus-prime/support.html
>=20
> Good luck!
Thank you, Emilian. I will check them out. I've looked at the videos befo=
re, and I'm still not sure I get it. I think I need someone to help me ove=
r TeamViewer + voice chat or something. Just enough to answer what are som=
e probably very basic questions, but they are show-stoppers / blockers for =
me today.
In the meantime...
A friend of mine has me working on a Scott CPU emulator at present. My des=
ign has a built-in single-step debugger, and emulates the Scott CPU from th=
e book "But How Do It Know?" by J. Clark Scott. That CPU is a real, functi=
onal, simple 8-bit CPU with less than 40 instructions encoding about 220 si=
ngle-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM:
http://www.buthowdoitknow.com/cpu_model_intro.html
This person is a professional CPU designer since the 70s, and he wants me t=
o complete my work and send him a copy of my code and design. He said he'd=
do the same and then send me his copy. We'd look them over and compare no=
tes with our approaches, designs, thoughts, extensions, how we implemented =
various things, etc.
I think he's using it as a teaching tool because he's told me how he design=
s things on paper and in emulators rather than in hardware. He came up wit=
h this design after I told him I was devoting development time to my Logici=
an tool. I think he's worried about me. :-) But, I can already design and=
write emulators. I'm looking now to move my designs into real hardware.
--=20
Rick C. Hodgin
Article: 160870
On Tuesday, December 11, 2018 at 5:58:43 PM UTC-5, Rick C. Hodgin wrote:
> In the meantime...
>=20
> A friend of mine has me working on a Scott CPU emulator at present. My d=
esign has a built-in single-step debugger, and emulates the Scott CPU from =
the book "But How Do It Know?" by J. Clark Scott. That CPU is a real, func=
tional, simple 8-bit CPU with less than 40 instructions encoding about 220 =
single-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM=
:
>=20
> http://www.buthowdoitknow.com/cpu_model_intro.html
If anyone's interested, here's the project:
http://www.libsf.org:8990/projects/LIB/repos/libsf/browse/hardware/scottcpu=
/emulator
http://www.libsf.org:8990/projects/LIB/repos/libsf/browse/hardware/scottcpu=
/emulator/scott_cpu_emulator.png
To build and test it:
c:\> git clone http://www.libsf.org:8990/scm/lib/libsf.git
Cloning into libsf...
c:\> cd hardware\scottcpu\emulator\
c:\hardware\scottcpu\emulator\> dir *.*
You can load the emulator.sln file in Visual Studio 2008 or later. Load th=
e Debug build profile. Rebuild and press F5 to run. In the emulator:
F10: Single step
F5: Run
F2: Toggle I/O registers
F3: Toggle GP registers
F4: Toggle Output/RAM
Ctrl+F5: Reset
You can also arrow around and input hex values only. If interested, Please=
report any bugs. It may lock up if you press F5 and your program doesn't =
have a termination point. Haven't tested that yet. It will also lock up i=
f it doesn't terminate on a JMP self instruction, like:
@@:
jmp @b
--=20
Rick C. Hodgin
Article: 160871Hi, What is the name of the circuit structure that generates a state machine's jumping signals? I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. What is the correct name? Thank you. WengArticle: 160872
On 13/12/2018 13:45, Weng Tianxiang wrote: > Hi, > > What is the name of the circuit structure that generates a state machine's jumping signals? > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > What is the correct name? > > Thank you. > > Weng > > > If then else or Case selectArticle: 160873
On 13/12/2018 13:45, Weng Tianxiang wrote: > Hi, > > What is the name of the circuit structure that generates a state machine's jumping signals? > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > What is the correct name? > > Thank you. > > Weng > > > Transition or next state logic? Hans www.ht-lab.comArticle: 160874
On Thursday, December 13, 2018 at 8:45:47 AM UTC-5, Weng Tianxiang wrote: > Hi, >=20 > What is the name of the circuit structure that generates a state machine'= s jumping signals? >=20 > I remember I looked at the circuit structure and wrongly remembered the s= tructure name as "decision tree". By looking at Wikipedia, I realize that i= t is a wrong name. >=20 > What is the correct name? I'm not sure there really is any universal term for this other than "logic"= . A state machine has two main elements, the memory or flip flops used to = store the state and the logic that generates the next state. Then there is= additional logic if outputs are required other than the state signals them= selves. I don't recall any formalism that names these logic blocks separat= ely other than perhaps "next state" and "output" logic.=20 What is the context of your question exactly? Maybe that will help.=20 Rick C.=20 Tesla referral code - https://ts.la/richard11209
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