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Messages from 17375

Article: 17375
Subject: Using Xilinx Foundation & Mentor Graphics
From: herry@poste.isima.fr
Date: Fri, 23 Jul 1999 08:59:49 GMT
Links: << >>  << T >>  << A >>
I'm using Renoir to write VHDL code and doing functionnal simulation.
With Leonardo I synthetize this code. Then I use Foundation 1.5 to
place & route (I import a XNF file produced by Leonardo). So when i go
back to Mentor software with my jedec file generated by Foundation 1.5,
I have problems to create a SCF file to do a timing simulation. Can
somebody hlep me, please?


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17376
Subject: Designing a Virtex board
From: Steven Derrien <sderrien@irisa.fr>
Date: Fri, 23 Jul 1999 14:20:21 +0200
Links: << >>  << T >>  << A >>
Hi,

I'm looking for advice, tips , or whatever information that would help
me with this : We'd like to design a Virtex daughter (WWW.Xilinx.com/)
board to plug on a s5933 matchmaker PCI prototype board
(www.amcc.com/XXX/). the daughterboard would include

- One SRAM Bank
- A programmable clock
- A power supply/Voltage regulator
- A small XCV50 for the daughterboard control
- An Atmel EEPROM for XCV50 configuration
- A large Virtex device to implement custom designs

The control FPGA would be initialised by an EEPROM on the board, and
would allow the second FPGA configuration through SelectMap mode with
configuration data coming from the PCI Bus.

I'm wondering about the complexity of the PCB design for this board as
relatively high clock frequency would be used (over 60 Mhz), and as
different supply voltage are needed : Amcc prototype board can supply
its daughterboard with 5v voltage, however Virtex chips require both
2.5v and 3.3v supply voltage.

This would just be a prototype used for academic purpose, so we don't
really care about EMC , PCI compliance or whatsoever, we just want it to
work on a standard x86 PCI slot ...

Can anyone gives me some tips or share experience on various problems I
may encounter. Specificallly I'd like to have an estimation about the
time required to design such a board : We would be four people involved
in the design, half of them having PCD CAD tool experience (although not
for such kind of boards).

Thanks

Steven


Article: 17377
Subject: Re: Designing a Virtex board
From: Ray Andraka <randraka@ids.net>
Date: Fri, 23 Jul 1999 08:49:40 -0400
Links: << >>  << T >>  << A >>
Have you looked at commercially available PCI virtex boards?  Look on
http://www.optimagic.com for a fairly comprehensive list of boards.  If you
roll your own, you will want at least 4 layers, probably 6 or 8.  You'll
also want to make sure the power distribution is clean and with adequate and
properly placed bypass.  Clocks and signals used as clocks (ie write
strobes) should be single source single destination, and should probably be
series terminated.  60MHz is not at all high for the Virtex silicon.
Assuming the 3.3 and 2.5 volt supplies are on board, make sure these
supplies have good high frequency characteristics (use good low ESR caps in
them).

Steven Derrien wrote:

> Hi,
>
> I'm looking for advice, tips , or whatever information that would help
> me with this : We'd like to design a Virtex daughter (WWW.Xilinx.com/)
> board to plug on a s5933 matchmaker PCI prototype board
> (www.amcc.com/XXX/). the daughterboard would include
>
> - One SRAM Bank
> - A programmable clock
> - A power supply/Voltage regulator
> - A small XCV50 for the daughterboard control
> - An Atmel EEPROM for XCV50 configuration
> - A large Virtex device to implement custom designs
>
> The control FPGA would be initialised by an EEPROM on the board, and
> would allow the second FPGA configuration through SelectMap mode with
> configuration data coming from the PCI Bus.
>
> I'm wondering about the complexity of the PCB design for this board as
> relatively high clock frequency would be used (over 60 Mhz), and as
> different supply voltage are needed : Amcc prototype board can supply
> its daughterboard with 5v voltage, however Virtex chips require both
> 2.5v and 3.3v supply voltage.
>
> This would just be a prototype used for academic purpose, so we don't
> really care about EMC , PCI compliance or whatsoever, we just want it to
> work on a standard x86 PCI slot ...
>
> Can anyone gives me some tips or share experience on various problems I
> may encounter. Specificallly I'd like to have an estimation about the
> time required to design such a board : We would be four people involved
> in the design, half of them having PCD CAD tool experience (although not
> for such kind of boards).
>
> Thanks
>
> Steven



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17378
Subject: Re: Low Cost latched I/O
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 23 Jul 1999 09:07:06 -0400
Links: << >>  << T >>  << A >>
Given your low-power requirements, may I suggest the Cool-Runner series
of CPLD's? These were developed by Philips and recently purchased by
Xilinx. Your local rep should be able to help you.

You can also take a look at www.coolrunner.com, if it is still up.

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 17379
Subject: System-on-Chip and its effect on VMEbus / uC Bus Products
From: "Wade D. Peterson" <peter299@maroon.tc.umn.edu>
Date: Fri, 23 Jul 1999 08:48:06 -0500
Links: << >>  << T >>  << A >>
We presented a paper on Tuesday called "System-on-Chip and its effect on
Microcomputer Bus Products" at the VMEbus Standards Organization (VSO) meeting
in Vancouver, B.C.  We got a pretty good response from the membership.  If
anybody is interested in this topic, they can download a copy of the
presentation from http://www.silicore.net/an072199.htm

--
Wade D. Peterson
Silicore Corporation
3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
TEL: (612) 722-3815, FAX: (612) 722-5841
URL: http://www.silicore.net/  E-MAIL: peter299@maroon.tc.umn.edu


Article: 17380
Subject: Re: Low Cost latched I/O
From: mikeandmax@aol.com (Mikeandmax)
Date: 23 Jul 1999 14:00:17 GMT
Links: << >>  << T >>  << A >>
James G posted-

>I have a requirement to expand a 8051 type microprocessor bus
>to a minimum of 50 latched I/O pins and up to 144  in some configurations.

James - 
another device you might want to consider would be the ispGDX family from
Lattice.  These devices are 'all i/o' with latches in each i/o pad fed by a 4:1
mux, built for bus interface and mux requirements.  Low cost, low power,
available from 80 to 160 i/o in 3.3v and 5v, JTAG programmable and testable. 
Give your local Lattice rep a call or try www.latticesemi.com.
good luck in your efforts -
Mike Thomas
LSC FAE NY
michael.thomas@latticesemi.com

Article: 17381
Subject: Re: Low Cost latched I/O
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 23 Jul 1999 07:56:40 -0700
Links: << >>  << T >>  << A >>
One set of devices that you might consider are the Triscend E5 configurable
systems-on-a-chip (http://www.triscend.com).  They contain an embedded
8051-compatible 8032 "Turbo" microcontroller, similar to the Dallas 80C320.
It's about 2.5 times higher performance at the same clock rate than the
original 8051.

Integrated on chip are the microcontroller, 16K to 64K of on-chip SRAM, a
high performance internal bus, and a large block of programmable logic that
is integrated with the bus.  The E5 family also has plentiful I/O--up to 316
user I/O pins on the largest device in the ball-grid package.

I would recommend the 208-pin PQFP package because you can move up and down
in density while maintaining the same footprint.  You can get up to 150 user
I/O pins in that package across four different pin-compatible devices.

The 8032 in the E5 also supports wait-states so either the processor or an
external device could change the I/O timing as required.

The E5 family is 3.3 volt CMOS and is TTL compatible and even can tolerate 5
volt inputs.

-- Steve Knapp


James G wrote in message ...
>Hello,
>I have a requirement to expand a 8051 type microprocessor bus
>to a minimum of 50 latched I/O pins and up to 144  in some configurations.
>When I posted this on comp.arch.embedded one suggestion was to
>use the 9572XL from Xilinx.  This chip does seem to be a very good
>low cost possibility.
>My main requirements are low cost.  The CPLD/FPGA will interface to
>an 8 bit bus with a 80 nanosecond cycle time, but if necessary the bus
>can be stretched to 1,000 nanoseconds (EZ-USB).  I prefer 3.3V if it
>is TTL compatible, but 5V could be used also.  The other requirement
>is low power.  I have about 20 mA for the CPLD/FPGA (at
>low clock frequency).
>Is the 9572XL a good choice?  It comes in a 100 pin package
>for about $3 in low quantity.
>Thanks for any help.
>James
>
>
>


Article: 17382
Subject: Re: Looking for proceedings
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 23 Jul 1999 08:06:26 -0700
Links: << >>  << T >>  << A >>
Most of the FCCM proceedings and all the latest FPL proceedings are
available on the Books section of The Programmable Logic Jump Station at
http://www.optimagic.com/books.html#Conferences.  There other titles listed
that may be of interest.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Eduardo Augusto Bezerra wrote in message <37972496.3A758964@sussex.ac.uk>...
>
>Hello
>
>I'd like to know where to buy the proceedings of the following
>conferences:
>
>- ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
>  FPGA '97, FPGA '98 and  FPGA '99
>
>- Reconfigurable Architectures Workshop: RAW 1997, 1998 and 1999
>
>- IEEE SYMPOSIUM ON FPGAs FOR CUSTOM COMPUTING MACHINES
>  FCCM '97, FCCM '98, FCCM '99
>
>- International Workshop on Field-Programmable Logic and Applications
>  FPL '97, FPL '98, FPL '99
>
>
>Thanks
>
>Eduardo.


Article: 17383
Subject: Re: Workstation with Synopsys license server
From: Paul Hands <phands@synopsys.com>
Date: Fri, 23 Jul 1999 16:38:50 +0100
Links: << >>  << T >>  << A >>
Please do not do this.
It is a breach of the terms and conditions of our licensing to sell or
transfer the licenses in this way.
You should contact Synopsys GmbH in Munich for further information.

Paul

"Friedhelm Rünz" wrote:

> Hello Everybody,
> We got a SPARC Workstation from a bankrupt client of us. By
> coincidence we found out, that this workstation was used as a file and
> license server for Synopsys tools.
> We don't know what this is worth, but that company owed us
> 160.000,--DM (~US$90.000,--) so we would like to sell this
> workstation. The best offer will get it.
> The license server has several licenses for the following Ver. 1999
> packages:
>         dc_expert ultra plus
>         test compiler
>         bahaviour, verilog, vhdl compiler
>         prime time
>         designware developer ultra
>         FPGA compiler II
>         etc.
>
> If someone is interested in this workstation please email me.
>
> ruenz@tzk.uni-konstanz.de
>
> Best regards
> Friedhelm

--
***********************************************************************
** Paul Hands,                                 Tel: +44 (0)118 931 3822
** District Technical Manager,                 Fax: +44 (0)118 975 0081
** Synopsys (Northern Europe) Ltd.,          Mobile: +44 (0)7050 095680
** Imperium, Imperial Way,
** Worton Grange,
** Reading, RG2 0TD                          email: phands@synopsys.com
** England
***********************************************************************


Article: 17384
Subject: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
From: "Asher C. Martin" <martin2@acm.uiuc.edu>
Date: Fri, 23 Jul 1999 15:32:55 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------C29D3CBA9944626D74339EC4
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Greetings,

My name is Asher and I am working on some VHDL code to control an
optical encoder (HEDS-9100) that will measure the angle that a device
has rotated.

Anyhow, I wanted to know how to drive a signal with multiple sources in
VHDL.  Here are some technical details.  I have two different processes
one called "grab_ch_A_data: PROCESS (angle_ch_A)" that triggers on the
EVENT that angle_ch_A changes and the other "grab_ch_B_data: PROCESS
(angle_ch_B)" triggers on the event that angle_ch_B changes.

Inside the first process I am keeping track of whether or not the device
is rotating clockwise or counter clockwise.  KEY POINT: I have this
variable called "clockwise" in both processes and they both should be
able to set "clockwise" to the direction of rotation.  The direction
depends on the current state of the input signals.

Could someone please help me out?  I would really appreciate it.

(SEE ATTACHED CODE)
 
Best regards,

>Asher<

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
 Asher C. Martin
 805 West Oregon Street
 Urbana, IL 61801-3825
 (217) 367-3877
 E-MAIL: martin2@acm.uiuc.edu
 http://fermi.isdn.uiuc.edu
 telnet://fermi.isdn.uiuc.edu
 ftp://feynman.isdn.uiuc.edu
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
--------------C29D3CBA9944626D74339EC4
Content-Type: text/plain; charset=us-ascii;
 name="angle.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="angle.vhd"

-- Asher C. Martin
-- Robotics and Computer Vision Lab

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY angle IS

	PORT
	(
		angle_ch_A		: IN	STD_LOGIC;	-- CHANNEL A FROM OPTICAL ENCODER
		angle_ch_B		: IN	STD_LOGIC;  -- CHANNEL B FROM OPTICAL ENCODER
		angle_ch_I		: IN	STD_LOGIC;  -- CHANNEL I (HIGH WHEN 360 DEG.)
		reset_switch	: IN	STD_LOGIC;  -- IF ANGLE GETS OFFSET THEN RESET THIS LINE	
		output_a		: OUT 	INTEGER RANGE 0 TO 255; --STD_LOGIC_VECTOR(7 downto 0)		
		output_b		: OUT 	INTEGER RANGE 0 TO 255; --STD_LOGIC_VECTOR(7 downto 0)
		clockwise		: INOUT	STD_LOGIC
	);
	
END angle;

ARCHITECTURE angle_architecture OF angle IS

	SIGNAL	a_counter	: INTEGER RANGE 0 TO 255;
	SIGNAL	b_counter	: INTEGER RANGE 0 TO 255;
	
BEGIN

-- THE FOLLOWING FIGURES OUT IF THE USER IS MOVING LEFT OR RIGHT
--direction: PROCESS () 
--	BEGIN
	
--END PROCESS direction;	

-- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
grab_ch_A_data: PROCESS (angle_ch_A)
	BEGIN
	
		IF reset_switch = '0' THEN -- FOR TESTING WITH THE PB_1 MAKE THIS ZERO FOR RESET
		
			a_counter <= 0;
			
		ELSIF (angle_ch_A'EVENT AND angle_ch_A = '1') THEN
			
			a_counter <= a_counter + 1;
			
		ELSE
		
			a_counter <= a_counter;	
										
		END IF;					
		
-- THE FOLLOWING FIGURES IF THE DIRECTION IS CLOCKWISE OR COUNTER CLOCKWISE		
		IF	(angle_ch_A = '1' AND angle_ch_B = '0') THEN
		
			clockwise <= '1';
			
		ELSE	
			
			clockwise <= clockwise;
			
		END IF; 
		
END PROCESS grab_ch_A_data;

-- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
grab_ch_B_data: PROCESS (angle_ch_B)
	BEGIN
	
		IF reset_switch = '0' THEN -- W/ B_1 MAKE '0' OTHERWISE KEEP '1'
		
			b_counter <= 0;
			
		ELSIF (angle_ch_B'EVENT AND angle_ch_B = '1') THEN
			
			b_counter <= b_counter + 1;
			
		ELSE
		
			b_counter <= b_counter;	
										
		END IF;					
		
-- THE FOLLOWING FIGURES IF THE DIRECTION IS CLOCKWISE OR COUNTER CLOCKWISE		
		IF	(angle_ch_A = '0' AND angle_ch_B = '1') THEN
		
			clockwise <= '0';
			
		ELSE	
			
			clockwise <= clockwise;
			
		END IF; 
		
END PROCESS grab_ch_B_data;


-- THE CURRENT ANGLE IS NOW LOCATED AT "ANGLE_OUTPUT"
	output_a <= a_counter;
	output_b <= b_counter;
	
END angle_architecture;



--------------C29D3CBA9944626D74339EC4--

Article: 17385
Subject: What does a SpartanXL look like prior to configuration?
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Fri, 23 Jul 1999 20:36:42 GMT
Links: << >>  << T >>  << A >>
Do all the pin's have weak pull-ups prior to configuration?
If so why do floating JTAG lines cause configuration woes?
Where is all this documented?  Data sheet, ap note, ... ?

I have taken the conservative approach of adding external pull-ups
everywhere so lines won't float prior to configuration.
Do I really need all these resistors?


Steve


Article: 17386
Subject: Re: What does a SpartanXL look like prior to configuration?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 23 Jul 1999 17:13:31 -0400
Links: << >>  << T >>  << A >>
All the programmable I/O do have weak pull-ups.  You do not need
external pullups on regular IOs to make the FPGA happy if there is
nothing connected to the pin.  These pull-ups may not be strong enough
to act as pullups for other logic attached to the pins, however.   The
pull-ups can also be overcome by emi picked up on undriven circuit
traces connected to the pin.  For signals that must be held at a known
level during configuration (like the JTAG TMS and/or TCK or write
strobes on attached memory), you would be well advised to supplement the
pull-ups to make sure noise picked up on the circuit trace doesn't cause
unwanted operation.  Only the signals that would upset operation need
pull-ups.

.Steve wrote:

> Do all the pin's have weak pull-ups prior to configuration?
> If so why do floating JTAG lines cause configuration woes?
> Where is all this documented?  Data sheet, ap note, ... ?
>
> I have taken the conservative approach of adding external pull-ups
> everywhere so lines won't float prior to configuration.
> Do I really need all these resistors?
>
> Steve



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17387
Subject: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 23 Jul 1999 18:11:55 -0400
Links: << >>  << T >>  << A >>
You might do this as a single process.  It would also be easier if you made this synchronous.  You need a
storage element to resolve the direction, which you have done with a pair of counters.  The direction
cannot be determined just by the current inputs, you need to know what they were before the latest change
too.  Normally a quadrature resolver uses a decoder circuit that then drives a single up-down counter.
The following code should give you the idea.   I've shortened angle_ch_A to ain and same with b to save my
fingers.   I just typed the code here, so I make no guarantees that it'll compile without error.  ain,
bin, index are the inputs from the encoder.


process(clk)
variable dir: std_logic_vector(1 downto 0)="00";
variable aold,bold: std_logic;
begin
    if index = '1' then
        angle<= (others=> '0');
    else
    if clk'event and clk='1' then
        dir := (ain xor aold) & (bin xor bold);
        aold:=ain;
        bold:=bin;
        case dir is
            when  "00" =>  --no change
                moved <= 0;    --leave cw output alone
           when  "01" =>  -- clockwise rotation
                angle <= angle +1;
                moved <= 1;
                cw <= 1;
            when "10" => --ccw rotation
                angle <= angle - 1;
                moved <= 1;
                cw <= 0;
           when "11" =>   -- this is an error condition...either a bad sensor or rotation is faster than
clock
        end case;
    end if;
end if;
end process;




Asher C. Martin wrote:

> Greetings,
>
> My name is Asher and I am working on some VHDL code to control an
> optical encoder (HEDS-9100) that will measure the angle that a device
> has rotated.
>
> Anyhow, I wanted to know how to drive a signal with multiple sources in
> VHDL.  Here are some technical details.  I have two different processes
> one called "grab_ch_A_data: PROCESS (angle_ch_A)" that triggers on the
> EVENT that angle_ch_A changes and the other "grab_ch_B_data: PROCESS
> (angle_ch_B)" triggers on the event that angle_ch_B changes.
>
> Inside the first process I am keeping track of whether or not the device
> is rotating clockwise or counter clockwise.  KEY POINT: I have this
> variable called "clockwise" in both processes and they both should be
> able to set "clockwise" to the direction of rotation.  The direction
> depends on the current state of the input signals.
>
> Could someone please help me out?  I would really appreciate it.
>
> (SEE ATTACHED CODE)
>
> Best regards,
>
> >Asher<
>
> <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
>  Asher C. Martin
>  805 West Oregon Street
>  Urbana, IL 61801-3825
>  (217) 367-3877
>  E-MAIL: martin2@acm.uiuc.edu
>  http://fermi.isdn.uiuc.edu
>  telnet://fermi.isdn.uiuc.edu
>  ftp://feynman.isdn.uiuc.edu
> <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
>
>   ------------------------------------------------------------------------
> -- Asher C. Martin
> -- Robotics and Computer Vision Lab
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
>
> ENTITY angle IS
>
>         PORT
>         (
>                 angle_ch_A              : IN    STD_LOGIC;      -- CHANNEL A FROM OPTICAL ENCODER
>                 angle_ch_B              : IN    STD_LOGIC;  -- CHANNEL B FROM OPTICAL ENCODER
>                 angle_ch_I              : IN    STD_LOGIC;  -- CHANNEL I (HIGH WHEN 360 DEG.)
>                 reset_switch    : IN    STD_LOGIC;  -- IF ANGLE GETS OFFSET THEN RESET THIS LINE
>                 output_a                : OUT   INTEGER RANGE 0 TO 255; --STD_LOGIC_VECTOR(7 downto 0)
>                 output_b                : OUT   INTEGER RANGE 0 TO 255; --STD_LOGIC_VECTOR(7 downto 0)
>                 clockwise               : INOUT STD_LOGIC
>         );
>
> END angle;
>
> ARCHITECTURE angle_architecture OF angle IS
>
>         SIGNAL  a_counter       : INTEGER RANGE 0 TO 255;
>         SIGNAL  b_counter       : INTEGER RANGE 0 TO 255;
>
> BEGIN
>
> -- THE FOLLOWING FIGURES OUT IF THE USER IS MOVING LEFT OR RIGHT
> --direction: PROCESS ()
> --      BEGIN
>
> --END PROCESS direction;
>
> -- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
> grab_ch_A_data: PROCESS (angle_ch_A)
>         BEGIN
>
>                 IF reset_switch = '0' THEN -- FOR TESTING WITH THE PB_1 MAKE THIS ZERO FOR RESET
>
>                         a_counter <= 0;
>
>                 ELSIF (angle_ch_A'EVENT AND angle_ch_A = '1') THEN
>
>                         a_counter <= a_counter + 1;
>
>                 ELSE
>
>                         a_counter <= a_counter;
>
>                 END IF;
>
> -- THE FOLLOWING FIGURES IF THE DIRECTION IS CLOCKWISE OR COUNTER CLOCKWISE
>                 IF      (angle_ch_A = '1' AND angle_ch_B = '0') THEN
>
>                         clockwise <= '1';
>
>                 ELSE
>
>                         clockwise <= clockwise;
>
>                 END IF;
>
> END PROCESS grab_ch_A_data;
>
> -- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
> grab_ch_B_data: PROCESS (angle_ch_B)
>         BEGIN
>
>                 IF reset_switch = '0' THEN -- W/ B_1 MAKE '0' OTHERWISE KEEP '1'
>
>                         b_counter <= 0;
>
>                 ELSIF (angle_ch_B'EVENT AND angle_ch_B = '1') THEN
>
>                         b_counter <= b_counter + 1;
>
>                 ELSE
>
>                         b_counter <= b_counter;
>
>                 END IF;
>
> -- THE FOLLOWING FIGURES IF THE DIRECTION IS CLOCKWISE OR COUNTER CLOCKWISE
>                 IF      (angle_ch_A = '0' AND angle_ch_B = '1') THEN
>
>                         clockwise <= '0';
>
>                 ELSE
>
>                         clockwise <= clockwise;
>
>                 END IF;
>
> END PROCESS grab_ch_B_data;
>
> -- THE CURRENT ANGLE IS NOW LOCATED AT "ANGLE_OUTPUT"
>         output_a <= a_counter;
>         output_b <= b_counter;
>
> END angle_architecture;



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17388
Subject: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
From: "Alvin E. Toda" <aet@lava.net>
Date: Fri, 23 Jul 1999 12:24:02 -1000
Links: << >>  << T >>  << A >>
On Fri, 23 Jul 1999, Asher C. Martin wrote:

> Inside the first process I am keeping track of whether or not the device
> is rotating clockwise or counter clockwise.  KEY POINT: I have this
> variable called "clockwise" in both processes and they both should be
> able to set "clockwise" to the direction of rotation.  The direction
> depends on the current state of the input signals.
> 
> Could someone please help me out?  I would really appreciate it.

I'm kind of weak on VHDL but I notice the statement

clockwise <= clockwise;

which is the default. Since you have typed this signal as
"inout", it seems to me this will create a problem for the
synthesizer since a tri-stated signal may not be driven
at all but floating. If you have taken care of all cases, then
it would seem that you would not need this statement.
How about defining a muxed output where there may be no
ambiguity-- it will either be one way or the other?
My $.02 .

--al toda

Article: 17389
Subject: EVERYTHING YOU WANT !!!! 7306
From: pbfrtl@NO.MAIL
Date: 23 Jul 1999 22:31:17 GMT
Links: << >>  << T >>  << A >>
LOVE FROM SANDY
http://wetdreams.free-teen.com

18+ only !!!!!
owdwqzdhrnwiuswspgoedrkjrsu

Article: 17390
Subject: Re: Solaris vs. NT
From: "Austin Franklin" <austin@dark88room.com>
Date: 23 Jul 1999 22:52:32 GMT
Links: << >>  << T >>  << A >>
> ...I realize that I can write an entire 12-page
> document with diagrams and color pictures using Microsoft Word in the
> time it takes me to remember what the proper key combination is to exit
> and save a text file from a Unix editor. 
> And give me Word any day over trying to hack runoff or LaTex.

I would agree, if it weren't for the 8 reboots it takes to get a 12 page
document entered...

;-)

Article: 17391
Subject: Re: Hardware FFT Design?
From: jmhill@twain.WPI.EDU (Jonathan M Hill)
Date: 23 Jul 1999 23:33:15 GMT
Links: << >>  << T >>  << A >>
Dennis;

    I cannot help much, but here is some advice.  I strongly suggest
that you find someone who knows about computer architecture and ask
about "Register Level Design".  Next find someone who knows something
about scientific computations and ask for advice on machine numbers.  
Soon you will be very intimate with the details that most programmers
take for granted.
                                                Good Luck;
                                                  Jonathan Hill

Drizzt (drizzt123@NOSPAM.hotmail.com) wrote:
: Hello,
: 
: I am part of a research group at my university and one of the things
: that we are tying to do is develop some core designs that can be used
: within different xilinx fpga's (4000 and Virtex)...
: 
: Currently I am trying to design a hardware FFTand was wondering if
: anyone could help me with a general (expandable) hardware design?  I
: have been able to find a lot of stuff on software algorithms, but
: there is very little about how to implement this in hardware... 
: 
: Thanks,
: Dennis
Article: 17392
Subject: Re: EVERYTHING YOU WANT !!!! 7306
From: "Tony" <tony@NO_SPAMencoreelectronics.com>
Date: Sat, 24 Jul 1999 00:15:45 GMT
Links: << >>  << T >>  << A >>
Asshole cross posting, non-reply prick. Why can't they keep this shit off
our newsgroups?




<pbfrtl@NO.MAIL> wrote in message news:7naqfl$7o7$1672@news1.xs4all.nl...
> LOVE FROM SANDY
> http://wetdreams.free-teen.com
>
> 18+ only !!!!!
> owdwqzdhrnwiuswspgoedrkjrsu
>


Article: 17393
Subject: Re: Hardware FFT Design?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 23 Jul 1999 20:17:59 -0400
Links: << >>  << T >>  << A >>
It is not for the faint of heart, but it can be done.  Alot depends on the
data rates and device size constraints.  Faster requires bigger.  There are
a number of approaches to performing the FFT butterflies in FPGA hardware,
including distributed arithmetic techniques, cordic, and straightforward
multiplies and adds.  There are also several algorithmic approaches to the
FFT, some of which are better suited to hardware than others.  For smaller
FFTs, the winograd FFT seems to work pretty well.  For a comprehensive look
at the FFT, I recommend Smith & Smith Handbook of real time fast fourier
transforms, which I think is an IEEE press book.  After that, you might
look for papers published on implementing FFTs in  FPGAs.  I know there are
papers by Les Mintzer and Chris Dick out there among others.  Good places
to look for such papers would be proceedings for the following conferences:
FCCM, FPGA, Asilomar, SPIE, RAW.

Jonathan M Hill wrote:

> Dennis;
>
>     I cannot help much, but here is some advice.  I strongly suggest
> that you find someone who knows about computer architecture and ask
> about "Register Level Design".  Next find someone who knows something
> about scientific computations and ask for advice on machine numbers.
> Soon you will be very intimate with the details that most programmers
> take for granted.
>                                                 Good Luck;
>                                                   Jonathan Hill
>
> Drizzt (drizzt123@NOSPAM.hotmail.com) wrote:
> : Hello,
> :
> : I am part of a research group at my university and one of the things
> : that we are tying to do is develop some core designs that can be used
> : within different xilinx fpga's (4000 and Virtex)...
> :
> : Currently I am trying to design a hardware FFTand was wondering if
> : anyone could help me with a general (expandable) hardware design?  I
> : have been able to find a lot of stuff on software algorithms, but
> : there is very little about how to implement this in hardware...
> :
> : Thanks,
> : Dennis



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17394
Subject: Re: EVERYTHING YOU WANT !!!! 7306
From: albaugh@agames.com (Mike Albaugh)
Date: 24 Jul 1999 01:30:57 GMT
Links: << >>  << T >>  << A >>
Tony (tony@NO_SPAMencoreelectronics.com) wrote:
: Asshole cross posting, non-reply prick. Why can't they keep this shit off
: our newsgroups?

	Um... who do you think "they" are that would have the power
to "keep ... off our newsgroups"? The original poster neither knows
nor cares about your opionion, and virtually nobody is "in charge"
of what gets posted to UseNet. Some people like the "frontier"
(e.g. me, most of the time), even while pining for the days
before all the carpet-baggers and Harold Hills (or Green Card
Lawyers) got here... :-)

	And, what was taht about "Non-reply". Kettle, meet pot... :-)

					Mike
| albaugh@agames.com, speaking only for myself
Article: 17395
Subject: Re: Frequency multiplier in XC4000
From: tbishop@sni.net (Tom Bishop)
Date: Sat, 24 Jul 1999 03:39:26 GMT
Links: << >>  << T >>  << A >>
I have also built a frequency multiplier in an XC4000 part. It uses a
line drawing algorithm for computer graphics called an integer DDA. It
can multiply by any integer multiple, as long as the output frequency
is less than half of the master clock frequency. In computer graphics,
the decision is whether to draw a pixel on the current row, or on the
row above, for instance. As a frequency multiplier, the decision is
whether to toggle the output or not. 

This is easier to implement than it is to describe. I would refer you
to any good computer graphics book to describe the operation of the
algorithm. If you still have questions, send me an email. 

Regards,
  Tom

On Mon, 19 Jul 1999 11:36:06 +0100, "bill morris"
<bill_morris99@hotmail.com> wrote:

>Has anybody tried to implement a frequency multiplier in XC4k? I need to
>implement a frequency multiplier by 2^n (n=1,2,3,4). I know VIRTEX contain
>DLL's which can implement that but unfortunately I have to use XC4kE.
>
>Please help!
>
>

--Remove .nospam from my email address for a reply.
Article: 17396
Subject: Re: "Contract Outsourcing?!"
From: "Margaret Dailey" <margaret@cyberhighway.net>
Date: Fri, 23 Jul 1999 20:45:37 -0700
Links: << >>  << T >>  << A >>
Aww, Blake, no fair.  How come you don't like us?  Dare I ask?





Article: 17397
Subject: Mixed Signal Design Engineers Wanted
From: "Margaret Dailey" <margaret@cyberhighway.net>
Date: Fri, 23 Jul 1999 21:27:43 -0700
Links: << >>  << T >>  << A >>
Oxford & Associates is one of the country’s leading suppliers of technical
personnel.  Our Portland, Oregon office is helping a local manufacturer of
production chip testing equipment look for a hardware designer.  Our client’
s customers are some of the best-known companies in the business.

Requirements:

--topnotch hardware design skills;
--5 years' experience with mixed signal products;
--design, synthesis, and verification using standard industry tools;
--work with signals from a few to several hundred mHz;
--BSEE; and
--the ability and desire to conceive, implement, and drive your projects.

Some background working on military communications projects is desirable.
This is a direct position, and the work is to be done at the client's
facility in suburban Portland, Oregon.

If you have a solid background in hardware engineering and are ready to
assume leadership of projects designed to take our client into the next
phase of technology, please email your resume or give me a call.  Principals
only, please.

Margaret Dailey
503-291-5250
margaret_dailey@oxfordcorp.com


Article: 17398
Subject: How to get Foundation synthesis result(gate level layout)?
From: ant <antmod@hotmail.com>
Date: Sat, 24 Jul 1999 05:12:35 -0400
Links: << >>  << T >>  << A >>
Hello,

I'm using Foundation to synthesis my VHDL code and I wonder whether I
can get gate level layout (schematic) from the synthesis result. I'm
having a hard time debugging the code so that all timing constraints
will be met and the Post Layout Timing Report doesn't help much at all.

Thank you very much,
Ant


Article: 17399
Subject: Re: Solaris vs. NT
From: Zoltan Kocsi <root@127.0.0.1>
Date: 24 Jul 1999 20:07:24 +1000
Links: << >>  << T >>  << A >>
husby@fnal.gov (Don Husby) writes:

> As did I.  And sometimes, when I'm forced to enter the Unix domain and
> use one of those editors, I realize that I can write an entire 12-page
> document with diagrams and color pictures using Microsoft Word in the
> time it takes me to remember what the proper key combination is to exit
> and save a text file from a Unix editor. 
> And give me Word any day over trying to hack runoff or LaTex.

I offered not to start editor wars ...

As far as I know, StarOffice has been designed to be a MS Office clone
and according to nettalk it is. I use Applixware as office package, I 
guess it is fairly similar in functionality. You can use Wordperfect,
which seems to be a reasonable WP. What I was referring to originally
was FrameMaker, WYSIWYG in nature, which was available on unix way 
before Windows '95 or NT 3.5.

Despite all that, apparently those who got used to LaTeX would not 
trade it for any WYSIWYG WP when it's time to generate publishing
quality technical or scientific documents.
Anyway, I don't know why would an MS Office clone be much harder to
use than Office itself ? Or Applixware, for that matter ?

By the way, to save a file in XEmacs you can click on the 'save' button, 
with that little floppy icon on it. To exit, choose File -> Exit.
If you want it otherwise, it's up to you to bind this functionality to 
any button, key, icon or whatever. Applixware is the same. Would that
really be so much easier under Windows ?

>   A visual C++ development environment is much better than any Unix
> environment I've ever used.  The visual C++ debugger is quite pleasant.
> Integrated object browsers, documentation, and resource editors make
> it almost too easy to develop (windows-based) software.  I've struggled
> with Unix debuggers, but never found them easier to use than just putting
> printf's in my code.

There might be a significant difference between the SW domains we are in.
When I write SW it is usually for one of those gizmos which I design the
FPGA for (all in al, it's comp.arch.fpga :-). It's much more important
to us to have an environment which can handle 100s of KLOC maintained,
revision controlled, code parts to be automatically written by scripts,
changes merged (we have external people doing code development who we
contact only by e-means). In addition, it is fairly important to us that
we can debug stuff specific to our HW, such as looking at slave CPUs
through the main CPU on the board, all using the single debugger.
gcc/gdb and the unix tools can easily cut it and XEmacs gives a 
not that glorious but convenient enough framework. 
Mind you, often the gizmo couldn't printf() for it lacks display, serial 
line or any form of output device except 2 or 3 LEDs :-)
I do not know if there are object browsers under unix for C++ application
development. I know that Applix comes with a GUI application builder with 
all sorts of CORBA and C++ and whichever object and resource browsers,
whatever they are - I'm not doing this stuff and I know nothing about it.
If you say that it's all rubbish compared to Visual C++, I'll believe you.
For complex embedded system works, however, I have not heard of a Windows
tool that offered the flexibility and adaptability of gcc, gdb, make, 
shell and the zillion tools which - in accordance to the unix philosophy -
do only one thing but do that right.

> Evolution?  I agree that Unix has an admirable history.  Once upon a time
> it was the best thing around (well except for VMS :)  It is especially 
> loved by people who like to develop more Unix tools and gadgets.  But

That might be true but I like it for other reasons. One could get into
the usual stuff about stability scalability and things like that.
While I like the fact that I only turn off the machines when I do some
HW changes, the most appealing unix feature to me is ultimate flexibility.
One incarnation of this is the screen I look at day by day. It looks like
something *I* like, all the window decorations behave the way that's
convenient to *me*, and in general everything works the way *I* want them
to do. Now others using the system make everything according to their 
taste - all in all, everyone is different, why would the computer dictate
a human how to do things.
An other, more important materialisation of the flexibility I praise so 
much is that when I have a problem to solve I am not forced by the system
to take a path that was pre-defined by some system designer.
I can shape the solution by building it from small blocks and the solution
will fit the problem. I do not like trying to shape the problem until it 
fits one of solutions offered by the environment. 
I'm also kinda happy about that the Sun box that runs the P&R sits in the 
corner without a keyboard, mouse or display and I can work on it from the 
same screen what I use on the local machine. I don't have to care about
the P&R running on an other machine except that in a relevant rc file
I sticked "xon menyus" in front of the command. Remote execution, X,
NFS, NIS and all the others make it a rather transparent operation.
I've heard that that's not that easy under Windows - I might be mistaken.

> for doing other work, Windows is simply more useful.  While Unix has
> thousands of hackers controlling its evolution, Windows has millions
> of customers and billions of dollars.  It has the support of office
> users, game players, scientific users, hardware developers, multimedia
> developers, and millions of software developers, too.  I agree that
> evolution applies here, but it looks to me that natural selection
> favors Windows.  I don't like this any more than you do, but I've
> accepted it.  

Well, I do not accept it, not yet anyway. Windows have a hell of a lot
of development force and billions of dollars behind it, for sure. 
However, Windows still lacks quite a few things that unix can offer to me.
Those developers care much more about the home user than a designer for
home user is what most of those millions of Windows users are. 
Natural selection, in the long run, might favour Windows for home use.
For development work natural selection should favour the flexibility
and efficiency over the asthetics, I think, therefore either Windows
changes significantly or unix is here to stay. Wishful thinking :-)

> I haven't seen this.  Do you have an example?  Are they porting GNU tools
> to windows because it's a fun game, or are they really using it to develop
> application software.

I had the feeling that Perl was a popular tool in the Windows word. 
I don't have statistics to prove it, though. On the other hand, you 
can make a living from offering unix tools for Windows, the company 
MKS does that as far as I know. I heard that scripting under Windows is
a tad hard, that might be an other reason for unix tools.
GNU tools have advantages over commercial tools. One is that gcc behaves
the same regardless of the environment. If you wrote a C program that
compiles under gcc on some unix you then can compile it on Windows, 
assuming that it is not a unix-specific program. If you do embedded 
systems design, this might be important to you: if you use unix and 
your customer wants to do some SW work themselves and they run on 
Windows (or vica-versa), GNU tools ease the compatibility related 
pain a lot. 
All other GNU tools share that property, if you created a task-specific 
environment using those tools the whole environment will be operational 
on any platform which the GNU tools run. 
If you write software and you have a product that uses C as its 
intermediate language then if you want platform independence, you 
might require gcc - the customer *can* get it for free (actually, you can 
distribute it on your CD) and it will work on any platform, identically.
Gcc, by the way, has some very neat language extensions which you may 
want. There are also other useful things which depend on GNU tools, for 
example RTEMS (a free RT kernel).
Don't forget that GNU tools come with source. This allows you to massage 
them to your needs. This can come handy especially with GDB. You can add
new debug interfaces without waiting for a vendor to write them, you
can add special commands catering for the more arcane features of your
HW and so on.
Notable too that although all these tools cost you exactly nothing, you
get better free support on the net for them than what you would get from
a vendor for money.
In addition, I've heard that the porting is anything but fun ...

> > By the way, what do you exactly do with graphics packages when you 
> > design FPGAs ? 
> 
> Sometimes I have to document my work.  :)

I misunderstood you. *That* kind of graphics is certainly available 
under unix - the office packages come with it, you can have CorelDraw
or even a few free packages that offer fairly good graphics capabilities.
I thought that you were talking about image processing, raytracing 
animation packages and alike (of which some are available under unix 
but I will believe you if you say they're toys compared to the Windows 
ones).

> Usually I use them to analyze scientific data.
> I have a chip floorplanner that runs under microsoft Excel, although
> you'd be happy to hear that it also uses ~1000 lines of AWK code.

No, I won't be happy, really. I don't mind what you use, it's your call.
The fact that you use a unix tool indicates to me that you use Windows 
for something it was not designed for, namely development work. However,
this is not my problem - use whatever you like and can solve your 
problem. You have to work with it day by day, you have to feel happy 
about it.

I only want to have tools for unix (more specifically Linux) so that I
can do my work with a system *I* like and what can efficiently solve 
*my* problems, the way *I* prefer.

In the original article of yours you said that unix was an inferior
development platform. I argue with you to the extent of the absoluteness
of that statement. If you had said that it was inferior *for you*, I 
wouldn't have said a word.

However, when vendors (or their reps) say to me, with the same 
generalisation, that unix is crappy for FPGA work because Windows Word is
much nicer to use than TeX and everyone uses Windows 3.1 (then '95, then 
NT) *and* they only make Windows tools, now that pisses me off. 
Not that it counts, though.

Regards,

Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+


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