Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 17850

Article: 17850
Subject: JERC6k
From: Jose Antonio Moreno Zamora <jmorenoz@lslsun.epfl.ch>
Date: Mon, 13 Sep 1999 22:31:37 +0200
Links: << >>  << T >>  << A >>
I'm trying use the JERC in a machine with Solaris OS, the problem is
with Webscope, each time I try compile with java if find for
( libWebScope.so ). In the distribution of Jerc I have (09-21-1998) from

ftp://ftp.xilinx.com/pub/utilities/6200/, the only library for WebScope
is  a .DLL, and it also happens with others like:

Pci6200.dll       WebScope.dll      XC6200DLL.dll

How can I do it to use these libraries in my Sun workstation? Do I must
to recompile? How do I can do it?

It's very important for me, I have developed a reconfigurable tool for
6200 with Hotworks board.

Thank you, and sorry for my poor english.

Josan M. (jmorenoz@lslsun.epfl.ch)

Article: 17851
Subject: Re: A mix is best
From: Ray Andraka <randraka@ids.net>
Date: Mon, 13 Sep 1999 21:00:44 -0400
Links: << >>  << T >>  << A >>


vortekdoug@my-deja.com wrote:

> ....
> The FPGA can do things like the frequency counter
> easily.  The micro just reads it when interupted.
> There is almost no software overhead.
>

If you have a system clock other than the one you are measuring, you
don't need to do any interrupts.  The FPGA can keep the measured
frequency in a register that can be read by the processor at any time.
The register is just updated at whatever measurement interval is
convenient.  Uses two counters, a register and a little sync logic.  One
counter just sets the sample period in terms of the reference clock, the
other counts cycles of the measured clock in the sample period, The
register is loaded from the second counter and the second counter is
reset each each time the first counter cycles.  That way as soon as the
first measurement is completed, the register always has a valid
frequency measurement that is no older than the sample period.  The sync
logic just resyncs the terminal count from the first counter to the
measured clock to keep everything kosher.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17852
Subject: Re: Relative Location attribute
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Tue, 14 Sep 1999 03:07:46 GMT
Links: << >>  << T >>  << A >>
See also my May 1999 posting on this subject,
http://www.deja.com/getdoc.xp?AN=478287358&fmt=text.

Jan Gray



Article: 17853
Subject: Re: A mix is best
From: gregneff@my-deja.com
Date: Tue, 14 Sep 1999 04:40:48 GMT
Links: << >>  << T >>  << A >>
In article <7rj41c$nvo$1@nnrp1.deja.com>,
  vortekdoug@my-deja.com wrote:
> I have to agree with Jashua (Msg 9).
> You will never get a microcontroller that is the
> perfect fit.  I always need one more counter or
> PWM.
> The last system I did uses a 80C32 and a Xilinx
> 5202.  The 5202 has decode logic, PWM controls, an
> SPI port, and an application specific frequncy
> measurement circuit.
> The FPGA can do things like the frequency counter
> easily.  The micro just reads it when interupted.
> There is almost no software overhead.
> The flexibility is great.  I redid the SPI port in
> two days when anouther engineer put an oddball
> Burr Brown A/D onto the serial bus.  We did not
> have to redo boards, or change any parts.
> Here is the kicker: 80C32 => $1.60, XC5202 =>
> $7.50.  That is hard to beat for totally custom
> hardware.
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.
>

Just to add in my ten cents worth, the mix strategy works best for us.
We are involved in very fast time to market projects, so we need a mix
that will keep the schedule tight.  In general, we use a core
microcontroller (just the processor, not a lot of built-in I/O) with a
memory mapped interface to an FPGA.

The COTS microcontrollers are cheap and easy to get.  We don't have to
worry about synthesizing it and proving that it works, and we can plug
in logic analyzers and emulators into the sockets.

The FPGA is responsible for all I/O (with the exception of very big I/O
functions such as complex UARTs).  We even avoid using general purpose
I/O on the microcontroller.  We quickly lay down the first-pass guts of
the FPGA implementation, lock the pins, and go to art.  We can then
clean up the FPGA design and run simulations while the boards are being
designed and manufactured.

We pick an FPGA that is at least twice as big as we think we need, and
we make sure that the footprint will allow the next size up again, if
needed.  This is how we get away with locking the pins early.  Xilinx
SpartanXL parts are inexpensive enough that the wasted resources are
not a big deal.  If you are going to build zillions of your widgets,
then you can cost reduce it later.

Making changes to the design in the debug phase is easy, you change the
FPGA to fix I/O problems, and change the microcontroller code to fix
software problems.  And your customer is in awe when you deliver a
first pass prototype with no blue wires.

Using this strategy we have turned around designs (spec to prototype to
first production lot) in less than two weeks, including PCB design,
FPGA design, software, assembly, test, and documentation.

IMHO, the microcontroller/FPGA mix is the fastest and most cost-
effective path to market.


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17854
Subject: Re: PROBLEMS WITH ORCA
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Sep 1999 00:47:31 -0400
Links: << >>  << T >>  << A >>
"Josť Luis Ayala" wrote:
> 
>         Hi,
>         Anyone have any experience with FPGAs from Lucent (ORCA FPGA)?
> I have a problem with the mapping process because the ORCA's software
> clips and removes all my output ports, giving error messages like:
> '<output_register_name>/NEOBUF (NEOINV) undriven or does not drive
> anything', '<output_register_name>/NEOLATCH (NEOLATCH) undriven or does
> not drive anything', '<pad_name>.PAD (NEOPAD) undriven or does not drive
> anything'.
>         Thanks a lot
> 
> Jose Luis Ayala
> Electronic Engineering Department
> Technical University of Madrid
> Spain
> 
>  Sent via Deja.com http://www.deja.com/
>  Share what you know. Learn what you don't.

I am not an expert, but I might be able to help. But you will need to
provide a little more info. What are you using for design entry, an HDL
or schematic? If you think your IOs are being clipped, have you traced
the netlist back to see what step is clipping them? Is it possible that
your net list out of your front end tool is not really connecting the IO
port to the rest of the circuit?

The error messages you give indicate that perhaps the rest of the
circuit has been clipped. Or are those messages from the tool that is
clipping the unconnected elements?


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17855
Subject: Re: Virtex Interconnect
From: Ray Andraka <randraka@ids.net>
Date: Tue, 14 Sep 1999 01:10:46 -0400
Links: << >>  << T >>  << A >>
I don't know off the top of my head, but I can tell you where to look.
Go into the FPGA editor (the replacement for EPIC) in the xilinx 2.1
tools.  Select a virtex part and turn on all the graphics.  Click on
each node in the switchboxes and it will show you where they can
connect.  light lines are inputs to the node, heavy lines are outputs
from the node.

Vijay Lakamraju wrote:

> Hi Folks,
>    I am in search of some information regarding
> the local routing resources provided in the Virtex
> Architecture.
>    I am specifically referring to the connection
> pattern in the Local Interconnection Matrix (LIM).
> I know that the output multiplexer(OMUX) is fully
> populated (i.e any of the 13 CLB outputs can drive
> any of the eight output pins) but the input
> multiplexer(IMUX) is not (i.e. every CLB input pin
> CANNOT connect to every input signal of the IMUX).
> I was wondering if anyone had some information
> regarding the pattern in which the inputs to the IMUX
> are connected to the inputs of the CLB. I know of the
> pattern that is used in XC5200 but havent been able to
> find the information for Virtex.
>
> Please email or post any information or pointers u may have
> regarding the connection pattern of the IMUX in Virtex.
>
> Thanks in advance,
>
> Vijay
>
> --
> Architecture and Real-time Lab
> 310 Knowles Engg. Bldg.
> UMass, Amherst, MA  01003
> email: vlakamra@ecs.umass.edu



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17856
Subject: tools for static timing analysis with VITAL?
From: Scherer Anton <a.scherer@zma.ch>
Date: Tue, 14 Sep 1999 09:01:50 +0200
Links: << >>  << T >>  << A >>
We are at the very beginning of developing a design-kit for a
mixed-signal semicostum gate-array.

Are there any tools for static timing analysis with VITAL-libraries?
Have you ever written a VITAL library? 
Are threre any special points to consider? 

Best regards,
Anton
Article: 17857
Subject: Re: Foundation Express Map abnormal error
From: Leon Heller <leon_heller@hotmail.com>
Date: Tue, 14 Sep 1999 07:25:32 GMT
Links: << >>  << T >>  << A >>
In article <7rinas$sqa$1@news.qub.ac.uk>,
  "Khaled BENKRID" <kbenkrid@microsoft.com> wrote:
> Hi All,
>
> I am a Foundation Express 1.5i user. I had recently some
> problems with my Operating System (Windows 95), I was obliged to
> reinstall it again along with all the software I had on machine
> (including Foundation software). Now, I have a problem with
> Foundation software. When I implement my project, the
> translation phase goes fine, but as soon as the mapping phase
> starts, I get the following error:
>
> ********
> This program has performed an illegal operation and will be shut
> down. If the problem persists, contact the program vendor.
> ********
>
> The program terminates abnormally. What should I do?

Try the Xilinx web site. There are several hints about this type of
error. I had a problem with the mapping caused by a buggy Visual C DLL.
I copied another version of the DLL from another machine and everything
was fine.

Leon



--
Leon Heller, G1HSM
Tel (Mobile): 079 9098 1221 (Work): 01327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17858
Subject: Lowest power FPGA
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Tue, 14 Sep 1999 08:07:20 -0500
Links: << >>  << T >>  << A >>
Which manufacturers are presently claiming to be the lowest power?  I know
Quicklogic and Actel (and others) go back and forth about who is fastest.
But who is the lowest power (given identical clock rates, func, etc.)?

I know Phillips/Xilinx Coolrunner is low power, but those are mainly for
gate intensive designs.  My application is flip-flop intensive.

Thanks in advance,
Keith

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com


Article: 17859
Subject: Opinions Wanted
From: "Ray Almond" <raya@noral.co.uk>
Date: Tue, 14 Sep 1999 14:21:50 +0100
Links: << >>  << T >>  << A >>
Hi,
I'm throwing this problem out to a wider audience for opinions.
The following simple VHDL...
    T <= '0' when (D = '1' and B= '1') or (D = '0' and S = '1') else '1';
when compiled by Xilinx WebFitter (version W011) generates the following
gate level implementation (* = AND, + = OR, / = NOT)...
    T  =  D * /B + /D * /S    (Earth shattering stuff eh!)
The problem I'm having is in the form of a low going glitch on the T output
for a low to high change in the D input when both B and S are low.
I know this should not happen from the above VHDL. But due to timing or
threshold differences on the two D signal paths inside the physical part
(Xilinx 9500 series CPLD) I definitely get a low glitch on the output.
Needless to say, the original source statement simulates with out any
problems in Active-HDL for these input conditions (I would guess no
simulator would show up anything as it's an implementation problem).
I've reported the problem to Xilinx, but they insist the generated gate
level implementation is logically correct, hence no problem of theirs.
Opinions would be greatly appreciated,
Ray Almond.



Article: 17860
Subject: Re: Opinions Wanted
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Tue, 14 Sep 1999 10:30:00 -0500
Links: << >>  << T >>  << A >>
What you're describing is a common problem with combinatorial logic.  As the
signal propagates through the device (this will vary from device to device
or even FPGA layout to FPGA layout in the same device) signals will arrive
at the various gates at different times and cause states to change.

Any digital design circuit that cannot handle a glitch needs to be
"synchronized" with a flip-flop.  The signal is only valid on the clock edge
and can glitch any time it wants in between them.  This is where good,
synchronous design practices are required and should be used.

If you have questions regarding basic synchronous design, check out AMIs
website www.amis.com

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com
Ray Almond <raya@noral.co.uk> wrote in message
news:937316958.25401.0.nnrp-10.9e98661e@news.demon.co.uk...
> Hi,
> I'm throwing this problem out to a wider audience for opinions.
> The following simple VHDL...
>     T <= '0' when (D = '1' and B= '1') or (D = '0' and S = '1') else '1';
> when compiled by Xilinx WebFitter (version W011) generates the following
> gate level implementation (* = AND, + = OR, / = NOT)...
>     T  =  D * /B + /D * /S    (Earth shattering stuff eh!)
> The problem I'm having is in the form of a low going glitch on the T
output
> for a low to high change in the D input when both B and S are low.
> I know this should not happen from the above VHDL. But due to timing or
> threshold differences on the two D signal paths inside the physical part
> (Xilinx 9500 series CPLD) I definitely get a low glitch on the output.
> Needless to say, the original source statement simulates with out any
> problems in Active-HDL for these input conditions (I would guess no
> simulator would show up anything as it's an implementation problem).
> I've reported the problem to Xilinx, but they insist the generated gate
> level implementation is logically correct, hence no problem of theirs.
> Opinions would be greatly appreciated,
> Ray Almond.
>
>
>


Article: 17861
Subject: ACTEL Viewlogic Problem
From: "Ingo Purnhagen" <purnhagen@ohb-system.de>
Date: Tue, 14 Sep 1999 18:04:46 +0200
Links: << >>  << T >>  << A >>
Hi all,

to fix/define the ACTEL pinning already in ViewDraw the PIN Attribute on
signals can be used (PIN= [ACTEL_Pin_Nr.]).
It works on single signals but not on busses.
PIN=[x:z] or PIN= x,y,z does not work.

Thanx for solutions!




Article: 17862
Subject: free/demo/low cost verilog synthesis tools available?
From: dr0ne@my-deja.com
Date: Tue, 14 Sep 1999 17:09:51 GMT
Links: << >>  << T >>  << A >>



Hi,

I'm currently doing some HW/SW codesign with xilinx & altera fpga's and
I was wondering if there are such things as low cost/demo/free verilog
synthesis software available? I use synplify but I'd like to be able to
do some stuff from home, without having to *sell* my home in order to
afford these tools. I don't need anything really complicated at
all...just something that'll take simple behavioral/structural verilog
and download it into a xilinx or altera chip (via JTAG if possible). Do
any of the companies out there offer time or functionality limited
demos?



Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17863
Subject: PCI core for Orca 3T
From: Robert Sefton <rsefton@cosinecom.com>
Date: Tue, 14 Sep 1999 10:55:06 -0700
Links: << >>  << T >>  << A >>
Has anyone successfully ported a PCI core to the Lucent Orca 3T family?
If so, who was the core vendor? Also, how fast did you run it and what,
if any, major problems did you encounter?

Thanks,

-- 

--------------------------
--
-- Robert Sefton
-- Senior Design Engineer
--
-- CoSine Communications
-- 1200 Bridge Parkway
-- Redwood City, CA 94065
--
-- Direct: 650.637.2441
-- Main:   650.637.4777
-- Fax:    650.637.2412
--
--------------------------
Article: 17864
Subject: Re: Opinions Wanted
From: gd@nospam.heliontech.com (Graeme Durant)
Date: Tue, 14 Sep 1999 19:08:03 GMT
Links: << >>  << T >>  << A >>
On Tue, 14 Sep 1999 14:21:50 +0100, "Ray Almond" <raya@noral.co.uk>
wrote:

>Hi,
>I'm throwing this problem out to a wider audience for opinions.
>The following simple VHDL...
>    T <= '0' when (D = '1' and B= '1') or (D = '0' and S = '1') else '1';
>when compiled by Xilinx WebFitter (version W011) generates the following
>gate level implementation (* = AND, + = OR, / = NOT)...
>    T  =  D * /B + /D * /S    (Earth shattering stuff eh!)
>The problem I'm having is in the form of a low going glitch on the T output
>for a low to high change in the D input when both B and S are low.
>I know this should not happen from the above VHDL. But due to timing or
>threshold differences on the two D signal paths inside the physical part
>(Xilinx 9500 series CPLD) I definitely get a low glitch on the output.
>Needless to say, the original source statement simulates with out any
>problems in Active-HDL for these input conditions (I would guess no
>simulator would show up anything as it's an implementation problem).
>I've reported the problem to Xilinx, but they insist the generated gate
>level implementation is logically correct, hence no problem of theirs.
>Opinions would be greatly appreciated,
>Ray Almond.
>
>
>

Hi Ray,

This is a classic case of how combinatorial logic behaves in the real
world....the relative delays in different paths in the circuit are
somewhat unpredictable, as are exact switching thresholds etc. as you
state.  Hence, you get a different result to the ideal, as
demonstrated by your observations.

This is, as Xilinx suggest, not their problem (although I do hope they
were a bit more helpful than that!).  It is a case of adjusting your
implementation.  The usual way is to make your design synchronous to a
clock of some sort, so that glitches which occur during signal
transitions are ignored.

If you would like to discuss this further, please email me directly.

Best Regards

Graeme Durant
HELION Technology Limited, Cambridge, UK.
Xilinx Xpert Consultancy

mailto:gd@heliontech.com
Graeme Durant
HELION Technology Limited
Programmable Logic Design Specialists
The Granary, Home End, Fulbourn, Cambridge CB1 5BS, UK.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
mailto:gd@heliontech.com
http://www.heliontech.com

XILINX CERTIFIED GOLD LEVEL DESIGN CONSULTANT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 17865
Subject: Re: free/demo/low cost verilog synthesis tools available?
From: Ray Andraka <randraka@ids.net>
Date: Tue, 14 Sep 1999 15:12:56 -0400
Links: << >>  << T >>  << A >>
you can get a one-time 30 day eval license from both synplicity and
exemplar for their tools.

dr0ne@my-deja.com wrote:

> Hi,
>
> I'm currently doing some HW/SW codesign with xilinx & altera fpga's and
> I was wondering if there are such things as low cost/demo/free verilog
> synthesis software available? I use synplify but I'd like to be able to
> do some stuff from home, without having to *sell* my home in order to
> afford these tools. I don't need anything really complicated at
> all...just something that'll take simple behavioral/structural verilog
> and download it into a xilinx or altera chip (via JTAG if possible). Do
> any of the companies out there offer time or functionality limited
> demos?
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17866
Subject: Re: Opinions Wanted
From: muzo <muzok@nospam.pacbell.net>
Date: 14 Sep 1999 12:27:59 PDT
Links: << >>  << T >>  << A >>
"Ray Almond" <raya@noral.co.uk> wrote:
>I know this should not happen from the above VHDL. But due to timing or
>threshold differences on the two D signal paths inside the physical part
>(Xilinx 9500 series CPLD) I definitely get a low glitch on the output.

this is normal and expectable.

>Needless to say, the original source statement simulates with out any
>problems in Active-HDL for these input conditions (I would guess no
>simulator would show up anything as it's an implementation problem).

Because your description of the hardware is not accurate. If you get
delay information from P&R and annotate it to your gate level netlist,
you will see similar glitches at your simulator too.

>I've reported the problem to Xilinx, but they insist the generated gate
>level implementation is logically correct, hence no problem of theirs.

They are probably right.

>Opinions would be greatly appreciated,

Whether you need to fix this problem depends on your design. If the
circuit which takes T as input can live with these glitches of course
there is no problem. If not, you need to remove the glitch by waiting
enough time before looking at T so that all internal nodes have
stabilized. There are various ways of doing this, one of which is to
use a system wide clock, set the period to maximum of the said delays
and register all outputs. Of course such a design methodology can give
you big, power hungry designs but they are much easier to design.
muzo

Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)
Article: 17867
Subject: Re: ACTEL Viewlogic Problem
From: "Adam J. Elbirt" <aelbirt@nac.net>
Date: Tue, 14 Sep 1999 15:34:41 -0400
Links: << >>  << T >>  << A >>
As far as I know the only solution is to break the bus into individual pins.

Adam

Ingo Purnhagen wrote:

> Hi all,
>
> to fix/define the ACTEL pinning already in ViewDraw the PIN Attribute on
> signals can be used (PIN= [ACTEL_Pin_Nr.]).
> It works on single signals but not on busses.
> PIN=[x:z] or PIN= x,y,z does not work.
>
> Thanx for solutions!

--
"Sometimes I think the surest sign that there's intelligent life on
other planets is that none of it has tried to contact us."
                                      - Calvin, "Calvin and Hobbes"


Article: 17868
Subject: Re: synthesis comparion between Synplify and FPGA express
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Tue, 14 Sep 1999 20:12:17 GMT
Links: << >>  << T >>  << A >>
I'm just going to throw my 2 cents in here, but If you look on
Xilinx's IP web site, you'll see CAST offering something that "sounds"
like the small version of the Free-DES core. ie 16 clock cycles,
change keys every block. encode/decode...

The difference? It requires 255 slices vs the FREE-DES Synplify 731
slices and runs at over 100 MHz in a -6, instead of the 32.5 MHz of
the Synplified Free-DES core.

Now, as I'm a good British "Subject" I have not seen what the Free-DES
core contains but if we assume that they do both implement the same
basic functionality, we should not infer that the two benchmarked
synthesis tools are appalling, should we?

No. Instead we should perhaps assume that one designer has a more
"elegant" solution than the other and that one synthesis tool makes a
better job with a "less optimal" design than the other.

I wonder what synthesis tool the Xentec suppliers of the CAST core
used? :-)

Comments and thoughts welcome.

Cheers
Stuart


On 21 Aug 1999 19:21:29 PDT, muzok@nospam.pacbell.net (muzo) wrote:

>just check-out http://www.free-ip.com/DES/index.htm and look for the
>comparisons between Synplify and FPGA express.
>muzo
>
>Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)

For Email remove "NOSPAM" from the address
Article: 17869
Subject: simple VHDL?
From: leejp@my-deja.com
Date: Tue, 14 Sep 1999 20:44:23 GMT
Links: << >>  << T >>  << A >>
For years now, I have programmed simple PALs using the free PALASM
package from AMD (now Vantis).  While PALASM is still adequate for much
of the designs that I do (mostly 26V12, 22V10 and 16V8 designs), I
will be doing some bigger devices in the near future (small MACH devices
and such) and wish to start learning VHDL since it is more "industry
standard".

So I'm looking for a free (or low cost) VHDL package with a reasonable
learning curve that I can use to program simple PALs and small FPGA's.

Additionally, is there a book or manual that addresses such
applications?  Most VHDL stuff I've seen tend to concentrate heavily on
the software side.

Thanks,


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17870
Subject: Re: Lowest power FPGA
From: vortekdoug@my-deja.com
Date: Tue, 14 Sep 1999 22:47:58 GMT
Links: << >>  << T >>  << A >>
In article <DNrD3.6480$gW5.2061399@homer.alpha.net>,
  "Keith Jasinski, Jr." <jasinski@mortara.com> wrote:
> Which manufacturers are presently claiming to be the lowest power?  I
know
> Quicklogic and Actel (and others) go back and forth about who is
fastest.
> But who is the lowest power (given identical clock rates, func, etc.)?
>
> I know Phillips/Xilinx Coolrunner is low power, but those are mainly
for
> gate intensive designs.  My application is flip-flop intensive.
>
> Thanks in advance,
> Keith
>
> --
> Keith F. Jasinski, Jr.
> kfjasins@execpc.com
>
>
The lowest power I have found is the Xilinx 3000L series.
Be warned, the specs say they will run down to 3.0V.  At 3.0V there is
about a 10 to 15% fallout.
I'm not sure how much support Xilinx will give these parts in the
future.
I have similar requirements (low power, FF oriented).  If anybody has
information I would like to hear it too.


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17871
Subject: Re: free/demo/low cost verilog synthesis tools available?
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 14 Sep 1999 21:17:42 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E2AFE954D28AC04A55FCC37C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Xilinx has updated their free tools for CPLD design so that they support VHDL and Verilog.  They are at:

http://www.xilinx.com/sxpresso/webpack.htm

dr0ne@my-deja.com wrote:

> Hi,
>
> I'm currently doing some HW/SW codesign with xilinx & altera fpga's and
> I was wondering if there are such things as low cost/demo/free verilog
> synthesis software available? I use synplify but I'd like to be able to
> do some stuff from home, without having to *sell* my home in order to
> afford these tools. I don't need anything really complicated at
> all...just something that'll take simple behavioral/structural verilog
> and download it into a xilinx or altera chip (via JTAG if possible). Do
> any of the companies out there offer time or functionality limited
> demos?
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

--------------E2AFE954D28AC04A55FCC37C
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------E2AFE954D28AC04A55FCC37C--

Article: 17872
Subject: Re: simple VHDL?
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 14 Sep 1999 21:20:57 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------5F0551CE04D299486F535EAD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

You can try the Xilinx Student edition.  It has a lab book that shows how to use VHDL for CPLD and FPGA designs.  And it comes with the Xilinx and FPGA Express tools for VHDL, Verilog, ABEL, and schematic design.  You can see more about it at http://www.xess.com/prod011.html.

leejp@my-deja.com wrote:

> For years now, I have programmed simple PALs using the free PALASM
> package from AMD (now Vantis).  While PALASM is still adequate for much
> of the designs that I do (mostly 26V12, 22V10 and 16V8 designs), I
> will be doing some bigger devices in the near future (small MACH devices
> and such) and wish to start learning VHDL since it is more "industry
> standard".
>
> So I'm looking for a free (or low cost) VHDL package with a reasonable
> learning curve that I can use to program simple PALs and small FPGA's.
>
> Additionally, is there a book or manual that addresses such
> applications?  Most VHDL stuff I've seen tend to concentrate heavily on
> the software side.
>
> Thanks,
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

--------------5F0551CE04D299486F535EAD
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------5F0551CE04D299486F535EAD--

Article: 17873
Subject: Re: simple VHDL?
From: Wayne Miller <wayne@goodware.com>
Date: Tue, 14 Sep 1999 18:38:41 -0700
Links: << >>  << T >>  << A >>
Cypress (www.cypress.com)  has a VHDL/Verilog package for $99. I was
able to get a free copy from the local Cypress rep. It has a VHDL/Verilog
compiler, simulator, and a finite state machine editor.

I doubt it supports the MACH parts. I think the stuff that Cypress offers
is similar. A few months back when I was looking their parts seemed
pretty good. They have CPLDs, not really FPGAs. I really needed
FPGAs and decided on QuickLogic (and Verilog). I did use the Cypress
tools (mostly VHDL)  for a few weeks and they seemed to be good.

leejp@my-deja.com wrote:

> For years now, I have programmed simple PALs using the free PALASM
> package from AMD (now Vantis).  While PALASM is still adequate for much
> of the designs that I do (mostly 26V12, 22V10 and 16V8 designs), I
> will be doing some bigger devices in the near future (small MACH devices
> and such) and wish to start learning VHDL since it is more "industry
> standard".
>
> So I'm looking for a free (or low cost) VHDL package with a reasonable
> learning curve that I can use to program simple PALs and small FPGA's.
>
> Additionally, is there a book or manual that addresses such
> applications?  Most VHDL stuff I've seen tend to concentrate heavily on
> the software side.
>
> Thanks,
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

Article: 17874
Subject: Re: differences between ALTERA-XILINX
From: edick@hotmail.com (Richard Erlacher)
Date: Wed, 15 Sep 1999 04:46:46 GMT
Links: << >>  << T >>  << A >>
On Mon, 13 Sep 1999 10:53:40 GMT, Davide Rizzo <el.pa@libero.it>
wrote:

>My point of view:
>Altera have (had) a better development system, but xilinx chips are
>cheaper.
>Altera doesn't provide internal 3-state signals, and emulates them with
>logic (a lot of logic !).
>eng. Davide Rizzo
>
>Yannis Mitsos wrote:
>
>> I would like to know which are the major differences between the PLD's
>> of the above companies. I have worked with ALTERA FLEX series.
>>
>> Thanks
>>
>> Yannis
>
====================================================
I have some reseration about these unquantified statements where cost
is concerned.  For what ONE large XILINX FPGA costs, you can buy a
VERY well-equipped PC.  What I can't understand is that these $800-900
parts keep popping up in things costing much less than that.  Can
anyone explain that?

Dick




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search