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Messages from 18525

Article: 18525
Subject: Re: Duty-cycle change in Virtex
From: Guy Eschemann <Guy.Eschemann@insa-lyon.fr>
Date: Thu, 28 Oct 1999 21:34:39 +0100
Links: << >>  << T >>  << A >>
what frequency should the generated signal run at ?

omid@rocketmail.com a écrit :

> Hi;
>
> I would like to generate a signal with 3/4 period high and 1/4 period
> low.
>
> The clock runs at 80MHz.
> I tried to use 270 degree shift output of DLLs but still no luck.
> Any idea how may I implement that?
>
> Regards;
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- Guy ESCHEMANN ----------------------------------------------
INSA de Lyon  --  departement de Genie Electrique  --  5e Annee
Guy.Eschemann@insa-lyon.fr                         ICQ:32312501
http://gentserver.insa-lyon.fr/web/ge00/geschemann/public_html/
---------------------------------------------------------------


Article: 18526
Subject: Re: Comparison between Altera and Xilinx
From: Ray Andraka <randraka@ids.net>
Date: Thu, 28 Oct 1999 17:23:00 -0400
Links: << >>  << T >>  << A >>
Oops... I was about to yell back to say I didn't say altera was better in all
other apps, but reading my post that is what my fingers typed.  I would by no
means say that Altera is best for everything else---it just plain isn't.  Those of
you who know me know that what I meant to type was "For other applications, the
Altera is sometimes better".   Altera tends to do better at collecting "random"
logic, especially for the user who isn't willing to do placement.  (Again, this is
not meant to be a blanket statement by any means).  Xilinx is better in the vast
majority of datapath designs, and is a hands down winner in arithmetic designs or
designs requiring delay queues.  When it comes down to it, the best device depends
on the application, and might even include non-technical considerations such as
tools ownership, designer experience etc.

I should start proofreading my posts more, eh?

Philip Freidin wrote:

> In article <38186192.C5198DD1@ids.net>, Ray Andraka  <randraka@ids.net> wrote:
> >Big architectural differences.  Which is best depends on your
> >application.  For signal processing, Xilinx is a hands down winner.  For
> >other apps, the Altera is better.  Look for my previous posts on this
> >subject in deja-news for more details.
>
> OH! I dissagree! Xilinx is the hands down winner in far more applications
> than "just" signal processing.  :-)  Then again, you (or I) might say
> that all applications are "signal processing" of one type or another.
>
> Philip
>
> >
> >Child K.L. Sun wrote:
> >
> >>         Have you tried both of the chips/software from these two
> >>         companies?
> >>         What's the difference between them?
> >>
> >>                                                         Child
> >
> >
> >
> >--
> >-Ray Andraka, P.E.
> >President, the Andraka Consulting Group, Inc.
> >401/884-7930     Fax 401/884-7950
> >email randraka@ids.net
> >http://users.ids.net/~randraka
> >
> >



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18527
Subject: Re: FPGA
From: Ray Andraka <randraka@ids.net>
Date: Thu, 28 Oct 1999 17:26:00 -0400
Links: << >>  << T >>  << A >>
Good point.  In fact, I think there were a number of fault tolerant
design papers there last year.  I didn't make it this year due to a
combination of personal and business factors.  I think MAPLD might be a
better starting point for searching for papers - it's more recent and I
know at least at '98 there were a few of them.

rk wrote:

>  hi,
>
> you may also wish to take a look at mapld '99 which covers this topic
> ...
>
> ... from session d:
>
> http://rk.gsfc.nasa
> gov/richcontent/MAPLDCon99/ProgramSessions/Session_D.html
>
> Abstract:
> http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.pdf
> Abstract:
> http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.ps
> John Lach
> UCLA Electrical Engineering Department
> D3: "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA
> Architectures"
>
> Abstract:
> http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.pdf
> Abstract:
> http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.ps
> Abderrahim Doumar
> Graduate School of Science and Technology
> Chiba University
> D4: "Fault Tolerant FPGAs by Shifting the Configuration Data"
>
> hope this helps,
>
> rk
>
> ====================================================
>
> Ray Andraka wrote:
>
>> check IEEE and ACM conference proceedings - specifically look at
>> FCCM, FPGA,
>> RAW conferences.  THere are periodically papers on fault tolerant
>> FPGAs there.
>>
>> Andreas Kröpfl wrote:
>>
>> > HI
>> >
>> > This are  Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter
>> Leiler
>> > leiler@sbox.tu-graz.ac.at. We are diplomand students at the
>> technical
>> > university of Graz and search for literature concerning FPGAs
>> >
>> > Perhaps someone can help us in one of the following points.
>> > * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs
>> > * introducing material concerning the development of FPGA (
>> summaries about
>> > the work on FPGAs )
>> > * state-of-the-art articles ... a.s.o.
>> >
>> > It would rather be interesting to get more literature via email
>> (.doc, .ps,
>> > ..) , some other email-adresses from people, who are working on
>> the same
>> > topic. Finally some homepages for better understanding can be a
>> great help.
>> >
>> > Thank you for your help !
>> > Greatings from Graz
>> >
>> >
>> ------------------------------------------------------------------------
>>
>> > ------
>> > Dipl.-Ing. Andreas R. Kroepfl  - research assistent
>> > Institut f. Technische Informatik - TU Graz
>> > Inffeldg. 16/1
>> > 8010 Graz
>> > Austria
>> >
>> > Tel.Nr.: +43 +316 873 6411
>> > Fax.Nr.: +43 +316 873 6903
>> > E-Mail: kroepfl@i.am
>> > Homepage: http://kroepfl.i.am
>> >
>> ------------------------------------------------------------------------
>>
>> > ------
>> >
>> >
>> ------------------------------------------------------------------------
>>
>> > ------
>> > Dieter Leiler - diploma student
>> > Institut f. Technische Informatik - TU Graz
>> > Inffeldg. 16/1
>> > 8010 Graz
>> > Austria
>> >
>> > Tel.Nr.: +43 +316 873 6411
>> > Fax.Nr.: +43 +316 873 6903
>> > E-Mail: leiler@iti.tu-graz.ac.at
>> >
>> ------------------------------------------------------------------------
>>
>> > ------
>>
>> --
>> -Ray Andraka, P.E.
>> President, the Andraka Consulting Group, Inc.
>> 401/884-7930     Fax 401/884-7950
>> email randraka@ids.net
>> http://users.ids.net/~randraka
>
>



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18528
Subject: Re: Xilinx Orientation Question
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Thu, 28 Oct 1999 14:42:17 -0700
Links: << >>  << T >>  << A >>
also,

On the 4KXLA parts, there are eight global clock pins, two on each of the
four sides of the chip.  They can be used as global clocks (for the whole
chip) or as early clocks for the quadrant they're part of.  The ones on the
left and right are faster than the ones on the top and bottom.  What's
interesting is that the left and right ones feed the IOBs for the whole side
of the chip that the pin is on, as well as the closest top or bottom, but
the top and bottom ones only feed the IOBs for the quadrant they're in.

Also, one of the clocks (on the 4013XLA, at least) doubles as the
configuration data output pin, so you can't easily use it.

-a


Tom Burgess wrote in message <3810BF2B.365DD348@hia.nrc.ca>...
>Also, the tristate long lines run horizontally, favoring
>left and right edges for I/O to bussed internal registers.
>
>Ray Andraka wrote:
>>
>> It comes from the fact that the carry chains run vertically.  The data
busses
>> not only should be along the sides, but they should also be arranged so
that
>> the LSB is at the bottom.  The reason is to keep the routing as short and
>> simple as possible.


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.



Article: 18529
Subject: Re: FPGA Timing Problem
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Thu, 28 Oct 1999 14:58:27 -0700
Links: << >>  << T >>  << A >>
Ahren Hartman wrote in message <3813286A.B05B9AB9@shure.com>...
>Hi,
>
>I have a digital audio design that takes up about 60% of a Xilinx
>Spartan 30 chip (mixed schematic and VHDL) and I am having what I think
>are timing problems.
>
>I am processing digital audio from two different sources with two
>complete clock recovery and frame detection circuits and I am switching
>between the two sources depending on the relative error rates of each
>channel.
>
>The symptom is as follows - sometimes when I change a part of the design
>and re-compile and re-implement, the design doesn't work properly.
>Sometimes only one channel will work, and sometimes neither channel will
>work.  I can't seem to narrow the problem down to one specific area of
>the circuit. My suspicion is that I'm not properly constraining the
>design for the the right timing relationships.  I've put constraints on
>what I think are the most critical signals but I'm afraid I've not done
>enough.
>
>Does anyone have any suggestions of what might be causing this and what
>Xilinx tools I should be using to analyze the problem?  (I'm pretty much
>a novice at FPGA design so any thoughts will help...)

Are you doing a completely synchronous design?  I'm assuming that you're
dealing with AES/EBU-type digital-audio streams (or perhaps even simpler:
just data from an ADC) and it's the bit clock you're trying to recover.

Have you done a logic (pre-route) simulation of the design?  You need a good
VHDL simulator as well as the Xilinx gate-level simulator to do this.

How have you set up the timing constraints for the design?

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.



Article: 18530
Subject: Re: generating power on initialisation
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Thu, 28 Oct 1999 15:01:17 -0700
Links: << >>  << T >>  << A >>
Nicolas Matringe wrote in message <3815CF64.91EDB107@dotcom.fr>...
>Hi
>
>Xilinx 4000 parts have a power-on reset capability, I suppose the Virtex
>ones have it too.
>You have to instantiate the startup component:
>
>COMPONENT startup
>PORT(gsr : IN std_logic);
>END COMPONENT;
>...
>startup_inst : startup
>  PORT MAP(gsr => rst); -- where rst is your reset signal
>...
>
>(you might have to tell your synthesis tool not to remove this component
>with no output)
>This will automatically set or reset your design on power on.

Nicolas,

I think all of the current synthesis tools infer GSR if you hook all of your
flops to the same reset signal.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.



Article: 18531
Subject: Re: Hold times for Xilinx FPGAs
From: "peter dudley" <padudle@worldnet.att.net>
Date: Thu, 28 Oct 1999 17:40:40 -0600
Links: << >>  << T >>  << A >>
Occasionally there are times when you cannot register all inputs in IOB's.
By not using the IOB register you should be just about guaranteed of zero or
negative hold times relative to the clock input. I think the timing analyzer
is an easier way than simulation to verify timing. Go to filters and define
your sources and destinations and then go to custom under analyze.

Let us know if you are able to get the info you need that way.

    Pete


Rick Filipkiewicz <rick@algor.co.uk> wrote in message
news:38183AD4.613F15B2@algor.co.uk...
> Does anybody now how I can get the hold time requirement between an
> external pin and an internal Flip-Flop ?
> I want to make sure that my PCI logic meets the 0-hold-time requirement.
>
> For Virtex there are pin-to-pin values in the data sheet but they only
> apply to IOB FFs. As far as I can see the only way to check this is via
> a post-route simulation with a min delay SDF hacked to set the PCICLK
> delay to max.
>
> BTW: In the latest BitGen documentation it appears to be possible to put
> a delay on the GClks but your are told to do this only under
> instructions from Xilinx. Has anybody worked out how to use them ?
>


Article: 18532
Subject: Re: schematics ==> www
From: "peter dudley" <padudle@worldnet.att.net>
Date: Thu, 28 Oct 1999 17:48:09 -0600
Links: << >>  << T >>  << A >>
I vote for this approach. I print directly to pdf form WVO 7.53 and send
those files to my customers as documentation.

When you install adobe acrobat you'll get another printer in your printer
list that is the pdf writer.

One caution, if you use OATS be sure to print with OATS so that the
recipient can read the reference designators.

    Pete

Ray Andraka <randraka@ids.net> wrote in message
news:381862E8.88D5E597@ids.net...
> Rich,
>
> If you have WVO 7.5 and adobe acrobat exchange, you can print to the
acrobat
> distiller to get the schematics in pdf format.
>
> rk wrote:
>
> > hi,
> >
> > i wish to publish some schematics for people to view on the www.  before
> > i start on this project, i thought i'd solicit some suggestions.
> > currently i have a viewlogic license but haven't had the greatest luck
> > with doing much with that wrt sharing schematics; perhaps i need to
> > fiddle with it more.  i also have veribest but haven't really explored
> > that at all so perhaps someone with some experience has some ideas or
> > thoughts.
> >
> > i could do .hgl (hp graphics language) output but not sure how readable
> > that would be.  usually when i import an .hgl into word it makes a mess.
> >
> > likewise, printing to .pdf has been far from successful.
> >
> > so,
> >
> > what's a portable way to share schematics here, approaching 2000, in the
> > so-called information age? :-)
> >
> > suggestions?
> >
> > rk
>
>
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>


Article: 18533
Subject: Re: schematics ==> www
From: Ray Andraka <randraka@ids.net>
Date: Thu, 28 Oct 1999 20:48:42 -0400
Links: << >>  << T >>  << A >>


peter dudley wrote:

> I vote for this approach. I print directly to pdf form WVO 7.53 and send
> those files to my customers as documentation.
>
> When you install adobe acrobat you'll get another printer in your printer
> list that is the pdf writer.

I've had trouble with pdf writer with graphics, although I don't recall if I saw
the problems with output from wvo 7.54 or not.  I've just gotten in the habit of
printing to acrobat distiller (which is also installed when you install
acrobat), since it generally produces better results for documents that have
anything more than very simple graphics.  Adobe told me to do that a while back
when I ran into problems like that, and I think it is recommended as a solution
in their help files.

>
>
> One caution, if you use OATS be sure to print with OATS so that the
> recipient can read the reference designators.
>

Yup.  been there done that.

>     Pete
>
> Ray Andraka <randraka@ids.net> wrote in message
> news:381862E8.88D5E597@ids.net...
> > Rich,
> >
> > If you have WVO 7.5 and adobe acrobat exchange, you can print to the
> acrobat
> > distiller to get the schematics in pdf format.
> >
> > rk wrote:
> >
> > > hi,
> > >
> > > i wish to publish some schematics for people to view on the www.  before
> > > i start on this project, i thought i'd solicit some suggestions.
> > > currently i have a viewlogic license but haven't had the greatest luck
> > > with doing much with that wrt sharing schematics; perhaps i need to
> > > fiddle with it more.  i also have veribest but haven't really explored
> > > that at all so perhaps someone with some experience has some ideas or
> > > thoughts.
> > >
> > > i could do .hgl (hp graphics language) output but not sure how readable
> > > that would be.  usually when i import an .hgl into word it makes a mess.
> > >
> > > likewise, printing to .pdf has been far from successful.
> > >
> > > so,
> > >
> > > what's a portable way to share schematics here, approaching 2000, in the
> > > so-called information age? :-)
> > >
> > > suggestions?
> > >
> > > rk
> >
> >
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
> >
> >



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18534
Subject: Re: Hold times for Xilinx FPGAs
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Oct 1999 21:21:35 -0400
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
> Rickman wrote:rnal Flip-Flop ?
> 
> > If I can ask the obvious question, why don't you use the IOB FF so that
> > you know the hold time?
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> >
> 
> I found that when designing a PCI interface I couldn't get it going at the
> full burst rate of 1 word/clock unless I could feed the PCI control inputs
> direct from the pins into the master/target state machines. So the inputs go
> to more than 1 register bit.. Maybe I wasn't doing it right but if I
> registered all the inputs in the IOBs the fastest I could go was 1 every 2
> clocks without the state machines getting into a tangle of special cases.

Then can I say that the PCI signal is passing through combinatorial
logic before entering the FF? If so, I am pretty sure that the hold time
is no more than 0. As another poster stated, you can verify this by
static timing analysis in the timing analyzer. I have often done this
for special signal paths. I think you will find the logic timing path is
more than twice the delay through the clock distribution. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 18535
Subject: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
From: Alexander Krebs <krebs@eas.iis.fhg.de>
Date: Fri, 29 Oct 1999 08:29:09 +0200
Links: << >>  << T >>  << A >>
Joerg RiTTer wrote:
> in (VSS) release note (version 1998.08) you can find the following
> 
>      VHDL- Simulator : Compiled Mode
>      48202    Compiled Simulation needs twice as much time as
>      interpreted simulation
> 
> Maybe that was the reason.

Thanks for your response.

Maybe. However, I can't remember a Synopsys release without any VSS
STARS regarding the compiled mode. ;-)

Probably, only one of the Xilinx gurus - hi Peter Alfke, still
listening? - can give a definite answer.

Alex.
Article: 18536
Subject: Re: FPGA Timing Problem
From: Peter <"peterc"@hmgcc.gov.uk (Peter)>
Date: Fri, 29 Oct 1999 09:45:48 +0100
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> Ahren Hartman wrote in message <3813286A.B05B9AB9@shure.com>...
> >Hi,
> >

<snip>

> >The symptom is as follows - sometimes when I change a part of the design
> >and re-compile and re-implement, the design doesn't work properly.
> >Sometimes only one channel will work, and sometimes neither channel will
> >work.  I can't seem to narrow the problem down to one specific area of
> >the circuit. My suspicion is that I'm not properly constraining the
> >design for the the right timing relationships.  I've put constraints on
> >what I think are the most critical signals but I'm afraid I've not done
> >enough.

<snip>
> 
> How have you set up the timing constraints for the design?

Once you have timing constraints on there, check the coverage in the
timing report. For a fully synchronous design with all the clocks
constrained it's possible to get 90-95% coverage with little effort. If
you're a long way short of that then check why.

-- 
Peter Crighton
Article: 18537
Subject: DSP board for FPGA (I need general info)
From: project <projectdspNOprSPAM@yahoo.com.invalid>
Date: Fri, 29 Oct 1999 03:55:16 -0700
Links: << >>  << T >>  << A >>
Hi. I'm doing my final project (DSP board for FPGA).
Basically will be composed: Analog input --> FILTER (LP) ---
-> ADC (14 bits) ---> FPGA (DSP) (84 pins) ---> DAC (14
bits) ----> FILTER (reconstruction).
Where can I find simillar projects or ather information
about the hardware (Converters, filters, etc..) in internet?
Do you suggest me any book that can it help me?
Thank you.


* Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful
Article: 18538
Subject: Altera - how to make probe to a routed chip ?
From: dulik@my-deja.com
Date: Fri, 29 Oct 1999 13:47:16 GMT
Links: << >>  << T >>  << A >>
Hello,
 I'm a Xilinx user who just made his first (quite complex) design with
Altera. I have a problem with debugging it, because I miss the comfort
of EPIC chip editor in the Max+plus II (v. 9.3) software. So my
question is:
How to make a probe to a routed chip ? I mean:
How to put a signal from inside the chip to an unused I/O pin without
drawing it into the schematics and routing it all again (which takes
cca 20 min on Celeron 366MHz) ?

Thanks in advance,
Tomas Dulik


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18539
Subject: Problems with Xilinx CPLD's
From: Klaus Falser <kfalser@durst.it>
Date: Fri, 29 Oct 1999 15:42:51 GMT
Links: << >>  << T >>  << A >>
Hello,

Some time ago I asked if somebody too had problems with the Webpack
fitter tools from Xilinx.
Since nobody answered and Xilinx claims that Wabpack is identical to
there Foundation 2.1i tool, I would like to repeat my question for
Xilinx Foundation 2.1 too.

Did anybody else had problems when passing from Foundation 1.5 to
2.1 ?

I have more than one design which works when fitted with Webpack 1.5 ( =
Foundation 1.5), but does not when fitted with Webpack 2.1WP2.x (the
last !).

Today I had a design, which works only when the options "Local Feedback"
and "Pin Feedback" are switched off. With the old fitter I can compile
it with this features enabled.
If I turn on the "Pin Feedback", I get a not working Jedec file,
although there is no use of the feature in the design.
The reports are completely identical, except the lines with date and
options, but the programmed device does not work in one case.

Should be a software error, I think.

I reported my problems to Xilinx a long time ago, but there was no
reaction.

Best regards and thanks for any information
   Klaus

--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18540
Subject: Re: Altera - how to make probe to a routed chip ?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Fri, 29 Oct 1999 17:56:00 +0200
Links: << >>  << T >>  << A >>
Hi
As far as I know, you can't. For any change in the design (even the
smallest), you have to re-synthesize and p&r it.

dulik@my-deja.com wrote:
> 
> Hello,
>  I'm a Xilinx user who just made his first (quite complex) design with
> Altera. I have a problem with debugging it, because I miss the comfort
> of EPIC chip editor in the Max+plus II (v. 9.3) software. So my
> question is:
> How to make a probe to a routed chip ? I mean:
> How to put a signal from inside the chip to an unused I/O pin without
> drawing it into the schematics and routing it all again (which takes
> cca 20 min on Celeron 366MHz) ?
> 
> Thanks in advance,
> Tomas Dulik
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 18541
Subject: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
From: Brian Philofsky <brianp@xilinx.com>
Date: Fri, 29 Oct 1999 11:06:09 -0700
Links: << >>  << T >>  << A >>
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The reason Xilinx changed to interpretive compile mode verses the
C-compiled method was because several people were having trouble getting
the compiled method to work properly for many different reasons.  Some
of these reasons were that some C-compilers worked (compiled without
errors), others didn't.  Some versions of C-compiler worked some
didn't.  Different C compilers required different switches.  Some
C-compilers required certain libraries.  Solaris OS does not come with a
C compiler so some users didn't even have a compiler availible or setup
properly.  On top of all of the variables I have mentioned, Synopsys
does not have much for clear documentation on how to use the -c option
with vhdlan and various C-compilers (probably for the above reasons).
In short, it became a support burden to compile the libraries in his
method.

The interpetive compilation method is the tested, documented, and
suggested flow simply because people have fewer problems with this
method.  For smaller designs, there is little difference between the two
methods.  As designs get larger though, it can become considerably
slower (longer simulation times) since the compiled version runs in the
machine's native language.  That is the trade-off that was made,
ease-of-use  or simulation speed.  If you can successfully compile the
libraries and your design simulation netlist for that matter using the
-c option without errors or problems, then most likely you can
successfully use this option and will enjoy faster simulations as the
benefit.  I have done successful simulations using Sparcworks C-compiler
for the libs and netlists before and simulation was speed up by using
it.  I have heard gcc works as well however have not tried it myself.
The risk you run though by doing this is that it is not a tested or
supported flow by Xilinx so if you do run into errors/problems Xilinx is
limited in what it can do and will probably advise you to go back to
interpretive compilation.

Hopefully that answers your question,


--  Brian Philofsky
     Xilinx Design Engineer





Alexander Krebs wrote:

> Joerg RiTTer wrote:
> > in (VSS) release note (version 1998.08) you can find the following
> >
> >      VHDL- Simulator : Compiled Mode
> >      48202    Compiled Simulation needs twice as much time as
> >      interpreted simulation
> >
> > Maybe that was the reason.
>
> Thanks for your response.
>
> Maybe. However, I can't remember a Synopsys release without any VSS
> STARS regarding the compiled mode. ;-)
>
> Probably, only one of the Xilinx gurus - hi Peter Alfke, still
> listening? - can give a definite answer.
>
> Alex.

--
-------------------------------------------------------------------
 / 7\'7 Brian Philofsky   (brian.philofsky@xilinx.com)
 \ \ `  Xilinx Design Engineer                   hotline@xilinx.com
 / /    2100 Logic Drive                         1-800-255-7778
 \_\/.\ San Jose, California 95124-3450          1-408-879-5199
-------------------------------------------------------------------



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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<p>The reason Xilinx changed to interpretive compile mode verses the C-compiled
method was because several people were having trouble getting the compiled
method to work properly for many different reasons.&nbsp; Some of these
reasons were that some C-compilers worked (compiled without errors), others
didn't.&nbsp; Some versions of C-compiler worked some didn't.&nbsp; Different
C compilers required different switches.&nbsp; Some C-compilers required
certain libraries.&nbsp; Solaris OS does not come with a C compiler so
some users didn't even have a compiler availible or setup properly.&nbsp;
On top of all of the variables I have mentioned, Synopsys does not have
much for clear documentation on how to use the -c option with vhdlan and
various C-compilers (probably for the above reasons).&nbsp; In short, it
became a support burden to compile the libraries in his method.
<p>The interpetive compilation method is the tested, documented, and suggested
flow simply because people have fewer problems with this method.&nbsp;
For smaller designs, there is little difference between the two methods.&nbsp;
As designs get larger though, it can become considerably slower (longer
simulation times) since the compiled version runs in the machine's native
language.&nbsp; That is the trade-off that was made, ease-of-use&nbsp;
or simulation speed.&nbsp; If you can successfully compile the libraries
and your design simulation netlist for that matter using the -c option
without errors or problems, then most likely you can successfully use this
option and will enjoy faster simulations as the benefit.&nbsp; I have done
successful simulations using Sparcworks C-compiler for the libs and netlists
before and simulation was speed up by using it.&nbsp; I have heard gcc
works as well however have not tried it myself.&nbsp; The risk you run
though by doing this is that it is not a tested or supported flow by Xilinx
so if you do run into errors/problems Xilinx is limited in what it can
do and will probably advise you to go back to interpretive compilation.
<p>Hopefully that answers your question,
<br>&nbsp;
<p>--&nbsp; Brian Philofsky
<br>&nbsp;&nbsp;&nbsp;&nbsp; Xilinx Design Engineer
<br>&nbsp;
<br>&nbsp;
<br>&nbsp;
<br>&nbsp;
<p>Alexander Krebs wrote:
<blockquote TYPE=CITE>Joerg RiTTer wrote:
<br>> in (VSS) release note (version 1998.08) you can find the following
<br>>
<br>>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VHDL- Simulator : Compiled Mode
<br>>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 48202&nbsp;&nbsp;&nbsp; Compiled Simulation
needs twice as much time as
<br>>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; interpreted simulation
<br>>
<br>> Maybe that was the reason.
<p>Thanks for your response.
<p>Maybe. However, I can't remember a Synopsys release without any VSS
<br>STARS regarding the compiled mode. ;-)
<p>Probably, only one of the Xilinx gurus - hi Peter Alfke, still
<br>listening? - can give a definite answer.
<p>Alex.</blockquote>

<pre>--&nbsp;
-------------------------------------------------------------------
&nbsp;/ 7\'7 Brian Philofsky&nbsp;&nbsp; (brian.philofsky@xilinx.com)
&nbsp;\ \ `&nbsp; Xilinx Design Engineer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; hotline@xilinx.com
&nbsp;/ /&nbsp;&nbsp;&nbsp; 2100 Logic Drive&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-800-255-7778&nbsp;
&nbsp;\_\/.\ San Jose, California 95124-3450&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-408-879-5199&nbsp;
-------------------------------------------------------------------</pre>
&nbsp;</html>

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title:<H3 ALIGN="CENTER"><img src="http://bennyhills.fortunecity.com/deadparrot/108/homer.gif" alt="Homer" align="center"> Design Engineer 
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--------------925F5E4A9CD899BAF34837F4--

Article: 18542
Subject: opencores.org announcement
From: "Damjan Lampret" <damjan.lampret@arnes.si>
Date: Fri, 29 Oct 1999 21:08:09 +0200
Links: << >>  << T >>  << A >>
Hello all,

I would like to announce OPENCORES.ORG. Check out our mission statement at
our web site at http://www.opencores.org for more information. Here are our
goals in just a short summary:

* to develop set of basic open source sythesizeable IP cores
(microprocessor, system controllers, general peripheral cores and
communication cores)
* to build a prototype computer system based on these cores using
reprogrammable ASICs (more commonly referred as FPGAs). The computer will
run Linux and RT eCos operating systems.
* to build a semicustom ASIC(s) (standard cell ASICs) computer system as a
SoC (system-on-a-chip) design. We hope to use .25 micron 3LM or .18 micron
3LM process.
* to develop open source development environment (not just mailing lists,
but a complete development environment starting from CVS managed multi
developer environment to web based VHDL/Verilog HDL design entry, web based
synthesis, placement & routing and finally web based verification and
debugging using our development boards with multi-million gates FPGAs
REMOTELY.)

Current status:

* we are working on a 32-bit RISC microprocessor, 32/64-bit PCI controller
and 16550 compatible UART
* we are working on two prototype boards. One simple board with 100k gates
Xilinx Virtex which was just finished and another PCI board with two bigger
FPGAs and with additional capabilities (video, ethernet, serial, EIDE ports
etc).
* we have a list of IP cores we would like to develop (help us !)
* we have raised funds in amount of US $5,000
* we have the latest tools for VHDL synthesis, simulation, and FPGA
Placement & routing
* we have working GNU C cross compiler for OpenRISC 1000 (our first 32-bit
RISC architecture) and working architectural simulator of OR1K (which also
supportx DLX though DLX is a lot different than our OR1K architecture)
* we have ideas for totally radical, new 64-bit RISC architecture (F-CPU is
traditional superpipelined superscalar 64-bit RISC, Intel IA-64 (EPIC) is
quite different (and will outperform F-CPU ;-), our OR2K is way different
than both mentioned architectures and will outperform both)
* we have generated a lot of interest at some Slovenian companies and at
university of Ljubljana, Faculty of Electrical Engineering. We are now
discussing if they could help us with funds, EDA tools, semicustom ASIC cell
libraries etc.

What we need:

* we need people with great ideas
* we need VHDL/Verilog HDL coders
* we need people with ASIC experience (semi & full-custom, reprogrammable
etc)
* we need companies to sponsor our activities (for example with with EDA
tools, semicustom libraries, funds etc.)

Please visit our web site at http://www.opencores.org and join our mailing
lists.

kinds regards,

Damjan Lampret
OPENCORES.ORG




Article: 18543
Subject: Re: Hold times for Xilinx FPGAs
From: Hernan Saab <hernan@synplicity.com>
Date: Fri, 29 Oct 1999 15:12:33 -0700
Links: << >>  << T >>  << A >>
Hello Peter,


I dont know that using an internal register will elliminate the possibility
of having hold time violation.  The reason is that data going into an IOB flip
flop will have a delay element added to it.  Signals that skip the IOB dff will
not use the delay element (unless you set it manually).
As a consequence, you may have a hold time violation if you use an internal
dff!!  Of course, if you manually add the delay element you will have a
guaranteed negative hold time.




peter dudley wrote:

> Occasionally there are times when you cannot register all inputs in IOB's.
> By not using the IOB register you should be just about guaranteed of zero or
> negative hold times relative to the clock input. I think the timing analyzer
> is an easier way than simulation to verify timing. Go to filters and define
> your sources and destinations and then go to custom under analyze.
>
> Let us know if you are able to get the info you need that way.
>
>     Pete
>
> Rick Filipkiewicz <rick@algor.co.uk> wrote in message
> news:38183AD4.613F15B2@algor.co.uk...
> > Does anybody now how I can get the hold time requirement between an
> > external pin and an internal Flip-Flop ?
> > I want to make sure that my PCI logic meets the 0-hold-time requirement.
> >
> > For Virtex there are pin-to-pin values in the data sheet but they only
> > apply to IOB FFs. As far as I can see the only way to check this is via
> > a post-route simulation with a min delay SDF hacked to set the PCICLK
> > delay to max.
> >
> > BTW: In the latest BitGen documentation it appears to be possible to put
> > a delay on the GClks but your are told to do this only under
> > instructions from Xilinx. Has anybody worked out how to use them ?
> >

--



Hernan Javier Saab
Western Area Applications Engineer
Email: HERNAN@synplicity.com
Direct Phone: 408-215-6139
Main Phone: 408-215-6000
Pager: 888-712-5803
FAX: 408-990-0295
Synplicity, Inc.
935 Stewart Drive
Sunnyvale, CA  94086  USA
Internet <http://www.synplicity.com >


Article: 18544
Subject: Xilinx TPSYNC constraint
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Fri, 29 Oct 1999 16:56:14 -0700
Links: << >>  << T >>  << A >>
I'm using an XC4KE part, I have a 32-bit bidirectional bus that comes out to
the pins and I'd like to constrain the tristate enable so that it's faster.

There's a constraint called TPSYNC, which "allows defintion of synchronous
points that are <i>not</i> FFS, RAMS, PADS or LATCHES" and they are
"commonly used with three-state buffers."

The example given in the Xilinx "timing and constraints" presentation is a
bit weak.   I have a signal called dataoe, which is a flip-flop output, and
that signal is used as the tri-state enable for the outputs, which are
called ramdata[31:0].  Any hints as to how to write this constraint?  Assume
that I want to constrain it to be 10 ns.

thanx,

a

--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.


Article: 18545
Subject: need reference to first paper on FPGA
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 29 Oct 1999 17:10:59 -0700
Links: << >>  << T >>  << A >>
Dear all,

does anyone have the reference to the paper where the FPGA
was first introduced?

Thanks in advance,

-Arrigo
--
Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	  			phone: (626) 395-3695
Pasadena, CA 91125	  			fax:   (626) 795-8649

Article: 18546
Subject: StateCAD versus Viewdraw
From: James Yeh <jiahau@uclink4.berkeley.edu>
Date: Fri, 29 Oct 1999 17:22:47 -0700
Links: << >>  << T >>  << A >>
I was wondering if somebody could tell me the trade offs of using one
over the other.

I have a design in Viewdraw currently (a SDRAM controller with a fairly
complex FSM, which I have implemented by hand).

The issues I have are

a)  I'm positive that StateCAD will do a better job in optimizing my FSM
(speed or space) and I know I can put gates and components down from the
Xilinx library.  But what about its simulation environment?  I
incorporate a Micron VHDL model in my viewdraw design for simulation,
and I was wondering if StateCAD does a good job of taking VHDL and
allowing it to interact with real Schematics.

b)  I was wondering if there were a lot of people who used StateCAD
because, granted I've only been doing stuff with FPGA's for about a
year, I just don't hear that much about the software (that actually
could be a good thing :) )

c)  Reliability.  I have Service Pack 5, and well Viewdraw and what not
is not the most stable software in the world, and was wondering if
Statecad was any better at not crashing (I'm guessing not...blame it all
on Bill anyway.....).
Article: 18547
Subject: Re: StateCAD versus Viewdraw
From: Ray Andraka <randraka@ids.net>
Date: Fri, 29 Oct 1999 21:05:07 -0400
Links: << >>  << T >>  << A >>
First, I don't use state cad, but then the state machines in my designs are
usually pretty simple.  For one-hot machines in schematics I've developed a
set of wrappers that makes the state machine look like a flow chart so it is
easy to understand, enter, and maintain.  I'm not sure a lack of hearsay on
statecad is necessarily good - could just be because no one is using it.

I've had virtually no problem with WVO 7.5.  It seems very stable and I
don't recall it ever crashing my NT box.  MS Office is another story
though.  I had seen lots of problems with earlier versions of WVO, but they
seem to be pretty well fixed.  I did have a problem with it not being
compatible with the latest sentinal driver, but viewlogic tech support
helped me around that.

James Yeh wrote:

> I was wondering if somebody could tell me the trade offs of using one
> over the other.
>
> I have a design in Viewdraw currently (a SDRAM controller with a fairly
> complex FSM, which I have implemented by hand).
>
> The issues I have are
>
> a)  I'm positive that StateCAD will do a better job in optimizing my FSM
> (speed or space) and I know I can put gates and components down from the
> Xilinx library.  But what about its simulation environment?  I
> incorporate a Micron VHDL model in my viewdraw design for simulation,
> and I was wondering if StateCAD does a good job of taking VHDL and
> allowing it to interact with real Schematics.
>
> b)  I was wondering if there were a lot of people who used StateCAD
> because, granted I've only been doing stuff with FPGA's for about a
> year, I just don't hear that much about the software (that actually
> could be a good thing :) )
>
> c)  Reliability.  I have Service Pack 5, and well Viewdraw and what not
> is not the most stable software in the world, and was wondering if
> Statecad was any better at not crashing (I'm guessing not...blame it all
> on Bill anyway.....).



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18548
Subject: Re: StateCAD versus Viewdraw
From: "Austin Franklin" <austin@darkroom0.com>
Date: 30 Oct 1999 01:26:31 GMT
Links: << >>  << T >>  << A >>
> I have a design in Viewdraw currently (a SDRAM controller with a fairly
> complex FSM, which I have implemented by hand).
> 
> The issues I have are
> 
> a)  I'm positive that StateCAD will do a better job in optimizing my FSM
> (speed or space) and I know I can put gates and components down from the
> Xilinx library.

I completely disagree with that.  At best, it can do an equal job,
depending on how good or bad your implementation is.  If you are good at
logic design, you should be able to do the absolute optimal design for both
speed and area using schematics.  Schematics give you absolutely the best
control you can get.

> But what about its simulation environment?  I
> incorporate a Micron VHDL model in my viewdraw design for simulation,
> and I was wondering if StateCAD does a good job of taking VHDL and
> allowing it to interact with real Schematics.

I have StateCAD integrated with Viewlogic.  I use either ViewSim or VCS for
simulation.  If you have a .vli file, or a schematic, you can just
instantiate it as a symbol on the schematic (with the correct attributes).

> b)  I was wondering if there were a lot of people who used StateCAD
> because, granted I've only been doing stuff with FPGA's for about a
> year, I just don't hear that much about the software (that actually
> could be a good thing :) )

I use it, it's OK.
 
> c)  Reliability.  I have Service Pack 5, and well Viewdraw and what not
> is not the most stable software in the world, 

I have never had any stability problems with any Viewlogic tools.  I use
7.53.

Another method I use is to do my state machines in Abel, and have it output
the optimized equations, and then I implement the equations in schematics,
and hand map/optimize them that way.  It works GREAT!  Not the fastest
design methodology to implement, but I get the most optimized results I
have been able to come up with, so for high speed designs, it saves me time
in the long run.

Article: 18549
Subject: Re: StateCAD versus Viewdraw
From: James Yeh <jiahau@pacbell.net>
Date: Sat, 30 Oct 1999 01:15:27 -0700
Links: << >>  << T >>  << A >>
Thanks.

Austin Franklin wrote:

> > I have a design in Viewdraw currently (a SDRAM controller with a fairly
> > complex FSM, which I have implemented by hand).
> >
> > The issues I have are
> >
> > a)  I'm positive that StateCAD will do a better job in optimizing my FSM
> > (speed or space) and I know I can put gates and components down from the
> > Xilinx library.
>
> I completely disagree with that.  At best, it can do an equal job,
> depending on how good or bad your implementation is.  If you are good at
> logic design, you should be able to do the absolute optimal design for both
> speed and area using schematics.  Schematics give you absolutely the best
> control you can get.
>
> > But what about its simulation environment?  I
> > incorporate a Micron VHDL model in my viewdraw design for simulation,
> > and I was wondering if StateCAD does a good job of taking VHDL and
> > allowing it to interact with real Schematics.
>
> I have StateCAD integrated with Viewlogic.  I use either ViewSim or VCS for
> simulation.  If you have a .vli file, or a schematic, you can just
> instantiate it as a symbol on the schematic (with the correct attributes).
>
> > b)  I was wondering if there were a lot of people who used StateCAD
> > because, granted I've only been doing stuff with FPGA's for about a
> > year, I just don't hear that much about the software (that actually
> > could be a good thing :) )
>
> I use it, it's OK.
>
> > c)  Reliability.  I have Service Pack 5, and well Viewdraw and what not
> > is not the most stable software in the world,
>
> I have never had any stability problems with any Viewlogic tools.  I use
> 7.53.
>
> Another method I use is to do my state machines in Abel, and have it output
> the optimized equations, and then I implement the equations in schematics,
> and hand map/optimize them that way.  It works GREAT!  Not the fastest
> design methodology to implement, but I get the most optimized results I
> have been able to come up with, so for high speed designs, it saves me time
> in the long run.



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