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Messages from 21250

Article: 21250
Subject: Re: DSP with FPGA
From: Ray Andraka <randraka@ids.net>
Date: Tue, 14 Mar 2000 02:51:08 GMT
Links: << >>  << T >>  << A >>
DSP is Digital Signal Processing or Processor.  Usually people automatically
jump to thinking a DSP microprocessor, which is a microprocessor whose
instruction set and bus architecture are optimized somewhat for signal
processing applications.  These generally have a single cycle multiply as well
as efficient looping constructs to streamline inner loops and often special
addressing modes.  Digital signal processing really encompasses much more
hardware than the traditional DSP microprocessor.  By using special purpose
(custom) hardware, you can get much higher data rates than a microprocessor is
capable of.  That's what I do with FPGAs.  DSP microprocessors are every
where....modems, graphics cards, sound cards, cell phones, CD players, disk
drives and so on.

"Jean-Réginald Louis" wrote:

> Excuse me! I didn't have a clear idea of what it's a DSP. In my course, I'm
> learning microcontroller. I have friends studying telecom (college level)
> and they using DSP to manipulate signal (like sound) and I automatically
> made an association between telecom and DSP.
>
> Can someone tell me the difference between a MCU (microcontroller), a DSP
> and a CPU. What type of processing unit are use in what type of
> project/environement/situation/etc ? Why a graphics card use a DSP (like the
> nVidia GeForce (if I'm not wrong)) ?
>
> > Hi!
> >
> > DSP is *Digital* signal processor or processing.
> >
> > You can not handle analog data in with an FPGA, you first have to
> > convert the analog signal to a digital signal and then process it.
> >
> > / Jonas
> >
> > On Mon, 13 Mar 2000 00:15:14 -0500, "Jean-Réginald Louis"
> > <louis.reginaldjean@teccart.qc.ca> wrote:
> >
> > >Hi. I'm new to this field. I have a good idea of what we can do with FPGA
> > >but I saw something that I can understand. I found a companie (in the
> Web)
> > >that do DSP with FPGA. If I'm not wrong DSP are like MCU, but
> specifically
> > >designed to handle analog data. So how can we handle analog data in FPGA
> > >pins. What's worst, I saw (in the same compagny) "Modulation and
> > >demodulation with FPGA". How can we do this?
> > >
> > >
> > >
> >
>
> > Hi!
> >
> > DSP is *Digital* signal processor or processing.
> >
> > You can not handle analog data in with an FPGA, you first have to
> > convert the analog signal to a digital signal and then process it.
> >
> > / Jonas
> >
> > On Mon, 13 Mar 2000 00:15:14 -0500, "Jean-Réginald Louis"
> > <louis.reginaldjean@teccart.qc.ca> wrote:
> >
> > >Hi. I'm new to this field. I have a good idea of what we can do with FPGA
> > >but I saw something that I can understand. I found a companie (in the
> Web)
> > >that do DSP with FPGA. If I'm not wrong DSP are like MCU, but
> specifically
> > >designed to handle analog data. So how can we handle analog data in FPGA
> > >pins. What's worst, I saw (in the same compagny) "Modulation and
> > >demodulation with FPGA". How can we do this?
> > >
> > >
> > >
> >

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21251
Subject: Survey on computer/electrical engineering – free book
From: editor@mail.booksonline.com
Date: Tue, 14 Mar 2000 05:50:23 GMT
Links: << >>  << T >>  << A >>
Kindly accept an invitation to participate in a survey about your
interest in and use of books on computer and electrical engineering.
Participating will involve spending about twenty to thirty minutes
taking an online survey. You'll need to answer a few qualifying
questions first. If you qualify and complete the survey, we will reward
you with your choice from a selection of books on computer and
electrical engineering. If you are interested, please click here
http://survey.informative.com/sb/survey?s=62000&hdr=1&xu=NGCAF
Thank you for your time and interest.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21252
Subject: Virtex IOB T register
From: bfredc@my-deja.com
Date: Tue, 14 Mar 2000 11:02:44 GMT
Links: << >>  << T >>  << A >>
Hi.

Would anyone know how can I use the T flip-flop
of an IOB in VIRTEX devices ?
Records #6214 and #7290 in the Xilinx Answers
Database don't fix my problem.


Thanks in advance to all who can help.

 Fred
Laboratoire Signaux et Système du CNAM PARIS



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21253
Subject: Is there a chance to synthesize that?
From: Guido Pohl <pohl@fokus.gmd.de>
Date: Tue, 14 Mar 2000 12:31:29 +0100
Links: << >>  << T >>  << A >>
Hallo and a Good Day,

I have the following solution (?) for a problem, but I cannot estimate its
implications.

Ok, there is a registered signal "withinReadCycle" that is asserted at the start
of a read cycle , i.e. by a certain condition (see below "condition1")
sunchronously to clock edge. The signal should be left asserted as long as
another condition ("condition2") does not occure. But when the condition occures
I would like to de-assert the signal "withinReadCycle" as quick as possible,
that is I don't want to wait for the rising clock edge - which certainly means
that I asynchronously de-assert that signal.

I would code that as follows in VHDL:


    read_regs: PROCESS (CLKxCI, RSTxRLI)
    BEGIN  -- PROCESS read_regs
        IF RSTxRLI = '0' THEN               -- asynchronous reset (active low)
            withinReadCycle <= '0';

        ELSIF (condition2 = '1') THEN
            withinReadCycle <= '0';
            
        ELSIF CLKxCI'event AND CLKxCI = '1' THEN  -- rising clock edge
            
            IF ( condition1 = '1' OR withinReadCycle = '1' ) THEN
		
		withinReadCycle = '1';
		bla;

            ELSIF ( condition1 = '0' ) THEN

                withinReadCycle <= '0';

	    END IF;

	END IF;
    END PROCESS read_regs;



And now, my questions:

(1) Is there a chance to be able to synthesize that code?
(2) The device for which to synthesize must have a product-term-driven reset,
right?
(3) In case that (1) can be answered with yes, would there be success for a
Xilinx4036?


I would appreciate any hint or comment and ...
.. thank, you so far


Guido
Article: 21254
Subject: Pb with Coregen in F2.1i
From: Steven Derrien <sderrien@irisa.fr>
Date: Tue, 14 Mar 2000 13:20:41 +0100
Links: << >>  << T >>  << A >>
I try to generate a pipelined multiplier, but have the following error,
any idea of the problem ?

ERROR: An internal error has occurred.  Please call Xilinx support.
ERROR: Sim has a problem implementing the selected core. Implementation
netlist will not be generated.
ERROR: SimGenerator: Failure of Sim to implement customization
parameters core mul16
WARNING: Core mul16 did not generate product ImpNetlist.
WARNING: Warnings and/or errors encountered while generating mul16
(Variable_Parallel_Multiplier 1.0) All output products requested may not
have been generated.

Thanks,

Steven

Article: 21255
Subject: Where've Xilinx hidden it then?
From: Sprow <rps102@york.ac.uk>
Date: Tue, 14 Mar 2000 12:52:49 +0000
Links: << >>  << T >>  << A >>

To save the bother of installing the whole M1.5 series CDs again does
anyone know which archive the 4020XL series of device personalities is
held in,or even better,where I can get those mischievous 5 files from?

Thanks in advance,
Robert. 

Article: 21256
Subject: JTAG by parallel port
From: mark_harvey@my-deja.com
Date: Tue, 14 Mar 2000 13:47:48 GMT
Links: << >>  << T >>  << A >>
Has anyone ever tried to program a JTAG device (eg XC9500) using the PC
parallel port directly connected to the JTAG pins? Got links to software
routines?

thanks,
MH.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21257
Subject: Can we read bits from a file in PCc using Altera or Xilinx ?
From: "Avinash Maddy" <maddy@eng.fsu.edu>
Date: Tue, 14 Mar 2000 10:36:28 -0500
Links: << >>  << T >>  << A >>
Can any one tell me how to write a VHDL code to read bits (1s and 0s) from a
file on the PC and another VHDL code to write output bits to a file on the
PC?
I am using both Altera and Xilinx platforms. Is it actually possible on
these platforms ?
Thanks in advance,
Avinash Maddy
maddy@eng.fsu.edu


Article: 21258
Subject: Re: JTAG by parallel port
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 14 Mar 2000 10:44:00 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------536BEF03B9142CF0CD7A4F0F
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

All our XS Boards use the parallel port for programming, including the XC9500-based boards which use JTAG.  We have our low-level programming routines at http://www.xess.com/xstools-source-2_0.zip and documentation at http://www.xess.com/xstools-src-doc-2_0.pdf.



mark_harvey@my-deja.com wrote:

> Has anyone ever tried to program a JTAG device (eg XC9500) using the PC
> parallel port directly connected to the JTAG pins? Got links to software
> routines?
>
> thanks,
> MH.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


--------------536BEF03B9142CF0CD7A4F0F
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;Dave
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-16464
fn:Dave Vanden Bout
end:vcard

--------------536BEF03B9142CF0CD7A4F0F--

Article: 21259
Subject: Re: I need parallel processor SIMULATOR
From: Tim Tyler <tt@cryogen.com>
Date: Tue, 14 Mar 2000 15:56:16 GMT
Links: << >>  << T >>  << A >>
Juan Antonio Gómez Pulido <jangomez@unex.es> wrote:

: Please, can anybody tell me if exits a PC simulator of parallel
: processors?

There are a number of varying types - which type you want depends on what
you're trying to do:

VHDL simulators:
 * 27000 Leapfrog VHDL Simulator 
 * ModelSim - a VHDL simulator - http://www.model.com/
 * MyVHDL - from Mycad - http://www.mycad.com/product/vhdl.html 
 * VHDL System Simulator - from Synopsis 
 * Cordis VHDL simulator

Cellular automata simulators:
 * WebsideCA - The Isle Ex CA Explorer (Applet) - http://jmge.net/wca.htm
 * Mirek's Java Cellebration: http://www.mirwoj.opus.chelm.pl/mjcell/mjcell.html

Alife parallel processing simulations:
 * AVIDA: http://www.krl.caltech.edu/avida/
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Some things have to be believed to be seen.
Article: 21260
Subject: DCT using FPGA
From: "Seb C" <Seb@stien.bizland.com>
Date: Tue, 14 Mar 2000 17:09:32 -0000
Links: << >>  << T >>  << A >>
Hi all !!
I need informations or references or the both on DCT implementation using
FPGA !!
If you've got it, please contact me !!

Thks
SEB

--
           .   ,
            '. '.  \  \
           ._ '-.'. `\  \
             '-._; .'; `-.'.
            `~-.; '.       '.
             '--,`           '.
                -='.          ;
      .--=~~=-,    -.;        ;
      .-=`;    `~,_.;        /
     `  ,-`'    .-;         |
        .-~`.    .;         ;      Seb@stien.bizland.com
         .;.-   .-;         ,\
           `.'   ,=;     .-'  `~.-._
            .';   .';  .'      .'   '-.
              .\  ;  ;        ,.' _  a',
             .'~";-`   ;      ;"~` `'-=.)
           .' .'   . _;  ;',  ;
           '-.._`~`.'  \  ; ; :
                `~'    _'\\_ '\\_



Article: 21261
Subject: Re: Virtex IOB T register
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 14 Mar 2000 10:16:39 -0800
Links: << >>  << T >>  << A >>
What makes you think there is a toggle flip-flop in the Virtex IOB?
Fig 2 on page 3-6 of the Xilinx data book clearly describes the
three flip-flops as D-type.
So you need to build the toggle logic in a CLB, but you can feed the
state of the output back through the input logic. This gives fastest
clock-to-out. Otherwise do the whole thing in a CLB and use the IOB
just as buffer.

Peter Alfke

bfredc@my-deja.com wrote:

> Hi.
>
> Would anyone know how can I use the T flip-flop
> of an IOB in VIRTEX devices ?
> Records #6214 and #7290 in the Xilinx Answers
> Database don't fix my problem.
>
> Thanks in advance to all who can help.
>
>  Fred
> Laboratoire Signaux et Système du CNAM PARIS
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 21262
Subject: Re: Virtex IOB T register
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 14 Mar 2000 11:44:38 -0800
Links: << >>  << T >>  << A >>
Sorry, that was a dumb posting of mine.
I saw "T-flip-flop" and did not realize that it, in this case, meant
the flip-flop controlling the 3-state ( or output Enable ).
Forget my toggle comments.

Peter Alfke

Peter Alfke wrote:

> What makes you think there is a toggle flip-flop in the Virtex IOB?
> Fig 2 on page 3-6 of the Xilinx data book clearly describes the
> three flip-flops as D-type.
> So you need to build the toggle logic in a CLB, but you can feed the
> state of the output back through the input logic. This gives fastest
> clock-to-out. Otherwise do the whole thing in a CLB and use the IOB
> just as buffer.
>
> Peter Alfke
>
> bfredc@my-deja.com wrote:
>
> > Hi.
> >
> > Would anyone know how can I use the T flip-flop
> > of an IOB in VIRTEX devices ?
> > Records #6214 and #7290 in the Xilinx Answers
> > Database don't fix my problem.
> >
> > Thanks in advance to all who can help.
> >
> >  Fred
> > Laboratoire Signaux et Système du CNAM PARIS
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

Article: 21263
Subject: Programming FPGAs via backplane (Xilinx)
From: Tom McLaughlin <tomm@arl.wustl.edu>
Date: Tue, 14 Mar 2000 13:53:47 -0600
Links: << >>  << T >>  << A >>
All,
Below is a link to a doc describing how we want to program multiple
FPGAs on mulitple boards across a backplane in a fairly large system.
Please review and comment.  The most non-standard thing is not hooking
up the INIT signals, but holding it low for a defined amount of time to
ensure the FPGAs are ready.  This way, we don't have to deal with a
bidirectional signal on the backplane.  Any and all comments welcome.

http://www.arl.wustl.edu/burst/reprogram/reprogram.pdf

Tom



Article: 21264
Subject: Re: Can we read bits from a file in PCc using Altera or Xilinx ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Mar 2000 15:34:45 -0500
Links: << >>  << T >>  << A >>
Avinash Maddy wrote:
> 
> Can any one tell me how to write a VHDL code to read bits (1s and 0s) from a
> file on the PC and another VHDL code to write output bits to a file on the
> PC?
> I am using both Altera and Xilinx platforms. Is it actually possible on
> these platforms ?
> Thanks in advance,
> Avinash Maddy
> maddy@eng.fsu.edu

I am pretty sure that this can be done, but it is not straightforward as
it would be in C. You might want to post this message to comp.lang.vhdl.
I would bet that you could get someone there to provide some sample
code. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21265
Subject: Re: Virtex IOB T register
From: Ray Andraka <randraka@ids.net>
Date: Tue, 14 Mar 2000 20:38:42 GMT
Links: << >>  << T >>  << A >>
In your design, just use a regular D flip-flop.  Don't put any
combinatorial logic in front of it (this isn't absolutely necessary, but
it makes it easier to meet timing)  and don't drive anything other than
the one tristate control with it.  When compiling the design turn on the
use-IOB flip-flops option in the mapper.  That will push the flip-flop
into the IOB as long as there is nothing goofy with it.

bfredc@my-deja.com wrote:

> Hi.
>
> Would anyone know how can I use the T flip-flop
> of an IOB in VIRTEX devices ?
> Records #6214 and #7290 in the Xilinx Answers
> Database don't fix my problem.
>
> Thanks in advance to all who can help.
>
>  Fred
> Laboratoire Signaux et Système du CNAM PARIS
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21266
Subject: Re: Virtex IOB T register
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Mar 2000 16:03:42 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> In your design, just use a regular D flip-flop.  Don't put any
> combinatorial logic in front of it (this isn't absolutely necessary, but
> it makes it easier to meet timing)  and don't drive anything other than
> the one tristate control with it.  When compiling the design turn on the
> use-IOB flip-flops option in the mapper.  That will push the flip-flop
> into the IOB as long as there is nothing goofy with it.

Ok, I give up. How do I know if the FF is "goofy".   ;-)

-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21267
Subject: Re: Programming FPGAs via backplane (Xilinx)
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Mar 2000 16:32:07 -0500
Links: << >>  << T >>  << A >>
Tom McLaughlin wrote:
> 
> All,
> Below is a link to a doc describing how we want to program multiple
> FPGAs on mulitple boards across a backplane in a fairly large system.
> Please review and comment.  The most non-standard thing is not hooking
> up the INIT signals, but holding it low for a defined amount of time to
> ensure the FPGAs are ready.  This way, we don't have to deal with a
> bidirectional signal on the backplane.  Any and all comments welcome.
> 
> http://www.arl.wustl.edu/burst/reprogram/reprogram.pdf
> 
> Tom

I don't see anything wrong with the way you are using the INIT, DONE and
other signals. I don't completly understand why you are driving two
clock lines from the misc card. Can't you just drive all the clock lines
from the Master card? 

Actually it just occured to me why you might be driving the clock from
the Misc board. If you are worried about the delays, then the signal out
from the PROM would have the least skew from the clock this way. 

One point that I think might be significant is the circuit you use to
delay the INIT signal to the PROM. You will need a delay in the 100s of
uS or mS range IIRC. A FF delay circuit as you have shown will take
many, many FFs unless you use a very slow clock. You could do better by
using a counter which is reset when the incoming INIT signal is at zero.
When INIT goes high, the counter starts counting until it reaches max
count. That signal is used to disable the counting and assert the INIT
to the PROM. Reset has to have priority over the count enable. This will
give you a much longer period with many fewer FFs. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21268
Subject: Atmel censors web access
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 14 Mar 2000 14:52:33 -0800
Links: << >>  << T >>  << A >>

--------------F22A3C3FBA5E4F438BDC1C0F
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

>>From my computer here at Xilinx, I can access all sorts of
semiconductor websites.
It's a joy.
I have Intel, AMD, National, Altera, Quicklogic, Actel, Cyprus at my
fingertips.
But not Atmel.
I get:

Forbidden

You don't have permission to access / on this server.

Apache/1.3.9 Server at www.atmel.com Port 80

Shame on you, Atmel !   What are you afraid of ?

Peter Alfke

--------------F22A3C3FBA5E4F438BDC1C0F
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
>>From my computer here at Xilinx, I can access all sorts of semiconductor
websites.
<br>It's a joy.
<br>I have Intel, AMD, National, Altera, Quicklogic, Actel, Cyprus at my
fingertips.
<br>But not Atmel.
<br>I get:
<h2>
<b><font color="#FF0A37">Forbidden</font></b></h2>

<h2>
<b><font color="#FF0A37">You don't have permission to access / on this
server.</font></b></h2>

<h2>
<b><font color="#FF0A37">Apache/1.3.9 Server at www.atmel.com Port 80</font></b></h2>
<font color="#000000">Shame on you, Atmel !&nbsp;&nbsp; What are you afraid
of ?</font><b><font color="#000000"></font></b>
<p><font color="#000000">Peter Alfke</font></html>

--------------F22A3C3FBA5E4F438BDC1C0F--

Article: 21269
Subject: Re: Programming FPGAs via backplane (Xilinx)
From: Mark Summerfield <m.summerfield@ieee.org>
Date: Wed, 15 Mar 2000 10:26:55 +1100
Links: << >>  << T >>  << A >>
Rickman wrote:
> One point that I think might be significant is the circuit you use to
> delay the INIT signal to the PROM. You will need a delay in the 100s of
> uS or mS range IIRC. A FF delay circuit as you have shown will take
> many, many FFs unless you use a very slow clock. You could do better by
> using a counter which is reset when the incoming INIT signal is at zero.
> When INIT goes high, the counter starts counting until it reaches max
> count. That signal is used to disable the counting and assert the INIT
> to the PROM. Reset has to have priority over the count enable. This will
> give you a much longer period with many fewer FFs.

I can't actually view the proposal document at the moment, because
our proxy server is down, but if this cdelay ircuit is external to any
programmable logic device, I'd suggest you just use a one-shot
(such as a 74121) for this purpose.  Why does everyone thing that
the best solution to everything must be digital these days?! ;-)

Mark
Article: 21270
Subject: Re: Programming FPGAs via backplane (Xilinx)
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 14 Mar 2000 15:31:55 -0800
Links: << >>  << T >>  << A >>
I am fairly sure that this design will work, but I would have designed it
differently.
You already have one special board containing the data source, the PROMs.
I would have made this the self-contained configuration source, controlled
by a small CPLD and a crystal oscillator ( total <$ 10.- )
Advantages:
CCLK is unidirectional and can be properly terminated, and definitely not
series-terminated ( I see problems with the series termination in the
present design, generating half-amplitude signals).

Configuration will be faster, since the oscillator is crystal-controlled.
Can cut configuration time in half.

The CPLD can also generate the stretch-time for INIT, with any desired
value.

I would also include a precision voltage monitor chip ( $ 1 ) to start
counting when Vcc is definitely there.

Just my $ 0.02 worth

Peter Alfke, Xilinx Applications


Tom McLaughlin wrote:

> All,
> Below is a link to a doc describing how we want to program multiple
> FPGAs on mulitple boards across a backplane in a fairly large system.
> Please review and comment.  The most non-standard thing is not hooking
> up the INIT signals, but holding it low for a defined amount of time to
> ensure the FPGAs are ready.  This way, we don't have to deal with a
> bidirectional signal on the backplane.  Any and all comments welcome.
>
> http://www.arl.wustl.edu/burst/reprogram/reprogram.pdf
>
> Tom

Article: 21271
Subject: Re: Atmel censors web access
From: "Scott Campbell" <scott.campbell@xilinx.com>
Date: Tue, 14 Mar 2000 15:54:50 -0800
Links: << >>  << T >>  << A >>
Well, the good news is that Boulder can still access the sight. You can refer information needs to us, and we can pass it on to the rest of the Xilinx community.
Article: 21272
Subject: Re: Atmel censors web access
From: ldoolitt@recycle (Larry Doolittle)
Date: 14 Mar 2000 23:55:52 GMT
Links: << >>  << T >>  << A >>
Peter Alfke (peter@xilinx.com) posted duplicate MIME-encoded copies of:

: From my computer here at Xilinx, I can access all sorts of
: semiconductor websites.
: It's a joy.
: I have Intel, AMD, National, Altera, Quicklogic, Actel, Cyprus at my
                                                          ^^^^^^ Cypress?
: fingertips.  But not Atmel.  I get:
:    Forbidden
:    You don't have permission to access / on this server.
:    Apache/1.3.9 Server at www.atmel.com Port 80
: Shame on you, Atmel !   What are you afraid of ?

So look at them from home, or use a redirector service
like www.anonymiser.com.

    - Larry Doolittle   <LRDoolittle@lbl.gov>
Article: 21273
Subject: Today's Unexplained Phenomena, Xilinx Department
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 14 Mar 2000 17:18:23 -0700
Links: << >>  << T >>  << A >>
OK, so I've got this design that's supposed to run at 80 MHz, and it fits
into about 60% of a 4013XLA.  Now, I'd read an appnote that mentioned the
Fast Capture Latches, and how they're faster than using just the input flop
in the IOB.  So, I instantiated all of these things, and because the early
clocks only go to part of the chip, I used three clock pins (all driven by
three different outputs of a PLL-type clock buffer).  Now, since the fast
capture latch requires both an early clock and a global-low-skew clock, I
had to instantiate them both.

Place, route, meets timing.

I noticed something weird in the map report. For each clock pin, a BUFG, a
BUFGLS and a BUFGE were used.  Looking at it with the FPGA Editor, I noticed
that indeed, the clock pin fed the BUFG, which fed both the BUFGLS and the
BUFGE.

I don't know what this means.  FPGA Express didn't stick the BUFG there, as
far as I can tell.

I then ripped out all of the fast capture latches and just used a single
clock.  Met timing fine.  And the only clock buffer inferred was the BUFGLS,
which is what one would expect.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens


Article: 21274
Subject: Re: Virtex IOB T register
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 14 Mar 2000 17:20:59 -0700
Links: << >>  << T >>  << A >>
Rickman wrote in message <38CEA92E.E3A21A45@yahoo.com>...
>Ray Andraka wrote:
>>
>> In your design, just use a regular D flip-flop.  Don't put any
>> combinatorial logic in front of it (this isn't absolutely necessary, but
>> it makes it easier to meet timing)  and don't drive anything other than
>> the one tristate control with it.  When compiling the design turn on the
>> use-IOB flip-flops option in the mapper.  That will push the flip-flop
>> into the IOB as long as there is nothing goofy with it.
>
>Ok, I give up. How do I know if the FF is "goofy".   ;-)

They get that way when you slip them a Mickey.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Reply-To: "Sherdyn" <sherdyn@yahoo.com>


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