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Messages from 22825

Article: 22825
Subject: Re: 8087 in FPGA?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 25 May 2000 11:00:08 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote in message <392CA185.7CE6333B@andraka.com>...
>
>
>> Probably not, since floating-point math is one of the few things FGPAs
don't
>> do well.
>
>You can do floating point just fine in FPGAs, but for it is usually not
very
>efficient use of the real estate, especially in DSP applications where your
>dynamic range usually only changes the exponent by a few counts if floating
>point is used.   In these cases, it is far more efficient to extend the
>precision of your fixed point arithmetic, plus you don't wind up with that
pesky
>floating point truncation working its way into your significand.  So the
bottom
>line, FPGAs do fine with floating point, but you pay dearly for it in area.

Ray, I did say that they don't do FP ops "well"!!

Imagine how much are transcendental functions would take!


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 22826
Subject: Re: 8087 in FPGA?
From: ldoolitt@recycle (Larry Doolittle)
Date: 25 May 2000 18:48:59 GMT
Links: << >>  << T >>  << A >>
Andy Peters (apeters.Nospam@nospam.noao.edu.nospam) wrote:

: Ray, I did say that they don't do FP ops "well"!!
: Imagine how much are transcendental functions would take!

I think Ray can well imagine how much area transcendental
functions would take.  Especially since the 8087 implements
them using the CORDIC algorithm.  All You Need [TM] to make
an 8087 on an FPGA is:
  1. An excellent understanding of floating point and
     the relevant algorithms, including normalization,
     exception handling, and CORDIC
  2. An excellent understanding of what FPGAs are good
     at, and how to make them do it.
  3. A license for relatively un-buggy design software :-p
  4. A 64-bit fixed-point arithmetic engine, including
     add/subtract, shift (for normalization), shift/add
     (multiply/divide), and CORDIC features
  5. A 16-bit exponent handler, not much more than
     increment/decrement, limit and equality detection
  6. 80x8 stack (mmm, two-cycle to get it into 40 logic cells)
  7. "microcoded" sequencing engine to make it all sing

I'm sure if you paid Ray enough, he'd do it for you!
It might not fit on a 4005, though :-( .

      - Larry
Article: 22827
Subject: Re: 8087 in FPGA?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 25 May 2000 14:53:16 -0400
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> Ray Andraka wrote in message <392CA185.7CE6333B@andraka.com>...
> >
> >
> >> Probably not, since floating-point math is one of the few things FGPAs
> don't
> >> do well.
> >
> >You can do floating point just fine in FPGAs, but for it is usually not
> very
> >efficient use of the real estate, especially in DSP applications where your
> >dynamic range usually only changes the exponent by a few counts if floating
> >point is used.   In these cases, it is far more efficient to extend the
> >precision of your fixed point arithmetic, plus you don't wind up with that
> pesky
> >floating point truncation working its way into your significand.  So the
> bottom
> >line, FPGAs do fine with floating point, but you pay dearly for it in area.
> 
> Ray, I did say that they don't do FP ops "well"!!
> 
> Imagine how much are transcendental functions would take!
> 
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
> 
> "A sufficiently advanced technology is indistinguishable from magic"
>      --Arthur C. Clarke

I would not say that floating point operations use tremendously more
real estate then fixed point operations. In both cases you have to have
a multiplier and/or an adder for the significant bits. Then you have a
barrel shifter to normallize/scale the result. 

In the case of floating point you need to add a shifter in front of the
adder and use an adder to deal with the exponent and of course there is
some extra control logic. That is the main difference. 

I think you will find that much of the difference that shows up in DSP
chips is more due to the difference in size of the significant bits of
16 vs. 24/25. The longer the word, the slower the carry and the larger
the multiplier O(N^2). But if you only need 16 bits of precision, then
you can use a smaller floating point format and save real estate and
increase speed. 

So doing a floating point is not tremendously more expensive than fixed
point, especially if you are designing a multiplier where the multiplier
operation uses the bulk of the real estate. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22828
Subject: Re: Fire Wire
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 25 May 2000 22:28:23 +0300
Links: << >>  << T >>  << A >>
Saqib wrote:

> Hi all,
>   I am currently doing my project on Fire Wire.  I have to develop the RTL core of IEEE-1394 Link Layer Controller, in Verilog.  So is there anyone who has worked in this field so can answer me few questions??
>
> Student Final Year,
> Computer System Engg.
> Pakistan.

You can't find free RTL code for OSI Layer 1 and Layer 2 protocol
implementations. Some companies sell RTL, also gate-level models,
but those extremely expensive. You must concentrate on the
academic researches, some of which are probably free. You can
find some papers in IEEE, hope so.

So, if it is practically impossible to find free RTL code, then the
best way to do it is behavioral modelling. If you can't take the
advantage of synthesizability feature of HDL languages, why
must the students deal with HDL languages? Then it is also good
to deal with MATLAB or C/C++. For a undergraduate and even for
graduate, I don't know how many students are in the same thesis,
it must be extremely difficult to design RTL implementation of an
OSI layer. Good luck.

Utku

--
I feel better than James Brown.



Article: 22829
Subject: Re: Programming using *.rbt file
From: fliptron@netcom.com (Philip Freidin)
Date: 25 May 2000 19:34:51 GMT
Links: << >>  << T >>  << A >>
>1)Do I need to shift out all the bits, starting with the dummy bits at
>the beginning of the header?

Yes.

>2)Has anyone else successfully programmed a Spartan part using the
>*.rbt file and if so, would you be willing to share your code?

Yes. Thousand of times. The Spartan you are using (an XCS10) is bit 
stream identical to an XC4005E, (and a strict superset of the XC4005).
Email me directly if the following paragraph doesn't solve your problems.



Since you have got to the point that DONE has gone high, you are almost 
there. The count in the header is correct. The trailing '1' bits in your 
RBT file need to be shifted out as well. I usually tack on an extra 8 '1' 
bits just to be sure. These bits are actually 'dont care', but the clock 
cycles of CCLK are used to cycle the startup statemachine, that takes a 
few clocks to run after DONE has gone high. This all assumes that you are 
using the default startup sequence, and the default CCLK for running the 
startup sequence.


Philip Freidin


In article <392d35c8.585742697@news.uswest.net>,
Steve Holle <steveh@link-comm.com> wrote:
>We've been trying to program a Spartan S10vq100 using the *.rbt file,
>the ASCII bit file generated by the Foundation tools.  We've noticed a
>couple of discrepencies, the first of which is that the Bits: value
>(95008) does not match the bit count encoded in the header line
>(95001).  Also, we have been unable to successfully program the part
>using the bits supplied in the *.rbt file.  We have captured the end
>of programming sequence by triggering on the DONE line.  By comparing
>what our uC generates and what is generated when we program from the
>Parallel Cable, it appears that we still have 7 bits of data to output
>after the DONE line goes high.  Although the DONE bit goes high and
>the INIT line does not go low again, the part does not operate
>properly.  I have two questions:
>
> >>> questions move to top of response.


Article: 22830
Subject: Re: 8087 in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 25 May 2000 19:47:51 GMT
Links: << >>  << T >>  << A >>
The floating point mulitplier is not much more than a fixed point mulitply.
Usually, you store floating point numbers in normalized form, so the
multiplication of the mantissa results in a worst case renormalizing of a single
bit shift, easy enough with a simple mux.  So the additional hardware for the
floating point multiply is the exponent adder (with a carry input from the
multiplier msb), a 2:1 mux and possibly rounding logic at the multiplier output.
Not expensive at all considering.

Where the real expense of floating point is, is in addition.  Here you need to
denormalize one of the addends to align the bit fields, perform the addition and
then renormalize.  To do this, you have to subtract the exponents to determine
which exponent is larger and the amount of shift to apply to the smaller, an
exchange network (two word-wide 2:1 muxes) to steer the smaller input's mantissa
through the input barrel shift and the larger exponent to the output.  After the
adder,  you need a leading sign bit detect to determine the number of redundant
sign bits. A barrel shift to renormalize and an adder to add number of shift
positions to the exponent, possibly followed by a rounding stage.  The barrel
shifts are fairly expensive in terms of numbers of gates.  It is the floating
point adds, not the multiplies that make floating point expensive in hardware.  It
is several times the gate count of a fixed point adder (more than 2*n*log2(n)
times as much)

Rickman wrote:

> I would not say that floating point operations use tremendously more
> real estate then fixed point operations. In both cases you have to have
> a multiplier and/or an adder for the significant bits. Then you have a
> barrel shifter to normallize/scale the result.
>
> In the case of floating point you need to add a shifter in front of the
> adder and use an adder to deal with the exponent and of course there is
> some extra control logic. That is the main difference.
>
> I think you will find that much of the difference that shows up in DSP
> chips is more due to the difference in size of the significant bits of
> 16 vs. 24/25. The longer the word, the slower the carry and the larger
> the multiplier O(N^2). But if you only need 16 bits of precision, then
> you can use a smaller floating point format and save real estate and
> increase speed.
>
> So doing a floating point is not tremendously more expensive than fixed
> point, especially if you are designing a multiplier where the multiplier
> operation uses the bulk of the real estate.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22831
Subject: Re: Why I can't place power symbols on my schematic?
From: Dominic <drreitma@iupui.edu>
Date: Thu, 25 May 2000 16:29:33 -0500
Links: << >>  << T >>  << A >>
If you are used to Foundation 1.5 or earlier the power symbols were on
the tool bar. With Foundation 2.1i you should have the power symbols
within the component library along with all the other gates, in your
case the XC9500 library. Look for the parts "GND" and "VCC".

Hope this helps,
Dominic Reitman

Simon Bilodeau wrote:

> sorry i am using Foundation 2.1i by Xilinx with a XC9500
>
> Simon Bilodeau <simon.bilodeau@htrc.com> a écrit dans le message :
> lNRW4.5112$BD1.153040@weber.videotron.net...
> > Why I can't place power symbols on my schematic?
> >
> >
> >
> >



Article: 22832
Subject: PCI LogiCore M1 Implementation
From: Dominic <drreitma@iupui.edu>
Date: Thu, 25 May 2000 17:17:57 -0500
Links: << >>  << T >>  << A >>
I am having difficulties implementing my PCI backend design. I am using
the XILINX LogiCORE PCI32 on a Virtex PCI board with the XC4062XL-HQ240
chip. My problem exists when I attempt to map my design using the M1
tools. I receive an error about combining logic into a single CLB. I
found this error on Xilinx's support page but the fix did not help.
Below is the script I'm using for the implementation along with a
portion of the map report.

Any help is be appreciated,
Dominic Reitman

***************
M1 tools script
***************
set GUIDE_OLD=TRUE
ngdbuild -sd ..\synthesis -sd ..\..\src\xpci -uc
..\..\src\ucf\m62ah240_09.ucf pcim_top
map pcim_top.ngd -o pcim_top.ncd pcim_top.pcf



***************
Map Report
***************
Design Information
------------------
Command Line   : m1map pcim_top.ngd -o pcim_top.ncd pcim_top.pcf
Target Device  : x4062xl
Target Package : hq240
Target Speed   : -09
Mapper Version : xc4000xl -- C.22

Design Summary
--------------
Number of errors   :   1
Number of warnings : 119

Section 1 - Errors
------------------
ERROR:OldMap:532 - Unable to obey design constraints which require the
   combination of the following symbols into a single CLB:
    FDPE symbol "PCI_CORE/PCI_LC/MASTER/OE_FRAME/OE_FRAME_INT" (output
   signal=PCI_CORE/PCI_LC/MASTER/OE_FRAME/OE_FRAME_INT)
    FMAP symbol "PCI_CORE/PCI_LC/MASTER/OE_FRAME/OEF1" (output
   signal=PCI_CORE/PCI_LC/MASTER/OE_FRAME/NS_OE_FRAME_INT)
    FDPE symbol "PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY"
(output
   signal=PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_COMMON)
    HMAP symbol "PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OTI_3"
(output
   signal=PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY_IN)
    FMAP symbol "PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OTI_1"
(output
   signal=PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/ACTIVE)
   No H function generator combinational inputs are available.  These
symbols
   share the same XBLKNM parameter.


Article: 22833
Subject: Re: 8087 in FPGA?
From: "Allen Litton" <alitton@celeritous.com>
Date: Thu, 25 May 2000 20:40:41 -0500
Links: << >>  << T >>  << A >>
To All,

It is indeed possible, but definitely not for the faint of heart!

We are currently involved in a project to create an 80C187 replacement ASIC
with the
intermediate design to be tested in an FPGA. At last count about 600K+ gates
in a Virtex 800 part and 15 months of effort and counting . A license from
Intel
is also required and not cheap.

for more information contact me through our web site at
http://www.celeritous.com

Allen Litton
CEO
Celeritous


"Ray Andraka" <ray@andraka.com> wrote in message
news:392CA185.7CE6333B@andraka.com...
>
>
> Andy Peters wrote:
>
> > shahzad2512@my-deja.com wrote in message
<8gflvq$jr4$1@nnrp1.deja.com>...
> > >8087 is a math coprocessor and does calculations in FP numbers.
> >
> > Yes, I know.
> >
> > >Is it wise to implement 8087 in an FPGA.
> >
> > Probably not, since floating-point math is one of the few things FGPAs
don't
> > do well.
>
> You can do floating point just fine in FPGAs, but for it is usually not
very
> efficient use of the real estate, especially in DSP applications where
your
> dynamic range usually only changes the exponent by a few counts if
floating
> point is used.   In these cases, it is far more efficient to extend the
> precision of your fixed point arithmetic, plus you don't wind up with that
pesky
> floating point truncation working its way into your significand.  So the
bottom
> line, FPGAs do fine with floating point, but you pay dearly for it in
area.
>
> >
> >
> > also, I think that Intel might step all over your buttocks if you tried
to
> > sell it.
> >
> > > I want to do this for a University project.
> >
> > you may want to consider doing a vending machine.
> >
> > -- a
> > -----------------------------------------
> > Andy Peters
> > Sr Electrical Engineer
> > National Optical Astronomy Observatories
> > 950 N Cherry Ave
> > Tucson, AZ 85719
> > apeters (at) noao \dot\ edu
> >
> > "A sufficiently advanced technology is indistinguishable from magic"
> >      --Arthur C. Clarke
>
> --
> P.S.  Please note the new email address and website url
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>
>


Article: 22834
Subject: Re: Help for Spartan XCS10
From: lkostov@my-deja.com
Date: Fri, 26 May 2000 04:08:20 GMT
Links: << >>  << T >>  << A >>
When I try to simulate the circuit all signals was in tri-state. I was
expected other thing but I didn't work with the Xilinx software before I
decide that I didn't make something which is required from the simulator. My
schematics which I want to implement in XC10 is very simple - one IBUF, 7
OBUF, 3 INV and the appropriate INPUTs and OUTPUTs connectors from Hierarchy
connector dialog box. When I didn't see the expected result in simulator I
try to program the XCS10 and to see the result on the board - the most
OUTPUTs is connected directly to the INPUT, others - by one Invertor.

Latchezar Kostov

In article <8gjpqn$7ij$1@noao.edu>,
  "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote:
> lkostov@my-deja.com wrote in message <8gj0et$b6$1@nnrp1.deja.com>...
> >Hello,
> >I must use Xilinx FPGA for my thesis and I try to make a simple design
> >with Xilinx Spartan XCS10 in PLCC 84 package to learn how it could be
> >programmed and how it operate.
> >I make a simple schematic only for connection to Vcc (2, 11, 22, 54,
> >63, 33, 42 and 74 pins), GND (1, 12, 21, 31, 43, 52, 64 and 76), JTAG
> >signals (TCK on 16, TDO on 75, TDI on 15 and TMS on 17) and a few LEDs
> >and Resistors to some I/O pins (3, 4, 5, 6, 46, 47, 48 and 49 pins).
> >I make a few designs in Xilinx Fondation Software and program the XCS10
> >by Parallel cable. I was expected that the XCS10 will begin to operate
> >like the implemented schematics but I have mistake. It didn't change
> >the state of noone I/O pin.
> >Could someone tell me if I make some mistake or to show me an example
> >of using XCS10? I have capacitors between all Vcc and GND and the
> >program of the XCS10 is successful (by Xilinx's software).
>
> Did you simulate your logic so you know that it actually functions as
> desired?
>
> -a-
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "A sufficiently advanced technology is indistinguishable from magic"
>      --Arthur C. Clarke
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22835
Subject: Re: CRC
From: Chris Shenton <chrissSP@AMpx.uk.com>
Date: Fri, 26 May 2000 11:29:01 +0100
Links: << >>  << T >>  << A >>
Check out this link, but in future, work it out for yourself.

http://www.easics.com/webtools/crctool

Saqib wrote:

> Hi all,
>    I have to implement CRC in Verilog, which is the same as used in IEEE-802, LAN.  Is there anyone who can help me out, and tell me the Standard implementation.  I shall be thankful to him/her.
>
> Student Computer System,
> NED university,
> Pakistan.

Article: 22836
Subject: Q:Itegration of FPGA functionality in an ASIC?
From: Oliver Maischberger <maischberger@vlsivie.tuwien.ac.at>
Date: Fri, 26 May 2000 15:39:23 +0200
Links: << >>  << T >>  << A >>
Do there exist some IP cores which implement FPGA functionality?
I do not mean FPGA dies for MCMs, but integrating the functionality
together with custom logic into a single die.

Oliver

Article: 22837
Subject: Abel conversion to VHDL
From: closset <closset@crf.canon.fr>
Date: Fri, 26 May 2000 16:02:33 +0200
Links: << >>  << T >>  << A >>
Hi all,

I would be grateful to find any help concerning translation
between abel code to vhdl code. The context is about a design
writen in schematic and including some abel code architectures, in
Xilinx Foundation environment. 
Regarding vhdl simulation (modelsim in this case) outside xilinx tools,
I naturalely asked
for a netlist conversion to vhdl code, but unfortunately, all abel codes 
can only be simulated with  "xabelsim"  library, obviously not
interpreted
with such vhdl simulator. 
As a consequence, it is actually not possible to simulate the design
functionaly,
but only after place and route. 

Does anybody know any solution for this problematic ?? 

Thanks in advance.

Arnaud.
Article: 22838
Subject: Re: Programming using *.rbt file
From: steveh@link-comm.com (Steve Holle)
Date: Fri, 26 May 2000 14:08:34 GMT
Links: << >>  << T >>  << A >>
On 25 May 2000 19:34:51 GMT, fliptron@netcom.com (Philip Freidin)
wrote:

>>1)Do I need to shift out all the bits, starting with the dummy bits at
>>the beginning of the header?
>
>Yes.
>
>>2)Has anyone else successfully programmed a Spartan part using the
>>*.rbt file and if so, would you be willing to share your code?
>
>Yes. Thousand of times. The Spartan you are using (an XCS10) is bit 
>stream identical to an XC4005E, (and a strict superset of the XC4005).
>Email me directly if the following paragraph doesn't solve your problems.
>
>
>
>Since you have got to the point that DONE has gone high, you are almost 
>there. The count in the header is correct. The trailing '1' bits in your 
>RBT file need to be shifted out as well. I usually tack on an extra 8 '1' 
>bits just to be sure. These bits are actually 'dont care', but the clock 
>cycles of CCLK are used to cycle the startup statemachine, that takes a 
>few clocks to run after DONE has gone high. This all assumes that you are 
>using the default startup sequence, and the default CCLK for running the 
>startup sequence.
This did fix my problem.  Thanks much for your help.
Article: 22839
Subject: Re: Xilinx tools
From: Nial Stewart <nials@sqf.hp.com>
Date: Fri, 26 May 2000 15:29:45 +0100
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> Christian Mautner wrote:
> >
> 
> >
> > I think that this is not good idea, not for the customers and not for
> > Xilinx. Especially if you consider that Altera is giving away a (not
> > 100% but useful) version of their tools (including a decent synthesis
> > tool) for free.
> 
> Does anyone know where to download the synthesis tools? There are
> headlines
> all over theor site saying "Available at the start of May", but I can't
> find them anywhere yet.
> Nial Stewart.

Ha, checked the Altera site again today and all the "available at
the start of May" messages have been changed to "Available at the
start of June".

Nial.
Article: 22840
Subject: help
From: jorge quintino <jquintinoNOjqSPAM@yahoo.com.invalid>
Date: Fri, 26 May 2000 12:22:11 -0700
Links: << >>  << T >>  << A >>
i have a dimm 128mg at 133mhz but i dont shore. whow a cant see
the mhz of the dim

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Article: 22841
Subject: Verilog PLI website
From: Swapnajit Mittra <mittra@my-deja.com>
Date: Fri, 26 May 2000 20:08:33 GMT
Links: << >>  << T >>  << A >>
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Article: 22842
Subject: Re: Abel conversion to VHDL
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 26 May 2000 22:05:46 +0100
Links: << >>  << T >>  << A >>


closset wrote:

> Hi all,
>
> I would be grateful to find any help concerning translation
> between abel code to vhdl code. The context is about a design
> writen in schematic and including some abel code architectures, in
> Xilinx Foundation environment.
> Regarding vhdl simulation (modelsim in this case) outside xilinx tools,
> I naturalely asked
> for a netlist conversion to vhdl code, but unfortunately, all abel codes
> can only be simulated with  "xabelsim"  library, obviously not
> interpreted
> with such vhdl simulator.
> As a consequence, it is actually not possible to simulate the design
> functionaly,
> but only after place and route.
>
> Does anybody know any solution for this problematic ??
>
>

A possible solution is to run your ABEL through the tools to get a .ngd
database. Then use ngd2vhdl to get a simulation netlist. This won't allow
source level simulation but it might be good enough.

Article: 22843
Subject: Re: Where can I find resource for USB?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 26 May 2000 23:46:23 -0400
Links: << >>  << T >>  << A >>
JX wrote:
> 
> Hi, All,
> 
>  My supervisor ask me to design some USB inferace with
> FPGA, where can I find any resource to implement that?
> 
> Thanks a lot!
> Jesse

The design of a USB interface usually includes a small microcontroller
in order to facillitate the handling of the data from the IO. If you
need to include a micro then you will need to use an FPGA that is not in
the low price end, or you will need to add a memory chip or two
(RAM/PROM). So unless you will already need to have the FPGA on the
board or you don't need the microcontroller and can hardwire the
circuitry, you are likely better off using a standard USB controller
chip. 

I have not priced USB controller chips, but I am sure that they are
pretty cheap. One of the primary constraints in developing the USB
specification was that the interface had to be very, very cheap so that
it could be used in $80 scanners and $30 mice and keyboards. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

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Internet URL http://www.arius.com
Article: 22844
Subject: Re: 8087 in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 27 May 2000 03:49:15 GMT
Links: << >>  << T >>  << A >>


Andy Peters wrote:

> Ray, I did say that they don't do FP ops "well"!!

point taken.

>
>
> Imagine how much are transcendental functions would take!

I believe the 8087 utilized a CORDIC rotator to do the transcendentals, so
probably not as much area as you might think.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22845
Subject: Re: [search] - ISA PnP specs
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 27 May 2000 00:03:46 -0400
Links: << >>  << T >>  << A >>
Sebastien Favard wrote:
> 
> Hi,
> 
> I search informations about the PnP dialogue between OS like Windows and
> ISA board.
> 
> Thanks for all your help
> 
> Sebastien,

There are some very good books on PnP. I believe one is published by
Mindspring. I can't remember the name. The protocol is not complex. Are
you asking so that you can design a PnP chip or FPGA? I believe Xilinx
has a good appnote on a PnP design on their website. I seem to recall
that it even includes a schematic level design. 

The basic operation is that there is a common register defined that all
PnP boards will respond to. It has one bit which on read is logically
or'd onto the data bus (I think it is an open collector output). A
command is sent to all of the boards to reset them and then an
identification process is started. The identification process queries
for an ID number one bit at a time. As each bit is read, the boards all
output their ID codes at the same time. Any boards reporting a zero bit
pull the line down. Any boards reporting a one bit leave the line high.
If a board is outputing a one and sees the line at a zero, it stops
responding to the ID reads. At the end of the 32 reads (IIRC), only one
board will be left. That board can then be selected by using the ID that
was read. This board is taken out of the config mode and the process is
repeated for each board in the system. This allows all of the boards to
be identified and individually controlled. 

Once the identification is complete, each board can be queried about
it's IO requirements and assigned an address range to complete the
configuration process. 

It has been a long time since I have looked at any of this so I may have
left out some significant steps. But the identification portion is the
core of process. 

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22846
Subject: AVNET Virtex Board
From: Paul Sutton <bal@hotpop3.com>
Date: Sat, 27 May 2000 12:17:58 +0800
Links: << >>  << T >>  << A >>
Hello,

I bought a Virtex board from AVNET recently. A little (but maybe just
sufficient) information about the board is bundled with the kit,
however, its web site doesn't have good supporting database as XESS
does. So, I would like to hear from those experienced users anything
about this board -  comments, info, code, bugs and fix, or warnings etc.

Thanks,

Paul.

Article: 22847
Subject: Re: Spartan II availability and pricing
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 27 May 2000 02:22:38 -0400
Links: << >>  << T >>  << A >>
I was checking prices and found that NuHorizons now has pricing on the
entire Spartan II family. They still don't show any stock or lead times,
but at least they list all of the parts and packages. They even show -6
speed grades now. 

         VQ100   TQ144   CS144   PQ208   FG256   FG456
XC2S15   $7.10   $8.15   $8.85
XC2S30   $10.05  $11.55  $12.55  $13.90
XC2S50           $12.85          $14.75  $16.65
XC2S100          $17.60          $19.55  $24.65  $31.00
XC2S150	                         $21.60  $27.00  $35.10
XC2S200                          $26.25  $32.45  $39.10

I am very impressed with the prices (even though you still can't get
100K gates for $10). But this will only come down as they get further
into production. I wish they would put more parts in the VQ100 or the
CS144 package. The TQ144 is just too large for my board. Xilinx never
wants to put the larger parts in the smaller packages. I only need 60
IOs, but there will be applications that need more than 15K or 30K gate
equivalents. 

I see that there is not much point in designing compatible IO with
Virtex parts. If I use an FG256 package, the largest Virtex part I can
use is XCV200 the same as the Spartan II XC2S200! Even if I go with the
FG456 package, I can only use one part larger in the Virtex family,
XCV300. Does anyone know if the pinouts are compatible other than the
small difference in IO count?


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the "reply to" address. To email me use the above address with
the XY removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22848
Subject: Re: Apex supply problem
From: Tom Burgess <tom.burgess@home.com>
Date: Sat, 27 May 2000 09:13:33 GMT
Links: << >>  << T >>  << A >>
I guess another unknown is the microprocessor power up characteristics ...
When does it wake up, what does it see on its inputs then and what does it
do about it. Maybe complicated if its inputs are coming from FPGAs that are
not quite ready for breakfast, though maybe a glass of orange juice and an
Aspirin would be gratefully accepted :) - You maybe have a delayed reset
on the microprocessor?

regards, tom

Michel Le Mer wrote:
> 
> Yes they have.
> 
> It is 100 ms rise time and our PCB has a maximum rise time of 10 ms.
> 
> Tom Burgess <tom.burgess@hia.nrc.ca> a écrit dans le message :
> 392D5B00.794FF9FB@hia.nrc.ca...
> > High startup current and minimum supply risetime requirements also apply
> to
> > Xilinx's Virtex parts. (See Virtex data sheet under Power-on Power
> Requirements)
> > Such is the price of progess :) Maybe Altera has a similar warning buried
> somewhere
> > in their literature - or ask them?
> >
> >
> > Michel Le Mer wrote:
> > >
> > > Hi
> > >
> > > Does anybody hear about power problem with Apex?
> > > We have a PCB with 3 Apex20K200E and a microprocessor. If the suplly
> rise
> > > slowly (about 10ms), the 3.3V supply 1 more ampere and the
> microprocessor
> > > bus (which is linked to the 3 fpgas) is unusable (conflict problem). If
> we
> > > start to download the fpga with the JTAG cable, the problem disappears
> at
> > > the beginning of the 3rd fpga downloading. If the suplly raises in less
> than
> > > 2 ms, the 3.3V and 1.8V rise in the same way and there is no problem.
> > > Does anybody have any idea?
> > >
> > > Thanks.
> > > Michel Le Mer       immeuble Cerium
> > > STA                      12, square du chaine Germain
> > > 02 23 20 04 72     35510 Cesson-Sévigné
> >
> > regards,
> > Tom Burgess
> > --
> > Digital Engineer
> > Dominion Radio Astrophysical Observatory
> > P.O. Box 248, Penticton, B.C.
> > Canada V2A 6K3
> > Email:        tom.burgess@hia.nrc.ca
Article: 22849
Subject: Re: 8087 in FPGA?
From: z80@ds2.com (Peter)
Date: Sat, 27 May 2000 09:16:07 +0000
Links: << >>  << T >>  << A >>

>We are currently involved in a project to create an 80C187 replacement ASIC
>with the
>intermediate design to be tested in an FPGA. At last count about 600K+ gates
>in a Virtex 800 part and 15 months of effort and counting . A license from
>Intel
>is also required and not cheap.

I bet the 8087 wasn't anywhere near 600k gates.


Peter.
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