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Messages from 24375

Article: 24375
Subject: Re: Memory specification
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 05 Aug 2000 00:23:07 -0400
Links: << >>  << T >>  << A >>
SDRAM or possibly older VDRAM. VDRAM is a standard DRAM with a second IO
port which is a serial 4 bit port. The page to be read/written is
selected from the standard port with a special command. The data is
loaded into what amounts to a 1024 bit shift register (I think it is
really a SRAM) and is shifted out at rates up to around 50 MHz or so. 

With SDRAM running at over 100 MHz the VDRAM has dropped from the
picture on the newer boards. It was also very expensive compared to
standard DRAM or even EDO DRAM. 

But all video cards for PCs use some form of DRAM since they are very
cost sensitive. 


Eric Braeden wrote:
> 
> What about the RAM they put on High end video cards.
> I'm looking at one right now that had 32 MB of on-board
> RAM and it only has two chips. What is this?
> Eric

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24376
Subject: Re: tutorial on configurable system-on-chip design is available
From: Dave Vanden Bout <devb@xess.com>
Date: Sat, 05 Aug 2000 06:59:16 -0400
Links: << >>  << T >>  << A >>

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> In time being, i can't take a look on them. but may be in future, i
> have to work on XESS board. will you remove this material from the
> web.

I assume there's a question mark at the end of the last sentence.  The  XESS
tutorial on Triscend CSoCs is there now, but it may not always be there.

>
>
> also, is the XESS board powerful, or is it just used for student
> initiation, sort of training for the beginners

The XSTE5 CSoC Board from XESS has a Triscend TE505 chip with 512
programmable logic cells, no on-board prototyping area, but can be plugged
into a solderless protoboard for building larger systems.  The official
Triscend development board has a TE520 chip with 2048 programmable logic
cells and an on-board prototyping area.  Other than that, the boards have
similar capabilities.  The schematics for the XSTE5 are included in its
manual so you can make an objective judgement of its features.

The Triscend development board is priced at $795 (last time I checked).  The
XESS  myCSoC Kit is priced at $169.95 and includes an XSTE5 Board and a
fully-licensed version (no time limits, no feature restrictions) of the
Triscend FastChip development software.  That price indicates the myCSoC Kit
is intended for students, universities, and beginners who are trying to
educate themselves on the suitability of CSoC technology for their
applications.  Engineers who are actively designing CSoCs into their
products and need full-featured support and guidance from Triscend and their
distributors should use another development system.

>
>
> Regards
>
> --Erika
>
> In article <39896091.E1BDB2C0@xess.com>,
>   Dave Vanden Bout <devb@xess.com> wrote:
> > XESS Corp. is releasing the sixth section of its "myCSoC" tutorial for
> > free downloading at http://www.xess.com/myCSoC-CDROM.html.  We will
> > release a new section each week.
> >
> > Each section describes a design example for the Triscend configurable
> > system-on-chip device (CSoC).  The Triscend TE505 CSoC integrates an
> > 8051 microcontroller core with a programmable logic array to create a
> > chip whose software and hardware are both reprogrammable.  The
> tutorial
> > examples show how the Triscend FastChip development software is used
> to
> > configure the TE505's programmable logic into peripheral functions
> that
> > cooperate with the microcontroller core.
> >
> > --
> > || Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
> > || devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
> > || http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


--------------510B7D2A4BA412605BDF1D22
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Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>

<blockquote TYPE=CITE>In time being, i can't take a look on them. but may
be in future, i
<br>have to work on XESS board. will you remove this material from the
<br>web.</blockquote>
I assume there's a question mark at the end of the last sentence.&nbsp;
The&nbsp; <a href="http://www.xess.com/myCSoC-CDROM.html">XESS tutorial
on Triscend CSoCs</a> is there now, but it may not always be there.
<blockquote TYPE=CITE>&nbsp;
<p>also, is the XESS board powerful, or is it just used for student
<br>initiation, sort of training for the beginners</blockquote>
The <a href="http://www.xess.com/prod021.html">XSTE5 CSoC Board</a> from
XESS has a <a href="http://www.triscend.com/products/dse5csoc.pdf">Triscend
TE505 chip</a> with 512 programmable logic cells, no on-board prototyping
area, but can be plugged into a solderless protoboard for building larger
systems.&nbsp; The official Triscend development board has a TE520 chip
with 2048 programmable logic cells and an on-board prototyping area.&nbsp;
Other than that, the boards have similar capabilities.&nbsp; The schematics
for the XSTE5 are included in its <a href="http://www.xess.com/manuals/xste5-manual-v1_0.pdf">manual</a>
so you can make an objective judgement of its features.
<p>The Triscend development board is priced at $795 (last time I checked).&nbsp;
The XESS&nbsp; <a href="http://www.xess.com/prod022.html">myCSoC Kit</a>
is priced at $169.95 and includes an XSTE5 Board and a fully-licensed version
(no time limits, no feature restrictions) of the Triscend FastChip development
software.&nbsp; That price indicates the myCSoC Kit is intended for students,
universities, and beginners who are trying to educate themselves on the
suitability of CSoC technology for their applications.&nbsp; Engineers
who are actively designing CSoCs into their products and need full-featured
support and guidance from Triscend and their distributors should use another
development system.
<blockquote TYPE=CITE>&nbsp;
<p>Regards
<p>--Erika
<p>In article &lt;39896091.E1BDB2C0@xess.com>,
<br>&nbsp; Dave Vanden Bout &lt;devb@xess.com> wrote:
<br>> XESS Corp. is releasing the sixth section of its "myCSoC" tutorial
for
<br>> free downloading at <a href="http://www.xess.com/myCSoC-CDROM.html">http://www.xess.com/myCSoC-CDROM.html</a>.&nbsp;
We will
<br>> release a new section each week.
<br>>
<br>> Each section describes a design example for the Triscend configurable
<br>> system-on-chip device (CSoC).&nbsp; The Triscend TE505 CSoC integrates
an
<br>> 8051 microcontroller core with a programmable logic array to create
a
<br>> chip whose software and hardware are both reprogrammable.&nbsp; The
<br>tutorial
<br>> examples show how the Triscend FastChip development software is used
<br>to
<br>> configure the TE505's programmable logic into peripheral functions
<br>that
<br>> cooperate with the microcontroller core.
<br>>
<br>> --
<br>> || Dr. Dave Van den Bout&nbsp;&nbsp; XESS Corp.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(919) 387-0076 ||
<br>> || devb@xess.com&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
2608 Sweetgum Dr.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (800) 549-9377
||
<br>> || <a href="http://www.xess.com">http://www.xess.com</a>&nbsp;&nbsp;&nbsp;&nbsp;
Apex, NC 27502 USA&nbsp;&nbsp; FAX:(919) 387-1302 ||
<br>>
<p>Sent via Deja.com <a href="http://www.deja.com/">http://www.deja.com/</a>
<br>Before you buy.</blockquote>

<p>--
<br>|| Dr. Dave Van den Bout&nbsp;&nbsp; XESS Corp.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(919) 387-0076 ||
<br>|| devb@xess.com&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
2608 Sweetgum Dr.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (800) 549-9377
||
<br>|| <A HREF="http://www.xess.com">http://www.xess.com</A>&nbsp;&nbsp;&nbsp;&nbsp; Apex, NC 27502 USA&nbsp;&nbsp;
FAX:(919) 387-1302 ||
<br>&nbsp;</html>

--------------510B7D2A4BA412605BDF1D22--

Article: 24377
Subject: Re: Verilog multiplier in Xilinx...
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 5 Aug 2000 14:57:18 GMT
Links: << >>  << T >>  << A >>
In the latest release of the Xilinx tools (3.1i...and I think they even
have a service pack out already...sigh) and the update to the 2.1i CoreGen,
there is a Virtex multiplier.  Unfortunately, it is a black box....and not
very efficient as far as resource utilization...but for now, it'll do.

I just can't believe there isn't a repository for these things.  I did find
one very very interesting web site:

http://modgen.fysel.ntnu.no/

I generated a few multipliers with it, and haven't tested them yet.


Austin Franklin <austin@d44arkroom.com> wrote in article
<01bffdc5$39629590$3606f7a5@drt1>...
> Anyone have any Verilog code they'd be willing to share for a 'decent'
> multiplier?  I am looking for something that can do a 24 x 24
multiply...it
> can take quite a few cycles, and it's for a Virtex architecture.
> 
> I already have x <= a * b ; //  ;-)
> 
> Thanks!
> 
> 
Article: 24378
Subject: Help! Troubles using async FIFO cores in Virtex
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Sat, 05 Aug 2000 21:16:00 GMT
Links: << >>  << T >>  << A >>
Hi,

I have a XCV50 design that uses 2 async 255x16 FIFOs generated with coregen.
One of them seems to work fine while other one sets its FULL flag after
about 270 writes instead of 255. This results in loss of data...

It also seems to me that the circuit changes behavior when I add probe pins
with FPGA Editor and as weird as it may seem it does not go back when I
delete probes (reprogram part with original file). I've been looking at this
for a week and totally lost and confused by now.

Has anyone seen anything like that?


Any input will be very much appreciated.


Mikhail


Article: 24379
Subject: Abel from dataIO?
From: Jack Lai <jwlai@mmmpcc.org>
Date: Sat, 05 Aug 2000 21:04:08 -0500
Links: << >>  << T >>  << A >>
Does anyone know who pickup the ABEL product line Dataio?

Thanks, in advance for your help.

Jck

Article: 24380
Subject: Re: Help! Troubles using async FIFO cores in Virtex
From: wq998@my-deja.com
Date: Sun, 06 Aug 2000 03:20:58 GMT
Links: << >>  << T >>  << A >>
Why not use RTL codes provided by Xilinx AppNote?


In article <ku%i5.865$rx5.21235@news.magma.ca>,
  "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca> wrote:
> Hi,
>
> I have a XCV50 design that uses 2 async 255x16 FIFOs generated with
coregen.
> One of them seems to work fine while other one sets its FULL flag
after
> about 270 writes instead of 255. This results in loss of data...
>
> It also seems to me that the circuit changes behavior when I add
probe pins
> with FPGA Editor and as weird as it may seem it does not go back when
I
> delete probes (reprogram part with original file). I've been looking
at this
> for a week and totally lost and confused by now.
>
> Has anyone seen anything like that?
>
> Any input will be very much appreciated.
>
> Mikhail
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24381
Subject: some basic rules on FPGA design
From: shoran@my-deja.com
Date: Sun, 06 Aug 2000 03:44:08 GMT
Links: << >>  << T >>  << A >>
Though FPGA designs are complicate, for a good design there must be
some basic rules you should abide by, such as synchronous design,
pipeline design etc. All those methods could optisize your design. So
could you professionals tell me more basic rules?

Thanks very much in advance.

Cheers

Shoran


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24382
Subject: Re: some basic rules on FPGA design
From: Bob Perlman <bobperl@best_no_spam_thanks.com>
Date: Sat, 05 Aug 2000 21:38:36 -0700
Links: << >>  << T >>  << A >>
On Sun, 06 Aug 2000 03:44:08 GMT, shoran@my-deja.com wrote:

>Though FPGA designs are complicate, for a good design there must be
>some basic rules you should abide by, such as synchronous design,
>pipeline design etc. All those methods could optisize your design. So
>could you professionals tell me more basic rules?

I've posted some general, high-level design guidelines at:

     http://www.best.com/~bobperl/howwe.htm

If I had to boil everything down to one rule, it'd be this: make
believe you're designing an ASIC.  Don't be taken in by the notion
that you can do a sort-of-OK design and fix it later through the magic
of reprogrammability.  Thoroughly design and simulate the FPGA before
you debug it in the lab.

If everyone did this, I'd have a lot less consulting work to do.
Fortunately, no one takes me seriously when I say this stuff.

Take care,
Bob

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 24383
Subject: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 06 Aug 2000 06:10:27 GMT
Links: << >>  << T >>  << A >>
I am working on optimized processor cores for Virtex
and I have a strange result, perhaps a bug in the tools.
This problem is with F2.1i SP6.
I would appreciate any ideas from you gurus before I
send it off to Xilinx tech support.


In my XC4000X xr16 core, I built a compact read-write register
file, not from dual-port RAM, but by time-multiplexing access
to single-port RAM.  When CLK is high, I read a value from the
RAM, and capture it in the same CLB's FFs on the CLK falling
edge.  When CLK is low, I present the write address and WE,
which the RAM captures as CLK rises.

That is, in each CLB in the register file, the 2 single-port RAMs
are configured to write on the CLK rising edge, and its 2 FFs
are configured to capture the RAMs' outputs on the CLK falling edge.
(The RAM addresses are outputs of a mux, selected by CLK.)


So recently I was investigating whether or not to use the same
trick in Virtex.  I was disappointed to learn that the Virtex
slice architecture does not provide separate programmable
CLK inverters on the RAM and the FF clocks, so you can either
write into the RAMs and clock the FFs BOTH on the rising edge
or BOTH on the falling edge, but not one on either edge.
Bummer!

Then I thought, hey, in my application a latch might do.
Not pretty, but the latch output is then reregistered in half
a clock anyhow.

But when I implemented a simple latch and looked
at its configuration in the FPGA Editor, I was surprised to
see that PAR had set the slice clock inverter.  I checked the
edif that came out of Foundation Express for my latch, and
it looked right, a simple instance of LD with no CLK inversion.
Should pass data on CLK high and hold it on CLK low.

Then I tried some more experiments, and I found that

1. when I constrain a rising edge triggered single-port RAM
   and a G=clk latch into the same slice, it passes PAR, but curiously,
   FPGA Editor again shows the slice clk mux selects inverted CLK
   for both!

2. when I constrain the same RAM and latch to be in different slices,
   the RAM slice shows up as rising edge triggered, but the latch
   slice again shows up with CLK inverted!

3. when I constrain a rising edge triggered single-port RAM and
   a G=~clk latch in the same slice, it fails PAR with the error

 ERROR:xvkpu - Unable to obey design constraints (LOC = CLB_R3C1.S1) which
   require the combination of the following symbols into a single slice:
    RAM symbol "r2" (Output Signal = o2)
    LATCH symbol "q2_reg" (Output Signal = q2)
   The clock signals don't agree.

I expected 3.  But I really don't understand why inverted CLK
is selected for the RAM and the latch in cases 1 and 2, and at
any rate why cases 1 and 2 don't receive identical CLK polarities.
This feels like a bug, either in PAR, or in FPGA Editor.

Any ideas?
Thanks.
Jan Gray
Gray Research LLC



Here is a trimmed down example (Foundation Express Verilog)

test.v:
module test(clk, rst, in, out);
 input clk, rst, in;
 output out;

 reg [3:0] a;
 reg we;
 reg d0, d1, d2;
  wire o0, o1, o2;
 reg q0, q1, q2;

 RAM16X1S r0(.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
    .D(d0), .O(o0), .WCLK(clk), .WE(we));

 RAM16X1S r1(.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
    .D(d1), .O(o1), .WCLK(clk), .WE(we));

 RAM16X1S r2(.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
    .D(d2), .O(o2), .WCLK(clk), .WE(we));

 always @(posedge clk) begin
  {we,a,d0,d1,d2} <= {a,d0,d1,d2,in};
 end
 always @(clk or o0) begin
  if (clk)
   q0 <= o0;
 end
 always @(clk or o1) begin
  if (clk)
   q1 <= o1;
 end
 always @(clk or o2) begin
  if (~clk)
   q2 <= o2;
 end
 assign out = q0 & q1 & q2;
endmodule


test.ucf:
net clk period = 10 ns;

INST q0_reg LOC=clb_r1c1.s1;  # located in the same slice
INST r0 LOC=clb_r1c1.s1; # but curiously with CLK inverted

INST q1_reg LOC=clb_r2c1.s1;  # clk inverted!?
INST r1 LOC=clb_r2c1.s0;  # clk not inverted!

#INST q2_reg LOC=clb_r3c1.s1;  # if you uncomment this you get
#INST r2 LOC=clb_r3c1.s1;      # the above error xvkpu (good)




Article: 24384
Subject: Re: FPGA selection
From: jamilkhatib@my-deja.com
Date: Sun, 06 Aug 2000 11:05:21 GMT
Links: << >>  << T >>  << A >>
Thanks for your recommendation.
In fact I am an EE person but I have also some experiance with CS

Thanks
In article <4tafm8.sdn.ln@data.pdorf.at>,
  com@mail.cmautner (Christian Mautner) wrote:
> On Thu, 03 Aug 2000 08:02:50 +0200, Jamil Khatib
<Khatib@opencores.org> wrote:
> >OK I give more priority on the price and the size of memory that can
be
> >implemented on it
> >
>
> Now, if you could tell us _how_much_ memory you need, it would be
easier for
> us to give a hint into the right direction. Like spartan/ACEX (cheap)
or
> virtex/APEX (large).
>
> And, if you tell me if you are more a EE or a CS person, I will
recommend
> Altera or Xilinx, respectively. ;-)
>
> chm.
>
> --
> cmautner@  -  Christian Mautner
> mail.com   -  Vienna/Austria/Europe
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24385
Subject: Asynchronous circuit on FPGA
From: "Phunjapa Ruangsinsup" <mpr@siampage.com>
Date: Sun, 6 Aug 2000 19:16:59 +0700
Links: << >>  << T >>  << A >>
Hi..
    I'm interest in designing Asynchronous circuit on FPGA, So I want any
comment or knowledge based about implementation. if somebody used to do it,
please introduce me.


Article: 24386
Subject: Re: FPGA selection
From: jimmy75@my-deja.com
Date: Sun, 06 Aug 2000 13:20:05 GMT
Links: << >>  << T >>  << A >>
In article <3987FB32.7580B4EA@opencores.org>,
  khatib@ieee.org wrote:
> Hi,
>
> Could you please suggest me the best FPGA to use that has minimum
price,
> maximum logic gates and provides maximum FIFO memory buffer.
>
> Thanks in advance
> Jamil Khatib
>
>

I have to say that it is a very vague question!
I think functionality comes first, then comes the price.
It depends on your applications. As far as DSP applications are
concerned (in general), Xilinx Spartan-Virtex devices are the most
suitable in my opinion. Reason:
1- Large amount of memory on-chip (see BlockRAM in SpartanII and Virtex
devices).
2- Efficient implementation of delay queues (see Synchronous
distributed RAMs)
3- Fast carry chain (fast adders---> Fast multipliers)

Ray has explained that many times in this NG with a comparison with
Altera devices (Flex10K - Apex). Make a search in deja news.

Spartan-II is a cheap version of Virtex devices with some features
removed (e.g. assynchronous BlockRAMs). But you probably do not need
these features anyway. I believe that the prices are < $10 a unit.
Check it out with Xilinx.

I am not a Xilinx representative. Their devices are really the best as
far as DSP is concernd. The software has developed drastically though
there are still some pitfalls. The support is also good.

Hope this helps!


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Before you buy.
Article: 24387
Subject: Re: Category : Subject
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 06 Aug 2000 09:38:18 -0400
Links: << >>  << T >>  << A >>
To the best of my knowledge every FPGA that Xilinx currently makes (with
the possible exception of the XC3000 family) can implement a 5 input LUT
in one CLB, or two to a CLB in the Spartan II and Virtex families.
Lucent also can do that in all of their ORCA parts (OR2, OR3). 

So there are many, many parts that can do what you want. Just pick one
that is large enough to have 2000 FFs. 


Jian Lin wrote:
> 
> Hi,
> Is there a FPGA part which has 5-input LUT and about 2000 Flip-flops?
> Thanks a lot.
> Jian

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24388
Subject: Help!! Virtex system gate count.
From: jimmy75@my-deja.com
Date: Sun, 06 Aug 2000 15:00:21 GMT
Links: << >>  << T >>  << A >>
Hi Folks,

I am pretty confused, how does Xilinx count the system gates for their
Virtex series? I understand that the logic cell count is 4.5 logic cell
per CLB (4.5 4LUT). How many gates does a logic cell represent??

I need this info urgently, please help!




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Article: 24389
Subject: Re: Help! Troubles using async FIFO cores in Virtex
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 6 Aug 2000 15:49:13 GMT
Links: << >>  << T >>  << A >>
> I have a XCV50 design that uses 2 async 255x16 FIFOs generated with
coregen.
> One of them seems to work fine while other one sets its FULL flag after
> about 270 writes instead of 255. This results in loss of data...
> 
> It also seems to me that the circuit changes behavior when I add probe
pins
> with FPGA Editor and as weird as it may seem it does not go back when I
> delete probes (reprogram part with original file). I've been looking at
this
> for a week and totally lost and confused by now.
> 
> Has anyone seen anything like that?

It sounds to me like a timing problem.  Is your design fully timespec'd,
and if so, when you route, does it make timing?  If your design is
timespec'd, then your timespecs might be wrong...

Did you run a simulation?

Article: 24390
Subject: Xilinx Alliance Base
From: "peter dudley" <padudle@spinn.net>
Date: Sun, 6 Aug 2000 10:12:02 -0600
Links: << >>  << T >>  << A >>
Last December I bought the Xilinx Alliance Base software for some home
projects that I had to do. Since then 3.1i has come out.

Does anyone know if I should receive a free update on this software?

--
Pete Dudley

Arroyo Grande Systems



Article: 24391
Subject: Circuit Drawing
From: "Goulas George" <george_goulas@hotmail.com>
Date: Sun, 6 Aug 2000 20:54:20 +0300
Links: << >>  << T >>  << A >>
It's a bit irrelevant to this newsgroup...

I need a drawing program that produces good looking digital circuit designs.
I've tried Visio, but I could n't find muxes or ffs.
I don't need all the graphic detail of the good digital
simulation programs, I just need to present some
circuits....

Thanks in advance



Article: 24392
Subject: Re: Help!! Virtex system gate count.
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sun, 06 Aug 2000 14:41:53 -0400
Links: << >>  << T >>  << A >>
What's your specific objective? are you looking to compare a Xilinx FPGA
to an ASIC? If so you can use the following rules of thumb. For an ASIC
design that is being dropped into a Xilinx part, take the synopsis gate
count and multiply by 6 to find the equivalent size Virtex part, i.e.
100,000 synopsis gates will fit in an XCV600. If the design is targeted
directly at Xilinx and you make heavy use of Xilinx specific features
like LUT RAMS, Block RAMs, delay lines, and synchronous clears, the
effective gate count is pretty close to what Xilinx claims, i.e. that
same XCV600 can hold 600K gates or more. The problem with doing a direct
comparison is that the value of a LUT varies tremendously depending on
how it is used. As a logic element it's only worth aproximately 3 gates,
in an ASIC a two wide AOI and a couple of inverters would do much the
same job. As memory it's worth a lot more, at least 16 ASIC gates, if
you compare it to an ASIC RAM, or maybe as many as 64 gates if the
equivalent structure was built out of random gates. 

Josh

jimmy75@my-deja.com wrote:
> 
> Hi Folks,
> 
> I am pretty confused, how does Xilinx count the system gates for their
> Virtex series? I understand that the logic cell count is 4.5 logic cell
> per CLB (4.5 4LUT). How many gates does a logic cell represent??
> 
> I need this info urgently, please help!
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 24393
Subject: Re: Help! Troubles using async FIFO cores in Virtex
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Sun, 06 Aug 2000 19:02:06 GMT
Links: << >>  << T >>  << A >>
I believe you are right and it is a timing problem. I set Read Enable of
this FIFO to GND and it behaves much more reasonably now except for it is
useless:)  Before I had a probe set right on the Block RAM Read Enable and I
could not see there any unexpected reads but now I think that there are some
glitches that confuse FIFO counters.

Yes I ran a simulation though not a full simulation. I simulated several
reads and writes and it worked fine. Regarding timing constraints I have
PERIOD type of constraints set for both read and write FIFO clocks. It is
difficult to set other constraints as the FIFO datasheet does not have any
timing specs. I could look up some data from the switching characteristics
of the Virtex BLOCKRAM but it seems that the problem is not related to the
BLOCKRAM itself... Clocks are not very fast BTW, one is 40MHz and another
just 10MHz...

Thanks for the input.

/Mikhail



Austin Franklin <austin@d44arkroom.com> wrote in message
news:01bfff3f$a5d6bf00$8c0af7a5@drt1...
>
> It sounds to me like a timing problem.  Is your design fully timespec'd,
> and if so, when you route, does it make timing?  If your design is
> timespec'd, then your timespecs might be wrong...
>
> Did you run a simulation?
>


Article: 24394
Subject: Re: Circuit Drawing
From: "JAKOB NIKLASSON" <jakob.niklasson@get2net.dk>
Date: Sun, 6 Aug 2000 20:30:09 +0100
Links: << >>  << T >>  << A >>
Orcad is offering there eCapture for free on there website. www.orcad.com It
is a very professionel product and very good. I think it is free because it
is a good way for them to get marked-shares, like netscape is for free. If
you want any other of there products, like the PCB part, you need to pay.
For your use it is perfect. I am not using it my self but I know severel
pepole who do, and they like it very much.

best regards

Jakob

Goulas George <george_goulas@hotmail.com> wrote in message
news:8mk8ue$en6$1@foo.grnet.gr...
> It's a bit irrelevant to this newsgroup...
>
> I need a drawing program that produces good looking digital circuit
designs.
> I've tried Visio, but I could n't find muxes or ffs.
> I don't need all the graphic detail of the good digital
> simulation programs, I just need to present some
> circuits....
>
> Thanks in advance
>
>
>


Article: 24395
Subject: Re: Circuit Drawing
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 06 Aug 2000 12:38:55 -0700
Links: << >>  << T >>  << A >>
On Sun, 6 Aug 2000 20:54:20 +0300, "Goulas George" <george_goulas@hotmail.com>
wrote:

What you probably want is a schematic capture package. If this
is a short duration project, a demo copy of a package like protel
would probably suit you. If you are going to want to do this a lot,
then two cheap options are the Xilinx Student edition, which
includes the Aldec schematic capture program, or the Lucent
entry level kit, that includes the Viewlogic ViewDraw program.

The Xilinx package is ~$100 , and the Lucent one was free at
one time. Don't know the price now, but it is probably also
around free or $100.

All these packages include a library of symbols, and if you need
new symbols, you just make them.

Of course, why not just make extra symbols for Visio?

Philip Freidin


>It's a bit irrelevant to this newsgroup...
>
>I need a drawing program that produces good looking digital circuit designs.
>I've tried Visio, but I could n't find muxes or ffs.
>I don't need all the graphic detail of the good digital
>simulation programs, I just need to present some
>circuits....
>Thanks in advance

Philip Freidin

Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Shell accounts, including mine.

My new primary email address is    philip@fliptronics.com

I'm sure the inconvenience to you will be less than it is for me.
Article: 24396
Subject: Re: Help!! Virtex system gate count.
From: jimmy75@my-deja.com
Date: Sun, 06 Aug 2000 21:33:15 GMT
Links: << >>  << T >>  << A >>

> comparison is that the value of a LUT varies tremendously depending on
> how it is used. As a logic element it's only worth aproximately 3
gates,
> in an ASIC a two wide AOI and a couple of inverters would do much the
> same job. As memory it's worth a lot more, at least 16 ASIC gates, if
> you compare it to an ASIC RAM, or maybe as many as 64 gates if the
> equivalent structure was built out of random gates.

That's what I do not understand. How does Xilinx count the system
gates? I understand the logic cell count (number of 4-LUTs). Now, what
does 4-LUT give in terms of gates? I mean do they take it as <=> 3
gates (simple LUT) or 16, 64 gates -as you said- for an equivalent
RAM??? it seems it is ~12 gates. Anyone from Xilinx can help me here???


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24397
Subject: Re: Help! Troubles using async FIFO cores in Virtex
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 6 Aug 2000 23:13:42 GMT
Links: << >>  << T >>  << A >>
> Clocks are not very fast BTW, one is 40MHz and another
> just 10MHz...

You're welcome.

clocks, eh?  Does that mean the FIFO has one clock for its input address
counter/flags and one for its output address counter/flags?  Are you using
gray coded counters, and have a single point of synchronization between
time domains?  Your flags must be referenced in the time domain you are
using them in...

What is your input tool, Verilog/Synplicity or
Schematics/Viewdraw....perhaps?

Article: 24398
Subject: Re: Circuit Drawing
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 6 Aug 2000 23:15:48 GMT
Links: << >>  << T >>  << A >>
> I need a drawing program that produces good looking digital circuit
designs.
> I've tried Visio, but I could n't find muxes or ffs.
> I don't need all the graphic detail of the good digital
> simulation programs, I just need to present some
> circuits....

If you are talking block diagrams, then Visio is fine, that's what I use. 
I can email you a sample block diagram if you like.  The shapes aren't that
hard to make.

Article: 24399
Subject: Re: Circuit Drawing
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 6 Aug 2000 23:18:12 GMT
Links: << >>  << T >>  << A >>
> Orcad is offering ... a very professionel product

Er, hum.  Never thought I'd see those words in the same paragraph...  This
I've gotta see ;-)



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