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Messages from 42350

Article: 42350
Subject: Re: Programming Spartan2 and external clock
From: "gianzi" <zisis@mhl.tuc.gr>
Date: Sun, 21 Apr 2002 19:38:56 +0300
Links: << >>  << T >>  << A >>

"Sean" <creon100@yahoo.com> wrote in message
news:b97bab2f.0204210651.7e2e0923@posting.google.com...
> I was just wondering if having an external clock running on one of the
> exterior global clock pins of the device causes problems in
> programming a Spartan2 device via slave-serial mode?  In other words,
> does that clock need to be disabled during programming?

I used Multilinx to download a bitstream into a Virtex, and while the
external clock was powered on I could redownload it with no problems.



Article: 42351
Subject: Re: clock management in Virtex-E (DLL)
From: "H.L" <alphaboran@yahoo.com>
Date: Sun, 21 Apr 2002 20:30:51 +0300
Links: << >>  << T >>  << A >>
Hi Falk,
first of all thanks for your answer! :)

The fast clock has fanout=82 while the divided by 2 clock has fanout=397,
this means that the slow clock has almost 5 times the load of the fast
clock? If yes is this very bad? (Timing analyzer reports no timing errors)

A question for the second DLL you suggested me to remove: how can I
eliminate the divided clock's skew if I dont use a DLL to control it?

You wrote thay the delay noticed in my post-MAP (and PAR) simulations is
owing to the bufg delay (6.44-4=2.4 ns), the 4 in the equation represents
what?

And the last question to clarify things, you say that clk0 and clkdv are
(should be) in phase. You mean that despite of the simulation phase
difference, in my FPGA these 2 clocks are in phase? Is this delay owing to
the way the simulator handles the FPGA delays and not an implementation
"problem"?
What about the post-PAR simulation I want to run to verify the correct
operation of the FPGA, if I have a phase difference between the 2 clocks how
can I simulate my FPGA correct?

Thanks a lot..

Best Regards,
Harris


Timing analyzer
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a9uq44$6ahv2$1@ID-84877.news.dfncis.de...
> "H.L" <alphaboran@yahoo.com> schrieb im Newsbeitrag
> news:a9ubr7$2gs$1@ulysses.noc.ntua.gr...
> > Hello all,
> > I use a XCV812E-BG560 for my design.
> >
> > I have as input a 155MHz clock that I divide by 2 with the use of
CLKDLLHF
> .
> > The external clock is LOC
> > constrained in an LVDS_DLL pin. I want to make use the clock155 and the
> > clock1/2 so I use 2 CLKDLLHF in
>
> AFAIK for this, you dont need two DLLs. Just connect the CLKDV output to
the
> second BUFG and you are done. BUT you should make sure that the two clock
> nets have (more or less) equal load, otherwise skew can bite you. Ray
> Andraka already commented this problem and suggested to do data transfers
> between the two clock domains on different clock edges.
> The problem is, that the second DLL is useless, since a DLL can AFAIK only
> be feed back with a x1 or x2 clock, not with a divided clock.
>
> > the way described below.
> >
> > I run the map, PAR simulation vhdl codes and I see that the clkdv output
> of
> > the first CLKDLLHF is not in
> > phase with the clk155 (the clk155_int is in phase, also the clk90 and
> clk180
> > are in phase with the clkin of the DLL). The clkdv rising edge has 4 ns
> > delay in relation to clk155's rising edge
>
> Sure, because there is a delay of (6.44 - 4 = 2.4 ns) in the clock buffer.
> But clk0 and clkdv are (should be) in phase.
>
> --
> MfG
> Falk
>
>
>
>



Article: 42352
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: kayrock66@yahoo.com (Jay)
Date: 21 Apr 2002 10:41:23 -0700
Links: << >>  << T >>  << A >>
> I looked at the XC2V6000, which costs up to US$ 8700,--. That is somewhere
> at a small car. My question to somebody involved in production of such
> parts: Why are these parts that expensive? Please don't misunderstand me,
> I really accept the price. I simply don't have any idea what can make a
> chip that expensive.
> 
> Another question: What are typical uses of a XC2V6000 with e.g. 1517 pins?
> :-) Are they used for fast routing of network traffic in Cisco Catalyst
> routers (or such things)? I guess, a PC will not use these parts. What
> are typical capabilities, what can one typically put together into one
> such FPGA?
> 
> Thanks
>   Hansi

Hansi,

To answer your question, "What makes them so expensive?"  The answer
is the answer is quite simply the free market.  The customer has the
ability and willingness to pay.  There is no preceived subsitute at a
lower price.  This whole business about how much money it costs Xilinx
to make one only tells you if its a viable buisiness or not, and
indicates little about the selling price.  In fact, in a surplus
situtation, you will often pay less than the cost of item.  I once
purchased a small car (great comparison by the way) for substatital
discount because of artificial surpluses generated by the govenments
CAFE(SP?) average milage regulations.

Q: "What do you use a chip like this for?"  The main use I've seen
them for is ASIC prototyping.  A way to run cycle acurate emulation of
your ASIC at reduced speed (usually about 1/4) against something that
you would not be able to simulate (like a Microsft operating system).

Cheers

Article: 42353
Subject: Re: 8051 Core for Motor Electronics
From: Peter Wallace <pcw@mesanet.com>
Date: Sun, 21 Apr 2002 11:00:18 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:

> "Felix Bertram" <f.bertram@trenz-electronic.de> schrieb im Newsbeitrag
> news:a9mqfj$4l83o$1@ID-31589.news.dfncis.de...
> > Steffen,
> >
> > > I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA.
>
> Hmm, maybe its worth a try to have a look at xapp213. The is a 8-Bit RISC,
> very small, but very clever and fast.
>
> 16 8 bit register
> 256 instructions program size
> >20 MIPS
> 8 bit IO port for additional hardware.
> interrupt capability.
> uses just 5% in a Spartan-II 100, even the smallest Spartan-II (XC2S15) can
> hold 1 and has still 40% free.
> all you have to add are the timers/PWM.
> This is easy, but this will change the project from a pure software issue to
> a FPGA/hardware issue.
>
> --
> MfG
> Falk

    Funny you should suggest that...  We have a working 4 axis dc servo motor
controller using the KCPSM  (50 MHZ ~25 MIPS) that fits easily in a XC2S100
with > 10KHZ sampling rate on all channels including 32 bit quadrature encoder
counters, PID+Feedforward loop, profile generation (48 bit accumulator) and
host interface logic. The KCPSM is amazingly small for it performance. One
thing we had to do was page the program and data memory, since 256 words of
either was not enough.

    We are now using our own 16 bit CPU (55 MHz 1 inst per clock) to be able to
do 8 axis plus fancy breakpoint/event logic in the same XC2S100. Our CPU is
nowhere near as clever or small as the KCPSM, but since it is simple VHDL, it
is easy to tweek...

Source for our whole KCPSM based motor controller + KCPSM source is freely
available should anyone want it...


Peter Wallace


Article: 42354
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 21 Apr 2002 14:12:33 -0400
Links: << >>  << T >>  << A >>
Johann Glaser wrote:
> 
> Hi!
> 
> > Come on, the Spartan-II(E)s are really cheap, have a look at
> >
> > www.nuhorizons.com
> 
> I see, an XC2S200-5PQ208 for US$ 26,25. But together with shipment and VAT
> (or customs) it goes up rapidely. At RS Components
> http://www.rs-components.at/ such a part costs EUR 64,46 (without VAT).
> This is double the price at nuhorizons. :-( (but RS at least has Spartan
> and Spartan-II at Austria (and Germany, I guess))
> 
> > even a poor student can afford them. So I really DONT like to play with
> > a just partly functioning IC, especially NOT for development. Debugging
> > you own mistakes is hard enough..
> 
> Nobody wants you to use partly defect ICs, I only thought to offer them.
> And that only makes sense if a detailed table with the tested errors is
> supplied. Or they give instructions how to test it by oneself.
> 
> I looked at the XC2V6000, which costs up to US$ 8700,--. That is somewhere
> at a small car. My question to somebody involved in production of such
> parts: Why are these parts that expensive? Please don't misunderstand me,
> I really accept the price. I simply don't have any idea what can make a
> chip that expensive.

The cost of a die is related to the costs of the wafer.  As others have
mentioned, the cost of large chips is not proportional to the size of
the die, but is an exponential function.  I have heard a rule of thumb
that it costs about $1K per wafer.  The cost of testing and packaging
must be added.  But to justify a $8000 price tag, there must be a rather
high profit margin.  

The bottom line is that you sell a chip for $8000 because you can. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 42355
Subject: Re: Some Questions about Pci configuration.
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 21 Apr 2002 13:28:34 -0500
Links: << >>  << T >>  << A >>
I think your question is not FPGA related, so you will like to repost
the question at news:comp.arch.embedded or other Linux related
newsgroups.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 42356
Subject: Re: FPGA books and tutorials ....
From: alw@al-williams.com (Al Williams)
Date: 21 Apr 2002 13:32:46 -0700
Links: << >>  << T >>  << A >>
> 
> So I'm looking for literature to teach beginners FPGAs.
> 
> Mister the Mayor.

Still under construction, but have a look at
http://www.al-williams.com/pictutor - There is a general slide show,
an Altera, and a Xilinx tutorial there in various stages of
completion. The hardware mentioned is not yet available, but the
Xilinx board will be very very soon.

Al Williams
AWC

Article: 42357
Subject: Re: NIOS ISS, MicroBlaze Cycle Accurate ISS
From: "Peter Ormsby" <faepete.deletethis@attbi.com>
Date: Sun, 21 Apr 2002 23:14:29 GMT
Links: << >>  << T >>  << A >>
Mark Aaldering <Mark.Aaldering@xilinx.com> wrote in message
news:3CC0C237.1C7C3467@xilinx.com...
> C-rob,
>
> Hmmmm - Peripherals don't by default cause the processor pipeline to
stall....unless I'm missing
> something about nios.
>
<snip>

Mark,

Creating a cycle-accurate simulator is quite a bit more complicated for a
processor system like Nios than it is for a processor like Microblaze.

The Nios internal bus is a non-blocking slave-side arbitrated bus.  What
this means is that custom-designed bus masters can be accessing a periheral
like a UART while the CPU is off doing something else.  If the CPU decides
that it now wants access to the UART, your cycle-accurate Instruction Set
Simulator (ISS) now needs to understand not only the arbitration scheme, but
also the behaviour of the user-created bus master #2 (or 3 or 4 or...).
Depending on the arbitration priorities, the custom bus master could hold
off the CPU several clock cycles.  How does your cycle-accurate Instruction
Set Simulator (ISS) account for these "hold-offs" without knowing anything
about how the custom-designed bus masters operate?

Even more interesting is what happens when you've created your own custom
instruction(s) in the Nios ALU.  Since custom instructions can interface to
user-created logic, I don't see how an ISS could accurately count cycles
without knowledge of the user-created hardware.  And just to make things
even more challenging for a cycle-accurate ISS, the user-created logic that
a custom instruction ties to can contain sequential logic so that an
instrution could take, for example, one clock cycle most of the time and
three clock cycles the rest of the time.  Once again, this makes a
cycle-accurate ISS practically impossible without knowledge of the other
hardware in the system.

Obviously, if you don't have all that flexibility in your system, it's
relatively easy to create a cycle-accurate ISS.  However, if your analysis
requires real clock-time simulation and you're designing in system with the
flexibility that Nios has (user-created bus masters, custom instructions,
etc) you need to have visibility into the rest of the system hardware to get
real timing information.  If you don't need the cycle-accurate simulation
(like the original poster), then the Nios ISS should satisfy the need.

-Pete-



Article: 42358
Subject: Re: Constraint editor error
From: rjshaw@iprimus.com.au (russell)
Date: 21 Apr 2002 17:25:16 -0700
Links: << >>  << T >>  << A >>
rjshaw@iprimus.com.au (russell) wrote in message news:<c3771dbf.0204210606.370af858@posting.google.com>...
> Hi,
> 
> When i do "Design Entry Utilities...

Doesn't matter now; rebooting the pc fixed it.

Article: 42359
Subject: Is the following Spartan-II FG456 package LogiCORE PCI pinout correct?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 22 Apr 2002 00:05:19 -0500
Links: << >>  << T >>  << A >>
        Hi, I will like to know if the following pinout is the correct
pinout LogiCORE PCI uses for a Spartan-II FG456 package.
I copied off a schematics I found from some website, however, the
application was using LogiCORE PCI as a host bridge, so I am not sure if
the pinout is correct for use in a PCI expansion card.
The Xilinx doesn't seem to want to give out pinout information LogiCORE
PCI uses unless I pay them several thousand dollars for a LogiCORE PCI
license.
I am poor and I did (doing) my own PCI IP core, so I have no intention
of licensing LogiCORE PCI.
However, I still want to use the same pinout Xilinx used because use of
a different pinout can adversely affect timings.
Here is the pinout I copied off the schematics I am talking about.



________________________________________________________________
NET "CLK" LOC = "C11";
NET "RST_n" LOC = "F5";
NET "AD<63>" LOC = "Y16";
NET "AD<62>" LOC = "V15";
NET "AD<61>" LOC = "AB17";
NET "AD<60>" LOC = "AB16";
NET "AD<59>" LOC = "Y15";
NET "AD<58>" LOC = "AA15";
NET "AD<57>" LOC = "AB15";
NET "AD<56>" LOC = "V14";
NET "AD<55>" LOC = "AA14";
NET "AD<54>" LOC = "V13";
NET "AD<53>" LOC = "Y13";
NET "AD<52>" LOC = "AA13";
NET "AD<51>" LOC = "AB13";
NET "AD<50>" LOC = "AA12";
NET "AD<49>" LOC = "Y12";
NET "AD<48>" LOC = "U12";
NET "AD<47>" LOC = "AB11";
NET "AD<46>" LOC = "W11";
NET "AD<45>" LOC = "V11";
NET "AD<44>" LOC = "Y10";
NET "AD<43>" LOC = "AB10";
NET "AD<42>" LOC = "W10";
NET "AD<41>" LOC = "Y9";
NET "AD<40>" LOC = "AB9";
NET "AD<39>" LOC = "V9";
NET "AD<38>" LOC = "AA8";
NET "AD<37>" LOC = "Y8";
NET "AD<36>" LOC = "W8";
NET "AD<35>" LOC = "W7";
NET "AD<34>" LOC = "AA7";
NET "AD<33>" LOC = "AB6";
NET "AD<32>" LOC = "AB5";
NET "AD<31>" LOC = "G5";
NET "AD<30>" LOC = "F3";
NET "AD<29>" LOC = "E2";
NET "AD<28>" LOC = "E1";
NET "AD<27>" LOC = "H5";
NET "AD<26>" LOC = "F2";
NET "AD<25>" LOC = "F1";
NET "AD<24>" LOC = "H4";
NET "AD<23>" LOC = "H2";
NET "AD<22>" LOC = "J5";
NET "AD<21>" LOC = "J2";
NET "AD<20>" LOC = "K5";
NET "AD<19>" LOC = "K1";
NET "AD<18>" LOC = "K3";
NET "AD<17>" LOC = "K4";
NET "AD<16>" LOC = "L6";
NET "AD<15>" LOC = "P2";
NET "AD<14>" LOC = "P4";
NET "AD<13>" LOC = "P3";
NET "AD<12>" LOC = "R2";
NET "AD<11>" LOC = "T1";
NET "AD<10>" LOC = "R4";
NET "AD<9>" LOC = "T2";
NET "AD<8>" LOC = "U1";
NET "AD<7>" LOC = "U2";
NET "AD<6>" LOC = "T3";
NET "AD<5>" LOC = "T4";
NET "AD<4>" LOC = "W1";
NET "AD<3>" LOC = "U4";
NET "AD<2>" LOC = "Y1";
NET "AD<1>" LOC = "W2";
NET "AD<0>" LOC = "Y2";
NET "C_BE_n<7>" LOC = "Y6";
NET "C_BE_n<6>" LOC = "AA4";
NET "C_BE_n<5>" LOC = "W6";
NET "C_BE_n<4>" LOC = "Y7";
NET "C_BE_n<3>" LOC = "G1";
NET "C_BE_n<2>" LOC = "L1";
NET "C_BE_n<1>" LOC = "N4";
NET "C_BE_n<0>" LOC = "R5";
NET "PAR" LOC = "N3";
NET "IDSEL" LOC = "H3";
NET "FRAME_n" LOC = "L4";
NET "IRDY_n" LOC = "L3";
NET "DEVSEL_n" LOC = "M3";
NET "TRDY_n" LOC = "M1";
NET "STOP_n" LOC = "M4";
NET "PERR_n" LOC = "M5";
NET "SERR_n" LOC = "N2";
NET "REQ_n" LOC = "D2";
NET "GNT_n" LOC = "B1";
NET "INTA_n" LOC = "E3";
NET "M66EN" LOC = "R1";
NET "REQ64_n" LOC = "V7";
NET "ACK64_n" LOC = "W3";
NET "PAR64" LOC = "AA5";
________________________________________________________________





Thanks,



Kevin Brace

Article: 42360
Subject: Wanted: Standard LogiCORE PCI pinout of various Xilinx FPGAs
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 22 Apr 2002 00:05:24 -0500
Links: << >>  << T >>  << A >>
Hi, I will also like to know the standard LogiCORE PCI pinout of various
Xilinx FPGAs.
The ones I am interested are: Virtex BG352, FG256, and FG680 package,
Spartan-II FG256 and FG456 package, Virtex-E BG432, FG256, FG676, and
FG680 package, Spartan-IIE PQ208 and FG456 package, and Virtex-II FG456
package.
Whoever willing to share the pinout information can E-mail me (Remove
"ihatespam99" twice.), or post the information here.



Thanks,



Kevin Brace

Article: 42361
Subject: Re: Using Virtex-II DCM to determine clock activity
From: Patrik Eriksson <patrik.eriksson@netinsight.net>
Date: Mon, 22 Apr 2002 05:18:24 GMT
Links: << >>  << T >>  << A >>


Austin Lesea wrote:

> Patrik,
> 
> The CLKIN_STOPPED status bit will tell you if the input to the DCM has
> stopped, and the LOCKED signal will tell you if it has gone unstable (ie
> lose lock).
> 
> The problem is that the BUFGMUX switches only between two transistioning
> clocks:  if you stop one or the other, it does not switch, as it is a state
> machine that requires both clocks to be present.  You may use a mux made
> from the CLB instead to control the source clock.  Delay is now not
> controlled, so you would need to use a third DCM to deskew the new clock if
> deskew is needed.  Otherwise get on the BUFG clock tree and go to work.


OK! I understand that I can't use the BUFGMUX for this purpose.
The clock has to be deskewed.


> 
> I would mux between CLKA input, and CLKB input, based on CLKIN_STOPPED OR
> NOT(LOCKED), and not use the CLK0 outputs of the DCM's, and pass the
> selected clock from the mux to the CLKIN of the third DCM for deskew.  That
> way, there is no jitter accumulation going through two DCMs.  The first DCMs
> are only used as clock monitors.


I didn't know that you were allowed to feed a DCM from CLB logic. 
Unfortunately I only have two DCM left in my design, but the primary 
function is to MUX between a non existing clock and an existing clock. 
The automatic detection is not a requirement but it would be nice.

If I can put user logic between the IBUFG and the DCM then there is no 
problem. I this is OK I will put one MUX on the input clocks and feed 
the MUX output to one DCM. The MUX control signal will be set during the 
reset phase of the design (by system software).


> 
> One would almost surely have to reset the third DCM after a switch to be
> sure you don't unhinge the third DCM by the asynchronous switch froma  bad
> clock, to the good clock.


OK When the correct clock input is selected the DCM will be reset!


> 
> Austin
> 
> 
> Patrik Eriksson wrote:
> 
> 
>>Hi,
>>
>>I have a design where the input clock is driven from one of two sources
>>depending on board configuration i.e. either from osc. A or from osc. B.
>>The two oscillators are never connected at the same time.
>>Each of the two input clocks are connected to one DCM respectively.
>>The clk0 output from the two DCMs are connected to an BUFGMUX which is
>>used to select which of the two input that should be used for the
>>internal clock. Is it possible to use the status output from the DCM(s)
>>to determine which clock input to use, i.e. control the BUFGMUX?
>>
>>                                         FPGA
>>                    +-------------------------------------------+
>>                    | +----------------+                        |
>>+-----+            | | +---+  fb      |                        |
>>| osc.|       _    | +-|DCM|          |                        |
>>|  A  |----->(_)---|-->|in |---+  +   |                        |
>>+-----+            |   |   |   |__|\  |                        |
>>                    |   +---+      | \_|___internal_clk         |
>>+-----+            |   +---+    __| / |                        |
>>| osc.|       _    |   |DCM|   |  |/| |                        |
>>|  B  |----->(_)---|-->|in |---+    | |                        |
>>+-----+            | +-|   |--------+ |                        |
>>                    | | +---+ status(1)|                        |
>>                    | |                |                        |
>>                    | +----------------+                        |
>>                    |          fb                               |
>>                    |                                           |
>>                    +-------------------------------------------+
>>
>>Thanks in advance
>>
>>Patrik Eriksson
>>
>>--
>>Patrik Eriksson              |  patrik.eriksson@netinsight.net
>>Net Insight AB               |  phone:  +46 8 685 04 89
>>Västberga Allé 9             |  fax:    +46 8 685 04 20
>>SE-126 30 STOCKHOLM, Sweden  |  http://www.netinsight.net
>>
> 


Thanks
/Patrik



-- 
Patrik Eriksson              |  patrik.eriksson@netinsight.net
Net Insight AB               |  phone:  +46 8 685 04 89
Västberga Allé 9             |  fax:    +46 8 685 04 20
SE-126 30 STOCKHOLM, Sweden  |  http://www.netinsight.net


Article: 42362
Subject: Re: Is the following Spartan-II FG456 package LogiCORE PCI pinout
From: Russell <rjshaw@iprimus.com.au>
Date: Mon, 22 Apr 2002 06:28:18 GMT
Links: << >>  << T >>  << A >>
Kevin Brace wrote:
> 
>         Hi, I will like to know if the following pinout is the correct
> pinout LogiCORE PCI uses for a Spartan-II FG456 package.
> I copied off a schematics I found from some website, however, the
> application was using LogiCORE PCI as a host bridge, so I am not sure if
> the pinout is correct for use in a PCI expansion card.
> The Xilinx doesn't seem to want to give out pinout information LogiCORE
> PCI uses unless I pay them several thousand dollars for a LogiCORE PCI
> license.
> I did (doing) my own PCI IP core...

Out of curiosity, do you need much test gear for doing
a PCI core? How hard is it to verify it's working right
in windows?

Article: 42363
Subject: Post-synthesis simulation
From: izuazua@ikerlan.es (Itsaso Zuazua)
Date: 21 Apr 2002 23:59:15 -0700
Links: << >>  << T >>  << A >>
Hi, 

 I have problems when I want to do a post-synthesis pre-place and
route simulation in Modelsim. I have synthetized a VHDL design in a
apex20ke (an FPGA family of Altera), and I have obtained another VHDL
design which is an FPGA-independent netlist ready for place and
route.This post-synthesis design exported from the synthesis tool give
me errors when I simulate it. Should I compile another library in my
work directory,first?Where could I find the entity´s architectures,
wich are instantiated in this vhdl design?


      Thanks, a lot.
                     Itsaso Zuazua

Article: 42364
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: Jens Hildebrandt <jens.hildebrandt@etechnik.uni-rostock.de>
Date: Mon, 22 Apr 2002 09:10:54 +0200
Links: << >>  << T >>  << A >>


Falk Brunner wrote:
> 
> "Johann Glaser" <Johann.Glaser@gmx.at> schrieb im Newsbeitrag
> news:a9q3it$5enur$1@ID-115042.news.dfncis.de...
> 
> > Would it be possible to offer medium size and large size parts (like
> > XC2S200, ...) for hobbyists, prototyping (or even production) at a really
> > low price, but with some small errors. E.g. that one or several (of the
> > many available) CLBs are defect.
> 
> Come on, the Spartan-II(E)s are really cheap, have a look at
> 
> www.nuhorizons.com
> 
> even a poor student can afford them. So I really DONT like to play with a
> just partly functioning IC, especially NOT for development. Debugging you
> own mistakes is hard enough..
> 
>  --
> MfG
> Falk
> 
> P.S. There is no real possibility to get single quantities of the fine
> Xilinx parts in germany (for hobby stuff) :-(

Hm, I got my two XC2S100-4TQ144 for EUR 27,00 at HOT-Electronic (see
www.hot-electronic.de for their phone numbers). Not too bad price, I think. Just
call them and ask.

Jens


Article: 42365
Subject: Re: XC9500XL problem
From: "Dziadek" <dziales@poczta.onet.pl>
Date: Mon, 22 Apr 2002 10:03:46 +0200
Links: << >>  << T >>  << A >>
I have been fighting a similar problem recently. My advice is:
1) Check the supply voltage during power-up. It shall start possibly fast
and in a monotonic way (no trip down). There is a point at approx. 2.5V when
XC95..XL consume more current - check voltage rise at this point. Make the
supply start time as short as possible.
2) Search Xilinx Answer Records - there are two records (don't have exact
number) that deal with it. There have been some production lots that have
had problems at low temp.

Regards,
Dziadek


Jim Raynor wrote in message ...
>hi guys,
>
>    I used the CPLD XC95288XL in my design and the program used up 97% of
>the macrocells of that CPLD.  Functional and Timing simulation were done
and
>everything is good.  However, my co-workers kept complaining the CPLD was
>mulfuntion sometimes.  I tried to reproduce the problem that he was having
>but I couldn't, the CPLD worked for me everytime.  I started to check the
>VHDL program and the signals using scope but they  looked fine for me.
>The problem for the CPLD kept coming.  He experienced that the problem
>happened 3 times out of 10 times when he powered up the CPLD.  And he said
>the problem happened everytime when he first powered up the CPLD when he
>came in in the morning.
>
>    I started thinking of it and I thought it might be the temperature
>problem.  So, I tried to reproduce the problem again by cooling down the
>CPLD with a can coke (!!put the ice cold can coke on the top of the CPLD
for
>30 secs) and powered that up afterward.  And I got that CPLD problem
>everytime now when I actually let the CPLD cool down and re-powered up.
>
>    Now I have solved the problem by putting some of the CPLD tasks into
the
>u-controller that used in the same system. And the new program only used up
>79% of the macrocells.
>
>    So I am wondering what did happen to the CPLD when the macrocells is
>almost used up?  Did you guys experience something like that before?
>
>Jim Raynor
>
>



Article: 42366
Subject: Signal saturation
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Mon, 22 Apr 2002 10:10:57 +0200
Links: << >>  << T >>  << A >>
Hi,

I was wondering if anyone can point me to any references on detecting of
saturated signals in the context of signal processing. Of course, you can go
with the brute force method of saying that whenever a signal goes beyond the
maximum input value, it is saturated, but there seems to be a complete lack
of statistical support in this method.

Thanks
Adrian




Article: 42367
Subject: Re: RAM function in Altera device
From: Graeme Gill <graeme_SPAMNOT@colorbus.com.au>
Date: Mon, 22 Apr 2002 19:22:31 +1000
Links: << >>  << T >>  << A >>
Marco Serafini wrote:
> in my design I'm using the Altera parameterized RAM function named
> lpm_ram_dq. MAX+PLUS II software automatically  implements suitable
> portions in the EABs of a FPGA device (ACEX 1K).
> I'm using a HEX File containing initial values for the memory to be
> passed to the compiler. After configuring the SRAM-based device, by a
> serial configuration device, the initialization memory data is loaded
> properly except the last memory location.
> Have you ever found such problem? Maybe a wrong parameters setting?

We recently came across a similar bug in Max+Plus II. Flex 10K,
with Auto EAB's on, writes to the RAM cells would sometimes write
to two adjacent locations, rather than just the one being addressed !
(Showed up in the simulator as well as real life).

Turning auto EAB off, made the problem go away. Either a bug in
the synthesizer, or some side effect of using EAB's to implement
ram decode or addressing logic ?

Graeme Gill.

Article: 42368
Subject: FoxFire II PCI Latency cards
From: point308@hotmail.com (point308)
Date: 22 Apr 2002 02:37:26 -0700
Links: << >>  << T >>  << A >>
Hello, 
Has anyone on this group used, or thought of using the FoxFire II PCI
test card for testing an FPGA implementation of a PCI bus interface?

I have a few of these cards and I'm wondering if I should sell them or
keep them until I get around to implementing my own PCI interface. 
They are US $995 new.
Any thoughts on their suitability are welcome. 
Thank you, 
Mark. 
---------------------------------

Here's some info from the website: 
http://www.pcisig.com/developers/test_card

"FoxFire II

Monitoring of write-latency,
Monitoring of TRDY latency 
BIOS testing, 
Power Management compliance testing . "

..."The second test capability tests two features. The first is that
it monitors all PCI traffic, looking for PCI transactions that don't
meet the 16-clock initial latency requirement. If a violation is
detected, the offending address is captured. The second feature tests
the Maximum Completion Time requirement that is an ECR to the 2.1 spec
and a part of the PCI 2.2 spec. The card monitors PCI memory write
transactions and will flag any write transaction that doesn't make
progress for 10 microseconds. Software for these tests is available
for both Win9x and NT4.0.

Anyone building a PCI component should use this test card as part of
their qualification testing to be sure that their product conforms
with the Initial Latency and Maximum Completion Time requirements.

The test card is a standard 32-bit, 33 MHz PCI addin card. All
software is for PC-compatible machines. Hardward documentation is
included so that test software can be written for other machine
architectures. "...

Article: 42369
Subject: Re: Simulating Unisim
From: Renaud Pacalet <pacalet@enst.fr>
Date: Mon, 22 Apr 2002 13:30:25 +0200
Links: << >>  << T >>  << A >>
Paulo Valentim a écrit :

Hi Paulo,

> I am having a tough time trying to simulate the following which
> was coded for the VIRTEX-E:
> 
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;

This has nothing to do with your problem but I mention it anyway: if
your tools support it you should use ieee.numeric_std instead of the
non standard ieee.std_logic_arith.

> 
> -- pragma translate_off
> library unisim;
> use unisim.vcomponents.all;

Another point that has nothing to do with your problem: as you're
using the vcomponents package of unisim library it could be that you
don't need to re-declare the BUFG, CLKDLL and SRL16 components.
Check the vcomponents package. By the way, why do you translate_off?

>...
> 
> I cannot use CLKDLLE because Leonardo Spectrum does not support
> it. But anyways, I cannot simulate this. I have compiled the
> unisim files for modelsim SE using the xilinx_lib_4.tcl script
> with no problems. But still when I load the code into Modelsim, it
> gives me "component not bound" warnings and the simluation doesn't
> work. HELP!!!

Unbound components are component instances that the elaborator did
not bound to an entity/architecture or to a configuration. In order
to bound your instances you need a configuration:

library unisim;

configuration clock_4x_cfg of clock_4x is
  for rtl
    for all: CLKDLL
      use configuration unisim.CLKDLL_cfg;
    end for;
    for U2: SRL16
      use entity unisim.SRL16(arc);
    end for;
  end for;
end clock_4x_cfg;

Write a configuration too for your testbench in order to configure
the instance of clock_4x:

configuration testbench_cfg of testbench is
  for sim
    for all: clock_4x
      use configuration work.clock_4x_cfg;
    end for;
  end for;
end testbench_cfg;

Elaborate testbench_cfg and it should be OK.

Hope it helps. Regards,

Renaud.
-- 
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.fr
###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ######

Article: 42370
Subject: Re: Simulating Unisim
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Mon, 22 Apr 2002 13:04:35 +0100
Links: << >>  << T >>  << A >>
Hi Renaud,

In article <aa0sfm$1089$1@avanie.enst.fr>, Renaud Pacalet
<pacalet@enst.fr> writes

>Unbound components are component instances that the elaborator did
>not bound to an entity/architecture or to a configuration. In order
>to bound your instances you need a configuration:

For your information, and with no criticism intended:  "bound" is 
past tense, or past participle (= lié ?);  the present tense is 
"bind", or "binds" for third person singular.

I wish my French were a tenth as good as your English.

Cheers
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 42371
Subject: Re: clock management in Virtex-E (DLL)
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 22 Apr 2002 14:40:54 +0200
Links: << >>  << T >>  << A >>
"H.L" <alphaboran@yahoo.com> schrieb im Newsbeitrag
news:a9ut0b$ne9$1@ulysses.noc.ntua.gr...

> The fast clock has fanout=82 while the divided by 2 clock has fanout=397,
> this means that the slow clock has almost 5 times the load of the fast
> clock? If yes is this very bad? (Timing analyzer reports no timing errors)

I dont know how strong the buffers (and the net behind) are. From the first
sight I would say, that there is a possibility of skew problems, but this is
just a rough estimate. Ray Andraka reported problems with skew of ~500ps.
If you want to transfer data between the clock nets, use a asynchronous
FIFO, this makes the transfer bullet proof. If you have to transfer control
signals, use the opposite clock edge.

> A question for the second DLL you suggested me to remove: how can I
> eliminate the divided clock's skew if I dont use a DLL to control it?

Good question. I dont know, since AFAIK the DLL cant deskew a divided clock
(just a x1 and x2)

> You wrote thay the delay noticed in my post-MAP (and PAR) simulations is
> owing to the bufg delay (6.44-4=2.4 ns), the 4 in the equation represents
> what?

The 4 ns of delay you noted.

> And the last question to clarify things, you say that clk0 and clkdv are
> (should be) in phase. You mean that despite of the simulation phase
> difference, in my FPGA these 2 clocks are in phase? Is this delay owing to

Hmm, If I got you drawing right (better use a fixed font without tabs next
time), you compare the phase og the 155MHz internal clock BEHIND the clock
buffer to the CLKDV output of the DLL. This can hardly work, since there is
lot of delay in the buffer.

> the way the simulator handles the FPGA delays and not an implementation
> "problem"?
> What about the post-PAR simulation I want to run to verify the correct
> operation of the FPGA, if I have a phase difference between the 2 clocks
how
> can I simulate my FPGA correct?

You could leave out the DLL and create the skewed clock on your own.

--
MfG
Falk




Article: 42372
Subject: Re: 8051 Core for Motor Electronics
From: Klaus_Leiss@ccl.hdpp.de (Klaus-Guenter Leiss)
Date: 22 Apr 2002 13:08:51 GMT
Links: << >>  << T >>  << A >>
In article <3CC2FE32.CA0E76CE@mesanet.com>, pcw@mesanet.com says...
>
>
>
>Source for our whole KCPSM based motor controller + KCPSM source is freely
>available should anyone want it...
>
>
>Peter Wallace
>

You could put it on opencores ( http://www.opencores.org/ )
if you dont mind. This way it would be available even if
you or your company would no longer want do support it. Also
since opencores is fairly known it would be easier to find
for people looking for such a core.

With kind regards

Klaus Leiss





Article: 42373
Subject: FPGA Express problems
From: Sasa Bremec <sasa@i-tech.si>
Date: Mon, 22 Apr 2002 16:02:02 +0200
Links: << >>  << T >>  << A >>
Hi!


Let me explain my synthesize problems of VHDL code

I have a design with few models (state machine, counter, s2p shifter...) 
when i put all this moduls together, the syntax is OK, but here comes 
the problem. When i start the synthesize tool i get this error

 >> Clock variable 'CLK' is being used as data <<

I don't  know what to do, i have used CLK only as process signal and 
always in 'event statemant.

Can any one help me?


Sash


Article: 42374
Subject: Re: ModelSim closes for unknown reason
From: "Phil Connor" <p.connorXXX@optionYYY.com>
Date: Mon, 22 Apr 2002 14:20:43 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0204191457.116c47fb@posting.google.com...

> In 5.4 of Modelsim PE I had similar behaviour that ended up being
> caused by improper port connections.  Try loading your design starting
> with a lower level of heirarchy and keep moving up untill it crashs,
> then check ports.
> 


Hi Jay,

Many thanks for the advice, I tried it and it works, I'm happy.

A mismatch had crept in when I swapped some modules.

Thanks

Phil


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