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Messages from 50625

Article: 50625
Subject: Re: SpartanII Internal Clock ?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 14 Dec 2002 15:14:57 GMT
Links: << >>  << T >>  << A >>
Well, sort of.  You could put a ring oscillator in there and divide it down.
You may have trouble with frequency consistency over voltage, temp, and process
however.  Without an external reference there is no guarantee that a design for
a particular frequency will be that frequency when those parameters are varied.

Rob Finch wrote:

> Is it possible to generate an internal clock signal in the range 20MHz-30MHz
> inside the Spartan2 ?
>
> Thanks,
> Rob

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 50626
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 14 Dec 2002 20:18:29 -0000
Links: << >>  << T >>  << A >>
Stephen Williams wrote
> Tim wrote:
> > Now there is yet another implementation of the Logic Analyzer
> > part, with some extra stuff added.  You can check out
> > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected
> > (USB-powered) Logic Analyzer.
>
> I don't suppose there is any sort of Linux support for this device?

The weeks after first shipment generate an interesting wish list :-)
Currently the major items on the software wish list stand at

  1. separate the GUI and the back-end software so the
     Ant8 can be driven by any program
     This is in testing.
  2. allow remote control of the Ant8 across a network
     This is dependent on 1 and comes real soon now.
  3. add Linux support
     Currently unscheduled.  Really depends on customer feedback.

There are other small cosmetic changes and various possible
firmware enhancements - the phrase "small cosmetic changes"
covers a suprising range in a manufacturer's lexicon :-)

Tim




Article: 50627
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 14 Dec 2002 20:24:54 -0000
Links: << >>  << T >>  << A >>
Eric Smith wrote
> Tim writes:
> > Now there is yet another implementation of the Logic Analyzer
> > part, with some extra stuff added.  You can check out
> > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected
> > (USB-powered) Logic Analyzer.
>
> Nice, and the price is quite attractive.
>
> Does it support adjustable thresholds?  If not, what are the
> standard thresholds?
>
> Any plans for a unit with more channels?

We have prototyped an embarrassing range of channel configurations,
but it is quite difficult to get plastics for the big numbers at an
acceptable price.  And the customers all said the same thing: "Since
you are not HP, the price had better be throw-away"

If this one works out, bigger stuff will surely follow, but we have
no firm plans.




Article: 50628
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 14 Dec 2002 20:29:22 -0000
Links: << >>  << T >>  << A >>
rickman wrote
>                                                       a better way to
> connect to the target is needed.  Microclips went out with DIPs.  On our
> last board we added 20 pin debug connectors which were pin compatible
> with HP logic analyzer probes when used with their adapters.  This was
> very nice since it allowed us to connect to the various busses on the
> board by simply plugging in the adapter.

The probe stuff is the "most inexpensive possible arrangement which is
not made from duct tape"  You can use any probe arrangement you like,
provided it plugs into the D-type on the Ant8.  And as you point out,
you cannot rely on getting the best results with the cheapest probes.

> Also, does the software allow more than one pod to be used with a common
> display?

Nope.  Though you can run multiple pods.




Article: 50629
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 14 Dec 2002 20:32:19 -0000
Links: << >>  << T >>  << A >>
Jay wrote
> Are you using Chipscope?

Nope.  It is a custom design.  Actually it is several custom
designs.  The configuration bitstream loaded into the Ant8 is
chosen on the basis of the requested sampling speed - 100Hz
and 500MHz require different techniques in parts of the design :-)

Tim




Article: 50630
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 14 Dec 2002 20:35:00 -0000
Links: << >>  << T >>  << A >>
Nicholas C. Weaver wrote
> Tim  wrote:
> >Now there is yet another implementation of the Logic Analyzer
> >part, with some extra stuff added.  You can check out
> >www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected
> >(USB-powered) Logic Analyzer.
>
> Nifty.
>
> Out of curiosity, what's the FPGA and how do you handle config (just a
> config prom?).

Real-time download.  We run the USB link at 12MHz, so configuration
is pretty quick.  A small PAL on the Ant8 takes config data from USB
and generates an FPGA serial stream.




Article: 50631
Subject: Re: hardware image processing - log computation
From: davem@cs.ubc.ca (Dave Martindale)
Date: Sat, 14 Dec 2002 20:43:46 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Kip Ingram" <Kip@NOkipSPAMingram.rom> writes:
>Good point.  That means you'd know how many terms you'd have to take in the
>polynomial to get a sufficiently accurate result.  Then the 2^N part just
>requires that you add N*log(2).

And if you're calculating base-2 logs (which makes more sense for this
applications than base-e or base-10 logs), the "N" constant becomes 1
and vanishes.  No multiply needed at all.

	Dave

Article: 50632
Subject: Quartus does not start on Windows ME
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sat, 14 Dec 2002 22:52:14 GMT
Links: << >>  << T >>  << A >>
I know, that Windows ME is not official supported by Altera. But an older
version of Quartus did run under Windows ME. And ME is just Windows 98 just
Windows 95. The problem (in ver. 2.1 and 2.2):

After starting Quartus I get a message box with: ...\QUARTUS.EXE abnormal
program termination. And that's it.

Any ideas?

Thanks
Martin
--
JOP - a Java Optimized Processor for FPGAs.
http://www.jopdesign.com




Article: 50633
Subject: Re: Two clocks for the same module
From: Mike Treseler <tres@fluke.com>
Date: Sat, 14 Dec 2002 15:01:01 -0800
Links: << >>  << T >>  << A >>
Jay wrote:

> I think you're on a wild goose chase with the metasability stuff.  The
> solution you are going to use is to have just one clock and then use
> the other edge sensitive signal to generate a synchronous pulse (via a
> synchronous edge detector) and use that as an input.


Well said. 99.999% of the problems associated with 

multiple clock domains or unsynchronized inputs
are a result of a logic race not a metastable event.

The output goes wrong because an input sets up
as both '1' and '0' at different registers.
A metastable event might compound the problem
one a century, but this is a mosquito.
The logic race is the charging rhinoceros.

        -- Mike Treseler


Article: 50634
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 14 Dec 2002 22:01:59 -0500
Links: << >>  << T >>  << A >>
Tim wrote:
> 
> rickman wrote
> >                                                       a better way to
> > connect to the target is needed.  Microclips went out with DIPs.  On our
> > last board we added 20 pin debug connectors which were pin compatible
> > with HP logic analyzer probes when used with their adapters.  This was
> > very nice since it allowed us to connect to the various busses on the
> > board by simply plugging in the adapter.
> 
> The probe stuff is the "most inexpensive possible arrangement which is
> not made from duct tape"  You can use any probe arrangement you like,
> provided it plugs into the D-type on the Ant8.  And as you point out,
> you cannot rely on getting the best results with the cheapest probes.
> 
> > Also, does the software allow more than one pod to be used with a common
> > display?
> 
> Nope.  Though you can run multiple pods.

One of your other posts said you had customers who would not buy your
device if it was not very, very cheap.  I suggest that you can be too
cheap.  We have *no* requirement for an 8 channel logic analyzer since
we have no designs where we only need to consider 8 channels at a time. 
If you can't accommodate more channels either though ganging of probes
or with wider probes, I can't see an application for this device with
the boards we design.  

As to the probing, cheap may be good, but if you provide a sixteen input
(plus clock) probe like HP has and make it pin compatible with the HP
probe, then this will be a usefull attachment.  The HP probe attach is
just a 20 pin ribbon cable connector.  I don't think this is
significantly more expensive than the sub-D connector.  

But again, without a 16 input probe and software to allow multiple
probes to be ganged, this is not a useful product for debugging our
boards.  Not trying to criticize, just giving some feedback.  Thanks for
listening.  That is something I don't feel like I get much from HP.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 50635
Subject: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
From: hamish@cloud.net.au
Date: 15 Dec 2002 08:01:25 GMT
Links: << >>  << T >>  << A >>
Kate Kelley <kate.kelley@xilinx.com> wrote:
> 
> I don't believe you want to use the DESKEW_ADJUST attribute.  This attribute is used if
> you are doing a source-synchronous designs as described in different Xilinx Source-Sync
> application notes.  Your clocking scheme does not match what Xilinx suggests.  If you are
> trying to line up a clock with the I/O, I would used the FIXED_PHASE_SHIFT attribute to
> adjust the phase of the clock.

Is there a difference between system synchronous with a phase shift of X
and source synchronous with a phase shift of Y?

I have had source synchonous working since before Xilinx offered this
feature; is there any advantage in switching, given that we have already
determined the appropriate phase shift for our application?


Thanks,
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 50636
Subject: Re: Quartus does not start on Windows ME
From: "Leon Heller" <leon@heller123.freeserve.co.uk>
Date: Sun, 15 Dec 2002 12:03:06 -0000
Links: << >>  << T >>  << A >>

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:yCOK9.20027$TA6.195082@news.chello.at...
> I know, that Windows ME is not official supported by Altera. But an older
> version of Quartus did run under Windows ME. And ME is just Windows 98
just
> Windows 95. The problem (in ver. 2.1 and 2.2):
>
> After starting Quartus I get a message box with: ...\QUARTUS.EXE abnormal
> program termination. And that's it.

Quartus II 2.1 works OK for me under Win ME.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 50637
Subject: Could you explain compact PCI, PCI and PCI bridge to me?
From: "Jeff" <dsfdsaf@hotmail.com>
Date: Sun, 15 Dec 2002 07:25:02 -0500
Links: << >>  << T >>  << A >>
Hi,
Recently my work is related one PMC board. The compact PCI, PCI and PCI
bridge come to me from different documatations. Some of the PCI boards are
quite large from photographs. What's the PCI slot in my PC computer at home?
It's a 33MHz 32 bit PCI normally?
Could you give me an explanation? Or some websites?
I have browsed www.pcisig.com, not too much help from there.


Thanks,




Article: 50638
Subject: Re: RPM Using ISE5.1i FloorPlanner
From: hamish@cloud.net.au
Date: 15 Dec 2002 12:30:35 GMT
Links: << >>  << T >>  << A >>
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote:
> Note that Floorplanner doesn't fully support RPM_GRID yet.

This needs to be fixed urgently, IMHO. The FPGA Editor is not the right
tool to use to look at macros but it is the only tool which can work
with the RPM_GRID.

5.1i's Floorplanner is IMHO a significant step back from 4.2i. Many of
the features seem to have moved to PACE and unfortunately been ruined in
Floorplanner in the process.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 50639
Subject: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
From: hamish@cloud.net.au
Date: 15 Dec 2002 12:35:05 GMT
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote:
> boards.  Not trying to criticize, just giving some feedback.  Thanks for
> listening.  That is something I don't feel like I get much from HP.  

You should probably talk to Agilent about logic analysis these days
instead :-)


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 50640
Subject: virtex PRO migration cost
From: nahum_barnea@yahoo.com (Nahum Barnea)
Date: 15 Dec 2002 06:20:24 -0800
Links: << >>  << T >>  << A >>
Hi ,
I consider the usage of virtex2 pro as a prototype for a chip.

I wonder what is the effect of the PowerPC 405 processor over the ease
of migration from fpga to an ASIC ?
Does it limit my ASIC vendor list to be only IBM ?

ThankX,
NAHUM.

Article: 50641
Subject: Re: Could you explain compact PCI, PCI and PCI bridge to me?
From: "Roger Green" <rgreen@bfsystems.com>
Date: Sun, 15 Dec 2002 09:40:03 -0700
Links: << >>  << T >>  << A >>
Hi Jeff,

The PCI slot in your PC is most likely 32-bit, 33MHz flavor.  You most
likely will have to look in very new hi-end computers or "server" type
platforms to find 64-bit, 66 MHz type PCI slots. PCI is the standard card
edge connector form factor.

CompactPCI is essentially the same protocol, but an entirely different form
factor.  It is based on "Euro-card" packaging and is in a "3U" or "6U" high
card which plugs into rack-mount cages. The card connector is a metric
pin/socket style and the whole system looks a lot like VME, if you're
familiar with that.

A PCI "bridge" refers to a chip/component that translates between multiple
PCI buses.  Since the speed of PCI allows a very limited number of "slots"
on a single PCI bus, it is common to arrange multiple PCI bus segments in a
"tree" arrangement. The PCI specification supports this in its addressing
scheme.  The "passive backplanes" used in CompactPCI systems commonly have
bridges incorporated to provide many card slots on a single backplane.

If you're interested in learning all the gory details of PCI, I would
recommend the book "PCI System Architecture" published by Mindshare, Inc.
Its a very good reference and is easier to understand that the PCI sig's
specifications, which they want $ for anyway.
--
Roger Green
B F Systems - Electronic Design Consultants
www.bfsystems.com


"Jeff" <dsfdsaf@hotmail.com> wrote in message
news:ly_K9.17$iQ3.16548@news20.bellglobal.com...
> Hi,
> Recently my work is related one PMC board. The compact PCI, PCI and PCI
> bridge come to me from different documatations. Some of the PCI boards are
> quite large from photographs. What's the PCI slot in my PC computer at
home?
> It's a 33MHz 32 bit PCI normally?
> Could you give me an explanation? Or some websites?
> I have browsed www.pcisig.com, not too much help from there.
>
>
> Thanks,
>
>
>



Article: 50642
Subject: EDIF LPM Support in Synthesis
From: tomahawkins@yahoo.com (Tom Hawkins)
Date: 15 Dec 2002 09:29:45 -0800
Links: << >>  << T >>  << A >>
Hello,

What synthesis tools accept EDIF LPM as an input format?
To what level is LPM supported?

I couldn't find a definitive answer just browsing
Synplicity's and Mentor's site.  Synopsys Design Compiler
collection mentions edif, but not specifically lpm.

What is the state of LPM?  It seems like its been around
for a while, but rarely mentioned on the web.

Thanks,
Tom

Article: 50643
Subject: Re: what makes an implementation a patent?
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Sun, 15 Dec 2002 13:16:32 -0500
Links: << >>  << T >>  << A >>
Hi Uwe,

> : what's differ a patent from a copyrighted work?
>
> A patent denies you to have the same idea as somebody other had and got a
> patent for this idea.  With copyrighted work you may not use his
> implementation for the idea, but you may implement it your way.

I don't agree with that.  You can take any patent, and implement the "idea"
any way you want, as long as you don't violate the patent.  An "idea", per
se, is not patentable, at least in the US.

Austin



Article: 50644
Subject: Re: what makes an implementation a patent?
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Sun, 15 Dec 2002 13:21:56 -0500
Links: << >>  << T >>  << A >>

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:Sh7K9.339038$P31.129678@rwcrnsc53...
>
> "hristo" <hristostev@yahoo.com> wrote in message
> news:b0ab35d4.0212120822.46ba96e@posting.google.com...
> > Hello,
> > general question here, sorry if it is off-topic.
> >
> > what makes an implementation be elligible for a patent status?
> >
> > i expect Novelty first. But if someone takes an architecture and
> > optimise it according to a special FPGA (eg.  Virtex), so he takes the
> > maximum of the chip features to implement it optimally. can he submit
> > this work for a patent??
>
> Since the XOR operator has been patented, and upheld twice,
> I would say that it doesn't take much to be eligible.

I had not heard that.  Do you have case numbers for those "upholdings"?

That would amaze me that it could even possibly be upheld (or even granted
in the first place)...as no one throughout time ever said "No one can be on
this horse, or either you or I can be on this horse, but not both of
us"...or something to that effect.

Austin



Article: 50645
Subject: Re: Packing clock enable flipflops into IOB
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 15 Dec 2002 10:25:04 -0800
Links: << >>  << T >>  << A >>
Roger Green wrote:
> Duane,
> 
> Having just been faced with similar challenges today - -
> 
> Check out the Xilinx answer database, record 2207, for a complete list of
> "rules" regarding IOB packing of registers.  I think you need to lose the
> "keep" attribute on the tristate enable signals as that will prevent the
> enable registers from going into the IOB.  Also you don't mention what your
> input/output signals are being clocked with.  All of the registers that go
> into a given IOB have to use the same clock and CE sources.

I met all those requirements, including those in record 2207. They work 
fine for getting signals to pack into the IOBs, but getting a common 
clock enable to pack into the IOBs seems to be a bit more of a problem.

Directly instantiating the FFs as black boxes works fine. So it appears 
to me that the problem is that XST is reducing the clock enable terms, 
and then map won't replicate the flipflop so that it can go into an IOB. 
Here is what worked for me.

    component FDPE
       port (
       PRE  : in std_logic;
       CE   : in std_logic;
       C    : in std_logic;
       D    : in std_logic;
       Q    : out std_logic
       );
    end component;

    attribute iob: string;
    attribute iob of Tn_array: label is "true";
--   attribute keep: string;
--   attribute keep of Tn_D: signal is "true";
    attribute noreduce: string;
    attribute noreduce of Tn_D: signal is "yes";
    attribute box_type : string;
    attribute box_type of FDPE: component is "black_box";

begin

   -- This is done to force the output enable signals into the IOB
   -- latches.
   FD_array: for i in 0 to 31 generate
     FD(i) <= DQ(i) when Tn_D(i) = '0' else 'Z';
   end generate;

   Tn_array: for i in 0 to 31 generate
     Tn_LATCH: FDPE
     port map (
       PRE => '0',
       CE => '1',
       C => C,
       D => Tn,
       Q => Tn_D(i)
     );
   end generate;



-- 
My real email is akamail.com@dclark (or something like that).


Article: 50646
Subject: Re: what makes an implementation a patent?
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Sun, 15 Dec 2002 13:33:33 -0500
Links: << >>  << T >>  << A >>

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:Sh7K9.339038$P31.129678@rwcrnsc53...
>
> "hristo" <hristostev@yahoo.com> wrote in message
> news:b0ab35d4.0212120822.46ba96e@posting.google.com...
> > Hello,
> > general question here, sorry if it is off-topic.
> >
> > what makes an implementation be elligible for a patent status?
> >
> > i expect Novelty first. But if someone takes an architecture and
> > optimise it according to a special FPGA (eg.  Virtex), so he takes the
> > maximum of the chip features to implement it optimally. can he submit
> > this work for a patent??
>
> Since the XOR operator has been patented, and upheld twice,
> I would say that it doesn't take much to be eligible.

Glen,

It appears that it is NOT the XOR operator that is patented, but using it
for screen cursors, and yes, though apparently "upheld", is a completely
bogus patent, IMO, and I am amazed it was upheld.  The patent was filed many
years after people had been using this technique, and not by the person who
actually used it first.

It's apparently patent # 4,070,710 granted in 1978....

Austin



Article: 50647
Subject: Matrics Memory controller
From: alisonjames1a@hotmail.com (alison)
Date: 15 Dec 2002 15:10:07 -0800
Links: << >>  << T >>  << A >>
I would like to implement a memory controller that allows
multiple components to access the same location at the same time
in a dual port ram I am using within a Virtex device.
What could be the best way to implement that? 
In software we can use semaphores to control the memory region
but how do I accomplish that in HDL.
Thanks for your help.

Article: 50648
Subject: Re: EDIF LPM Support in Synthesis
From: Mike Treseler <tres@fluke.com>
Date: Sun, 15 Dec 2002 15:22:16 -0800
Links: << >>  << T >>  << A >>
Tom Hawkins wrote:

> Hello,
> 
> What synthesis tools accept EDIF LPM as an input format?


Brand M and S can generate lpm instances for brands A and X
in the .edf output. The input format is vhdl.


> To what level is LPM supported?


search google groups: vhdl lpm open source

      -- Mike Treseler





Article: 50649
Subject: Re: EDIF LPM Support in Synthesis
From: nkavv@skiathos.physics.auth.gr (Uncle Noah)
Date: 15 Dec 2002 16:31:33 -0800
Links: << >>  << T >>  << A >>
tomahawkins@yahoo.com (Tom Hawkins) wrote in message news:<6440cb25.0212150929.315280d2@posting.google.com>...
> Hello,
> 
> What synthesis tools accept EDIF LPM as an input format?
> To what level is LPM supported?
> 
> What is the state of LPM?  It seems like its been around
> for a while, but rarely mentioned on the web.
> 
> Thanks,
> Tom

Unfortunately, LPM is now unsupported from Altera as stated at:
http://www.edif.org/lpmweb. Check if this link is still up.

However, you can get the library and documentation on the modules from 
there. If you search hard at Altera and Xilinx websites you can find 
references on example uses of LPM. 

Uncle "The G.B. Man" Noah



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1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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