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"James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in message news:20030525233314058+1200@news.paradise.net.nz... > Hi Leon, > > >> I have a 'getting started' page on using the 9536 on my web site. > > Just checked out your site, you've got some handy information up there! > > I was just wondering what U1 was on the schematic on your pld_starter > page? Also, what size caps do you use there? U1 is a clock oscillator module, I should have made that clear. The decoupling caps are the usual 100n. You've spurred me on to update the page. 8-) Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 55976
I want to implement the uclinux in nios. Is there any free uclinux version for nios? what should I do?Anyone could help me? Thanks & RegardsArticle: 55977
I want to implement uclinux in Nios. Is there any free uclinux version for nios. Would anyone help me? Thanks and Regards.Article: 55978
Followup to: <vd091ds4u219f9@corp.supernews.com> By author: "Jerry" <nospam@nowhere.com> In newsgroup: comp.arch.fpga > > Altera has some nice ones. I think thier NIOS development board is on > special for $495. > It is: http://www.arrow.com/Arrow%20Web%20Site/CDA/Cyclone/order_nios.htm -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 55979
A current list of boards from pretty much all suppliers is maintained by me at: http://www.fpga-faq.com/FPGA_Boards.shtml Philip On 23 May 2003 21:57:51 -0700, atif@kics.edu.pk (Atif) wrote: >I'm new to FPGA's. Can anyone please suggest me where to start? >AlsoI want to buy an FPGA board. Please tell me the specifications of >any FPGA board that costs about $200-$500. From where I'll purchase >it? >Thanks >Atif =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 55980
Cooley wrote: > I want to implement uclinux in Nios. > > Is there any free uclinux version for nios. > > Would anyone help me? Consider joining the uclinux-dev mailing list, via www.uclinux.org. The maintainers have just about got the full NIOS uclinux source tree checked in to the standard uclinux distribution. It needs people to test it out, so maybe you can get involved. Regards, JohnArticle: 55981
Hi folks,
I gather that with the Xilinx DCM, for synthesis the various parameters
such as clock divide and multiply factors must be set via attributes,
rather than vhdl instantiation generics, is that correct?
My question is then, can I create a vhdl wrapper around the DCM and pass
in these parameters via VHDL generics, and have them converted into
attributes? An example:
entity my_dcm_wrapper is
generic (c_multiplier : integer := 1;
c_divider : integer := 1;
c_clkin_period : real := 10.0
);
port (
...
)
architecture dcm_wrapper_struct is
attribute CLKFX_DIVIDE : integer;
attribute CLKFX_DIVIDE of DCM_INST : label is c_divider;
attribute CLKFX_MULTIPLY : integer;
attribute CLKFX_MULTIPLY of DCM_INST : label is c_multipler;
attribute CLKIN_PERIOD : real;
attribute CLKIN_PERIOD of DCM_INST : label is c_clkin_period;
component DCM blah blah blah
begin
DCM_INST : DCM
port map (....
)
...
Can you see what I'm trying to achieve here, populating the synthesis
attributes with values passed in via VHDLs generics mechanism?
Do vhdl syntax and semantics support this construction? From my
investigations it appears not, just looking for confirmation.
Can anybody explain why the DCM block can only have its parameters set
via attributes, rather than as generic VHDL instantiation parameters?
It makes it rather inconvenient because I'll either need a new wrapper
for every different clock divider/multipler ratio, or modify the source
of this one each time. I'm doing this so I can easily use the DCM in my
Microblaze / Xilinx EDK designs, without having to use the Proj Nav flow.
Any enlightned words on the subject?
Thanks,
John
Article: 55982I wrote: > Hi folks, > > I gather that with the Xilinx DCM, for synthesis the various parameters > such as clock divide and multiply factors must be set via attributes, > rather than vhdl instantiation generics, is that correct? I should add that I'm using XST for synthesis. Thanks, JohnArticle: 55983
Briefly, yes you can pass in values as generics, then assign those values to attributes. Often, you *have* to, as ModelSim doesn't recognise attributes, & XST doesn't recognise generics (Grr.. grr.. PITA... grr..) A case in point is initialising block RAMs. Another nice bit is that XST rejects "real" generic types, saying it doesn't support them. Makes life interesting doing those clock dividers. John Williams <jwilliams@itee.uq.edu.au> wrote: :I wrote: :> Hi folks, :> :> I gather that with the Xilinx DCM, for synthesis the various parameters :> such as clock divide and multiply factors must be set via attributes, :> rather than vhdl instantiation generics, is that correct? : :I should add that I'm using XST for synthesis. : :Thanks, : :JohnArticle: 55984
Hi David, David R Brooks wrote: > Briefly, yes you can pass in values as generics, then assign those > values to attributes. Often, you *have* to, as ModelSim doesn't > recognise attributes, & XST doesn't recognise generics (Grr.. grr.. > PITA... grr..) > A case in point is initialising block RAMs. > > Another nice bit is that XST rejects "real" generic types, saying it > doesn't support them. Makes life interesting doing those clock > dividers. After a bit of fiddling I seem to have it working. I'm just firing up the logic analyser now to make sure these clocks are doing what I think they should. This stuff is more cryptic than it is difficult - once you get over the initial hump of "what on earth is going on here?" it's not too bad. Cheers, JohnArticle: 55985
Synplify supports generics for instantiation. It's pretty easy to get Synplify through the university program. John Williams wrote: > Hi folks, > > I gather that with the Xilinx DCM, for synthesis the various parameters > such as clock divide and multiply factors must be set via attributes, > rather than vhdl instantiation generics, is that correct? > > My question is then, can I create a vhdl wrapper around the DCM and pass > in these parameters via VHDL generics, and have them converted into > attributes? An example: > > entity my_dcm_wrapper is > generic (c_multiplier : integer := 1; > c_divider : integer := 1; > c_clkin_period : real := 10.0 > ); > port ( > ... > > ) > > architecture dcm_wrapper_struct is > > attribute CLKFX_DIVIDE : integer; > attribute CLKFX_DIVIDE of DCM_INST : label is c_divider; > attribute CLKFX_MULTIPLY : integer; > attribute CLKFX_MULTIPLY of DCM_INST : label is c_multipler; > attribute CLKIN_PERIOD : real; > attribute CLKIN_PERIOD of DCM_INST : label is c_clkin_period; > > component DCM blah blah blah > > begin > > DCM_INST : DCM > port map (.... > > ) > > ... > > Can you see what I'm trying to achieve here, populating the synthesis > attributes with values passed in via VHDLs generics mechanism? > > Do vhdl syntax and semantics support this construction? From my > investigations it appears not, just looking for confirmation. > > Can anybody explain why the DCM block can only have its parameters set > via attributes, rather than as generic VHDL instantiation parameters? It > makes it rather inconvenient because I'll either need a new wrapper for > every different clock divider/multipler ratio, or modify the source of > this one each time. I'm doing this so I can easily use the DCM in my > Microblaze / Xilinx EDK designs, without having to use the Proj Nav flow. > > Any enlightned words on the subject? > > Thanks, > > John >Article: 55986
Ben Jackson wrote: > > In article <3ED05CCA.A4C36FBE@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >Ben Jackson wrote: > >I found a Lattice CPLD that > >not only does the job very well, it is tons cheaper and allows you to > >trade off banks of logic as memory! This is getting very close to FPGA > >functionality and it uses a *lot* less power! > > I forgot to ask in my reply: Which part? I went to latticesemi.com > and to pare down the selection to reasonable items I tried DigiKey > for prices, but they don't have anything. Neither does Mouser. Where > are you buying them? When you can't find an item at a distributor, you need to check the manufacturer's pages to see who they use for distribution. IIRC, Lattice uses Arrow and Avnet. But you need to check with them to be sure. As to the logic count, you need to understand the part in order to fully use the features. Your data registers only use the registers and do not use the main logic in the macrocell. So features like your muxes can use the logic and need no registers. Keep that in mind as you implement your design. Atmel also makes some CPLD parts that have double the registers. I don't remember what parts and their web site is not so easy to browse I think. There are also some anti-fuse parts from Actel that have small chunks of logice like an FPGA. So you can likely get more registers in a small package, but I have not looked hard at them. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55987
Uwe Bonnes wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > : I am doing a new design which needs 5 volt tolerance on a large number > : of pins. FPGAs with 5 volt inputs are long gone and the Xilinx CPLDs > : that fit this socket are very expensive. I found a Lattice CPLD that > : not only does the job very well, it is tons cheaper and allows you to > : trade off banks of logic as memory! This is getting very close to FPGA > : functionality and it uses a *lot* less power! > > SpartanII and XC95XL run from 3.3V but are perfectly 5Volt tolerant... I don't know about "perfectly". Did you read my statement about the cost? The SpartanII and XC95XL are very power hungry compared to the low power CPLDs. The XCR3 family was about four times the price of the Lattice parts. Check it out for yourself. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55988
Hello everyone,
I am currently working on a project aimed to find out new solutions to
implement DSP functions in FPGA devices. So far I have looked into more RAM,
dedicated multipliers, and better carry_save logic. But this morning I have
been thinking about another soltuion: bigger logic elements.
I have begun my discussions taking into account simple 4 input look-up
tables, but when implementing multipliers and carry lookahed adders, a
single LUT is not enough..... So I thought: what if we have a 6, 8, 10 input
lookup table? Would that actually improve performance? What I also thought
about was to maybe offer multiple outputs, by combining 2, 3 or 4 LUTs
together in a big logic element.
Do you think it would provide an advantage in terms of performance and area?
Are there any documents available on the subject, if anyone has thought
about it before?
Thanks very much
F
Article: 55989rickman <spamgoeshere4@yahoo.com> wrote: : Uwe Bonnes wrote: :> :> rickman <spamgoeshere4@yahoo.com> wrote: :> : I am doing a new design which needs 5 volt tolerance on a large number :> : of pins. FPGAs with 5 volt inputs are long gone and the Xilinx CPLDs :> : that fit this socket are very expensive. I found a Lattice CPLD that :> : not only does the job very well, it is tons cheaper and allows you to :> : trade off banks of logic as memory! This is getting very close to FPGA :> : functionality and it uses a *lot* less power! :> :> SpartanII and XC95XL run from 3.3V but are perfectly 5Volt tolerant... : I don't know about "perfectly". Did you read my statement about the : cost? The SpartanII and XC95XL are very power hungry compared to the : low power CPLDs. The XCR3 family was about four times the price of the : Lattice parts. Check it out for yourself. I only talked about the 5 Volt tolerance. The othere issues hold. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55990
Frank wrote: > > I have begun my discussions taking into account simple 4 input look-up > tables, but when implementing multipliers and carry lookahed adders, a > single LUT is not enough..... So I thought: what if we have a 6, 8, 10 input > lookup table? Would that actually improve performance? What I also thought > about was to maybe offer multiple outputs, by combining 2, 3 or 4 LUTs > together in a big logic element. > > Do you think it would provide an advantage in terms of performance and area? > > Are there any documents available on the subject, if anyone has thought > about it before? I'm convinced the manufacturers made and continue to make studies where the optimaum balance of the LUT block is. And indeed, different families have different properties there. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 55991
That would implement Matlab/Simulink/DSP Builder generated DSP/communications block(s) like FFT/IFFT, QAM, ... and implement simple proccessor that controls these blocks ? Proccessor (NIOS type) should execute my own state-machine/kernel (written in C), or some type of uCLinux. Ideally, the board should include AD/DA codec, and be in ~$1000 range So far "DSP Development Kit" from Altera looks good, but again, it is ~$1500. "Nios Development Kit" does not include AD/DA. Any comments on "APEX DSP Development Kit", or Xilinx equivalents ? Any comments on ease-of use of tools that come with these type of kits like : Quartus II DSP Builder SOPC Builder DSP IP (or Xilinx equivalents) ? thank you very much for your time, DubiArticle: 55992
You might also look at the distributed arithmetic tutorial page on my website.
DAB sounds worse than FM wrote:
> PawelT wrote:
> >> I've tried downloading the newer version off the net but it's a big
> >> file and I've got a 56k modem and my ISP cuts me off after 2 hours
> >> which makes it impossible to download it in time. :(
> > maybe some kind of dowload manager can help, if the connection is
> > beak. I use flashget, but (fortunately) i've got "permanent"
> > connection to the Internet.
> >
> >>
> >> I think I might ring up Altera in the UK to see if they'll send me a
> >> CD.
> >
> > Try to subscribe Digital Library from Altera - there is a Baseline,
> > and other digital data.
> > Or just call to lokal representative, or other firm with sell software
> > for digital circuits.
>
> I think I'll ring them up to see if they'll send me a CD to save me
> downloading it for hours and hours.
>
> BTW, I read this and it has a better description of distributed arithmetic
> than in the DSP with FPGAs book:
>
> http://www.xilinx.com/appnotes/dspguide.pdf
>
> Also there's loads of useful Application Notes for DSP with FPGAs here:
>
> http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=literature_training
>
> --
> DAB sounds worse than FM, Freeview, Digital Satellite and Cable --
> http://www.digitalradiotech.co.uk/
>
> Subscribe for free to the Digital Radio Listeners' Group Newsletter
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55993"Frank" <nc300e@doc.ic.ac.uk> wrote in message news:<basn5p$st3$1@harrier.doc.ic.ac.uk>... > Hello everyone, > I am currently working on a project aimed to find out new solutions to > implement DSP functions in FPGA devices. So far I have looked into more RAM, > dedicated multipliers, and better carry_save logic. But this morning I have > been thinking about another soltuion: bigger logic elements. > > I have begun my discussions taking into account simple 4 input look-up > tables, but when implementing multipliers and carry lookahed adders, a > single LUT is not enough..... So I thought: what if we have a 6, 8, 10 input > lookup table? Would that actually improve performance? What I also thought > about was to maybe offer multiple outputs, by combining 2, 3 or 4 LUTs > together in a big logic element. > > Do you think it would provide an advantage in terms of performance and area? > > Are there any documents available on the subject, if anyone has thought > about it before? > > Thanks very much > > F Up until recently FPGAs used to have bigger logic elements - they were called small asynchronous embedded RAMs, you know. They are out of fashion now - don't fit 200MHz+ designs especially good. Do you see a lesson here ? Proper balance between dedicated multipliers and dual-ported RAM blocks is easily the single most important factor in the DSP performance of the FPGA. Now what's a proper balance ? I believe, 2.5 to 3 16bit (or 17bit) memories per 17x17=35bit multiplier is o.k. It's an obvious part. Both Xilinx and Altera figured it out long time ago. Xilinx is a bit on the small side with memory blocks but compensates with its distributed RAM option. Now what single feature I would like to add ? It depends on type of the design. 1. Predominantly parallel designs. Actually existing high-end FPGA architectures a pretty good here. I would like to add super pipelined hardware multipliers. Would be nice to have 2 multiplication results on each 4ns clock and I don't care if the latency would be as much as 12ns or more. 2. Unfortunately, predominantly parallel problems are rare. Most real life tasks require combination of the parallel and sequential DSP. And sequential DSP is PITA. Of coarse, soft CPU cores could help a little, but this cores are often an overkill and waste of resources. 2000LC core to feed one or two multipliers ? Doesn't sound too good for me. Hard CPU cores ? You can't have enough of them. There are many FPGA applications that can't benefit from hard core at all, so it make no sense for the FPGA manufacturer to dedicate more than 2-3% of chip's real estate to the hard cores. The element I would like to have is hardware mux. Something like 32x9 or 64x9 synchronous mux which runs at least as fast as hardware multipliers. Unfortunately it has 293 (or 582) inputs. It's probably impossible to have many elements like this in the FPGA and if you have only few it doesn't help. So forget about hardware mux. We need to find something with better usefulness/fan-in ratio. What's about programmable switch fabric ? Like the mux, it has huge fan-in, but the switch is potentially many times more useful than the simple mux. I should think more about it really... Here is a time to stop talking and start filling a patent :-)Article: 55994
Hi, I'm currently trying to use the IP 'Pos Phys L4' of Altera, but I have many problems to simulate the Testbench add on this IP. Anyone could help me? Thanks in advance. Benoit.Article: 55995
DB wrote: > That would implement Matlab/Simulink/DSP Builder generated > DSP/communications block(s) like FFT/IFFT, QAM, ... and implement simple > proccessor that controls these blocks ? > Proccessor (NIOS type) should execute my own state-machine/kernel (written > in C), or some type of uCLinux. > Ideally, the board should include AD/DA codec, and be in ~$1000 range > > So far "DSP Development Kit" from Altera looks good, but again, it is > ~$1500. > "Nios Development Kit" does not include AD/DA. It shouldn't be too hard to an ADC and DAC, should it ? What speed and resolution did you think about ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 55996
"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message news:26f756a166ca56b70f4f55fdb7a62668@TeraNews... > DB wrote: > > That would implement Matlab/Simulink/DSP Builder generated > > DSP/communications block(s) like FFT/IFFT, QAM, ... and implement simple > > proccessor that controls these blocks ? > > Proccessor (NIOS type) should execute my own state-machine/kernel (written > > in C), or some type of uCLinux. > > Ideally, the board should include AD/DA codec, and be in ~$1000 range > > > > So far "DSP Development Kit" from Altera looks good, but again, it is > > ~$1500. > > "Nios Development Kit" does not include AD/DA. > > > It shouldn't be too hard to an ADC and DAC, should it ? > What speed and resolution did you think about ? > > Rene Rene thanks, "DSP Development Kit" has two channel ADC/DAC in the range of ~100M samples/sec. For my simple comm design range of ~ few M samples/sec should be adequate. Any hints/references how to interface "Nios kit" (also Stratix family but EP1S10 instead of EP1S25) with off-board CODEC ? Any experience with "Open Core Plus" DSP blocks ? thanks, DubiArticle: 55997
DB wrote: > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > news:26f756a166ca56b70f4f55fdb7a62668@TeraNews... > >>DB wrote: >> >>>That would implement Matlab/Simulink/DSP Builder generated >>>DSP/communications block(s) like FFT/IFFT, QAM, ... and implement simple >>>proccessor that controls these blocks ? >>>Proccessor (NIOS type) should execute my own state-machine/kernel >> > (written > >>>in C), or some type of uCLinux. >>>Ideally, the board should include AD/DA codec, and be in ~$1000 range >>> >>>So far "DSP Development Kit" from Altera looks good, but again, it is >>>~$1500. >>>"Nios Development Kit" does not include AD/DA. >> >> >>It shouldn't be too hard to an ADC and DAC, should it ? >>What speed and resolution did you think about ? >> >>Rene > > > Rene thanks, > > "DSP Development Kit" has two channel ADC/DAC in the range of ~100M > samples/sec. > For my simple comm design range of ~ few M samples/sec should be adequate. > Any hints/references how to interface "Nios kit" (also Stratix family but > EP1S10 instead of EP1S25) with off-board CODEC ? > > Any experience with "Open Core Plus" DSP blocks ? Not yet. I have a NIOS Stratix kit and will have a look at that subject soon. There is a range of ADC/DAC available from different manufacturers. They operate similarly. I'll possibly opt for an affordable 50Msample pair. They shouldn't be too hard to add on a little board. ReneArticle: 55998
Hi Leon, > You've spurred me on to update the page. 8-) Good to know ;-) Please let me know when you've done it, as I would like to read your updates. > U1 is a clock oscillator module, I should have made that clear Um, at the risk of sounding stupid, what part are you using for this? Ben Jackson posted a link to a Xilinx app note that uses a 555 timer to generate a 14Hz clock signal, but this seems kinda slow. I thought these CPLD's were supposed to operate in the ~100Mhz range? Cheers, JamesArticle: 55999
"Benoit" <bhb22l@yahoo.fr> wrote in message news:batgp1$lhj$1@s1.read.news.oleane.net... > Hi, > > I'm currently trying to use the IP 'Pos Phys L4' of Altera, but I have many > problems to simulate the Testbench add on this IP. > > Anyone could help me? Can you help yourself? How about saying what some of the problems are? Cheers, JonB
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