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db wrote: >I have to ask the question why XST prints such a useless message as: > >FATAL_ERROR:Xst:Portability/export/Port_Main.h:126:1.13 - This >application has discovered an exceptional condition from which it >cannot recover. Process will terminate. To resolve this error, >please consult the Answers Database and other online resources at >http://support.xilinx.com. If you need further assistance, please open >a Webcase by clicking on the "WebCase" link at >http://support.xilinx.com >Error: XST failed > >This tells me absolutely nothing about the problem. Looking at the >Xilinx website has never gleaned any useful information. I am able to >figure out the what the problem is, but I waste a lot time doing this >trying to pin down the problem when I get such uninformative messages >as above. > >So if XST knows something is wrong, why is it unable to tell me. > A FATAL_ERROR means that XST terminated unexpectedly, which is why it can't tell you what happened. > If it >wont tell me, I certainly can not tell tech support if I want to open >a WebCase. > If you submit the design that failed, our engineers can debug the problem and probably find a workaround. Steve > >I hope someone from Xilinx can give me an answer to this. > >Article: 57801
What are the best techniques for stretching single-clock pulses? Here
"best" defined as either faster or smaller logic.
I've been using the following technique with great success, the idea is to
add a few clock cycles to a pulse prior to having it cross a clock domain or
send it somewhere where it would be safer to have it be active longer:
reg [3:0] counter;
reg single_clock_pulse;
reg [3:0] strecher_sr;
reg longer_pulse;
// Generate a test pulse
always @(posedge clock)begin
counter <= counter + 1;
single_clock_pulse <= & counter;
end
// Stretch the pulse
always @(posedge clock)begin
stretcher_sr <= {stretcher_sr[2:0], single_clock_pulse};
longer_pulse <= | stretcher_sr;
end
By changing the length of the shift register I can control the new pulse
duration. This is obviously not a good technique for very long durations.
What are some of the other techniques? Anything more "elegant" than this?
Thanks,
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Article: 57802
Christoph Grundner <christoph.grundner@agfa.com> wrote:
: antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0307040005.6e6ba1ab@posting.google.com>...
:> impact generates JAM files, well called STAPL but it is the same thing.
:> there are some problems though most of the files generates will not
:> work with non-patched JAM player :(
:>
:> antti
: Are there any required patches somewhere for download? Or do i have to
: write my own one?
I needed to remove whitespaces:
--- source.orig/jamexec.c Mon Nov 13 18:58:26 2000
+++ source/jamexec.c Tue Dec 3 22:05:25 2002
@@ -816,6 +816,23 @@
long *long_ptr = NULL;
JAM_RETURN_TYPE status = JAMC_SUCCESS;
+ /* remove all white space */
+ while (statement_buffer[in_index] != JAMC_NULL_CHAR)
+ {
+ if ((!jam_isspace(statement_buffer[in_index])) &&
+ (statement_buffer[in_index] != JAMC_TAB_CHAR) &&
+ (statement_buffer[in_index] != JAMC_RETURN_CHAR) &&
+ (statement_buffer[in_index] != JAMC_NEWLINE_CHAR))
+ {
+ statement_buffer[out_index] = statement_buffer[in_index];
+ ++out_index;
+ }
+ ++in_index;
+ }
+ statement_buffer[out_index] = JAMC_NULL_CHAR;
+ in_index = 0;
+ out_index = 0;
+
while ((status == JAMC_SUCCESS) &&
((ch = statement_buffer[in_index]) != '\0'))
{
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 57803Hey, I'm trying to implement a code that requires the use of interrupts on the Xilinx rpp. I'm using the core module CM7TDMI. In order to do this I have to set the interrupt disable flag in the CPSR register to low, but I can't find any information on where this register is located, and which bits corresponds to these interrupt disable flags. If anyone has any information on this please post it here, or tell me where I can find it. Thank you BojanArticle: 57804
I have not been having a good day (weekend actually) trying to download the Altera web edition software. Large downloads like this normally take three or so tries to get the full file. But I find that I am not able to get a license file anyway. I don't have an Ethernet adapter in the PC where I will be running the tools and the web site is not set up for anything else. So what do I need to do to get running with quartus web edition? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57805
Chris, This is Jesse Jenkins, from the Xilinx CPLD operation. Maybe I can clear up some things for you. As I recall, looking back at your email thread, you have some concerns about adopting a CPLD due to product discontinuation. Xilinx did discontinue the XC7300 family about 6-7 years back, but we made a pin compatible XC9500 family (and two successors) that we transitioned 99% of our customers to. We also offered a generous time frame for customers to stock up on XC7300 parts so they could comfortably qual the new parts without having to drop everything and do it instantly. When Xilinx purchased the Philips CPLD product line, there were very few users of the 5V parts, which were being manufactured by Philips in Holland. At that time, Philips had introduced only a couple of the 3V family called XPLA3. Xilinx chose to provide the Philips created silicon for a while, with an agreement to give customers a lengthy discontinuation notice, as we brought the XPLA3 family up at our Taiwan fab, UMC. The XPLA3 family has core voltage of 3.3V, and can tolerate 5V inputs. CoolRunner-II incorporates aspects of both the XPLA3 family and the XC9500 family, in a 1.8V core technology (read: 0.18 micron). I saw some concern about discontinuing CoolRunner-II, which is absurd. It was just released in the last few months to full production and cost Xilinx multi millions of dollars to create. To date, the XC9500 family and its 3.3V XC9500XL, and 2.5V XC9500XV family are all alive and doing very well! The low power XPLA3 and CoolRunner-II family are also doing very well. If you have any doubts, you can start opening up various PDAs, cellphones and digital cameras and see them in there! Anyway, it is good to see that you are considering Xilinx CPLDs for adoption, we have spent a lot of time and money developing them as well as their software support. Don't hesitate to ask more questions in your CPLD quest. Jesse Jenkins, Xilinx Chris_S wrote: > > Exactly which new families did not "make it" in the market? > > QuickLogic, AMD, ICT, Phillips, etc. there are quite a few. They start off > touting a new line/family, the reps come in pushing the stuff and telling me > it is great and it will be around a long time. They don't end up winning > enough market share, and the companies drop future plans to fill out the > line, or they obsolete parts, or they sell the line off and someelse does > the same. > > > any reason to expect the LC4000 (which is what I believe you are calling > > Mach 4000) will not be here as long as any other PLD family. > > I talked to the Lattice factory HotLine on Thursday. I asked him: "Why are > there so few packages available for the 4000? > "Which would be better to design in, the 4000 or 4A?" He recommended the > 4A. I asked him why I did not see much dist activity with the 4000, there > was ten times the amount with the 4A. He said the majority of what they > sell is still in the 1000 and 2000 lines. There was a lot more business > with 4A as compared to 4000. > > The majority of business with prog logic is already established in older > designs using older parts. These new familes that come out have a hard time > winning new sockets. There are more new familes coming out than there is > business for all of them, and some of them will not survive. They will not > win enough market share. > > >> ... better pricing on the Lattice parts than I have on the Xilinx CR. > >> Once the size gets up a bit, the CR parts get very, very expensive. > > Is that true comparing the CR-II parts as well? The CR-II pricing seemed > very good. It is looking more attractive to me. > > Chris.Article: 57806
The decision on what works "better" is dependent on why you need to stretch
the pulse.
If you need a signal that's big enough to be sensed in a different clock
domain, an "acknowledge" can be brought back to the first time domain to
shut the pulse back off. This assumes that two pulses won't be close enough
to interfere.
If we stick with your original approach, rather than using the |stretcher in
your construct below, I'd turn longer_pulse into a set/reset flop that's
started with the single_clock_pulse and ended with the stretcher_sr[2], i.e.
longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse;
Two very-close events would only produce one pulse with this arrangement
rather than the extension that you'd get with the wide or. The only reason
to use the alternative arrangement is to get the shift register in an SRL
for a Xilinx device or to reduce the width of the logic for a wider pulse
than what you're using.
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:atiOa.105$FA6.16959707@newssvr14.news.prodigy.com...
> What are the best techniques for stretching single-clock pulses? Here
> "best" defined as either faster or smaller logic.
>
> I've been using the following technique with great success, the idea is to
> add a few clock cycles to a pulse prior to having it cross a clock domain
or
> send it somewhere where it would be safer to have it be active longer:
>
> reg [3:0] counter;
> reg single_clock_pulse;
> reg [3:0] strecher_sr;
> reg longer_pulse;
>
> // Generate a test pulse
> always @(posedge clock)begin
> counter <= counter + 1;
> single_clock_pulse <= & counter;
> end
>
> // Stretch the pulse
> always @(posedge clock)begin
> stretcher_sr <= {stretcher_sr[2:0], single_clock_pulse};
> longer_pulse <= | stretcher_sr;
> end
>
> By changing the length of the shift register I can control the new pulse
> duration. This is obviously not a good technique for very long durations.
> What are some of the other techniques? Anything more "elegant" than this?
>
> Thanks,
>
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
>
>
Article: 57807I'm part of a new startup, Zeidman Technologies, that's developing a new software tool, called SynthOS, that will automatically generate an RTOS that's optimized for your hardware. This RTOS has a tiny footprint, only includes code that you actually use, checks for certain hazards and race conditions, and can speed your development time. It can be used for multi-processor systems. It's particularly useful for platform SOCs like the ones from Xilinx, Altera, and LSI Logic. We're looking for beta customers. If you think that this tool can help you on an upcoming project, please contact me (see contact info below). Feel free to forward this message to colleagues that might benefit from SynthOS. Thanks, Bob Zeidman President Zeidman Technologies Phone: 408.255.9279 Fax: 408.255.4881 Web: www.ZeidmanConsulting.com Email: Bob@ZeidmanConsulting.comArticle: 57808
GpsBob wrote: > Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one > of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this > under the EDK 3.2 works fine on eval board. But, if I change line 163 > of the file "opb_pwm_core.vhd" which reads: > > SIn_DBus(I) <= '0'; > > to > > SIn_DBus(I) <= '1'; > > which just changes the default output of the user IP, the system just > hangs after downloading the bitstream to the eval board. Any ideas? > Could there be some kind of contention within the OPB bus? I assume > that contentions are generally caught by the synthesis tools. If I > inspect the automatically generated vhdl, it seems that the bus > interfaces are generated correctly for the various peripherals tied to > the OPB bus. So, I'm at a loss as to why this is happening! > > Bob > > I've build SoC's where the muxing between IP-blocks were a big OR, thus blocks that were inactive had to output zeros, if they didn't the values read would be garbage. (it wouldn't create contention) Don't know anything OPB, could it be that it is implemented the same way? -LasseArticle: 57809
I think we covered the archive a while back. > It's hardly realistic to expect todays tools to support parts that have > been obsolete for 10 years. Again, we are talking Spartan which has not been obsolete for ten years. > Periodically some major component of the tools > gets completely rewritten, when that happens it's hard enough for them to > put in support for all of the current parts let alone add support for all > of the old parts. Altera just keeps adding more support for their older devices to Quartus. It's their newest tool. Maybe they have more time on their hands.Article: 57810
I guess everyone is trying to download Quartus 3.0 at once during daytime. The file weights 137MB and has just been released, so a busy server is understandable today. I got it late last night and the download was very fast. As for Ethernet adapters, nobody likes to jump into hoops to get a software running, but it's not so bad to buy a cheap Ethernet card, and I guess they want to keep their licensing options open. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F09B67B.1E2765E4@yahoo.com... > I have not been having a good day (weekend actually) trying to download > the Altera web edition software. Large downloads like this normally > take three or so tries to get the full file. > > But I find that I am not able to get a license file anyway. I don't > have an Ethernet adapter in the PC where I will be running the tools and > the web site is not set up for anything else. So what do I need to do > to get running with quartus web edition? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57811
Gentlemen:
I have a situation where some of my compatriots want to be able to reset
a Virtex2 in order to reload the program from the 18V04 chips. Generally,
they are going to want to do this after they have loaded a new image into
the eprom's and they want to do it under program control.
Would I be correct in assuming that all they need to do is instantiate
glbl.v in their design and assert the GSR signal hi? At that point, the chip
should tri-state that same assertion and all the other signals, read the
eproms and start afresh?
Charles
Article: 57812Charles Krinke <someone@pacbell.net> wrote: : Gentlemen: : I have a situation where some of my compatriots want to be able to reset : a Virtex2 in order to reload the program from the 18V04 chips. Generally, : they are going to want to do this after they have loaded a new image into : the eprom's and they want to do it under program control. : Would I be correct in assuming that all they need to do is instantiate : glbl.v in their design and assert the GSR signal hi? At that point, the chip : should tri-state that same assertion and all the other signals, read the : eproms and start afresh? GSR is for resetting the configured circuit. To reconfigure, you need to toggle the program pin. If you hav a connection from the PROM CF pin to the programm pin, you can do so via Jtag. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57813
I wrote a program in vhdl with ISE 5.1 and when I try to simulate the post translate VHDL model or Post Map or Post place and route, I receive the follow error: ERROR: Hidden remap failed Reason: None appears in Reason !!! What is the cause of this error ? And the remedy ? I've tried also to upgrade to ISE5.2 sp.3 but the problem remains same. The program in the FPGA works well but I have ever the dubt that something inside it is wrong !!! Regards GiuseppeArticle: 57814
Lasse Langwadt Christensen wrote: > GpsBob wrote: > >> Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one >> of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this >> under the EDK 3.2 works fine on eval board. But, if I change line 163 >> of the file "opb_pwm_core.vhd" which reads: >> >> SIn_DBus(I) <= '0'; >> >> to >> >> SIn_DBus(I) <= '1'; >> >> which just changes the default output of the user IP, the system just >> hangs after downloading the bitstream to the eval board. Any ideas? >> Could there be some kind of contention within the OPB bus? I assume >> that contentions are generally caught by the synthesis tools. If I >> inspect the automatically generated vhdl, it seems that the bus >> interfaces are generated correctly for the various peripherals tied to >> the OPB bus. So, I'm at a loss as to why this is happening! >> >> Bob >> >> > > I've build SoC's where the muxing between IP-blocks were a big > OR, thus blocks that were inactive had to output zeros, if they > didn't the values read would be garbage. (it wouldn't create contention) > > Don't know anything OPB, could it be that it is implemented the same > way? > > -Lasse > Lasse, Bob: I used that dreaded word (contention) far too loosely in my post; sorry if I scared anyone. Lasse, that is indeed how the OPB bus is built (an OR'd structure). There will not be contention, there will be garbage data in Bob's case if he drives a '1' onto the bus while another peripheral is trying to drive a '0'. Just as Lasse was implying, the reason the synthesis tool(s) will let you do this is that from a hardware standpoint you're not doing anything wrong by driving the bus with two peripherals since they're ORed. Ryan Laity Xilinx ApplicationsArticle: 57815
jesse jenkins wrote: > <snip> > CoolRunner-II incorporates aspects of both the XPLA3 family and the > XC9500 family, in a 1.8V core technology (read: 0.18 micron). > I saw some concern about discontinuing CoolRunner-II, which is absurd. > It was just released in the last few months to full production and > cost Xilinx multi millions of dollars to create. To date, the XC9500 family > and its 3.3V XC9500XL, and 2.5V XC9500XV family are all alive > and doing very well! The low power XPLA3 and CoolRunner-II family > are also doing very well. If you have any doubts, you can start opening > up various PDAs, cellphones and digital cameras and see them in there! <snip> Do you have any comments on Chris's mention (FAE attributed IIRC) that there is a new Coolrunner soon to replace the CR2 ? - or is it more a complementary family, like the lattice 4000/5000 series ? - or just an urban myth ? -jgArticle: 57816
"John_H" <johnhandwork@mail.com> wrote: > If you need a signal that's big enough to be sensed in a different clock > domain, an "acknowledge" can be brought back to the first time domain to > shut the pulse back off. This assumes that two pulses won't be close enough > to interfere. Right. I've used this approach in some modules, like both sides of a FIFO operating across clock-domain boundaries. I had to resort to stretching when the signal in question had to go to multiple desitinations and it didn't seem practical to generate and maintain different pulse <-> ack channels. My personal bias is that it made everything seems a bit messy. My general approach to clock domain crossing has been to stretch the pulse (if necessary) to guarantee that it will span several of the receiver's clock cycles; re-sample with at least four F/F's and edge-detect. So far, so good. > longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse; > > Two very-close events would only produce one pulse with this arrangement > rather than the extension that you'd get with the wide or. The only reason > to use the alternative arrangement is to get the shift register in an SRL > for a Xilinx device or to reduce the width of the logic for a wider pulse > than what you're using. A single SRL sounds good to me. Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57817
Followup to: <bebnhi$36kqm$1@ID-61213.news.dfncis.de> By author: "Giuseppeł" <miaooaim@inwind.it> In newsgroup: comp.arch.fpga > > <cut> > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > > > Hello Rick, > > > > Would you care to explain how you set the serial number ? > > I've looked before but never been able to find out how. > > > > Michael Kellett > > www.mkesc.co.uk > > > > Just using the program "VOLUMEID.exe" from the www.sysinternals.com site. > For Ethernet cards, too; for most it's trivial to flash a new MAC address permanently. You need hardware-specific tools to do it, but virtually all modern Ethernet cards have the MAC address in a serial EEPROM of some sort. You can still, obviously, not have two Ethernet cards with the same MAC address on the same network. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57818
I have a problem with the word:" replace". When your wife has a second baby, that does not replace your firstborn. It may now get its undue share of attention, but the old one is still going to be around and be loved and be useful.. In a previous post I explained the different aspects of obsolescence. Yes, we are always working on new products that somehow are so much better (or cheaper) that they supplant the older parts for new designs, but in our product line-up hardly anything is ever being "replaced." Old PLDs never die, they just fade into obsolescence. Peter Alfke ============== Jim Granville wrote: > > > Do you have any comments on Chris's mention (FAE attributed IIRC) > that there is a new Coolrunner soon to replace the CR2 ? > - or is it more a complementary family, like the lattice 4000/5000 > series ? > - or just an urban myth ? > -jgArticle: 57820
You might want to look at an article I wrote some time ago: "Moving data across asynchronous clock boundaries". You find it among the TechXclusives. http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp Peter Alfke, Xilinx ============ Martin Euredjian wrote: > > "John_H" <johnhandwork@mail.com> wrote: > > > If you need a signal that's big enough to be sensed in a different clock > > domain, an "acknowledge" can be brought back to the first time domain to > > shut the pulse back off. This assumes that two pulses won't be close > enough > > to interfere. > > Right. I've used this approach in some modules, like both sides of a FIFO > operating across clock-domain boundaries. I had to resort to stretching > when the signal in question had to go to multiple desitinations and it > didn't seem practical to generate and maintain different pulse <-> ack > channels. My personal bias is that it made everything seems a bit messy. > > My general approach to clock domain crossing has been to stretch the pulse > (if necessary) to guarantee that it will span several of the receiver's > clock cycles; re-sample with at least four F/F's and edge-detect. So far, > so good. > > > longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse; > > > > Two very-close events would only produce one pulse with this arrangement > > rather than the extension that you'd get with the wide or. The only > reason > > to use the alternative arrangement is to get the shift register in an SRL > > for a Xilinx device or to reduce the width of the logic for a wider pulse > > than what you're using. > > A single SRL sounds good to me. > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 57821
Hey Rickman, In article <3F0AE7CC.68F9D9D0@yahoo.com>, spamgoeshere4@yahoo.com says... > I need to vent a little steam. So at risk of making myself look stupid > (or more stupid) I will do it here. > > I have been trying to get the Quartus 3.0 software and a license since > last Thursday. I tried three times over the weekend to download it, but > the slow modem link I have to use would not complete the entire transfer > without a problem. I think I have that licked as my brother tells me he > has downloaded it for me. You might want to look into a *great* utility called "wget". It's probably comes standard on every modern FreeBSD/Linux implementation, but not many people in the Windows world know about it... See this for a command-line vanilla Windows version: http://space.tin.it/computer/hherold/ and see this for a Visual Basic GUI wrap-around: http://www.jensroesner.de/wgetgui/ If you use the plain-vanilla command-line version, just launch like this: wget -c <url> -c tells it to continue if a download is aborted...this way if your modem drops, when you re-connect, just re-issue wget -c <url> and it'll continue where the file was chopped off. Also, as other people have suggested, the path of least resistance really is to get an el-cheapo NIC and stick it in. It's not elegant, it's not "right" but it's the fastest way to get what you want. Thanks! TR.Article: 57822
The ssp0 core has a mir interface within. You need to assign the addresses for the mir registers. I.E: BEGIN opb_core_ssp0 PARAMETER INSTANCE = opb_core_ssp0_1 PARAMETER HW_VER = 1.00.b PARAMETER c_BASEADDR = 0x21000000 PARAMETER c_HIGHADDR = 0x210000ff PARAMETER c_mir_BASEADDR = 0x21000100 PARAMETER c_mir_HIGHADDR = 0x210001ff PORT opb_clk = sys_clk PORT led = led BUS_INTERFACE SOPB = opb END Matthias Dyer wrote: > Hello, > > We are trying to implement an OPB slave user core as described in the "User > Core Template Reference Guide" (Jan 2003). We are using the template > "opb_core_ssp0_v1_00_a". We have connected the user core to the OPB Bus of a > Microblaze system (generated with Xilinx EDK3.2 SP1 tools). Now, having > this core as the only opb slave on the bus causes no problems. But when we > connect other pre-build peripherials such as the "uart-lite", our core > interfers somehow with the other cores. In particular the uart output is > croped after 16 chars if our user core is present. This is a weird behavior > since our core should have a well defined opb addres space and does only > read from the opb and does not write to it. > > This effect even occurs when we take an empty user core template! > > Have anyone had the same experience or can anyone help? > > Thanks a lot and best regards, > > Matthias > >Article: 57823
dataOut <= dataForRead when (doAread = '1') else
(others => 'Z');
Muhammad Khan wrote:
> HI Fellows,
> The process given below is to read and write to Vertex device ( only
> vhdl part is shown here not C ). I want to tristate SR_DATA_IO_int
> when not driven as read.
> First of all the code below for write and read is correct or not!!!!
> SR_DATA_IO_int pins ( which are 32 , I am using upper 7 bits only )
> will be acting as bi directional pins. While writing these will take
> bits from PCI interface to device and while reading they will exactly
> opposite. But while writing I have to tristate SR_DATA_IO_int so as to
> avoid short circuiting. Any help on tristate will be highly
> appreciated.
>
>
process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
> begin
> if RISING_EDGE(CLK_2X) then
> if SR_IVCS_V3_int = '0' then
> if SR_IWR_int = '0' then
> if SR_ADDR_IO_int = "001100" then
> RESULT <= SR_DATA_IO_int(6 downto 0);
> End if ;
> Elsif SR_IRD_int = '0' then
> if SR_ADDR_IO_int = "001101" then
> SR_DATA_IO_int(6 downto 0)<=RESULT ;
> End if;
> End if;
> End if;
> End if;
Article: 57824I've had no problem. I just don't use the tft. Antti Lukats wrote: > Hi > > I am trying to use xilinx PLB TFT LCD core with EDK/XPS but the core > is not even listed, it is in the cores directory (marked obsolete) > > ML300 TFT works well with xilinx demos, but there is no EDK example > with TFT support, anybody succeeded to use EDK meaningfully for > V2Pro/ML300 ? > > tnx > Antti
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