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Messages from 58075

Article: 58075
Subject: Re: DCM CLKFX simulation
From: "l nguyen" <>
Date: Mon, 14 Jul 2003 11:53:57 -0700
Links: << >>  << T >>  << A >>
hi John, 
I see what going on... for all the others. I may not need to 
see the CLKFX on simulator anymore, it's kind of fake result. 

Well, you are rite, its funny the DCM.  Looking at  DCM block in FPGA 
editor, I can see all other attributes changing accordingly to my entry 
design such as CLKDV_DIVIDE, DLL frequency, startup wait,... but the 
mistery M and D values not show up anywhere.  Beside, there is a strange 
FACTORY JF always stay at 0xC0 and 0x80. 

Do you have any idea where I 
can verify the M and D setting.  

Thanks,

Article: 58076
Subject: Aurora Reference Design help
From: Josh Kramer <kramerj@udel.edu>
Date: Mon, 14 Jul 2003 14:54:13 -0400
Links: << >>  << T >>  << A >>
I am currently using version 1.7 of the VHDL Aurora 401 reference
design.  For testing I am currently using one MGT with the TX and RX
pins connected.  Everything works correctly if the pins are connected
when the FPGA (Virtex II Pro XC2VP7)  is turned on (ie. CHANNEL_UP
goes high and I can send data).  Also after RESET or POWER_DOWN is
asserted the channel is reinitialized correctly.  If the pins are not
connected on powerup or the pins are disconnected then reconnected
CHANNEL_UP  is never asserted.  Asserting RESET or POWER_DOWN does not
help.  The protocol engine is sending the Sync and Polarity sequence
but the link is nerver initialized.  Is this a known problem with
Aurora or is there something else that may be wrong?


Regards,

Josh Kramer

-- 
Research Assistant
University of Delware, ECE Dept.
CVORG

Article: 58077
Subject: Re: Post-fit simulation question
From: brad@tinyboot.com (Brad Eckert)
Date: 14 Jul 2003 12:06:44 -0700
Links: << >>  << T >>  << A >>
gilad_coh@walla.co.il (Gilad Cohen) wrote in message news:<8f9a8978.0307120946.10624a6a@posting.google.com>...
> brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0307111552.189961b8@posting.google.com>...
> 
> Hello Brad.
> 
> Firstly, why do you need a synthesizable testbench?
> You wrote you only need it for simulation. 
> Do you plan to synthesize it as well?

Bad wording. The testbench isn't synthesizable. It's full of waits and
asserts.
 
> Secondly - I think you are being far too pessimistic about the static
> timing analysis tools.
> 
> From my experience, they are quite reliable - if you constrain them
> correctly.
> What you should do, is apply multi-cycle path and false path
> constraints where needed, and just let the tool perform the analysis
> based on the clock frequency you specify.

That's the way to go. Thanks for pointing it out. I'll see what XST
allows.

I've noticed something else. When I start hanging peripherals and
other things on my CPU core and don't apply any constraints other than
minimum clock, the system clock frequency goes down significantly. The
CPU is the bottleneck, not the peripherals so I'm wondering why this
is so.

Article: 58078
Subject: problems on using CLKDLL in Xilinx ISE
From: whli_interqos@yahoo.com.hk (Stephen)
Date: 14 Jul 2003 12:07:41 -0700
Links: << >>  << T >>  << A >>
Hi Everyone,
    I have got the following problem when I use following CLKDLL
configuration in Xilinx ISE 5.1.

// input of clock source

IBUFG ibufg_lclk(
    .I      (lclk),
    .O      (lclk_ibufg));

BUFG in_bufg_lclk(
    .I      (lclk_ibufg),
    .O      (lclk_bufg));

CLKDLL dll_lclk(    
    .CLKIN  (lclk_bufg),
    .CLKFB  (clk),
    .RST    (dllrst),
    .CLK0   (lclk0),
	 .CLK2X	(lclk2x0),
    .LOCKED (locked_lclk));

BUFG bufg_lclk(
    .I      (lclk0),
    .O      (clk));
BUFG bufg_lclk2x(
    .I      (lclk2x0),
    .O      (clk2x));

IBUFG ibufg0(
    .I      (ramclki[0]),
    .O      (ramclki_ibufg[0]));

CLKDLL dll0(
    .CLKIN  (lclk_bufg),
    .CLKFB  (ramclki_ibufg[0]),
    .RST    (dllrst),
    .CLK2X   (ramclko[0]),
    .LOCKED (locked_ramclk[0]));

IBUFG ibufg1(
    .I      (ramclki[1]),
    .O      (ramclki_ibufg[1]));


CLKDLL dll1(
    .CLKIN  (lclk_bufg),
    .CLKFB  (ramclki_ibufg[1]),
    .RST    (dllrst),
    .CLK2X   (ramclko[1]),
    .LOCKED (locked_ramclk[1]));

I have got the following errors. And I have set the enviroment
variable to 1.
ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
is driving
   a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
driven by
   a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
error, set
   environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
is driving
   a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
driven by
   a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
error, set
   environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
is driving
   a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
driven by
   a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
error, set
   environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
Errors found during logical drc.

Anyone have idea about it? Thanks.

Article: 58079
Subject: Re: Combinational logic and gate delays - Help
From: "Avrum" <avrum@REMOVEsympatico.ca>
Date: Mon, 14 Jul 2003 15:10:20 -0400
Links: << >>  << T >>  << A >>
There are a couple of things that can be causing this.

First, you don't mention if you are using synthesis or schematic capture -
if you are using synthesis, then what you are drawing may not be what is
implemented. The basic logic unit in an FPGA is the four input lookup. The
synthesis tool will build "optimal" circuits based on that. Since there are
only three signals here, it is likely that a synthesis tool would implement
OP1 and OP2 independently - so OP2 would be a function of the clock and the
2 control signals, and would NOT use the output of the logic generating OP1.
By the way, gating signals with clocks is also not a really good idea in
FPGAs

Second, a very significant portion of FPGA timing is determined by the
routing, not by the logic implemented. So even if OP2 is fed from the output
of OP1, it is possible that (say) the routing from OP1 to the output pad is
FAR longer than the routing from OP2 to its output pad.

In general, what you are trying to do is NOT recommended - it is VERY
difficult to control the combinational timing of output signals. If you are
comitted to doing this, then you have to control the placer/router to
acheive the desired results. For example, you can put a constraint on OP1
specifying that it should come very quickly after the clock, and a second
constraint on OP2 specifying that it must have a minimum propagation time.
However, FPGA tools are not notoriously good at this, and the mechanism for
specifying these constraints is not trivial. If you are really a masochist,
then you can try and place and route the components yourself - that will
lock down the timing, but is INCREDIBLY hard to do! In general you REALLY
don't want to try and control the timing of combinational signals in an FPGA
(or in an ASIC, for that matter, but its a little easier in an ASIC).

Instead of posting questions on how to get the tool to do something it
really doesn't like doing, why don't you broaden the topic and tell us what
you are trying to do - what you are trying to control with this circuit, and
why do you need this timing relationship. There is almost always a way of
doing what you want to accomplish without resorting to controlling
combinational delays.

Avrum



"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message
news:184c35f9.0307140637.71a0f69c@posting.google.com...
> Hi Peter and All
>
> This implementation and consequent resulting delays issue is begining to
> drive me around the bend.
>
> Below is a small diagram of my schematic.
> To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
> I set up the circuit as shown.
> However I find in my simulation results that OP2 changes state
> before OP1.
> This appears to defy the laws of physics but Im sure there is a simple
> explenation.
>
> Signals control 1 and control 2 are low throughout.
>
> Regards
>
> Denis
>
>                               OP2
>     OP1                       _|_
>      |                         OR
>      |                        |__|
>      |                         ||____ control 1
>      |                         |
>      |_____________| Not |_____|
>     _|_
>      OR
>     |__|
>      ||____
>      |     |
>      |    Not
> control2   |
>            |
>          Main Clk
>
>
> Peter Alfke <peter@xilinx.com> wrote in message
news:<3F11F909.A2E41D61@xilinx.com>...
> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored
bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.
> >
> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all
prefer.
> >
> > Peter Alfke, Xilinx Applications
> > ============================
> > Denis Gleeson wrote:
> > >
> > > Hello All
> > >
> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.
> > >
> > > My problem is that I need a certain timing relationship between four
of
> > > the outputs.
> > >
> > > I realise that normally to obtain a given timing relationship one
would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.
> > >
> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:
> > >
> > > (a) Different logic gates have different delays, A NOT has less delay
than
> > >     an OR gate. May be this should have been obvious to me. Is it
correct?
> > >
> > > (b) If I add a gate to create a delay, it seems to be getting
optimised out.
> > >     Is there some way to stop a gate added for this purpose from being
removed?
> > >
> > > Thanks for all assistance in advance.
> > >
> > > Denis



Article: 58080
Subject: Re: Graduation Day: My first 4-layer PCB
From: news@sulimma.de (Kolja Sulimma)
Date: 14 Jul 2003 12:22:14 -0700
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vh475j86lssh06@corp.supernews.com>...
> >    Also, I detest high value ceramics.  From painful experiences with
> >strange leakage behavior (such as behaving like a low voltage zener) I am
> >now avoiding them like the plague.

I made good experiences with large ceramic caps, but one should note
that some linear regulators such as the LM1086 need the higher ESR for
the large caps to avoid oszillation.

Also everyone concerned about high frequency noise shoul read:
"High Speed Digital Design - A Handbook of Black Magic".
It has been recommended in this newsgroup a couple of times before.

Kolja Sulimma

Article: 58081
(removed)


Article: 58082
Subject: Re: Graduation Day: My first 4-layer PCB
From: james <>
Date: Mon, 14 Jul 2003 15:57:45 -0400
Links: << >>  << T >>  << A >>
On Mon, 14 Jul 2003 03:00:03 -0000, hmurray@suespammers.org (Hal
Murray) wrote:

>>    Also, I detest high value ceramics.  From painful experiences with
>>strange leakage behavior (such as behaving like a low voltage zener) I am
>>now avoiding them like the plague.
>
>Seems strange.  Was it just one cap, or one batch?  Lots of people are
>using them because they have better ESR than tantalum for the same value.
*********************************************

Ceramics do have their problems. If the case or the terminations have
micro cracks then mositure leakage can occur. Also the termination can
have dendritic growth if not properly plated or the board properly
cleaned of chlorides. 

Still I prefer them in the 1 to 10 uF range over tants, especially in
supply lines to RF circuits. 

james


Article: 58083
Subject: Re: programming a PLD/CPLD with a PIC?
From: ben@ben.com (Ben Jackson)
Date: Mon, 14 Jul 2003 20:03:59 GMT
Links: << >>  << T >>  << A >>
In article <c10cd8da.0307140345.f0999e@posting.google.com>,
javid <javodv@yahoo.es> wrote:
>
>I was wondering if it is possible to program a PLD/CPLD via a PIC
>(without connecting external memory). The PIC I am using has a
>internal RAM of 768 bytes and 16k of flash. I have seen some app.notes
>from Altera/Xilinx/Lattice but I think that I need a more powerful
>micro for doing the CPLD reprograming with it. Is there any new small
>CPLD easy to reprogram?. I would appreciate any suggestion or link.

You could probably bit-bang JTAG with a PIC.  I'm not at a computer
with a Xilinx dev env, but I bet the files are pretty big relative to
PIC flash size.  And obviously you'd want at least 2 of them, since
otherwise you'd just leave the CPLD flashed permanently...

-- 
Ben Jackson
<ben@ben.com>
http://www.ben.com/

Article: 58084
Subject: Re: Graduation Day: My first 4-layer PCB
From: james <>
Date: Mon, 14 Jul 2003 16:07:55 -0400
Links: << >>  << T >>  << A >>
My experience comes from layout of small circuit boards for wireless
data communications. In this arena the reciever antenna was generally
not more than 0.5 inch distance from one to two microcontrollers and
memeory chips. So the minimization of any ground and power loops and
radiation was a primary concern as they were the high current carrying
traces. Even at 1 Mhz internal buss frequency you would be surprised
how much noise comes out of an MC68HC11 micro controller. Especially
when the receiveing antenna is only half an inch away from the chip.

Ceramic chips do have their problems with dendrites if the PCB is not
thoroughly cleaned of chlorides. Tantalums can be damaged during
drops. They also do not like RF currents either. 

Then there is ESD spikes! that is another subject to its own.
 
james


On Sun, 13 Jul 2003 22:53:46 -0400, "t hicks" <hicksthe@egr.msu.edu>
wrote:

>James,
>    Some good points, however I will disagree on two issues.  First, I
>personally do my power routing last on multilayer boards.  I expect that I
>will need to shove some traces slightly in order to get them in.  However,
>for me this gets better overall routing with very short traces to power
>pads.  The one exception to this is in FPGA designs where I do carefully
>route the FPGA supplies first.  Even then I expect that I will need to do
>some substantial re-routing to finally get all the signals in.
>    Also, I detest high value ceramics.  From painful experiences with
>strange leakage behavior (such as behaving like a low voltage zener) I am
>now avoiding them like the plague.
>    Of course, these are only my personal experiences.  The routing, I am
>sure is puerly a matter of personal preference.  I know that many people use
>large value ceramics with no problems, so consider that to be just a
>warning.  If you see the same issues, then you usually can get away with
>mounting a small tantalum on a large (1206 size or bigger) ceramic as long
>as the voltage is very low.  By the way, I use many more bulk capacitors
>that the norm as I have had problems with noise showing up in the low noise
>analog parts of my system.  On a spartan2e, I am using 8 0.1uf ceramics and
>8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per
>supply) .  And before you ask... Is that _really_ necessary?  Yes, it does
>seem to show up in the final system noise behavior.
>
>Thanks,
>Theron
>
><james> wrote in message news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com...
>> Many of the comments here have been great.
>>
>> I would add this from some thoughts and experience in layout.
>>
>> If the device is not being used near any RF circuitry then the bypass
>> caps are of adequate value. If there is nearby RF circuitry then add
>> either 100pF or 30pF caps. The 100pF is good for VHF frequencies and
>> the 30pF cap is good for UHF. I would change from tant caps to ceramic
>> for the 10uF caps though.
>>
>> Still all the steps used to elliminate EMI suggested are good. A note
>> on the 208 pin package,  it is big and it will radiate no matter how
>> careful your bypasses are and board layout.
>>
>> I reccommend that the you do a signal layer, followed by a ground
>> layer, then power,  and finally the bottom layer can be mixed but
>> should primarily be signal. The power layer can have multiple voltages
>> on the plane. It is best to keep a 20 to 1 separation between powers.
>> Thus if you are using a 0.062 laminate,  you will have between 18 and
>> 22 mils between layers. I then would leave at least 40 mils preferably
>> 80 mils between traces on the different power busses. This will
>> minimize E-fields that fringe off the power runners.
>>
>> I am not a big fan of blind vias as Xilinx shows in their app note.
>> They are expensive and difficult to troubleshoot. Heaven forbid if one
>> is open either. The board is then shot. Avoid them at all costs.
>>
>> Vias to the ground plane and power should be at least two of them per
>> trace. Especially in high current, peak or constant, traces. Good idea
>> in case the PCB fabricator screws up on the plated through holes. Vias
>> through the power and ground planes should have at least 20 mil anular
>> space around the via. More on faster switching lines if possible.
>>
>> One very important thing. Layout power and ground first. Before you
>> route any signal line do power and ground first. They should be as
>> direct from the source to the devices as possible. Avoid power loops.
>> Branch power from the power buss to the components.  Also keep all
>> power runners 40 to 80 mils from the edge of the board. Ground plane
>> can extend to about 10 mils to the edge. Signals should not be closer
>> than 20 mils to the edge.
>>
>> some thoughts
>>
>> james
>>
>> On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.."
>> <gabsterblue@hotmail.com> wrote:
>>
>> >Hi,
>> >
>> >I'm made many 2-layer PCB's in the past years, but I'm about to start the
>> >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx
>> >Spartan IIE XC2S300 in PQ208 package running at 12MHz), 3 power supply
>> >regulators, an oscillator block, a PROM and a logic IC.
>> >
>> >In addition to other literature, I read the following document:
>> >http://www.xilinx.com/xapp/xapp623.pdf
>> >but it is rather complicated and not straight foward for a rookie like me
>in
>> >FPGA design! So here's a few direct questions:
>> >
>> >1) 4-layer, why is it so important?
>> >
>> >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or
>> >TOP/POWER/GND/BOTTOM), why?
>> >
>> >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1F
>per
>> >power pin (1.8V and 3.3V) + one 10F per power supply (1.8V and 3.3V). Is
>> >that accurate? Should I do more? What should I avoid?
>> >
>> >4) What is the concept surrounding islands on the power plane? What
>should
>> >that plane look like? What should I avoid? What the hell about it, this
>> >plane is a mystery for me!!!
>> >
>> >In order to avoid asking 1000's other questions, I wonder if someone
>could
>> >also direct me toward a complete document talking about PCB design
>> >guidelines for PQ package FPGA's. I found that for the BGA packages on
>> >xilinx website, but it didn't help me much.
>> >
>> >Thanks a lot,
>> >Gabriel
>> >
>>
>


Article: 58085
Subject: Re: Combinational logic and gate delays - Help
From: Ray Andraka <ray@andraka.com>
Date: Mon, 14 Jul 2003 16:13:52 -0400
Links: << >>  << T >>  << A >>
A Spartan XL precludes some of the tricks you could have done with a DLL or DCM.  The
problem you are running into is due to the fact that a susbtantial part of the propagation
delay is comprised of routing delays.  Your circuit is most likely being implemented in
two LUTs with parallel inputs.  While the LUT delays are fairly consistent, the delays
incurred in getting the signals to the LUTs and the outputs from the LUTs to the I/O are
in all likelihood not matched.  Unfortunately, the router is not really set up for
matching delays, so you'll probably have to resort to hand routing it using FPGA editor if
this approach is really necessary.  If you could obtain a 2x or 4x clock in the context of
your system, it may be far easier to deal with.  You might also consider using a small
CPLD instead, the routing there is usually less sensitive to the tools.

Denis Gleeson wrote:

> Hi Peter
>
> Thanks as always for your help.
>
> I am using a Spartan XL XCS05XL. I dont think features
> like that from the Virtex - II are available.
>
> Thanks for the point on the delay. As you can see Im new to
> some of the more basic points. Amazing how far you can get
> without understanding everything that goes on under the hood.
>
> In the simulation of my final design I can see that signals that
> travel through more gates in my schematic have a greater delay. Does this
> tie in with the look up table implementation.
>
> Thanks
>
> Denis
>
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F11F909.A2E41D61@xilinx.com>...
> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.
> >
> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all prefer.
> >
> > Peter Alfke, Xilinx Applications
> > ============================
> > Denis Gleeson wrote:
> > >
> > > Hello All
> > >
> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.
> > >
> > > My problem is that I need a certain timing relationship between four of
> > > the outputs.
> > >
> > > I realise that normally to obtain a given timing relationship one would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.
> > >
> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:
> > >
> > > (a) Different logic gates have different delays, A NOT has less delay than
> > >     an OR gate. May be this should have been obvious to me. Is it correct?
> > >
> > > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> > >     Is there some way to stop a gate added for this purpose from being removed?
> > >
> > > Thanks for all assistance in advance.
> > >
> > > Denis

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58086
Subject: Re: An All Digital Phase Lock Loop
From: Ray Andraka <ray@andraka.com>
Date: Mon, 14 Jul 2003 16:20:07 -0400
Links: << >>  << T >>  << A >>
Yes, we have.   One approach we had success with was one that used a DDS type
setup where the increment value got bumped up/down depending on the phase of the
accumulator vs the reference.  Works quite well as long as the reference is
fairly stable.   In our case we needed to track a mechanical system which had a
fairly high variance on the reference, so we wound up putting a lot of extra
crap on the design to improve the transient response without it going into
oscillation.  Still lots smaller than doing a digital equivalent of an analog
PLL though.

Jason Berringer wrote:

> Hello guru's
>
> I was wondering if anyone has ever attempted a phase lock loop in digital
> before (specifically VHDL). I'm looking for some examples or pointers on
> trying to build one for a low frequency range of 200 Hz to 200 kHz. I would
> appreciate any comments or suggestions. Google didn't get me very far, so if
> you know of any app notes, etc. please let me know.
>
> Thanks,
>
> Jason

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58087
Subject: Re: An All Digital Phase Lock Loop
From: "Kevin Neilson" <kevin_neilson@removethistextcomcast.net>
Date: Mon, 14 Jul 2003 21:49:39 GMT
Links: << >>  << T >>  << A >>
My all-digital PLL was similar and worked very well.  My reference clock and
system clock were pretty stable so I didn't do a lot of analysis.  I just
designed the loop with a small gain, so it took a bit to lock on (which
wasn't a problem in my application) but once it was locked it was very
stable and didn't oscillate.  The only problem with the low gain is that it
took forever to lock in the simulation, so I made an adjustable loop gain so
I could kick it up for simulations and see it lock faster (although it rung
a bit before locking.)
-Kevin

"Ray Andraka" <ray@andraka.com> wrote in message
news:3F131077.9C3A8039@andraka.com...
> Yes, we have.   One approach we had success with was one that used a DDS
type
> setup where the increment value got bumped up/down depending on the phase
of the
> accumulator vs the reference.  Works quite well as long as the reference
is
> fairly stable.   In our case we needed to track a mechanical system which
had a
> fairly high variance on the reference, so we wound up putting a lot of
extra
> crap on the design to improve the transient response without it going into
> oscillation.  Still lots smaller than doing a digital equivalent of an
analog
> PLL though.
>
> Jason Berringer wrote:
>
> > Hello guru's
> >
> > I was wondering if anyone has ever attempted a phase lock loop in
digital
> > before (specifically VHDL). I'm looking for some examples or pointers on
> > trying to build one for a low frequency range of 200 Hz to 200 kHz. I
would
> > appreciate any comments or suggestions. Google didn't get me very far,
so if
> > you know of any app notes, etc. please let me know.
> >
> > Thanks,
> >
> > Jason
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 58088
Subject: Booth Multipliers
From: "Kevin Neilson" <kevin_neilson@removethistextcomcast.net>
Date: Mon, 14 Jul 2003 22:03:12 GMT
Links: << >>  << T >>  << A >>
Since I started my unpaid permanent sabbatical, I've been studying a few
things I'd neglected.  (Mind you, I'm not studying TOO hard.)  I've been
learning a bit about adder and multiplier structures since that was
something I never had to worry about with Xilinx since the hardware was
built in.  I've been learning about carry lookahead structures, and I was
wondering if that structure is commonly used in ASICs.  Also, does an adder
in Xilinx use the carry-chain structure because it's the fastest possible
hardware, or is it a compromise that allows for fairly fast adding without
all the hardware of carry lookahead?

I've also been learning about Booth multipliers.  I'm ignorant as to how the
Virtex-II multiplier is constructed; does it have a Booth architecture?  And
if you synthesize a multiplier in a Virtex part, does it just shifted adders
or will the synthesizer create a Booth-type structure?

Do ASIC guys worry about this anymore, or do their synthesizers just pick an
appropriate adder or multiplier for them?  I would think with all the gates
in an ASIC, you wouldn't have to spend a lot of time trying to save gates by
using ripple adders making other compromises that had to be made in the
past.

-Kevin



Article: 58089
Subject: Re: Booth Multipliers
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 14 Jul 2003 22:06:11 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <AMFQa.61612$ye4.43895@sccrnsc01>,
Kevin Neilson <kevin_neilson@removethistextcomcast.net> wrote:
>Since I started my unpaid permanent sabbatical, I've been studying a few
>things I'd neglected.  (Mind you, I'm not studying TOO hard.)  I've been
>learning a bit about adder and multiplier structures since that was
>something I never had to worry about with Xilinx since the hardware was
>built in.  I've been learning about carry lookahead structures, and I was
>wondering if that structure is commonly used in ASICs.  Also, does an adder
>in Xilinx use the carry-chain structure because it's the fastest possible
>hardware, or is it a compromise that allows for fairly fast adding without
>all the hardware of carry lookahead?

The Xilinx FPGAs use ripple-carry adders mostly because they can be
arbitrarily aligned.  A carry-lookahead structure, although
asymptotiacally faster, has alignment boundries which would make the
placement problem harder.

Also, since the FPGA uses dedicated (non-switched) interconnect,
adders are so much faster than normal logic, so the need to make
asymtopically faster adders isn't necessary, as the rest of the logic
is slow once signals go over the general interconnect.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 58090
Subject: Re: DCM CLKFX simulation
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 15 Jul 2003 08:15:40 +1000
Links: << >>  << T >>  << A >>
l nguyen wrote:
> I can see all other attributes changing accordingly to my entry 
> design such as CLKDV_DIVIDE, DLL frequency, startup wait,... but the 
> mistery M and D values not show up anywhere. 

That's pretty wierd.  I suggest you double-check your design, and also 
read through the various Xilinx App notes about the DCMs.

John


Article: 58091
Subject: Re: Combinational logic and gate delays - Help
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 14 Jul 2003 15:15:47 -0700
Links: << >>  << T >>  << A >>
Denis, you may just have been lucky. The software can pack any logic
with four inputs and one output into one LUT, with almost the same dalay.
Don't assume blindly that more logic always means a longer delay...
Peter Alfke
===========
Denis Gleeson wrote:
> 
> 
> In the simulation of my final design I can see that signals that
> travel through more gates in my schematic have a greater delay. Does this
> tie in with the look up table implementation.
> 
> Thanks
> 
> Denis
>

Article: 58092
Subject: Re: Combinational logic and gate delays - Help
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 14 Jul 2003 15:21:33 -0700
Links: << >>  << T >>  << A >>
Denis, it seems that you are gating the clock. This is not exactly
illegal or immoral, but definitely a bad and dangerous habit. Try to
avoid that. (Use CE instead).

Also remember that the software can compile your combinatorial logic
structure any way it sees fit. In synchronous logic, this does not
matter. But you seem to expect that it does the logic "your way"...
Peter Alfke

Denis Gleeson wrote:
> 
> Hi Peter and All
> 
> This implementation and consequent resulting delays issue is begining to
> drive me around the bend.
> 
> Below is a small diagram of my schematic.
> To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
> I set up the circuit as shown.
> However I find in my simulation results that OP2 changes state
> before OP1.
> This appears to defy the laws of physics but Im sure there is a simple
> explenation.
> 
> Signals control 1 and control 2 are low throughout.
> 
> Regards
> 
> Denis
> 
>                               OP2
>     OP1                       _|_
>      |                         OR
>      |                        |__|
>      |                         ||____ control 1
>      |                         |
>      |_____________| Not |_____|
>     _|_
>      OR
>     |__|
>      ||____
>      |     |
>      |    Not
> control2   |
>            |
>          Main Clk
> 
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F11F909.A2E41D61@xilinx.com>...
> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.
> >
> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all prefer.
> >
> > Peter Alfke, Xilinx Applications
> > ============================
> > Denis Gleeson wrote:
> > >
> > > Hello All
> > >
> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.
> > >
> > > My problem is that I need a certain timing relationship between four of
> > > the outputs.
> > >
> > > I realise that normally to obtain a given timing relationship one would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.
> > >
> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:
> > >
> > > (a) Different logic gates have different delays, A NOT has less delay than
> > >     an OR gate. May be this should have been obvious to me. Is it correct?
> > >
> > > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> > >     Is there some way to stop a gate added for this purpose from being removed?
> > >
> > > Thanks for all assistance in advance.
> > >
> > > Denis

Article: 58093
Subject: Re: Missing something...
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Jul 2003 19:17:29 -0400
Links: << >>  << T >>  << A >>
Thank you for the advice.  I always appreciate it when others take time
out of their day to assist others.  


Stifler wrote:
> 
> Rick,
> 
> You are missing something. Any shred of digital design capability or
> ability to solve any problem on your own. Why don't you just give up?
> McDonald's is always looking for someone with your ability.
> 
> I would recommend you go to college and get a BSEE. Concentrate on
> digital design techniques.
> 
> Is Arius even a company? I'd be embarassed if my boss could see my
> incompetence so publicly. You must be the CEO, President, VP of
> Engineering and lone grunt at Arius all rolled into one.
> 
> Good luck buddy.
> 
> Stifler
> 
> rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F0EEEC8.D5038C4B@yahoo.com>...
> > Amontec Team wrote:
> > >
> > > For myself, I never use both ieee.numeric_std.all and
> > > ieee.STD_LOGIC_ARITH together ... can produce many troubles since there
> > > describe same functions. It is very dangerous, because the compiler or
> > > syntheziser can interprete different things.
> > >
> > > For your code, why
> > > ELSE  STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z');
> > >
> > > and not
> > > ELSE (others => 'Z');
> > >
> > > maybe this casting can be not so nice, try to skip it, you very don't
> > > need that!
> >
> > I need to sit back down with my books!  It has been so long since I have
> > written VHDL that I don't remember what all the libraries do.  I do
> > remember that you want to use numeric_std rather than the Synopsis
> > signed and unsigned libraries.
> >
> > The type cast was held over from where I started with this example.  I
> > started with a 16 bit data bus and an 8 bit register.  I had it written
> > to force the unused bits to 0 like this...
> >
> > Data <= STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z') & ScratchReg;
> >
> > This is the sort of thing that is not always obvious in VHDL since the
> > strong typing can get in the way of what you want to do.  I remember
> > that aggregates and concatenation could give errors very easily between
> > the language *features* and the compiler bugs.
> >
> > Now my work is to build this up into a useful circuit while mapping out
> > all the quirks of the tools.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58094
Subject: Re: Missing something...
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Jul 2003 19:19:20 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Stifler, do what your mother should have taught you: wash out your mouth
> with soap.
> We do not tolerate your arrogant tone in this newsgroup. Rickman has
> made many valuable contributions to this newsgroup, which is more than
> can be said about you.
> Style derailments like yours must be "nipped in the bud," to use a mixed metaphor.
> Now, lets get back to our normal civilized and helpful tone.
> Peter Alfke

Thanks Peter.  It is nice to know that my presence here is appreciated.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58095
Subject: Re: Quartus VHDL problem with aggregate and type cast
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Jul 2003 19:37:26 -0400
Links: << >>  << T >>  << A >>
Alan Fitch wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3F0F337C.27A8ED76@yahoo.com...
> <snip>
> > -- VERSION 1
> > -- These lines work correctly
> > --  Data (15 downto 8) <=  (others => '0')  WHEN  (ReadScratchReg =
> '1')
> > --    ELSE  (others => 'Z');
> > --  Data (7 downto 0) <=  ScratchReg  WHEN  (ReadScratchReg = '1')
> > --    ELSE  (others => 'Z');
> >
> > --  VERSION 2
> > --  This line fails by disabling the tristate buffers
> > --    Data  <=  STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
> > ScratchReg  WHEN  (ReadScratchReg = '1')
> > --      ELSE  (others => 'Z');
> > -- The difference seems to be the use of the type cast.
> > -- Using a type cast with the (others => aggregate seems to fail in
> > other cases as well.
> >
> > --  VERSION 3
> > --  This version produces open drain outputs
> >     Data  <=  DataOut  WHEN  (ReadScratchReg = '1')
> >       ELSE  (others => 'Z');
> > --  This seems to work ok
> > --    DataOut <= "00000000" & ScratchReg;
> > --  This produces no register and open drain drivers
> >     DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
> > ScratchReg;
> >
> 
> Hallo Rick,
>            just out of curiosity, have you tried using a named
> subtype?
> E.g.
> 
>    architecture...
>       subtype vec8 is std_logic_vector(7 downto 0);
>    begin
> 
>      ...
> 
> --  VERSION 3
> --  This version produces open drain outputs
>       Data  <=  DataOut  WHEN  (ReadScratchReg = '1')
>       ELSE  (others => 'Z');
> --  This seems to work ok
> --    DataOut <= "00000000" & ScratchReg;
> --  This produces no register and open drain drivers
>      DataOut <= Vec8'(others => '0') & ScratchReg;
> 
> I wondered if Quartus is getting confused by the (15 downto 8) slice?
> 
> The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8)
> you create an anonymous subtype, and I know that anonymous subtypes
> are not always allowed where named subtypes are allowed. For instance,
> it's illegal to declare a function returning an anonymous subtype,
> but it's OK with a named subtype.
> 
> regards
> 
> Alan

Alan, yes, that worked.  Is this a bug that I should report to Altera? 
Or is this to be expected in VHDL?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58096
Subject: Re: An All Digital Phase Lock Loop
From: Ray Andraka <ray@andraka.com>
Date: Mon, 14 Jul 2003 20:13:20 -0400
Links: << >>  << T >>  << A >>
Mine used a barrel shift in the feedback to get a gain that increased with the
size of the error.  Had to do that to get a quick lock and still be able to
chase the reference.  The reference was derived from a quad encoder on the
mechanical media path.  The PLL had to adjust a process to keep a certain number
of events between encoder pulses.  All in all, it was a pretty nasty problem
because of the dynamics and limited resolution of the encoder.

Kevin Neilson wrote:

> My all-digital PLL was similar and worked very well.  My reference clock and
> system clock were pretty stable so I didn't do a lot of analysis.  I just
> designed the loop with a small gain, so it took a bit to lock on (which
> wasn't a problem in my application) but once it was locked it was very
> stable and didn't oscillate.  The only problem with the low gain is that it
> took forever to lock in the simulation, so I made an adjustable loop gain so
> I could kick it up for simulations and see it lock faster (although it rung
> a bit before locking.)
> -Kevin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3F131077.9C3A8039@andraka.com...
> > Yes, we have.   One approach we had success with was one that used a DDS
> type
> > setup where the increment value got bumped up/down depending on the phase
> of the
> > accumulator vs the reference.  Works quite well as long as the reference
> is
> > fairly stable.   In our case we needed to track a mechanical system which
> had a
> > fairly high variance on the reference, so we wound up putting a lot of
> extra
> > crap on the design to improve the transient response without it going into
> > oscillation.  Still lots smaller than doing a digital equivalent of an
> analog
> > PLL though.
> >
> > Jason Berringer wrote:
> >
> > > Hello guru's
> > >
> > > I was wondering if anyone has ever attempted a phase lock loop in
> digital
> > > before (specifically VHDL). I'm looking for some examples or pointers on
> > > trying to build one for a low frequency range of 200 Hz to 200 kHz. I
> would
> > > appreciate any comments or suggestions. Google didn't get me very far,
> so if
> > > you know of any app notes, etc. please let me know.
> > >
> > > Thanks,
> > >
> > > Jason
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58097
Subject: Re: An All Digital Phase Lock Loop
From: "Jason Berringer" <look_at_bottom_of@email.com>
Date: Mon, 14 Jul 2003 20:49:39 -0400
Links: << >>  << T >>  << A >>
Thanks for all of the responses, it's a great place to get going from.
Having further looked into this analog design it seems as though the analog
phase lock loop IC was being implemented in a circuit that essential is a
frequency lock loop more than anything else. The input signal goes through
this phase lock loop chip and then through a very heavy analog filter which
converts the differential output of the IC to a single ended DC voltage that
then is used to steer a VCO, the VCO output then gets divided down and the
resulting waveform is used to drive the main circuitry (off of which the
reference or input signal is derived).

This being the case if you try to create a digital version of this, your
output waveform is essentially a rock solid wave and since it is driving the
circuit that your reference or input signal is derived from nothing moves,
i.e when you turn it on it is locked almost instantly. If you ideally want
your system frequency to wander slightly (say +/- 200 Hz around a frequency
of say 25000 Hz) according to certain conditions such as temperature,
current, etc. how is that analog type lag created in the digital domain.
Would it just be a delay from input to output or something similar. In
essence what I'm looking for is to create an oscillator that maintains it's
peak amplitude, as temperatures increase (due to circuit current) the tuned
circuits' peak value changes, and the circuit frequency naturally wants to
move to the peak.

Does this make sense? It's an interesting problem, and I don't think that
the answer is very easy. I'm approaching it from a few angles at present.

Once again thanks for the responses.

Jason


"Ray Andraka" <ray@andraka.com> wrote in message
news:3F134720.D19A8BCA@andraka.com...
> Mine used a barrel shift in the feedback to get a gain that increased with
the
> size of the error.  Had to do that to get a quick lock and still be able
to
> chase the reference.  The reference was derived from a quad encoder on the
> mechanical media path.  The PLL had to adjust a process to keep a certain
number
> of events between encoder pulses.  All in all, it was a pretty nasty
problem
> because of the dynamics and limited resolution of the encoder.
>
> Kevin Neilson wrote:
>
> > My all-digital PLL was similar and worked very well.  My reference clock
and
> > system clock were pretty stable so I didn't do a lot of analysis.  I
just
> > designed the loop with a small gain, so it took a bit to lock on (which
> > wasn't a problem in my application) but once it was locked it was very
> > stable and didn't oscillate.  The only problem with the low gain is that
it
> > took forever to lock in the simulation, so I made an adjustable loop
gain so
> > I could kick it up for simulations and see it lock faster (although it
rung
> > a bit before locking.)
> > -Kevin
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:3F131077.9C3A8039@andraka.com...
> > > Yes, we have.   One approach we had success with was one that used a
DDS
> > type
> > > setup where the increment value got bumped up/down depending on the
phase
> > of the
> > > accumulator vs the reference.  Works quite well as long as the
reference
> > is
> > > fairly stable.   In our case we needed to track a mechanical system
which
> > had a
> > > fairly high variance on the reference, so we wound up putting a lot of
> > extra
> > > crap on the design to improve the transient response without it going
into
> > > oscillation.  Still lots smaller than doing a digital equivalent of an
> > analog
> > > PLL though.
> > >
> > > Jason Berringer wrote:
> > >
> > > > Hello guru's
> > > >
> > > > I was wondering if anyone has ever attempted a phase lock loop in
> > digital
> > > > before (specifically VHDL). I'm looking for some examples or
pointers on
> > > > trying to build one for a low frequency range of 200 Hz to 200 kHz.
I
> > would
> > > > appreciate any comments or suggestions. Google didn't get me very
far,
> > so if
> > > > you know of any app notes, etc. please let me know.
> > > >
> > > > Thanks,
> > > >
> > > > Jason
> > >
> > > --
> > > --Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930     Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
> > >
> > >  "They that give up essential liberty to obtain a little
> > >   temporary safety deserve neither liberty nor safety."
> > >                                           -Benjamin Franklin, 1759
> > >
> > >
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 58098
Subject: Re: problems on using CLKDLL in Xilinx ISE
From: "Jay" <yuhaiwen@hotmail.com>
Date: Tue, 15 Jul 2003 10:11:27 +0800
Links: << >>  << T >>  << A >>
how about not use in_bufg_lclk, and use lclk_ibufg as the CLKIN

"Stephen" <whli_interqos@yahoo.com.hk>
??????:63d01b4.0307132323.7b58a4f1@posting.google.com...
> Hi Everyone,
>     I have got the following problem when I use following CLKDLL
> configuration in Xilinx ISE 5.1.
>
> // input of clock source
>
> IBUFG ibufg_lclk(
>     .I      (lclk),
>     .O      (lclk_ibufg));
>
> BUFG in_bufg_lclk(
>     .I      (lclk_ibufg),
>     .O      (lclk_bufg));
>
> CLKDLL dll_lclk(
>     .CLKIN  (lclk_bufg),
>     .CLKFB  (clk),
>     .RST    (dllrst),
>     .CLK0   (lclk0),
> .CLK2X (lclk2x0),
>     .LOCKED (locked_lclk));
>
> BUFG bufg_lclk(
>     .I      (lclk0),
>     .O      (clk));
> BUFG bufg_lclk2x(
>     .I      (lclk2x0),
>     .O      (clk2x));
>
> IBUFG ibufg0(
>     .I      (ramclki[0]),
>     .O      (ramclki_ibufg[0]));
>
> CLKDLL dll0(
>     .CLKIN  (lclk_bufg),
>     .CLKFB  (ramclki_ibufg[0]),
>     .RST    (dllrst),
>     .CLK2X   (ramclko[0]),
>     .LOCKED (locked_ramclk[0]));
>
> IBUFG ibufg1(
>     .I      (ramclki[1]),
>     .O      (ramclki_ibufg[1]));
>
>
> CLKDLL dll1(
>     .CLKIN  (lclk_bufg),
>     .CLKFB  (ramclki_ibufg[1]),
>     .RST    (dllrst),
>     .CLK2X   (ramclko[1]),
>     .LOCKED (locked_ramclk[1]));
>
> I have got the following errors. And I have set the enviroment
> variable to 1.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
>    a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
>    a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
>    environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
>    a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
>    a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
>    environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
>    a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
>    a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
>    environment variable  XIL_MAP_ALLOW_ANY_DLL_INPUT.
> Errors found during logical drc.
>
> Anyone have idea about it? Thanks.



Article: 58099
Subject: Re: Fpga design with multiple audio rate (44, 48khz ...)
From: "David" <gretzteam@hotmail.com>
Date: Mon, 14 Jul 2003 22:28:21 -0400
Links: << >>  << T >>  << A >>
Hi,
I'm happy to know that it would make sense! However, when I look at the
256Fs clock signal on my oscilloscope, it really looks crappy. I wonder if
there are anything that can be done (maybe inside the fpga) to make sure the
clock will be precise.
Thank you very much
David



> This would make sense.  Typically you feed that clock into a PLL/DLL,
> and your "other" clock into another PLL/DLL on the chip.


> > -The easiest one would be to clock the fpga using the clock signal
generated
> > by the CS8416 chip (it outputs a 256Fs clock). This way, I would always
be
> > synchronous with the CS8416. I wonder however if it is a good design
> > practice to use this kind of signal to clock the fpga. Furthermore,
since
> > this clock is not always present (during reset and startup), I would
need
> > another clock directly fed in the fpga to clock the controller and other
> > logic. Is this acceptable?
> >






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