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Article: 64275
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Article: 64276
Subject: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Tue, 23 Dec 2003 21:01:57 GMT
Links: << >>  << T >>  << A >>
"Swarna B" wrote:

> I am having a problem with one of my designs on Virtex II.
...
> I have noticed that the BIT files I generate do not behave
> consistently (most of the times it's working erroneously).
...
> - The DCM I have used to multiply an input clock by 2X. (I use the
> multiplied clock all over the design.)


What's the input frequency into the DCM?
Is the design fully synchronous?
How many clock domains?  If more than one, how are you crossing them?
What's the source of the data this chip is processing?
Is there a reset tree?  How is it designed?

More context would be useful.



-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





Article: 64277
Subject: Re: Xilinx Johnson counter Verilog example bug?
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Tue, 23 Dec 2003 21:11:04 GMT
Links: << >>  << T >>  << A >>
Hi - 

Verilog has both a blocking assignment (the type that appears in your
code fragment, and which uses the = sign) and a non-blocking
assignment, in which "=" is replaced by "<=".  With non-blocking
assignments, the right side of the assignment is saved in a temp
variable that you never see.  The temp variable is then transferred to
the left-hand side only after all such temp assignments have been made
for the clock event in question, including events that occur in other
always statements.  It's sort of the way things are actually done in
hardware, with data being stored in a master latch that closes at the
start of the new clock cycle, then transferred to a slave latch.
(Note to Verilog gurus: I know how inadequate an explanation this is,
but what were you expecting from a hardware designer?)

Try replacing:
          q[3:1] = q[2:0];     //Shift lower bits (Left Shift)
          q[0] = !q[3];	      //Circulate inverted MSB to LSB
with
          q[3:1] <= q[2:0];   //Shift lower bits (Left Shift)
          q[0] <= !q[3];      //Circulate inverted MSB to LSB

Bob Perlman
Cambrian Design Works

On Tue, 23 Dec 2003 10:25:05 -0800, Chris Carlen
<crcarle@BOGUS.sandia.gov> wrote:

>Greetings:
>
>I have set out to learn Verilog, and thus to learn to use the ModelSim 
>XE II v5.7c Starter simulation program that comes with Xilink WebPack 
>5.2i.  Yesterday I got the software all installed and ready for today's 
>first venture into my shiny new textbook "A Verilog HDL Primer" by J 
>Bhasker.
>
>I began by making sure I knew how to use the software by compiling and 
>simulating the example jc2_top.v together with jc2_test.tf (the test 
>bench) from the WebPack .../ISEexamples/jc2_ver directory.
>
>The readme for the verilog source says that it should implement a 
>Johnson counter with the pattern (depending on the count direction 
>selected):
>
>left	right
>0000	0000
>0001	1000
>0011	1100
>0111	1110
>1111	1111
>1110	0111
>1100	0011
>1000	0001
>0000	0000	(repeats)
>
>
>But in fact the counter produces the following result in the simulator 
>(initial state not shown, only repeated pattern):
>
>left	right
>0001	1000
>0011	1100
>0111	1110
>1110	0111
>1100	0011
>1000	0001
>0001	1000	(repeats)
>
>The Verilog they provided is (just counter section within an always @ 
>(posedge clk) begin procedural construct):
>
>//Counter section:
>    if(run) begin
>       if(dir) begin
>          q[3:1] = q[2:0];	//Shift lower bits (Left Shift)
>          q[0] = !q[3];		//Circulate inverted MSB to LSB
>       end
>       else begin
>          q[2:0] = q[3:1];	//Shift upper bits (Right Shift)
>          q[3] = !q[0];		//Circulate inverted LSB to MSB
>       end
>    end
>
>
>Before knowing anything at all about Verilog, I proceded to tinker with 
>this code.  I suspected that this represents stated logic, and so all 
>statements are executed in parallel at each clock edge (which turns out 
>not to be the right assumption, which I learned after reading a bit from 
>my Verilog text).
>
>So I modified the code to be this way to test this hypothesis:
>
>//Counter section:
>    if(run) begin
>       if(dir) begin
>          q[0] = !q[3];		//Circulate inverted MSB to LSB
>          q[3:1] = q[2:0];	//Shift lower bits (Left Shift)
>       end
>       else begin
>          q[3] = !q[0];		//Circulate inverted LSB to MSB
>          q[2:0] = q[3:1];	//Shift upper bits (Right Shift)
>       end
>    end
>
>Which of course produced the following pattern:
>
>left	right
>0011	1100
>0111	1110
>1111	1111
>1100	0011
>1000	0001
>0000	0000
>0011	1100	(repeats)
>
>This led me to suspect that the code is actually executed sequentially 
>not in parallel.  Looking at my new Verilog text confirmed this to be 
>the case.
>
>The questions are thus:
>
>1. Why did Xilinx incorrectly implement what was described in the README?
>
>2.  Has anyone encountered this screwed up example before?
>
>3.  What is the correct implentation?
>
>Oh no, that's too easy.  I'm supposed to be learning this language, so 
>I'll take a crack at it.
>
>After several frustrating attempts to fix the counter code, I realized 
>that there was no conceivable logic with which to determine the value of 
>the q[0] bit *after* copying the q[2:0] bits over the q[3:1] bits, 
>because I need to work with the original q[3] bit (left counting case).
>
>One way would be to put in another register bit, but this would be a 
>kuldgy waste of ffs.  At the brink of demoralization (and recognizing 
>that the brick wall was self-imposed by my not knowing how to do 
>anything besides the behavioral style of coding, which forces the 
>sequential execution which I don't want, I finally happened upon the 
>answer to my hopes: a way to assign the bits of the result based on the 
>bits of the previous state, all in parallel.  That is the concatenation 
>operation, leading to:
>
>//Counter section:
>    if(run) begin
>       if(dir) begin
>          q[3:0] = {q[2], q[1], q[0], ~q[3]};
>       end
>       else begin
>          q[3:0] = {~q[0], q[3], q[2], q[1]};
>       end
>    end
>
>Whew, it works!
>
>What a way to learn a language.  This was my first day of Verilog.  I 
>planned to start by typing in an example from my textbook, but instead I 
>just couldn't resist trying to fix the Xilinx example.  Now off to 
>typing in my first Verilog code from scratch to finish.
>
>Good day!


Article: 64278
Subject: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
From: billh40@aol.com (Bill Hanna)
Date: 23 Dec 2003 15:19:33 -0800
Links: << >>  << T >>  << A >>
swarnakumar_ba@yahoo.com (Swarna B) wrote in message news:<11b5e6c5.0312230813.420bf400@posting.google.com>...
> Hi everybody,
> 
> I am having a problem with one of my designs on Virtex II.
> I have been trying to get this working for quite some time now ( I
> have generated around 50 BIT files by now) and have not yet got it :(
> I have noticed that the BIT files I generate do not behave
> consistently (most of the times it's working erroneously). i.e if I
> make some small modification and regenerate the BIT file it goes
> haywire. I am just sending out a constant data through a mux and some
> registers. The data gets corrupted. This I observed by connecting the
> outputs to a logic analyzer. I also am using ChipScope and I can see
> that the data gets corrupted even as seen in ChipScope.
> Currently I am suspecting things like -
> - The DCM I have used to multiply an input clock by 2X. (I use the
> multiplied clock all over the design.)
> - My timing constraints, because, some of the corruptions I observed
> hint at clock skew > Data delay.
> - A high fanin MUX in the data path.
> 
> But ISE is not giving me any errors/warnings in this regards. It says
> all constraints met as seen in the TWR file.
> 
> Is this a known issues of somekind! I can post more details(what?) if
> somebody can analyze the specific nature of the problem.
> 
> Any information regarding this would be greatly helpful!
> 
> I looked through some of the older posts in this groups which talked
> about clock jitter. One thing I have to do is - I have to look at my
> input clock jitter spec. I definitely need more info :)
> 
> Thanks and Regards,
> Swarna

    1) Use one global clock buffer for all  clock lines.

    2) Next, if you still have problems , then use 2-phase clocking.
 
    3) OR , add 2 nsec clock skew constraints on local clock lines.

      Line delays can reach 20 nsecs on lines that have no time constraints.

    4) Use the AREA Block constraint to locate logic in close areas to minimize

       long routing path delays.

Bill Hanna

Article: 64279
Subject: Re: Spartan3 availability
From: Ray Andraka <ray@andraka.com>
Date: Tue, 23 Dec 2003 18:24:33 -0500
Links: << >>  << T >>  << A >>
They don't make very dense DA LUTs for distributed arithmetic filters.  The M512s
only give you 9 taps vs 4 with an SRL16, and there are a lot less of them than
LEs.  They also don't help you for reloadable LUTs, which I use as a poor-man's
reconfiguration (I use SRL16's for the DA LUTs in xilinx to permit me to make a
reloadable DA filter, as well as for a DA adaptive filter).

The shifters work fine if it is just a shift register you are after, however the
power of the SRL16 is not so much the shift, but the ability to use them as a
reloadable LUT and for the dynamic shift, which is useful for reordering, for
instance in an FFT.

Mike Treseler wrote:

> Ray Andraka wrote:
> > The Altera parts still don't have a workable equivalent of the Xilinx SRL-16,
> > which can be used to huge advantage in DSP applications...if you code to it.
> > Otherwise, I'd agree.
>
> What's the downside of using the stratix block memory shifters?
>
>      -- Mike Treseler

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 64280
Subject: Re: Net name convention for Xilinx UCF files.
From: "One Day & A Knight" <kelvin8157@hotmail.com>
Date: Wed, 24 Dec 2003 13:21:25 +0800
Links: << >>  << T >>  << A >>
Yeah, that is indeed a copy error.

Now I switch to a single "clk_36"...and it seemed to work. "clk_36" is an
implicitly defined wire label.

I do remember there is a document said all the names and definitions in the
source code will
remain unchanged, but how come it doesn't in my case.

In the source code, there is no simple *u_testctrl?clk36_pll_o. All I found
from the ngd2ver is a
totally new definition u_testctrl/Mmux_clk36_pll_o_Result1_1. This is quite
strange to me.

And I am sure there is no command called ngc2ver now.

Thank you Muthu and Martin.


Best Regards,
Kelvin





Muthu <muthu_nano@yahoo.co.in> wrote in message
news:28c66cd3.0312230751.2ed46516@posting.google.com...
> "One Day & A Knight" <kelvin8157@hotmail.com> wrote in message
news:<3fe7b5c1$1@news.starhub.net.sg>...
> > Hi, all:
> >
> > I am writing some UCF files for synthesis. In XST I set the hierarchy
> > seperator to / and bus symbol to []...
> >
> > Now after I write the UCF files and build, the ISE6.1 complain can't
find
> > the net-names.
> >
> > How do I find the correct names of the various symbols in my Verilog
codes?
> > Is it possible to write a "netlist" in the NGC files?
> >
> >
> > Best Regards,
> > Kelvin
> >
> >
> >
> >
> > In core.v
> > Module main;
> >
> > testctl u_testctrl(
> >     ...
> >     .srck_i(p_srck_i),                     //testctrl  input
> >
> >     .arstn_testrx_i(arstn_testrx),         //testctrl  input
> >     .clk36_pll_i(clk_36),                  //testctrl  input
> > );
> >
> > ...
> > endmodule
> >
> > in core_ucf.ucf
> > NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
> > TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o"
27.8
> > ns HIGH 50 %;
> >
> >
> > Error in core.bld
> > ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
> >    'u_testctrl/clk36_pll_i' in the design.  To suppress this error
specify
> > the
> >    correct net name or remove the constraint.
>
> Hi,
>
> Your .ucf having "pll_o" and ERROR shows "pll_i". I think you have
> copied wrong lines. thats ok.
>
> XST tools will not change the instance names during synthesis. so,
> whatever you type in RTL should be valid in PAR too.
>
> I am doubting, the hiearchy seperator only. Because, XST by default
> takes "." as hiearchy seperator. Pls check that again, whether you
> have forced correctly to "/"
>
> and you can generate netlist after Translation phase.
>
> it is "ngd2ver" application from Xilinx tools.
>
> Get back for any clarification.
>
> Regards,
> Muthu



Article: 64281
Subject: VHDL-Xilinx-Simulation (signal not connected to port) ?
From: "Jarek" <lab@televox.pl>
Date: Wed, 24 Dec 2003 09:45:15 +0100
Links: << >>  << T >>  << A >>
Hi.

How to simulate (observe) signals not connected to port (Xiilinx ISE
WebPack-ModelSim XE).
For example signal counter in project test.vhd.

Best regards
Jarek

-----test.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test is
    Port ( clock:  in  std_logic;   -- system clock (25 MHz)
           resetn: in  std_logic;   -- active low reset
           c_out:  out std_logic);
end Test;

architecture Behavioral of Test is

  signal counter:  std_logic_vector(3 downto 0);
begin

  COUNT: process (clock, resetn)
  begin
    if (resetn = '0') then
      counter <= (others => '0');
    elsif (clock'event and clock = '1') then
      counter <= counter + 1;
    end if;
  end process;

  c_out <= counter(3);

end Behavioral;

--------------VHDL Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
 constant Period    : time := 40 ns; -- 25 MHz System Clock
END testbench;

ARCHITECTURE behavior OF testbench IS

 COMPONENT test
  PORT(
       clock : IN std_logic;
       resetn : IN std_logic;
       c_out : OUT std_logic
      );
 END COMPONENT;

 SIGNAL clock :  std_logic := '0';
 SIGNAL resetn :  std_logic;
 SIGNAL c_out :  std_logic;

BEGIN

  uut: test PORT MAP(
        clock => clock,
        resetn => resetn,
        c_out => c_out
        );

  clock <= not clock after (Period / 2);
  resetn <= '0', '1' after Period;

   tb : PROCESS
   BEGIN
    wait; -- will wait forever
   END PROCESS;

END;



Article: 64282
Subject: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
From: swarnakumar_ba@yahoo.com (Swarna B)
Date: 24 Dec 2003 04:04:45 -0800
Links: << >>  << T >>  << A >>
Hi Martin, Bill,
Thank you for the quick responses,
I have listed down some more details about the problem.

1. The DCM input clock is 40 MHz and hence the DCM would be in low
frequency mode.
2. I use the 2x output of the DCM to clock the data under
consideration, there are other clock domains in my design but I am not
crossing domains.
3. There is a host processor interface, this is asynchronous.
4. All the clocks are passed through global buffers, no local clocks
are used.
5. Just for trials I used the 40 MHz input clock directly, the problem
is gone. But if I use the 40MHz output (1x clock out) of the DCM the
problem is still there.

Thanks and regards,
Swarna

Here is the DCM I instantiated.
The input line CLKIN_IN is passed through a IBUFG before connecting to
this instant.

// Module ClockDouble
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST

module ClockDouble(
      RST_IN,
      LOCKED_OUT,
      CLKIN_IN,
      CLK2X_OUT,
      CLK0_OUT
      );

input RST_IN;
input CLKIN_IN;

output LOCKED_OUT;
output CLK2X_OUT;
output CLK0_OUT;

wire CLKFB_IN;
wire CLK0_BUF;
wire CLK2X_BUF;
wire CLKIN_IN_BUF;

DCM DCM_INST(
    .CLKIN (CLKIN_IN),
    .CLKFB (CLKFB_IN),
    .RST (RST_IN),
    .PSEN (1'b0),
    .PSINCDEC (1'b0),
    .PSCLK (1'b0),
    .DSSEN (1'b0),
    .CLK0 (CLK0_BUF),
    .CLK90 (),
    .CLK180 (),
    .CLK270 (),
    .CLKDV (),
    .CLK2X (CLK2X_BUF),
    .CLK2X180 (),
    .CLKFX (),
    .CLKFX180 (),
    .STATUS (),
    .LOCKED (LOCKED_OUT),
    .PSDONE ());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "2X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is 2
// synthesis attribute CLKFX_DIVIDE of DCM_INST is 1
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is 4
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is 25
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is
"SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute PHASE_SHIFT of DCM_INST is 0
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synthesis translate_off
 defparam DCM_INST.CLK_FEEDBACK="2X";
 defparam DCM_INST.CLKDV_DIVIDE=2;
 defparam DCM_INST.CLKFX_DIVIDE=1;
 defparam DCM_INST.CLKFX_MULTIPLY=4;
 defparam DCM_INST.CLKIN_DIVIDE_BY_2="FALSE";
 defparam DCM_INST.CLKIN_PERIOD=25;
 defparam DCM_INST.CLKOUT_PHASE_SHIFT="NONE";
 defparam DCM_INST.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
 defparam DCM_INST.DFS_FREQUENCY_MODE="LOW";
 defparam DCM_INST.DLL_FREQUENCY_MODE="LOW";
 defparam DCM_INST.DUTY_CYCLE_CORRECTION="TRUE";
 defparam DCM_INST.PHASE_SHIFT=0;
 defparam DCM_INST.STARTUP_WAIT="FALSE";
// synthesis translate_on

BUFG CLK0_BUFG_INST(
    .I (CLK0_BUF),
    .O (CLK0_OUT));

BUFG CLK2X_BUFG_INST(
    .I (CLK2X_BUF),
    .O (CLKFB_IN));

assign CLK2X_OUT = CLKFB_IN;

endmodule

Article: 64283
Subject: Re: Spartan3 availability
From: already5chosen@yahoo.com (Michael S)
Date: 24 Dec 2003 04:08:13 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<3FE8CEB1.ECF2D342@andraka.com>...
> They don't make very dense DA LUTs for distributed arithmetic filters.  The M512s
> only give you 9 taps vs 4 with an SRL16, and there are a lot less of them than
> LEs.  They also don't help you for reloadable LUTs, which I use as a poor-man's
> reconfiguration (I use SRL16's for the DA LUTs in xilinx to permit me to make a
> reloadable DA filter, as well as for a DA adaptive filter).
> 
> The shifters work fine if it is just a shift register you are after, however the
> power of the SRL16 is not so much the shift, but the ability to use them as a
> reloadable LUT and for the dynamic shift, which is useful for reordering, for
> instance in an FFT.
> 
> Mike Treseler wrote:
> 
> > Ray Andraka wrote:
> > > The Altera parts still don't have a workable equivalent of the Xilinx SRL-16,
> > > which can be used to huge advantage in DSP applications...if you code to it.
> > > Otherwise, I'd agree.
> >
> > What's the downside of using the stratix block memory shifters?
> >
> >      -- Mike Treseler
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

I don't follow you point about reloadability. How are M512 less
reloadable than SRL16? For me, they are more reloadable, in the sense
that unlike SRL16 M512 allows random-access reload.
The point about density is also questionable. In the absence of hard
data I would guess that one M512s is physically smaller than 20 SRL16
it replaces in DA applications.
Of course the point about moderate total amount of M512 vs. enormous
amount of SRL16 is hard to argue.

Article: 64284
Subject: Emulation on PRODESIGN Platinum Edition
From: sateesh@ims.uni-hannover.de (Lagudu Sateesh)
Date: 24 Dec 2003 07:28:49 -0800
Links: << >>  << T >>  << A >>
Hello:

I have mapped a design on Virtex2-6000 grade-4 device, and i would
like to emulate the design on ProDesign Platinum Edition Board.

PostLayout simulation of the design is working properly with the
testbench. i.e after Place and Route, backannotated the design and
static timing simulation is done. Results are matched after
postlayout. There are no timing errors after PAR. After configuring
the Platinum board with the '.bit' file (Configuration sw is supplied
by Prodesign), design is not visible to the PC. i.e. user Client
Application Modules (User CAPIMs) are not recognised by 'UMR Shell
script'. that means, emulated design is not visible. (Design size is
35%of Total FPGA)

In another case, with the some other test design (design size of <5%)
and with the same CAPIM, emulation software becomes visible to the PC
and CAPIMs are found by 'UMR shell script' and the design is also
perfectly functional.

Can any body suggest the ideas to solve the above problem? i.e does it
depend on size of design? and if yes, how? or any other solution

sateesh

Article: 64285
Subject: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Wed, 24 Dec 2003 09:46:38 -0600
Links: << >>  << T >>  << A >>
Swarna B wrote:

> 5. Just for trials I used the 40 MHz input clock directly, the problem
> is gone. But if I use the 40MHz output (1x clock out) of the DCM the
> problem is still there.

These symptoms indicate DCM is not asserting lock. Does your logic wait
until DCM achieves lock? DCM outputs are invalid and the output clock
freq. keeps on changing until DCM achieves lock. You should take into
consideration.

You may also want to try another alternate way of connecting the DCM
feedback. Instead of using clk2x as feedback, try using clk0 as feedback.
You need to modify the following in your code

// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
defparam DCM_INST.CLK_FEEDBACK="1X";

In DCM instantiation change

.CLKFB (CLK0_OUT),


Hope this helps !

Regards
Vikram




Article: 64286
Subject: Re: Spartan3 availability
From: Ray Andraka <ray@andraka.com>
Date: Wed, 24 Dec 2003 11:42:49 -0500
Links: << >>  << T >>  << A >>
A DA LUT contains all the possible sums of the input taps, which for a serial filter is
one tap per address bit.  As you increase the number of taps, the corresponding table size
grows exponentially.  With LUTs, you get 4 taps per LUT (which you can do with LE's
provided you don't need to reload the LUTs).  If you have to reload them, then using an
M512 only gives you 9 taps per M512, and each M512 is associated with a number of LABs,
each containing 10 LEs.  Thus the density of a reloadable DA LUT using the DA_LUTs is
considerably lower than what you'd get if using LEs.

Yes, the M512 is reloadable, I am not disputing that.  My point is that it is not a
substitute for reloadable LUTs in the LEs.  The densities simply do not compare.



Michael S wrote:

> Ray Andraka <ray@andraka.com> wrote in message news:<3FE8CEB1.ECF2D342@andraka.com>...
> > They don't make very dense DA LUTs for distributed arithmetic filters.  The M512s
> > only give you 9 taps vs 4 with an SRL16, and there are a lot less of them than
> > LEs.  They also don't help you for reloadable LUTs, which I use as a poor-man's
> > reconfiguration (I use SRL16's for the DA LUTs in xilinx to permit me to make a
> > reloadable DA filter, as well as for a DA adaptive filter).
> >
> > The shifters work fine if it is just a shift register you are after, however the
> > power of the SRL16 is not so much the shift, but the ability to use them as a
> > reloadable LUT and for the dynamic shift, which is useful for reordering, for
> > instance in an FFT.
> >
> > Mike Treseler wrote:
> >
> > > Ray Andraka wrote:
> > > > The Altera parts still don't have a workable equivalent of the Xilinx SRL-16,
> > > > which can be used to huge advantage in DSP applications...if you code to it.
> > > > Otherwise, I'd agree.
> > >
> > > What's the downside of using the stratix block memory shifters?
> > >
> > >      -- Mike Treseler
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
>
> I don't follow you point about reloadability. How are M512 less
> reloadable than SRL16? For me, they are more reloadable, in the sense
> that unlike SRL16 M512 allows random-access reload.
> The point about density is also questionable. In the absence of hard
> data I would guess that one M512s is physically smaller than 20 SRL16
> it replaces in DA applications.
> Of course the point about moderate total amount of M512 vs. enormous
> amount of SRL16 is hard to argue.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 64287
Subject: Re: Spartan3 availability
From: already5chosen@yahoo.com (Michael S)
Date: 24 Dec 2003 14:42:14 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<3FE9C209.66051EED@andraka.com>...
> A DA LUT contains all the possible sums of the input taps, which for a serial filter is
> one tap per address bit.  As you increase the number of taps, the corresponding table size
> grows exponentially.  With LUTs, you get 4 taps per LUT (which you can do with LE's
> provided you don't need to reload the LUTs).  If you have to reload them, then using an
> M512 only gives you 9 taps per M512, and each M512 is associated with a number of LABs,
> each containing 10 LEs.  Thus the density of a reloadable DA LUT using the DA_LUTs is
> considerably lower than what you'd get if using LEs.
> 

There are two possibilities:
1. I am totally clueless about DA.
2. You have never read Stratix datasheet and have no idea what is
M512.
Understandably, I prefer the 2nd option.

Nobody in his right mind will use M512 for DA in 512x1b configuration,
like you suggest. The natural configuration would be 32x16b or 32x18b.
In such configurations one M512 provides 25% more DA bandwidth than 16
(or 18, depending on required precision) SRL16 cells. So we can say
that one M512 replaces 20 (or 22.5) SRL16 cells. Additionally, each
shift-accumulate block is amortized over 25% more taps, providing
additional space saving.
Taking all this into account, I don't believe that M512 is less dense
than SRL16. Less available - probably yes, but not less dense.

Article: 64288
Subject: a question about flex10 configure
From: "panwh" <panwenhui_work@163.com>
Date: Thu, 25 Dec 2003 07:58:37 +0800
Links: << >>  << T >>  << A >>
When I configure my flex10k, sometimes maxplus tell me that configure is not
successful, and the device does not work. Once the condition happens ,it
will be still for sometime, such as several hours or several days. But,
after that , it will be configured successfully and work well.
Can you tell me why and how to do ???



Article: 64289
Subject: Re: a question about flex10 configure
From: Leon Heller <aqzf13@dsl.pipex.com>
Date: Thu, 25 Dec 2003 05:14:52 +0000
Links: << >>  << T >>  << A >>


panwh wrote:
> When I configure my flex10k, sometimes maxplus tell me that configure is not
> successful, and the device does not work. Once the condition happens ,it
> will be still for sometime, such as several hours or several days. But,
> after that , it will be configured successfully and work well.
> Can you tell me why and how to do ???

It's some time since I've used a Flex10K but I've never noticed this. 
Presumably you are configuring it with a ByteBlaster. Have you checked 
all the connections, you might have a poor solder joint?

Leon
-- 
Leon Heller, G1HSM
Email: aqzf13@dsl.pipex.com
My low-cost Philips LPC210x ARM development system:
http://www.geocities.com/leon_heller/lpc2104.html


Article: 64290
Subject: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
From: nospampleeeeze@yahoo.com (A.y)
Date: 25 Dec 2003 01:30:39 -0800
Links: << >>  << T >>  << A >>
do you have potential problems with I/O timings ?
rgrds
ay

Article: 64291
(removed)


Article: 64292
Subject: How to get first bit '0' position in certain register?
From: newhand@edacn.net (Newhand)
Date: 25 Dec 2003 07:15:05 -0800
Links: << >>  << T >>  << A >>
Dear all, 

For certain register, say stream = 16'b1111010011111111; 
the position of first bit '0' is: 8 (from LSB); 
if stream = 16'b1111000100010011, then the position is 2; 

what I need is to get the position. 

Since it should be done in one clock cycle, combination logic in 
Verilog might be a better choice. 

Could anybody give me some pieces of suggestion? Thanks in advance. 

Newhand

Article: 64293
Subject: Question regarding the sample design in XAPP290.
From: "Kelvin, Chee" <kelvin8157@hotmail.com>
Date: Thu, 25 Dec 2003 23:34:43 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am reading the sample design in XAPP290, regarding the partial
reconfiguration of Vertex class FPGAs.

I want to know what is the purpose of the Assembly, it seems to me, after
assembly, all three bit streams
are same 42Kb, meaning the full length.

I feel that, in the flow, from Active Module to Assembly, the link is broken
somewhere.

Do I send the bit-streams in the three Active Module to do reconfiguration,
or the three bit-streams from the assembly?

Besides that, how do I find information regarding the AREA constraints? My
chip is Vertex-2Pro 8000K. I need to see
find out the X##Y## are defined in the respective documents and how to use
it.

What is the probability of burning a chip when the synthesis, say, is no
good and caused contention...or any sorts of messed-up
errors in the bit-stream?

Best Regards,
Kelvin.






set XIL_MAP_MULTI_IN_PORTS=1

@echo Running Initial Stage (Top)
@echo =====================
cd Top\Initial
copy ..\..\Src\calctop.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..

@echo Running Initial Stage (Top1)
@echo =====================
cd Top1\Initial
copy ..\..\Src\calctop1.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..

@echo Running Initial Stage (Top2)
@echo =====================
cd Top2\Initial
copy ..\..\Src\calctop2.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..

@echo Running Active module (pushbutton)
@echo =====================
cd Modules\pushbutton
copy ..\..\Src\pushbutton.edf pushbutton.edf
call active.cmd
if errorlevel 1 goto DONE

@echo Running Active module (lcd_driver)
@echo =====================
cd ..\lcd_driver
copy ..\..\Src\lcd_driver.edf lcd_driver.edf
call active.cmd
if errorlevel 1 goto DONE

@echo Running Active module (capture)
@echo =====================
cd ..\capture
copy ..\..\Src\capture.edf capture.edf
call active.cmd
if errorlevel 1 goto DONE

@echo Running Active module (adder)
@echo =====================
cd ..\adder
copy ..\..\Src\adder.edf adder.edf
call active.cmd
if errorlevel 1 goto DONE

@echo Running Active module (subtractor)
@echo =====================
cd ..\subtractor
copy ..\..\Src\subtractor.edf subtractor.edf
call active.cmd
if errorlevel 1 goto DONE

@echo Running Assemble Stage (Top)
@echo ======================
cd ..\..\Top\Assemble
copy ..\..\Src\calctop.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE

@echo Running Assemble Stage (Top1)
@echo ======================
cd ..\..\Top1\Assemble
copy ..\..\Src\calctop1.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE

@echo Running Assemble Stage (Top2)
@echo ======================
cd ..\..\Top2\Assemble
copy ..\..\Src\calctop2.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
cd ..\..


:DONE



Article: 64294
Subject: Re: How to get first bit '0' position in certain register?
From: "Robert Sefton" <rsefton@abc.net>
Date: Thu, 25 Dec 2003 07:58:44 -0800
Links: << >>  << T >>  << A >>
This function is called "find first one" and is fairly common. You could
use a for loop or if-else construct in Verilog. Try Googling on "find
first one" - you may find something you can use.

Robert

"Newhand" <newhand@edacn.net> wrote in message
news:e59512cb.0312250715.106d9d97@posting.google.com...
> Dear all,
>
> For certain register, say stream = 16'b1111010011111111;
> the position of first bit '0' is: 8 (from LSB);
> if stream = 16'b1111000100010011, then the position is 2;
>
> what I need is to get the position.
>
> Since it should be done in one clock cycle, combination logic in
> Verilog might be a better choice.
>
> Could anybody give me some pieces of suggestion? Thanks in advance.
>
> Newhand



Article: 64295
Subject: Re: How to get first bit '0' position in certain register?
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 25 Dec 2003 18:59:19 -0000
Links: << >>  << T >>  << A >>
>This function is called "find first one" and is fairly common. You could
>use a for loop or if-else construct in Verilog. Try Googling on "find
>first one" - you may find something you can use.

Another term to search on is priority encoder.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 64296
Subject: Re: How to get first bit '0' position in certain register?
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 25 Dec 2003 23:45:51 GMT
Links: << >>  << T >>  << A >>
"Newhand" wrote:

> For certain register, say stream = 16'b1111010011111111;
> the position of first bit '0' is: 8 (from LSB);
> if stream = 16'b1111000100010011, then the position is 2;
>
> what I need is to get the position.
>
> Since it should be done in one clock cycle, combination logic in
> Verilog might be a better choice.
>
> Could anybody give me some pieces of suggestion? Thanks in advance.


Two possible approaches:

1) Priority encoder


always @(posedge CLOCK)begin
         if(~A[0]) OUT <= 4'd0;
    else if(~A[1]) OUT <= 4'b1;
    else if(~A[2]) OUT <= 4'b2;
    ... // etc., etc.
end


2) Counter

The basic idea is simple: If your operating clock is slow enough, generate a
16x clock by whatever means your device allows.  On every 1x clock, start a
counter at 16x and stop it when the first "0" is found.



-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 64297
Subject: Fast Fourirer Using Xilinx ISE
From: natara@eng.fsu.edu (Hari)
Date: 25 Dec 2003 17:33:13 -0800
Links: << >>  << T >>  << A >>
Hi,
   I have an automatically generated code from some source
"cztgen.exe". I am working on performing FFT (C-Z Tfranform).The code
basically has filter (FIR)coefficient computation.I am using two other
code to perform multiplication and
store coefficient/twiddle factors(not that of filter). My problem is I
am not getting write answers when i simulate the codes.The multiplier
and coefficent(not that of filter) codes are working fine. When put
together, I don't get right answer. I suspect there is some problem
with the filter coefficent code.
How do I check the code? and where can I find the source for the
filter coeff. code.If u need the code, I can email it to u.
Thank you.
Hari

Article: 64298
Subject: Re: How to get first bit '0' position in certain register?
From: palfke@earthlink.net (Peter Alfke)
Date: 25 Dec 2003 21:48:55 -0800
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vumcs7q5nrua43@corp.supernews.com>...
> >This function is called "find first one" and is fairly common. You could
> >use a for loop or if-else construct in Verilog. Try Googling on "find
> >first one" - you may find something you can use.
> 
> Another term to search on is priority encoder.
If you can restrict your search to the first 24 bits, and if you have
a Virtex-II BlockRAM available, you can feed the upper 12 bits as
address to one port, and the lower 12 bits as address to the other
port, and make the BlockRAM give you the 4-bit position information
within the 12 address bits. You then have to combine the two port
outputs. You can get the answer in one clock cycle (faster than all
the suggested software solutions) at well over 100 MHz,
ocnservatively.

Peter Alfke, Xilinx Applications (answering from home)
Merry Christmas to everybody on this newsgroup, and an interesting and
interactive 2004!

Article: 64299
Subject: LVPECL_33 to LVPECL_25 (virtex-II pro)
From: "jicho" <jicho@it.co.kr>
Date: Fri, 26 Dec 2003 16:06:22 +0900
Links: << >>  << T >>  << A >>
Dear all,

I am trying to use differential LVPECL interface on Xilinx virtex-II pro
device.

I have to connect some standard LVPECL(3.3V) signal to virtex-II pro device.
But I know that Virtex-II Pro devices support only LVDS_25 and LVPECL_25.
There is no problem with Spartan-IIE or Virtex-II device because they have a
LVPECL_33 I/O.

I want to know how I connect between standard LVPECL(3.3V) signal and
virtex-II pro LVPECL_25 signal in differential manner.

Could anybody give me some answer ?

Thanks,
james.





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