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Messages from 64350

Article: 64350
Subject: Re: predictable timing for xilinx cpld?
From: guillerodriguez@terra.es (guille)
Date: 29 Dec 2003 18:08:51 -0800
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vv0r59qpb4bu45@corp.supernews.com>...
> >As I said in my first mail, the procedure outlined in whitepaper 122
> >always takes the maximum value for all internal parameters when deriving
> >other (external) parameters, which may not be correct in all situations.
> >See the comments from Peter Alfke too.
>  
> >Since the analyzer internally just applies the same procedure outlined
> >in whitepaper 122, the timing report it produces doesn't help.
> 
> I think this is one of those cases where you have to read between
> the lines a bit.
> 
> What are you trying to do?  Understand the data sheet or justify
> running the chip slightly over spec?

None of the two.

I already explained in my first mail, I have a system where some
signals go through a CPLD and end up in an expansion bus. Example,
imagine a CE# signal coming from a CPU, going through the CPLD,
then ending up on an expansion bus. I have to derive the timing
specs for those signals in the expansion bus, for which I need to
know the delays and timing relationships of signals going through
the CPLD.


> 
> Peter's 70% rule-of-thumb seems like a reasonable estimate.  So the
> clock delay can't be much faster than worst case if the rest of the
> parameters are all close to worst case.

That was a nice rule of thumb but in the next paragraph of his
mail Peter himself said this method was no longer valid for many
parameters in recent CPLDs.

> 
> What can they actually test?  They probably test what you really
> want to know rather than the smaller pieces.  If you just want to
> run the chip at full speed like everybody else, I'd just go for it.
> 
> If you are trying to cheat and push things a bit, please tell us more.

Not the case...

Guillermo Rodriguez

Article: 64351
Subject: Re: predictable timing for xilinx cpld?
From: palfke@earthlink.net (Peter Alfke)
Date: 29 Dec 2003 20:09:54 -0800
Links: << >>  << T >>  << A >>
Timing analysis is easy when you just have to add values. The
worst-case max is the sum of the worst-case maxes.
Trouble starts when you must subtract. Then the worst-case total max
must use the min value of the subtracted parameter.
That's where the tracking rules come in.
These things have not changed in 15 years ( you can read explanations
in the 1989 Xilinx data book.) As I mentioned, the 70% rule has served
us well, but don't use it blindly for unrelated parameters that might
depend on different physical phenomena, or involve deliberately and
cleverly stabilized parameters.

Peter Alfke
===================
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3FF07CC3.90902@flukenetworks.com>...
> guille wrote:
> 
>  > Tsu_min = Tin_max + Tlogi_max + Tsui_max - Tgck_min
>  >
>  > With no known value for Tgck_min one would need to assume a minimum 0 ns
>  > for this parameter, which would yield a worst case Tsu of 6.8 ns.
> 
> 
> Consider using synchronous design techniques
> and the fpga's global clock distribution network.
> 
> This will allow you to verify timing
> without requiring any MIN specifications at all.
> 
> In fact, the place and route software
> will do this "static timing analysis" for you.
> 
>   -- Mike Treseler

Article: 64352
Subject: Re: This design contains an RPM macro bm_0 which is to be automaticallyplaced, but it contains TBUF elelements that are not allowed during automaticplacement of RPMs?
From: "One Day & A Knight" <kelvin8157@hotmail.com>
Date: Tue, 30 Dec 2003 14:56:23 +0800
Links: << >>  << T >>  << A >>
Thank you Durkin!

The BUS Delimiter/Hierarchy separater/etc. can only be found Advanced
mode...I was not aware of this mode in ISE6.1...

I managed to place & route a bus macro...it seems to me, a BM is a 4SX2S
rectangular box, but previously I
placed them in a gap with 1 slices wide between my two modules, so it caused
some mistakes. I treated it like
a 1SX8S verticle pole...

Now I managed to run a synthesis and P&R successfully all in GUI. Thank you
for your reply.

Lastly, is there any options to limit the amount of RAM in ISE? My PC has
only 256MB and is not sufficient for a
50K ASIC gate design. ISE tends to eat as much as that is available.

Best Regards,
Kelvin





Sean Durkin <23@iis.42.de> wrote in message news:3ff03b8d$1@news.fhg.de...
> A Day & A Knight wrote:
>
> > Thanks, Durkin.
> > However that is the thing I don't understand. In my UCF file I put
> > constraints like these in the UCF file.
> > 1)   INST "bm_0" LOC = "TBUF_X0Y0" ;
> > 2)   INST "bm_0" LOC = "TBUF_X0Y0:TBUF_X0Y7" ;    # Since I use all four
> > pins.
> > I tried both cases but I always end up in this error 205, and Xilinx
Answers
> > don't have this error :(
> Version 1) should suffice. For each macro there is one pin defined as
> the reference, and that pin is used to place the macro. All the other
> pins of the macro are then fixed, because the routing and placement is
> specified in the macro itself, relative to the reference pin.
>
> Version 2) should give you an error, since TBUF_X0Y0:TBUF_X0Y7 is an
> ambiguous location, so that should not work at all, as I understand it.
>
> Since you don't get an error other than 205 when using version 2, and it
> still says "RPM macro bm_0 which is to be AUTOMATICALLY placed", even
> though you have placed it manually in the .UCF, I suspect that ISE
> doesn't really use your .UCF-file at all.
>
> How did you add the .UCF to your design? You should just add it as a
> source file (just like your verilog source codes), and assign it to your
> top-level design file when asked.
>
> > I have another question. How come the XST GUI's Properties ask for a
.XCF
> > file? Is that similar  to .UCF?
> The .XCF is for synthesis, the .UCF is for mapping and the place and
> route process. In the .XCF you can put special constraints for XST, like
> if it should optimize away equivalent registers, automatically add
> IO-buffers and things like that. The .XCF is for use with XST,
> exclusively and does not work with FPGA Express and other synthesis
> tools (at least as far as I know).
>
> In the .UCF you put more global things, like which IOBs to use, timing
> constraints for your clock signals, area constraints for modules etc.,
> i.e. things that relate to the implementation of your design, that is
> mapping, placing and routing. A .UCF can be used with tools from other
> vendoers as well.
>
> > How do I compile my verilog codes with XST GUI while control the
> > bus-delimiter with () instead of the default <>?
> In Project Navigator, select your top-level design file, right-click on
> "Synthesize", and chose "Properties". After scrolling down (!) you can
> specify the "Bus delimiter" in the "Synthesis Options" tab.
>
> > Also, how come in the GUI, the UCF&XCF is in XST, while in commandline
mode,
> > the UCF is in NGDBuild?
> As I stated above, the .UCF should be added to the design just like your
> verilog source codes, not in the XST settings. It's possible that your
> .UCF is simply ignored when added in the XST settings, which would
> explain your problem.
>
> > Why so many exceptions and so much inconsistency in ISE 6.1! :(
> > In my procedure, I have only XST (ISE6.1.03) in my PC, so I used command
> > line XST to make
> > sure that the bus delimiter is (), then in commandline to run the
NGDBuild
> > with -uc my_top.ucf...then
> > return back to GUI to do MAP and P&R...
> > Only P&R doesn't work!
> P&R needs a .PCF (physical constraints file) to work. This .PCF is
> generated automatically from your .UCF during mapping. Normally, par
> looks for a file named <your_design>.pcf or <your_design_map>.pcf in the
> working directory, and uses that automatically. If it's not there, it
> tries to place everything itself. I suspect that this is what happens in
> your case. Check and see if a .PCF file is generated somewhere along the
> way.
>
> But I guess if you run the entire flow in the GUI (after changing the
> bus delimiter like described above), everything will work fine
> automatically.
>
> --
> Sean Durkin
> Fraunhofer Institute for Integrated Circuits (IIS)
> Am Wolfsmantel 33, 91058 Erlangen, Germany
> http://www.iis.fraunhofer.de
>
> mailto:23@iis.42.de
> ([23 , 42] <=> [durkinsn , fraunhofer])




Article: 64353
Subject: Re: predictable timing for xilinx cpld?
From: palfke@earthlink.net (Peter Alfke)
Date: 29 Dec 2003 23:19:51 -0800
Links: << >>  << T >>  << A >>
I said "in modern FPGAs".  To the best of my knowledge, CPLDs do not
use these fancy compensation schemes. CPLDs are much simpler than
FPGAs, so they do not need sophisticated clock management, etc.
Peter Alfke

guillerodriguez@terra.es (guille) wrote in message news:<5d891e95.0312291808.3eac24b@posting.google.com>...
> hmurray@suespammers.org (Hal Murray) wrote in message news:<vv0r59qpb4bu45@corp.supernews.com>...
> > >As I said in my first mail, the procedure outlined in whitepaper 122
> > >always takes the maximum value for all internal parameters when deriving
> > >other (external) parameters, which may not be correct in all situations.
> > >See the comments from Peter Alfke too.
>  
> > >Since the analyzer internally just applies the same procedure outlined
> > >in whitepaper 122, the timing report it produces doesn't help.
> > 
> > I think this is one of those cases where you have to read between
> > the lines a bit.
> > 
> > What are you trying to do?  Understand the data sheet or justify
> > running the chip slightly over spec?
> 
> None of the two.
> 
> I already explained in my first mail, I have a system where some
> signals go through a CPLD and end up in an expansion bus. Example,
> imagine a CE# signal coming from a CPU, going through the CPLD,
> then ending up on an expansion bus. I have to derive the timing
> specs for those signals in the expansion bus, for which I need to
> know the delays and timing relationships of signals going through
> the CPLD.
> 
> 
> > 
> > Peter's 70% rule-of-thumb seems like a reasonable estimate.  So the
> > clock delay can't be much faster than worst case if the rest of the
> > parameters are all close to worst case.
> 
> That was a nice rule of thumb but in the next paragraph of his
> mail Peter himself said this method was no longer valid for many
> parameters in recent CPLDs.
> 
> > 
> > What can they actually test?  They probably test what you really
> > want to know rather than the smaller pieces.  If you just want to
> > run the chip at full speed like everybody else, I'd just go for it.
> > 
> > If you are trying to cheat and push things a bit, please tell us more.
> 
> Not the case...
> 
> Guillermo Rodriguez

Article: 64354
Subject: Re: Parallel Cable 4 & Linux
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 30 Dec 2003 00:45:26 -0800
Links: << >>  << T >>  << A >>
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message news:<slrnbv0usm.ird.ldoolitt@recycle.lbl.gov>...
> 
> If you open up the parallel cable 4, you will see it is
> built with a big CPLD, so it is clearly a parallel-serial
> converter (serializer).  The PC sends in bytes in a
> normal "line printer" strobed mode, and the CPLD turns
> that into the JTAG data stream.

Actually, right after powerup, it does behave just like a
Parallel Cable 3. I can toggle the lines and read the sense
just as it is documented for the Par. Cable 3.

I wonder however, how to put the cable in to the "enhanced"
mode, e.g. using the parallel to serial conversion.

> If you can take the performance hit, I recommend you switch
> back to Parallel Cable 3, for which Linux drivers are trivial
> and widely published.  Also, I can put you in touch with
> someone who made an "open source" USB-to-JTAG programmer,
> out of an XC2S30 and an FT245B.  Schematics, FPGA code, and
> software are published.  Linux drivers are provably possible,
> but not demonstrated -- of course, Xilinx packaged software
> will probably never support this device.  I personally have
> access to one board.  

Yes, definitely, please post that info.

I started writing a program that would emulate the JTAG tap
controller but got stuck, as I could not debug it. If there
is anybody interested in working with me on that, I would like
to continue the project ...

I also looked at app note 058, which pretty much does what I need,
except it again requires you to run a translator program (svf->xsvf
on a Windoze box). I converted ALL my systems that where running
the Windoze Trojan Horse/Worm/Obscure Piece of Crap OS to Linux.

>     - Larry

Thanks,
rudi
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Article: 64355
Subject: Re: This design contains an RPM macro bm_0 which is to be automaticallyplaced,
From: Sean Durkin <23@iis.42.de>
Date: Tue, 30 Dec 2003 10:01:29 +0100
Links: << >>  << T >>  << A >>
One Day & A Knight wrote:
> Thank you Durkin!
> The BUS Delimiter/Hierarchy separater/etc. can only be found Advanced
> mode...I was not aware of this mode in ISE6.1...
Ah, yes, I should've thought about that. But that's always the first 
option you set after installing... :)

> I managed to place & route a bus macro...it seems to me, a BM is a 4SX2S
> rectangular box, but previously I
> placed them in a gap with 1 slices wide between my two modules, so it caused
> some mistakes. I treated it like
> a 1SX8S verticle pole...
You can just load it into FPGAEditor and look at it.

> Lastly, is there any options to limit the amount of RAM in ISE? My PC has
> only 256MB and is not sufficient for a
> 50K ASIC gate design. ISE tends to eat as much as that is available.
Not that I know of...

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])

Article: 64356
Subject: Re: predictable timing for xilinx cpld?
From: guillerodriguez@terra.es (guille)
Date: 30 Dec 2003 03:37:10 -0800
Links: << >>  << T >>  << A >>
Peter,

palfke@earthlink.net (Peter Alfke) wrote in message news:<e9ba0b8.0312292009.7ac13004@posting.google.com>...
> Timing analysis is easy when you just have to add values. The
> worst-case max is the sum of the worst-case maxes.

Yes, that one was clear :)

> Trouble starts when you must subtract. Then the worst-case total max
> must use the min value of the subtracted parameter.

Yes.

> That's where the tracking rules come in.
> These things have not changed in 15 years ( you can read explanations
> in the 1989 Xilinx data book.) As I mentioned, the 70% rule has served
> us well, but don't use it blindly for unrelated parameters that might
> depend on different physical phenomena, or involve deliberately and
> cleverly stabilized parameters.

Thanks a lot for that, this is very useful. I had missed that you
were referring to FPGAs only and not to CPLDs when you mentioned
the compensation techniques.

The only question left is why the device datasheet (and the output
from the timing analyzer) lists external parameters which have been
derived by adding and substracting max values always, without using
this 70% rule... I can imagine this could lead to problems in some
designs.

I think I will derive all my timings from the internal parameters
only -- seems to be the safest bet.

Your help is very much appreciated!

Guillermo Rodriguez

Article: 64357
Subject: Re: Spartan3 prices again...
From: news@sulimma.de (Kolja Sulimma)
Date: 30 Dec 2003 09:53:47 -0800
Links: << >>  << T >>  << A >>
> If you think there's even a chance that you're going to be designing
> in a certain component, get a formal price quote from the salesman,
> rep, or distributor.  And if you can't get a quote, maybe you can't
> get the part, either.
> > Bob Perlman
> Cambrian Design Works

The issue was, that the formal quotes for pieces in 5k quantities
where a factor of 20 above the prices quoted by Xilinx for 250k
quantities.
And nobody in this group really believed that you get a 95% volume
discount.

It's not as bad in my case. I only have to pay a factor of 7 more for
1k quantities.

Kolja Sulimma

Article: 64358
Subject: virtex-II problems
From: agunos@cox.net (ed)
Date: 30 Dec 2003 10:01:35 -0800
Links: << >>  << T >>  << A >>
I'm building a multi-channel frequency synthesizer in a Xilinx
XC2V6000-6 ES. I have verified a one and two channel build, but when I
move to four channels the design stops working (slice usage goes from
12% with one channel to 50% with four). It looks as if the design is
not clocking (all registers are returning '0' and there is no response
to inputs). The only differences between the builds are the number of
times the "channel module" is generated, a modification to a priority
LUT, and a different adder to sum all the outputs of each "channel
module". All timing constraints are met.

I have tried a number of things: Different reset logic on the DCMs,
removing the DCMs altogether and just using the IBUFGs and BUFGs,
using a non-ES version of the chip, etc. Nothing seems to work. Does
anyone have any ideas?

Thanks

To send private email:
xy@cox.net
where
"xy"  =  "ed.agunos"

Article: 64359
Subject: Re: Xilinx Parallel cable
From: news@sulimma.de (Kolja Sulimma)
Date: 30 Dec 2003 10:08:43 -0800
Links: << >>  << T >>  << A >>
do_not_reply_to_this_addr@yahoo.com (Sumit Gupta) wrote in message news:<ae680d56.0312281224.3235d90e@posting.google.com>...
> Hi
> 
> Is there is cheap source or alternative to Xilinx parallel cable ?
Thorsten Trenz has a spartan-II development board with download cable
included for 99. I am confident that he will sell you a seperate
download cable on request, albeit it is not listed in his shop.
http://www.te-shop.de/catalog/

> Also is it leagal to make my own cable (from the schemetic provided by
> Xilinx) and sell it.
Please don't. The cable has lots of flaws. Search this newsgroup about
that topic.
Design your own cable. With heavy schmitt triggers added. And sell
that.
You can use a 1$ cpld and use seperate pins for the schmitt-trigger
feedback.
There also is an open source usb downloadcable available somewhere on
the net.

Regards,

Kolja Sulimma

Article: 64360
Subject: Re: virtex-II problems
From: Mark Schellhorn <mark@seawaynetworks.com>
Date: Tue, 30 Dec 2003 13:14:40 -0500
Links: << >>  << T >>  << A >>
Try looking in the Answers Database for ES "anomalies" that might be biting you. 
I searched on XC2V6000-6 ES and came up with a bunch of potential hits like this 
one regarding quadrant restrictions for IBUFG routing:

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11756

There are other ES errata that apply to DCM usage, but you say that you've 
already tried running without DCMs.

    Mark


ed wrote:
> I'm building a multi-channel frequency synthesizer in a Xilinx
> XC2V6000-6 ES. I have verified a one and two channel build, but when I
> move to four channels the design stops working (slice usage goes from
> 12% with one channel to 50% with four). It looks as if the design is
> not clocking (all registers are returning '0' and there is no response
> to inputs). The only differences between the builds are the number of
> times the "channel module" is generated, a modification to a priority
> LUT, and a different adder to sum all the outputs of each "channel
> module". All timing constraints are met.
> 
> I have tried a number of things: Different reset logic on the DCMs,
> removing the DCMs altogether and just using the IBUFGs and BUFGs,
> using a non-ES version of the chip, etc. Nothing seems to work. Does
> anyone have any ideas?
> 
> Thanks
> 
> To send private email:
> xy@cox.net
> where
> "xy"  =  "ed.agunos"


Article: 64361
(removed)


Article: 64362
Subject: Re: Parallel Cable 4 & Linux
From: "Peter C. Wallace" <pcw@freeby.mesanet.com>
Date: Tue, 30 Dec 2003 11:22:52 -0800
Links: << >>  << T >>  << A >>
On Tue, 30 Dec 2003 00:45:26 -0800, Rudolf Usselmann wrote:

> Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message
> news:<slrnbv0usm.ird.ldoolitt@recycle.lbl.gov>...
>> 
>> If you open up the parallel cable 4, you will see it is built with a
>> big CPLD, so it is clearly a parallel-serial converter (serializer).
>> The PC sends in bytes in a normal "line printer" strobed mode, and the
>> CPLD turns that into the JTAG data stream.
> 
> Actually, right after powerup, it does behave just like a Parallel Cable
> 3. I can toggle the lines and read the sense just as it is documented
> for the Par. Cable 3.
> 
> I wonder however, how to put the cable in to the "enhanced" mode, e.g.
> using the parallel to serial conversion.
> 
>> If you can take the performance hit, I recommend you switch back to
>> Parallel Cable 3, for which Linux drivers are trivial and widely
>> published.  Also, I can put you in touch with someone who made an "open
>> source" USB-to-JTAG programmer, out of an XC2S30 and an FT245B.
>> Schematics, FPGA code, and software are published.  Linux drivers are
>> provably possible, but not demonstrated -- of course, Xilinx packaged
>> software will probably never support this device.  I personally have
>> access to one board.
> 
> Yes, definitely, please post that info.
> 
> I started writing a program that would emulate the JTAG tap controller
> but got stuck, as I could not debug it. If there is anybody interested
> in working with me on that, I would like to continue the project ...
> 
> I also looked at app note 058, which pretty much does what I need,
> except it again requires you to run a translator program (svf->xsvf on a
> Windoze box). I converted ALL my systems that where running the Windoze
> Trojan Horse/Worm/Obscure Piece of Crap OS to Linux.

Jim Kearney is doing some firmware upgrades to the USB-JTAG at the moment
but we would welcome anyone wanting to help port the software to Linux.

There is a FTDI driver for Linux (and xBSD), so the low level interface
should not be too difficult.

I am willing to give free hardware to anyone that contributes to porting
or improving the software (Larry I have a REVB assembed card here if you 
stop by and pick it up) 

Currently status is as follows:

BITfile download, SVF player work from Windows
Shift rates from 250 KHZ to 48 MHz
2 independent TAP controllers
programmable series termination on TCK output and parallel passive
termination on TDO (primary TAP only)
Firmware bug fixes/ REVB card updates being done now (Thanks Jim!)

GPLed software,firmware, and schematics are located here:

http://www.mesanet.com/software/parallel/jtag.zip



Peter Wallace

  




> 
>>     - Larry
> 
> Thanks,
> rudi
> ========================================================
>    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores
> -> http://www.asics.ws/  <- FREE EDA Tools

Article: 64363
Subject: Re: virtex-II problems
From: "Ken Morrow" <junk@not_morro.co.uk>
Date: Tue, 30 Dec 2003 21:32:23 -0000
Links: << >>  << T >>  << A >>
Could well be incorrect logic produced by an error in the synthesiser.

I seem to be finding a lot of these recently.

Try running a post place and route simulation. to check for this, if
possible.

Good Luck,

Ken,
Morrow Electronics Limited.

"Mark Schellhorn" <mark@seawaynetworks.com> wrote in message
news:kgjIb.5382$Vl6.1404008@news20.bellglobal.com...
> Try looking in the Answers Database for ES "anomalies" that might be
biting you.
> I searched on XC2V6000-6 ES and came up with a bunch of potential hits
like this
> one regarding quadrant restrictions for IBUFG routing:
>
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11756
>
> There are other ES errata that apply to DCM usage, but you say that you've
> already tried running without DCMs.
>
>     Mark
>
>
> ed wrote:
> > I'm building a multi-channel frequency synthesizer in a Xilinx
> > XC2V6000-6 ES. I have verified a one and two channel build, but when I
> > move to four channels the design stops working (slice usage goes from
> > 12% with one channel to 50% with four). It looks as if the design is
> > not clocking (all registers are returning '0' and there is no response
> > to inputs). The only differences between the builds are the number of
> > times the "channel module" is generated, a modification to a priority
> > LUT, and a different adder to sum all the outputs of each "channel
> > module". All timing constraints are met.
> >
> > I have tried a number of things: Different reset logic on the DCMs,
> > removing the DCMs altogether and just using the IBUFGs and BUFGs,
> > using a non-ES version of the chip, etc. Nothing seems to work. Does
> > anyone have any ideas?
> >
> > Thanks
> >
> > To send private email:
> > xy@cox.net
> > where
> > "xy"  =  "ed.agunos"
>



Article: 64364
Subject: Re: Spartan3 prices again...
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Tue, 30 Dec 2003 22:22:23 GMT
Links: << >>  << T >>  << A >>
On 30 Dec 2003 09:53:47 -0800, news@sulimma.de (Kolja Sulimma) wrote:

>> If you think there's even a chance that you're going to be designing
>> in a certain component, get a formal price quote from the salesman,
>> rep, or distributor.  And if you can't get a quote, maybe you can't
>> get the part, either.
>> > Bob Perlman
>> Cambrian Design Works
>
>The issue was, that the formal quotes for pieces in 5k quantities
>where a factor of 20 above the prices quoted by Xilinx for 250k
>quantities.
>And nobody in this group really believed that you get a 95% volume
>discount.

If a formal quote for 5k pieces comes in at 20X a formal quote for
250k pieces, that's interesting information.  But if a formal quote
for 5k pieces is 20X the 250k price stated in a press release, that's
hardly surprising.

Which is it?
 
Any price you see in a press release should have a "j" after it.

Bob Perlman
Cambrian Design Works


Article: 64365
Subject: Re: Parallel Cable 4 & Linux
From: Steve Lass <lass@xilinx.com>
Date: Tue, 30 Dec 2003 17:53:33 -0700
Links: << >>  << T >>  << A >>
Rudolf Usselmann wrote:

>Steve Lass <lass@xilinx.com> wrote in message news:<bs79d2$84a1@cliff.xsj.xilinx.com>...
>  
>
>>ISE 6.2i will support the Parallel 4 cable on Linux.
>>    
>>
>
>
>Thats great. So what am I supposed to do in the mean while ?
>  
>
The MultiLinx cable works today under Linux.  You could try contacting 
your local rep, distributor or FAE and ask to borrow a
MultiLinx cable until 6.2i is released.  I'm betting somebody has one 
that they can lend you.  It will work with the serial connection
(not the USB connection) on your PC under Linux.

>Seriously, this is a real problem, and nobody seems to have
>a solution. I tries modifying the software in app 058, but
>that also needs a PC piece of SW to translate svf to xsvf
>files.
>
>Can you, Steve, or somebody else at Xilinx provide a Linux
>version (or source code) for the svf to xsvf translator ?
>
As for creating XSVF files (if you really want to go down this path), 
that can be done on Linux today using iMPACT.  Basically
just go into iMPACT, and target an XSVF file.  There is no need for the 
external SVF2XSVF translator in 6.1i.

>Also, in the answer records, it states the schematic for
>parallel cable 4 is unavailable because it is a "proprietary"
>design. This seems to me really nonsense, you guys make
>money with FPGAs not with cables. releasing the schematic
>will enable users to support them selves when you  guys
>can't. Could you please ask the appropriate people to
>reconsider this choice ?
>
I'll forward your request.

>Do you have a date for 6.2i (patch?) ?
>
February 2004.

Regards,

Steve

>
>Thanks,
>rudi               
>========================================================
>   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
>..............::: FPGAs * Full Custom ICs * IP Cores :::
>FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools
>  
>


Article: 64366
Subject: dynamic memory allocation NIOS
From: jwing23@hotmail.com (J-Wing)
Date: 30 Dec 2003 22:38:34 -0800
Links: << >>  << T >>  << A >>
i am using dynamic memory allocation to run in NIOS.
i) this means using malloc to get the memory needed
ii) and using free to free the memory needed

after testing, i think that the free function does not do anything. is
there any way to free the memory allocated?

Article: 64367
Subject: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: kkaranasos@in.gr (kpk)
Date: 31 Dec 2003 00:22:06 -0800
Links: << >>  << T >>  << A >>
Can anyone send me a 4-bit binary divider circuit in this email :
kkaranasos@in.gr  ? I must make this homework for my university and i
am late.
I have to make this circuit only with NAND gates. 

PLEASE HELP !!!!!!!!!

Thanks a lot

Article: 64368
Subject: Re: 4-bit binary divider circuit PLEASE!!!!!!!
From: "Gregory C. Read" <readgc.invalid@hotmail.com.invalid>
Date: Wed, 31 Dec 2003 09:51:29 GMT
Links: << >>  << T >>  << A >>
15 NANDS
------------  =  3
5 NANDS

-- 
Greg
readgc.invalid@hotmail.com.invalid
(Remove the '.invalid' twice to send Email)


"kpk" <kkaranasos@in.gr> wrote in message
news:f2753b28.0312310022.7c2153f6@posting.google.com...
> Can anyone send me a 4-bit binary divider circuit in this email :
> kkaranasos@in.gr  ? I must make this homework for my university and i
> am late.
> I have to make this circuit only with NAND gates.
>
> PLEASE HELP !!!!!!!!!
>
> Thanks a lot



Article: 64369
Subject: A dilemma: which signal to use as a master?
From: "valentin tihomirov" <valentinNOSPAM@abelectron.com>
Date: Wed, 31 Dec 2003 14:48:39 +0200
Links: << >>  << T >>  << A >>
Two related signals control a process. The process is launched if Sig1 or
Sig2 is active. This does not mean OR logic. I bring an illustration  of a
register just to make it clear.
You have a register that can be in loaded or in empty state. It accepts data
(becomes LOADED) when is EMPTY and WRITE input is active. At a clock edage
when register is being loaded it responds with ACK signal, releasing data
provider. That is, ACK is active when WRITE and EMPTY = '1'. There are two
options when to load data FFs of the register:
    - when EMPTY = '1', that is when reg. contains no valid data; or
    - when ACK = '1', i.e. reg. responds the fact it loads data.
Logically, the device will function equvalently. The pseudo-code:

entity:
    WRITE: in std_logic
    ACK: out std_logic
    DIN, DOUT: std_logic_vector;

architecture
    EMPTY: std_logic;

begin
    ACK <= EMPTY and WRITE;

@CLK: -- the option1:
        if ACK then
            DOUT <= DIN;

@CLK: -- the option2:
--        if EMPTY then
--            DOUT <= DIN;



This is dilemma that I think is very typical in HW (In SW you would use the
variable/flag that is most recently used and is most likely cached).
Preference of one signal to another does not affect behaviuor, it affects
tracing and ethernal HW considerations  (size/frequency) ultimately. From
one point of view, I would choose the most frequently used signal because
its trace is broader available on PCB/PLD. On the other hand, if a signal is
frequently used this means that the greater number of destinations enforced
by its longer trace cause a high load of the signal.

Are PCB/FPGA considerations the same regarding this problem? Which general
rule do you use? Does this issue deserve any attention at all? Do you see
the issue?

Thanks.



Article: 64370
Subject: Re: This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
From: "A Day & A Knight" <kelvin8157@hotmail.com>
Date: Wed, 31 Dec 2003 21:35:53 +0800
Links: << >>  << T >>  << A >>
Hi, Durkin:

I am a little confused with the partial reconfiguration flow.

In the Active module implementation, I found that I must use the *.NGO file.
However .NGO file is only
available when I use EDIF file as input, and XST cannot produce EDIF file.

Does it mean I have no choice but to use something other than XST (e.g.
Synplicity) to synthesize my designs?

ngdbuild  -p xc2v250-fg256-4 -modular module -active iq_gen
../../top1/initial/sig_gen.ngo

Best Regards,
Kelvin





"Sean Durkin" <23@iis.42.de> wrote in message news:3ff00882$1@news.fhg.de...
> One Day & A Knight wrote:
>
> > Hi, there:
> > I want to know how to fix this kind of problem?
> >
> > Phase 1.1
> > ERROR:Place:205 - This design contains an RPM macro bm_0 which is to be
> > automatically placed, but it contains TBUF elelements that are not
allowed
> > during automatic placement of RPMs.  You must either pick an absolute
> >    location for the macro using a LOC constraint, or remove the TBUF
element
> >    from the macro.
> It tells you right there: "You must pick an absolute location for the
> macro"...
>
> Looks like you're using a bus macro here. Those will not be placed
> automatically, you have to position them manually with
> floorplanner/PACE. Or you can just put a corresponding location
> constraint into your .UCF, something like this:
>
> INST "bm_0" LOC = "TBUF_X0Y0" ;
>
> This would place the busmacro with the instance name "bm_0" in the lower
> left corner of the FPGA. Of course you have to do this for every
> instance, with different locations.
>
> Where you have to put it depends on what you want to do with it.
> Usually, you use bus macros to communicate between two modules of a
> design, so you place the macro so it straddles the border between the
> two modules it's supposed to connect.
>
> --
> Sean Durkin
> Fraunhofer Institute for Integrated Circuits (IIS)
> Am Wolfsmantel 33, 91058 Erlangen, Germany
> http://www.iis.fraunhofer.de
>
> mailto:23@iis.42.de
> ([23 , 42] <=> [durkinsn , fraunhofer])



Article: 64371
Subject: boolean to std_logic
From: "valentin tihomirov" <valentinNOSPAM@abelectron.com>
Date: Wed, 31 Dec 2003 16:30:05 +0200
Links: << >>  << T >>  << A >>
Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?



Article: 64372
Subject: Re: A dilemma: which signal to use as a master?
From: Keith R. Williams <krw@attglobal.net>
Date: Wed, 31 Dec 2003 09:44:52 -0500
Links: << >>  << T >>  << A >>
In article <bsugk7$1gv0l$1@ID-212430.news.uni-berlin.de>, 
valentinNOSPAM@abelectron.com says...
> Two related signals control a process. The process is launched if Sig1 or
> Sig2 is active. This does not mean OR logic. I bring an illustration  of a
> register just to make it clear.
> You have a register that can be in loaded or in empty state. It accepts data
> (becomes LOADED) when is EMPTY and WRITE input is active. At a clock edage
> when register is being loaded it responds with ACK signal, releasing data
> provider. That is, ACK is active when WRITE and EMPTY = '1'. There are two
> options when to load data FFs of the register:
>     - when EMPTY = '1', that is when reg. contains no valid data; or
>     - when ACK = '1', i.e. reg. responds the fact it loads data.
> Logically, the device will function equvalently. The pseudo-code:
> 
> entity:
>     WRITE: in std_logic
>     ACK: out std_logic
>     DIN, DOUT: std_logic_vector;
> 
> architecture
>     EMPTY: std_logic;
> 
> begin
>     ACK <= EMPTY and WRITE;
> 
> @CLK: -- the option1:
>         if ACK then
>             DOUT <= DIN;
> 
> @CLK: -- the option2:
> --        if EMPTY then
> --            DOUT <= DIN;
> 
> 
> 
> This is dilemma that I think is very typical in HW (In SW you would use the
> variable/flag that is most recently used and is most likely cached).
> Preference of one signal to another does not affect behaviuor, it affects
> tracing and ethernal HW considerations  (size/frequency) ultimately. From
> one point of view, I would choose the most frequently used signal because
> its trace is broader available on PCB/PLD. On the other hand, if a signal is
> frequently used this means that the greater number of destinations enforced
> by its longer trace cause a high load of the signal.
> 
> Are PCB/FPGA considerations the same regarding this problem? Which general
> rule do you use? Does this issue deserve any attention at all? Do you see
> the issue?

If I understand the question (it is confusing) you want to know *which* 
option to use to enable the register, ACK or WRITE.  Since ACK is EMPTY 
*AND* WRITE, ACK is at least one gate delay later than EMPTY.  If the 
logic doesn't matter (WRITE was irrelevant) I'd normally opt to take 
the faster signal to improve the setup time.  ...but perhaps I don't 
see the issue.

-- 
  Keith
 

Article: 64373
Subject: Re: A dilemma: which signal to use as a master?
From: "valentin tihomirov" <valentinNOSPAM@abelectron.com>
Date: Wed, 31 Dec 2003 17:52:13 +0200
Links: << >>  << T >>  << A >>
> If I understand the question (it is confusing) you want to know *which*
> option to use to enable the register, ACK or WRITE.
ACK or EMPTY, you cannot load a register if it is loaded.

> I'd normally opt to take the faster signal to improve the setup time.
...but perhaps I don't
> see the issue.
This is an option, thanks. I do not take it into consiteration since setup
time is the longest way the signal travels. As I have both signals (ACK and
EMPTY) anyway, there is no additional gate delay. However, if reg loading
controlling signal turns out to appear at the longest trace this option may
gain sense. But (I may mistake) in modern HW traces play as an important
role as the gates. If a signal is available at a certain part of a design
then why to trace another one?

So, any other options?



Article: 64374
(removed)




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