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Messages from 87175

Article: 87175
Subject: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 18 Jul 2005 19:47:22 +0200
Links: << >>  << T >>  << A >>
Hi

I think I can confirm that V4 silicon is breaking the 1GHz barrier in the
main FPGA fabric, as I did measure clock actual speeds of 952MHz in lowest
speed grade V4-LX25. Faster speed grades would defenetly run over 1GHz. Sure
there isnt much that can be done at those internal clock rates, but at least
some flip-flops can toggle at that rate. What is already pretty amazing.

FAST! but be aware not all internal circuitry speeds are scaled similarly in
V4 - LUT4 propagation delay as example is MUCH faster than in S3, but the
minimum clock low/high times are almost the same as in S3.

Antti



Article: 87176
Subject: Re: pricing of Virtex-4
From: "Peter Alfke" <peter@xilinx.com>
Date: 18 Jul 2005 11:25:24 -0700
Links: << >>  << T >>  << A >>
I am sorry that you did not get a quote from any distributor.
I usually stay out of such issues, but here is some help:
Single quantity LX15 in SF363 package used to be around $ 125
LX 25 was around $ 200.

For reasonable quantities and a few months out, I think the price will
be half those numbers.
For really large quantitities and even further out it might be cut in
half again.
Just my guess, based on a few decades of experience...
This is a public newsgroup, and I don't want to contradict our
marketing and sales folks.
Peter Alfke


Article: 87177
Subject: Re: pricing of Virtex-4
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Mon, 18 Jul 2005 14:37:50 -0400
Links: << >>  << T >>  << A >>
Peter,

First, thank for very much for the answer.

Yeah, I understand that giving V4 1-2 more years on the market will result 
in something like 20%-30% or more price reduction
and yet giving birth to Spartan-4-like family of cost-reducted V4 FPGAs, 
but... we need them yesterday :o() as always

Anyway, thanks again, appreciate it a lot.

Vladislav



"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1121711124.732297.69260@o13g2000cwo.googlegroups.com...
>I am sorry that you did not get a quote from any distributor.
> I usually stay out of such issues, but here is some help:
> Single quantity LX15 in SF363 package used to be around $ 125
> LX 25 was around $ 200.
>
> For reasonable quantities and a few months out, I think the price will
> be half those numbers.
> For really large quantitities and even further out it might be cut in
> half again.
> Just my guess, based on a few decades of experience...
> This is a public newsgroup, and I don't want to contradict our
> marketing and sales folks.
> Peter Alfke
> 



Article: 87178
Subject: sample for virtex4
From: "chat" <someone@somedomain.com.invalid>
Date: Mon, 18 Jul 2005 20:55:51 +0200
Links: << >>  << T >>  << A >>
i m look for a sample for virtex4 fx12 from avnet
there are 3 week,
 i'm trying to make a flickering led on my board,
an nothing.
I'm using ise 7
all sample from avnet are microblaze ou power pc

May be if y found a sample in vhdl/verilog/shematic to virtex4
 i understand why my design are false

Thank's
François Rigaud


--------------=  Posted using GrabIt  =----------------
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-=  Get GrabIt for free from http://www.shemes.com/  =-


Article: 87179
Subject: Re: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
From: "austin" <austin@xilinx.com>
Date: 18 Jul 2005 12:01:29 -0700
Links: << >>  << T >>  << A >>
Antti,

Well, the secret is out.  Yes, V4 is darn fast.  We have seen the DSP48
filters running at > 1 GHz clock rate (and working fine).  Even some
amount of fabric runs this fast. Don't expect everything to work
together at those rates, however (e.g. DCM, PPC, EMAC...).

I would suppose that for some real hotshots out there, who wanted to
get the fastest possible performance, they could design, characterize,
and test an application running in these stratospheric ranges.

But, they would be on their own, as they would have to closely regulate
the temperature and voltage to keep these working (we just do not
verify, characterize, nor specify it there).

I prefer to use my Intel Pentium IV where is was designed to work, and
not overclock it.  In the same way, you can get really impressive
performance from the V4, but we don't test it there.

Similar, are folks who want really low power, and run V4 at 1.0 volts
(+/- 5%).  They get 44% less dynamic power, and less than 1/2 the
static power, but it runs probably at 1/3 the max clock rates.

How many folks out there would like to buy a super low power version of
V4?  We could test to a special screen program for 1 V operation.  Let
me know...if no one wants it, we are unlikey to do anything.  But if
there is business out there, we'd like to be your supplier of choice!

In my past lives, I have designed product that was used where the
manufacturer didn't specify, and yes, I was on my own, but with careful
engineering, the products worked great.

I don't see that much anymore, as engineers have become "risk adverse"
in many areas (as they have become very "jobless adverse").

Of course, no risk, no reward.  So, those who never take any risks are
most likely to also never really get anywhere.

Austin

Antti Lukats wrote:
> Hi
>
> I think I can confirm that V4 silicon is breaking the 1GHz barrier in the
> main FPGA fabric, as I did measure clock actual speeds of 952MHz in lowest
> speed grade V4-LX25. Faster speed grades would defenetly run over 1GHz. Sure
> there isnt much that can be done at those internal clock rates, but at least
> some flip-flops can toggle at that rate. What is already pretty amazing.
>
> FAST! but be aware not all internal circuitry speeds are scaled similarly in
> V4 - LUT4 propagation delay as example is MUCH faster than in S3, but the
> minimum clock low/high times are almost the same as in S3.
> 
> Antti


Article: 87180
Subject: Re: setting XUP new board
From: Paul Hartke <phartke@Stanford.EDU>
Date: Mon, 18 Jul 2005 12:04:11 -0700
Links: << >>  << T >>  << A >>
The blinking red LED is normal--as the manual indicates it means there
is no System-ACE card inserted.  Since you don't have a CompactFlash
card, I'm not sure what your problem is.  

I have an older USB controller in my laptop and get that warning as
well.  You do need to upgrade to XP Service Pack 1:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20429  

The "Using Base System Builder" Quickstart at
http://www.xilinx.com/univ/xupv2p.html has info on just how to create
such a "Hello World" SoC design.

Paul

elinore2005@yahoo.fr wrote:
> 
> Hi
> 
> Here purchased a XUP VIIpro board (Digilent) today and trying a test
> with no success :)
> I am using EDK / ISE 6.3i with latest software update, Windows XP
> laptop PC.
> 
> It seems to have two problems.
> 
> First, when I first power-on, 'SYSTEM ACE' LED blinks in red, meaning
> something is wrong.
> 
> According to the hardware manual ug069, " JTAG configuration is by
> default from the Compact Flash. If a JTAG-based configuration is
> selected and a valid configuartion file is not found on the Comppact
> Flash card, the SYSTEM ACE ERROR LED flashes. "
> 
> One thing is that I do not have a Flash card !! -:
> It seems that I need to change jumpers or switches (i am not sure), but
> no idea how to manage this.
> 
> Second, when I first USB-connected between PC and the board, Windows
> machine automatically tried to find a device driver. Then something
> popped up saying  " Hi speed USB device plugged into non-hi speed USB
> hub. ....will function at reduced speed ".
> 
> Still I am not sure if those 2 problems are really problems -:
> Anyway when I run 'hyperterminal' (with correct setting - 9600baud,
> 8data bits, No Parity, 1 Stop bit and No flow control), nothing appears
> in hyperterminal. So it should be something wrong.
> 
> My goal is to configure using USB cable without Flash card and run
> 'hello world' with microblaze :)
> If someone has this experience (especially with XUP board), let me know
> how to shoot trouble.
> 
> Thankyou in advance

Article: 87181
Subject: EHLO, board designers
From: "Brannon" <brannonking@yahoo.com>
Date: 18 Jul 2005 12:38:06 -0700
Links: << >>  << T >>  << A >>
Why can I not purchase a PCI board with a Spartan3, some SRAM, and a
DRAM slot for $200? That's way more than the cost of the parts. Heck,
with Xilinx's recent anouncements about 3rd party PCI-Express support I
should be able to get that interface for the same price. What I'm
picturing is general coprocessing. Nobody seems to think FPGAs are
valuable for everyday coprocessing if you judge by the boards being
made. Cray, Starbridge, SGI, Nallatech, and others recognize the value
in coprocessing but they are targeting the HPCS market. It's the wrong
market. All the other PCI boards I've seen lately are made for
prototyping or DSP processing, especially in the sub $5k range. A
simple Spartan3-based board for coprocessing could change the world.
Video game companies could ship neural net modules, math companies
could ship libraries that use it for acceleration, CAD and imaging
companies could take advantage of it for acceleration, etc; for that to
happen, everybody needs one. For that to happen, they have to be as
cheap as a decent graphics card and compilers for them must be as cheap
as GNU gcc. And they don't need a freakin' serial port, ethernet port,
parallel port, USB port, half a dozen different RAM ports, proprietary
connectors, and the kitchen sink for prototyping! How are we going to
get there and why are we not there already?


Article: 87182
Subject: Re: EHLO, board designers
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 18 Jul 2005 21:47:23 +0200
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> schrieb im Newsbeitrag
news:1121715486.789777.277650@g47g2000cwa.googlegroups.com...
> Why can I not purchase a PCI board with a Spartan3, some SRAM, and a
> DRAM slot for $200? That's way more than the cost of the parts. Heck,
> with Xilinx's recent anouncements about 3rd party PCI-Express support I
> should be able to get that interface for the same price. What I'm
> picturing is general coprocessing. Nobody seems to think FPGAs are
> valuable for everyday coprocessing if you judge by the boards being
> made. Cray, Starbridge, SGI, Nallatech, and others recognize the value
> in coprocessing but they are targeting the HPCS market. It's the wrong
> market. All the other PCI boards I've seen lately are made for
> prototyping or DSP processing, especially in the sub $5k range. A
> simple Spartan3-based board for coprocessing could change the world.
> Video game companies could ship neural net modules, math companies
> could ship libraries that use it for acceleration, CAD and imaging
> companies could take advantage of it for acceleration, etc; for that to
> happen, everybody needs one. For that to happen, they have to be as
> cheap as a decent graphics card and compilers for them must be as cheap
> as GNU gcc. And they don't need a freakin' serial port, ethernet port,
> parallel port, USB port, half a dozen different RAM ports, proprietary
> connectors, and the kitchen sink for prototyping! How are we going to
> get there and why are we not there already?
>

changing the world huh? challenging is it not?

the board you wish isnt there, either somethign missing or something too
much.

I would say it makes MUCH more sense to get it done with PCIe - hmmm as my
last inquiry the Avnets Spartan-3 + PCIe evaluation kit was supposed to be
available end of June - but I havent asked about it for some while maybe its
even out already.

there are some cheap Lattice EC boards with DIMM sockets, but also a little
above the 200$ range

humm the PCIe board could actually be CHEAPER than the PCI board - smaller
and no need for those 5V translators :)

Antti



Article: 87183
Subject: Re: EHLO, board designers
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Mon, 18 Jul 2005 22:54:59 +0200
Links: << >>  << T >>  << A >>
Hi Antti,
> 
> humm the PCIe board could actually be CHEAPER than the PCI board - smaller
> and no need for those 5V translators :)

True...

... but I'd first have to shell out $500 for a new mobo, CPU and memory.
Hmmm... how to get budget for that...



Ben


Article: 87184
Subject: Re: Virtex-4 5V tolerance
From: "austin" <austin@xilinx.com>
Date: 18 Jul 2005 14:41:41 -0700
Links: << >>  << T >>  << A >>
Yes, it does.

Austin


Article: 87185
Subject: Re: EHLO, board designers
From: "Joel Kolstad" <JKolstad71HatesSpam@yahoo.com>
Date: Mon, 18 Jul 2005 14:58:27 -0700
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> wrote in message
news:1121715486.789777.277650@g47g2000cwa.googlegroups.com...
> Why can I not purchase a PCI board with a Spartan3, some SRAM, and a
> DRAM slot for $200?

Because, given the low demands for boards like that, it costs a lot more than
$200 once you factor in the time needed for someone to design & debug that
board.  You might expect Xilinx to do this -- many semiconductor sell
evaluation boards at what's effectively "giveaway" prices in that they lose
money on the sale, but figure they'll make it up in sales of the actual
part -- but unfortunately Xilinx doesn't (at present).

> That's way more than the cost of the parts.

Costs of parts is an incredibly small factor in determining sales price in
many products.

> A
> simple Spartan3-based board for coprocessing could change the world.
> Video game companies could ship neural net modules, math companies
> could ship libraries that use it for acceleration, CAD and imaging
> companies could take advantage of it for acceleration, etc; for that to
> happen, everybody needs one.

You need a lot more than a simple evaluation board to get all those companies
to adopt your co-processing model -- you also need large, sophisticated
libraries that help programmers make use of the co-processing features.  And
keep in mind some of the main downfalls of any hardware based co-processor:
It's a given that Intel, AMD, etc. will crack out faster and faster processors
every year, so your specialized hardware ends up having to be re-designed
regularly to continue to keep its "edge" -- this is an on-going expense
(Patterson & Hennessy, in their Computer Architecture book, talk about how IBM
once had a hard drive with a specialized co-processor to perform text string
searches, but that over time as CPUs became faster and the specialized
hardware remained the same, eventually it became slower to use that
specialized hardware than to just burn CPUs cycles to perform the search.
Similarly, by the time the Commodore Amiga computers were running 25MHz 68030
CPUs, it had become faster to use the CPU to perform some graphical functions
such as text scrolling than to use the old Blitter graphics co-processor
running at 7.14MHz).  If your application really DOES catch on, it'll just be
designed into a custom chip or made part of a CPU anyway -- witness Intel's
MMX instructions and the proponderence of WinModems today, look at how
graphics cards now have "GPUs" that are often on par in sophistication with
general purpose CPUs, notice how the better sound cards have on-board ASICs
containing lots of DSP hardware, etc.

So... all I'm really saying is that, while there certainly are applications
for "general purpose" co-processing, any application of such technology that's
particularly successful will just be moved into an ASIC where far more people
will benefit from lower price, lower power consumption, etc. anyway.

> How are we going to
> get there and why are we not there already?

How about if you put in your own time and effort to design such a card and its
corresponding software (as an "open source" hardware project) and they start
selling the boards for $200?  Many people here would probably buy one! :-)

---Joel Kolstad



Article: 87186
Subject: Re: Virtex-4 5V tolerance
From: "Peter Alfke" <peter@xilinx.com>
Date: 18 Jul 2005 15:07:55 -0700
Links: << >>  << T >>  << A >>
Let me put my tutorial hat on:
Virtex-4 pins should not see a voltage significantly more positive than
4 V, because that would overstress the thin gate oxide in some
transistors.
As a means to avoid damage from electro-static discharge, there is a
diode between each pin and its Vcc supply connection, preventing the
pin from going more positive than Vcco + 0.7 V.

If you drive the pin with a voltage >4 V, this diode gets
forward-biased and will conduct tens of milliamps (provided Vcco is 3.3
V, which it should be if you want to be 5-V tolerant.)
Now you need something to limit the current that the 5-V output drives
into the protection diode, and through it into the 3.3-V supply.
Limiting it to <10 mA is a good idea. A resistor comes in handy.

The accuracy of that resistor is irrelevant. A higher value would slow
down the signal, since the pin represents a capacitive load. If speed
is not an issue, use 1 kilohm. But remember that this resistor might
also be in the way when the FPGA pin is an output.
With an even higher resistor, the voltage tolerance goes up.
With a 10 kilom (1W!) resistor, it becomes 100-V tolerant, if anybody
would care.  :-)
This is really Basic Electricity 101.
Peter Alfke


Article: 87187
Subject: Re: Reading a PS/2 mouse
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Tue, 19 Jul 2005 10:26:58 +1200
Links: << >>  << T >>  << A >>
greenplanet wrote:
> Thanks for your reply, Jeremy!

np.

> I was using Xilinx Spartan 2E 200 on Digilent D2Sb with DIO4 extension
> board.  I'm driving the line to 'Z' not to '1'.  However, after probing
> the PS/2 port (6 pin mini-DIN)on the board without attaching a mouse, I
> found that the data and clk stay at '0' always (according to the
> schematic from Digilent, there is no pull up circuit on both PS/2 data
> and clk lines).  When I probe the corresponding fpga pins, they work as
> I programmed (logic 1 = 3.3V, logic 0 ~0V).  Seems like the fpga
> couldn't take control of the port!

!?  Sounds a touch odd.  If the pins are connected to the PS/2 port, 
then you would expect the port and the pins to be the same.  If you take 
the PS/2 port as the reference, then it would perhaps be a case of 
enabling the pullup resistors in the IOB (xc_pullup attribute for 
synplify - the xilinx attribute is PULLUP (from memory))).  This 
wouldn't explain your original problem though.

Guess you need to find out why the pins and the port don't match :)  The 
other point of course, is that you state that the protocol uses 5V - but 
you're driving 3.3V?

> I will try to use another board (XESS XSA3S1000 with Xstend V3.0) and
> see if this happens.

Jeremy

Article: 87188
Subject: EDK 7.1 with ML401 (paging Antti)
From: "Pete Fraser" <pfraser@covad.net>
Date: Mon, 18 Jul 2005 16:01:56 -0700
Links: << >>  << T >>  << A >>
I'm just about to start a small ML401 design,and am not
sure if I should use EDK 6.3 or EDK 7.1.

Has anyone (Antti?) been able to get the reference design
working with 7.1, or should I stick to 6.3?

Thanks




Article: 87189
Subject: ethernet EMAC cores available for Microblaze
From: kurapati77@gmail-dot-com.no-spam.invalid (kurapati)
Date: Mon, 18 Jul 2005 19:16:48 -0500
Links: << >>  << T >>  << A >>
Hi

Xilinx offers different IP cores for ethernet. like opb_ethernet,
plb_ethernet, plb_temac, plb_gemac, ll_temac, ll_gemac, etc. 

Which of those IPs can be used to have a gigabit MAC using Microblaze
processor. 

Recently EDK servicepack 3 has been released and there is a plb_temac
but I could not find the posibilty to use it with microblaze
processor. 

And there is a 1-Gigabit MAC available and was used in GSRD design but
its also for PowerPC processor. 

I want to have gigabit ethernet to be used with microblaze either with
 hard/soft TEMAC or with gigabit soft core. Where can find the
performance differnces between these two. 

The distinction between microblaze and powerPC use for different EMAC
cores is really appreciated.

regards
Rajesh


Article: 87190
Subject: Re: EDK 7.1 with ML401 (paging Antti)
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 19 Jul 2005 11:50:13 +1000
Links: << >>  << T >>  << A >>
Pete Fraser wrote:
> I'm just about to start a small ML401 design,and am not
> sure if I should use EDK 6.3 or EDK 7.1.
> 
> Has anyone (Antti?) been able to get the reference design
> working with 7.1, or should I stick to 6.3?

We've been working with the ML401 on EDK6.3 for a few months now, and 
apart from some minor glitches it mostly works OK.  Make sure you read 
Xilinx solution record 20060 about XMD_LX and updated opb_mdm core, if 
you want to do MicroBlaze hardware debugging.

I installed EDK7.1-SP2 the other day, but haven't had a chance to try it 
yet.  I did notice an updated ML401 reference design on xilinx.com, so 
presumably that should build out of the box.

One thing I did see, the newest XBD files (for Base System Builder) for 
the ML401 don't contain any timing constraints on the DDR nets and pins. 
  So, it seems unlikely that any BSB projects targetting the ML401 will 
work with DDR.  One of our students is checking this out, hopefully 
we'll know for sure in a day or two.

Cheers,

John

Article: 87191
Subject: Driving the FPGA output.
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 18 Jul 2005 23:11:27 -0700
Links: << >>  << T >>  << A >>
Hello all,
     I am working on a ARM development board. I am modifting its system
FPGA which controls the peripherals. A signal output from the fpga is
now in the high impedance stete from the fpga and is pulled up with a
10k resistor. VCC is 3.3V. Another signal is pulled down to gnd using a
4.7K resistor. is it possible to drive these signals from the FPGA. if
yes what is the necessary modifications to be done in the ucf file
(about the drive strength, pad type etc). i tried with
LVTTL,PULLEDUP,Drive strength 12. But the value didnot changed. I
working with a Xilinx VirtexE FPGA. Please advice me on this issue.
Sumesh


Article: 87192
Subject: Re: Driving the FPGA output.
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 08:48:52 +0200
Links: << >>  << T >>  << A >>
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag
news:1121753487.138517.30330@g14g2000cwa.googlegroups.com...
> Hello all,
>      I am working on a ARM development board. I am modifting its system
> FPGA which controls the peripherals. A signal output from the fpga is
> now in the high impedance stete from the fpga and is pulled up with a
> 10k resistor. VCC is 3.3V. Another signal is pulled down to gnd using a
> 4.7K resistor. is it possible to drive these signals from the FPGA. if
> yes what is the necessary modifications to be done in the ucf file
> (about the drive strength, pad type etc). i tried with
> LVTTL,PULLEDUP,Drive strength 12. But the value didnot changed. I
> working with a Xilinx VirtexE FPGA. Please advice me on this issue.
> Sumesh
>
yes, it is possible. you need some meaningful and useful design into FPGA.
nobody else except you know what you want to implement so nobody can help
with that. as long as FPGA output is not driving the value on those pins
will remain controlled by those ext. pullup pulldown resistors as the FPGA
pullup/down resistors are very large nominal comparing to 10Kohms.


Antti




Article: 87193
Subject: Re: setting XUP new board
From: "Alex Gibson" <news@alxx.net>
Date: Tue, 19 Jul 2005 16:56:49 +1000
Links: << >>  << T >>  << A >>

<elinore2005@yahoo.fr> wrote in message 
news:1121692247.873313.136410@g43g2000cwa.googlegroups.com...
> Hi
>
> Here purchased a XUP VIIpro board (Digilent) today and trying a test
> with no success :)
> I am using EDK / ISE 6.3i with latest software update, Windows XP
> laptop PC.
>
> It seems to have two problems.
>
> First, when I first power-on, 'SYSTEM ACE' LED blinks in red, meaning
> something is wrong.

No ,  just means you don't have a compact flash card plugged in.

> According to the hardware manual ug069, " JTAG configuration is by
> default from the Compact Flash. If a JTAG-based configuration is
> selected and a valid configuartion file is not found on the Comppact
> Flash card, the SYSTEM ACE ERROR LED flashes. "
>
> One thing is that I do not have a Flash card !! -:
> It seems that I need to change jumpers or switches (i am not sure), but
> no idea how to manage this.

Read the user/reference manual
available here
http://www.digilentinc.com/info/XUPV2P.cfm
or
http://www.xilinx.com/univ/xupv2p.html

>
> Second, when I first USB-connected between PC and the board, Windows
> machine automatically tried to find a device driver. Then something
> popped up saying  " Hi speed USB device plugged into non-hi speed USB
> hub. ....will function at reduced speed ".
>
> Still I am not sure if those 2 problems are really problems -:

They are not problems. Standard annoying windows message
when you plug a high speed(up to 480Mbps) usb device into a low speed(1Mbps) 
or full speed (12Mbps) port.

> Anyway when I run 'hyperterminal' (with correct setting - 9600baud,
> 8data bits, No Parity, 1 Stop bit and No flow control), nothing appears
> in hyperterminal. So it should be something wrong.

Using a standard serial cable ?

> My goal is to configure using USB cable without Flash card and run
> 'hello world' with microblaze :)
> If someone has this experience (especially with XUP board), let me know
> how to shoot trouble.
>
> Thankyou in advance

Worked straight out of the box without problems here.
other than the memory test - due to not having a supported dimm - tried to 
use a  dual bank 256MB.
Haven't had time to build a microblaze project yet.
Hopefully some time this week , I also want to give uclinux and linux a 
whirl.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html

Try setting switch9  on to sw9-1 up (on) and up (on)
that'll give you the goldern  (builtin)  config.


Alex 



Article: 87194
Subject: Re: EDK 7.1 with ML401 (paging Antti)
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 09:02:43 +0200
Links: << >>  << T >>  << A >>
"Pete Fraser" <pfraser@covad.net> schrieb im Newsbeitrag
news:11dod73k02gui25@news.supernews.com...
> I'm just about to start a small ML401 design,and am not
> sure if I should use EDK 6.3 or EDK 7.1.
>
> Has anyone (Antti?) been able to get the reference design
> working with 7.1, or should I stick to 6.3?
>
> Thanks
>
>

Hi Pete,

me no - I do not happen to own any Xilinx developed Xilinx boards :( only
vendor boards.

as of 7.1 - I would say go ahead, the issues I had are rather corner cases
1) XMD 7.1 SP1 + USB Cable + V4 combination does not work, possible fixed in
EDK SP2
2) trouble with Microblaze 4.0, had to downgrade to 3.0

but otherwise the migration to 7.1 was rather painless

Antti




Article: 87195
Subject: Re: EHLO, board designers
From: "Arash Salarian" <arash.salarian@epfl.ch>
Date: Tue, 19 Jul 2005 10:56:07 +0200
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> wrote in message 
news:1121715486.789777.277650@g47g2000cwa.googlegroups.com...
> Why can I not purchase a PCI board with a Spartan3, some SRAM, and a
> DRAM slot for $200? That's way more than the cost of the parts. Heck,
> with Xilinx's recent anouncements about 3rd party PCI-Express support I
> should be able to get that interface for the same price. What I'm
> picturing is general coprocessing. Nobody seems to think FPGAs are
> valuable for everyday coprocessing if you judge by the boards being
> made. Cray, Starbridge, SGI, Nallatech, and others recognize the value
> in coprocessing but they are targeting the HPCS market. It's the wrong
> market. All the other PCI boards I've seen lately are made for
> prototyping or DSP processing, especially in the sub $5k range. A
> simple Spartan3-based board for coprocessing could change the world.
> Video game companies could ship neural net modules, math companies
> could ship libraries that use it for acceleration, CAD and imaging
> companies could take advantage of it for acceleration, etc; for that to
> happen, everybody needs one. For that to happen, they have to be as
> cheap as a decent graphics card and compilers for them must be as cheap
> as GNU gcc. And they don't need a freakin' serial port, ethernet port,
> parallel port, USB port, half a dozen different RAM ports, proprietary
> connectors, and the kitchen sink for prototyping! How are we going to
> get there and why are we not there already?

The problem is that the number of applications usefull for normal users 
where a "tiny" FPGA like Spartan3 can make a significant speed-up in 
comparision to a 3.8GHz Pentium IV, is quite small. Do you notice that 
currently, GPUs for example are monsters with 300+ million transistors? 
FPGAs, even the fattest ones are way too small to justify their application 
in GENERAL processing markets. Don't take me wrong, I do DSP in FPGA and not 
with processors exactly for performance reasons but I use it for very 
special applications not for say, accelerating games or CAD applications as 
you suggest. If you could get an FPGA board with a capacity of 10 million 
gaits in less than $200 in the market, then I could start thinking of some 
small applications for it in general PC market. With smaller FPGAs, just 
forget it. 



Article: 87196
Subject: Re: Lattice MachXO is LAUNCHED NOW!
From: "Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org>
Date: Tue, 19 Jul 2005 19:49:54 +1000
Links: << >>  << T >>  << A >>

"Antti Lukats" <antti@openchip.org> wrote in message
news:dbgc00$ced$01$1@news.t-online.com...
> Finally launched!
>
> additional features (what I did not know)
>
> 1) standby
> 2) 20MHz on chip oscillator
> 3) distributed memory in all devices
>
> and first devices should be available already !!
>
> WAU!!
>
> Antti
>
Seen any pricing yet?  I'm guessing about US$2-$4 for smallest to largest in
(say) 1k lots.   Will ask the rep tomorrow.

Pity about the lack of small useable (non-bga) packages (a 20 pin SOIC or 44
pin TQFP would have been nice).  I've also got a ready application for one
thats 4 times as big as the biggest.

Cheers,
Alf



Article: 87197
Subject: Re: Lattice MachXO is LAUNCHED NOW!
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 12:31:11 +0200
Links: << >>  << T >>  << A >>
"Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org> schrieb im
Newsbeitrag news:42dcccc1$0$25427$afc38c87@news.optusnet.com.au...
>
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:dbgc00$ced$01$1@news.t-online.com...
> > Finally launched!
> >
> > additional features (what I did not know)
> >
> > 1) standby
> > 2) 20MHz on chip oscillator
> > 3) distributed memory in all devices
> >
> > and first devices should be available already !!
> >
> > WAU!!
> >
> > Antti
> >
> Seen any pricing yet?  I'm guessing about US$2-$4 for smallest to largest
in
> (say) 1k lots.   Will ask the rep tomorrow.
>
> Pity about the lack of small useable (non-bga) packages (a 20 pin SOIC or
44
> pin TQFP would have been nice).  I've also got a ready application for one
> thats 4 times as big as the biggest.
>
> Cheers,
> Alf
>

yep, TSOP20 would be nice! or QFN32

the only pricing I have is approx 8$USD for machXO1200 qty 100

thats not so bad as I you get a free PLL too :)

the bad thing is that the free tools support for machXO is promised in
August only :(

Antti






Article: 87198
Subject: Re: Lattice MachXO is LAUNCHED NOW!
From: Luc <lb.edc@pandora.be>
Date: Tue, 19 Jul 2005 13:19:38 +0200
Links: << >>  << T >>  << A >>
Alf,

100p TQFP is a quite useful package, don't you think?

If you're looking for a big 'MachXO', then you end up with the
LatticeXP - 10K LUT's. The only trade off is that you'll need a BGA
package, I'm afraid.

Cheers,

Luc

On Tue, 19 Jul 2005 19:49:54 +1000, "Unbeliever"
<alfkatz@remove.the.bleedin.obvious.ieee.org> wrote:

>
>"Antti Lukats" <antti@openchip.org> wrote in message
>news:dbgc00$ced$01$1@news.t-online.com...
>> Finally launched!
>>
>> additional features (what I did not know)
>>
>> 1) standby
>> 2) 20MHz on chip oscillator
>> 3) distributed memory in all devices
>>
>> and first devices should be available already !!
>>
>> WAU!!
>>
>> Antti
>>
>Seen any pricing yet?  I'm guessing about US$2-$4 for smallest to largest in
>(say) 1k lots.   Will ask the rep tomorrow.
>
>Pity about the lack of small useable (non-bga) packages (a 20 pin SOIC or 44
>pin TQFP would have been nice).  I've also got a ready application for one
>thats 4 times as big as the biggest.
>
>Cheers,
>Alf
>


Article: 87199
Subject: Re: EHLO, board designers
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 19 Jul 2005 12:25:00 +0100
Links: << >>  << T >>  << A >>
Making the case as a board manufacturer the cost of a board is not just the 
chips on there. The development board market is not a hugh volume market and 
usually assembly and test of boards is considerably more that you would 
incur in a consumer product volume level. Companies in this market are also 
not charities and at least like to get the development labour costs back on 
a board development. Man time, or even women time, is expensive and if 
advertised over a few hundred boards still makes a considerable effect on a 
board price. And to cap all that it is even nice to make the odd bit of 
profit. This tends to keep the shareholders happy which is often a good 
thing.

And to make our case I agree there are a lot boards out there than have 
features that most people individually don't want but you don't want to make 
individual boards for everyone due to the costs involved. As we don't have 
manufacturer lines to push, unlike some of our competitors, our approach 
here is to go for a minimalist fixed fit of functions and then to make up 
for this with cheap simply manufactured modules. We also design our boards 
so that you can add your own add-ons easily.

Our boards come close to general use scenario and we already supplying some 
number of boards in this way. Volume customers do get substantial discounts 
as the batch handling, shipping etc has a much lower cost base for us to 
cover.

At the moment PCI-E is a lot dearer to implement than 32bit PCI. The PCI-E 
core also eats a large part of your FPGA unless you have a large device to 
start with. The Philips device listed for the phy part of the design is 
currently hard to get, and dearer than the 3 bus switches we use on 32 bit 
PCI, although I believe that supply issue will ease shortly.

And to end this long rant and to wake up those skinflints now sleeping we 
will have a cheap product that at least in part will meet your needs late 
September or early October. Still not happy then go make your own.

John Adair
Enterpoint Ltd. - Soon to be the home of Raggedstone1. The very very cheap 
PCI Development Board.
http://www.enterpoint.co.uk


"Brannon" <brannonking@yahoo.com> wrote in message 
news:1121715486.789777.277650@g47g2000cwa.googlegroups.com...
> Why can I not purchase a PCI board with a Spartan3, some SRAM, and a
> DRAM slot for $200? That's way more than the cost of the parts. Heck,
> with Xilinx's recent anouncements about 3rd party PCI-Express support I
> should be able to get that interface for the same price. What I'm
> picturing is general coprocessing. Nobody seems to think FPGAs are
> valuable for everyday coprocessing if you judge by the boards being
> made. Cray, Starbridge, SGI, Nallatech, and others recognize the value
> in coprocessing but they are targeting the HPCS market. It's the wrong
> market. All the other PCI boards I've seen lately are made for
> prototyping or DSP processing, especially in the sub $5k range. A
> simple Spartan3-based board for coprocessing could change the world.
> Video game companies could ship neural net modules, math companies
> could ship libraries that use it for acceleration, CAD and imaging
> companies could take advantage of it for acceleration, etc; for that to
> happen, everybody needs one. For that to happen, they have to be as
> cheap as a decent graphics card and compilers for them must be as cheap
> as GNU gcc. And they don't need a freakin' serial port, ethernet port,
> parallel port, USB port, half a dozen different RAM ports, proprietary
> connectors, and the kitchen sink for prototyping! How are we going to
> get there and why are we not there already?
> 





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