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Threads Starting Mar 2002
40174: 02/03/01: Thomas Zipper: high-speed clock distribution/divider in a FPGA?
40186: 02/03/01: Austin Lesea: Re: high-speed clock distribution/divider in a FPGA?
40187: 02/03/01: Theron Hicks (Terry): Re: high-speed clock distribution/divider in a FPGA?
40188: 02/03/01: Austin Lesea: Re: high-speed clock distribution/divider in a FPGA?
40176: 02/03/01: Colin Bury: Clock multiplier/ADPLL in PLD
40181: 02/03/01: Ray Andraka: Re: Clock multiplier/ADPLL in PLD
40190: 02/03/01: John_H: Re: Clock multiplier/ADPLL in PLD
40198: 02/03/01: Ray Andraka: Re: Clock multiplier/ADPLL in PLD
40211: 02/03/02: John_H: Re: Clock multiplier/ADPLL in PLD
40185: 02/03/01: Antonio: clock nets use non-dedicated resources
40194: 02/03/01: Nicholas Weaver: Xilinx Virtex Family die photos...
40215: 02/03/02: Speedy: Re: Xilinx Virtex Family die photos...
40217: 02/03/02: Nicholas Weaver: Re: Xilinx Virtex Family die photos...
40274: 02/03/04: Austin Lesea: Re: Xilinx Virtex Family die photos...
40197: 02/03/01: jerry1111: Altera Excalibur
40205: 02/03/01: Paul: Re: Altera Excalibur
40212: 02/03/01: James Horn: Re: Altera Excalibur
40216: 02/03/02: Peter Ormsby: Re: Altera Excalibur
40219: 02/03/02: jerry1111: Re: Altera Excalibur
40220: 02/03/02: Victor Schutte: Re: Altera Excalibur
40221: 02/03/02: jerry1111: Re: Altera Excalibur
40226: 02/03/02: Muzaffer Kal: Re: Altera Excalibur
40232: 02/03/02: Petter Gustad: Re: Altera Excalibur
40235: 02/03/03: Peter Ormsby: Re: Altera Excalibur
40241: 02/03/03: jerry1111: Re: Altera Excalibur
40202: 02/03/01: praveen: simulating time_sim.vhd file
40224: 02/03/02: Joey Nelson: Embedding counting in an FSM.
40230: 02/03/02: Mike Treseler: Re: Embedding counting in an FSM.
40248: 02/03/03: rickman: Re: Embedding counting in an FSM.
40250: 02/03/03: Rick Filipkiewicz: Re: Embedding counting in an FSM.
40252: 02/03/03: Hal Murray: Re: Embedding counting in an FSM.
40253: 02/03/03: Rick Filipkiewicz: Re: Embedding counting in an FSM.
40227: 02/03/02: Vladimir Ralev: turnaround cycle?
40231: 02/03/02: Kevin Brace: Re: turnaround cycle?
40238: 02/03/03: Vladimir Ralev: Re: turnaround cycle?
40242: 02/03/03: Rick Filipkiewicz: Re: turnaround cycle?
40255: 02/03/03: Kevin Brace: Re: turnaround cycle?
40228: 02/03/02: Ray Andraka: Re: What FPGA to use?
40290: 02/03/04: Jay: Re: What FPGA to use?
40314: 02/03/05: Remco Poelstra: Re: What FPGA to use?
40330: 02/03/05: Ray Andraka: Re: What FPGA to use?
40229: 02/03/02: Remco Poelstra: What FPGA to use?
40233: 02/03/02: Mike Treseler: Re: What FPGA to use?
40234: 02/03/02: Paul: Re: What FPGA to use?
40278: 02/03/04: John_H: Re: What FPGA to use?
40236: 02/03/02: Al Williams: Xilinx WebPack Simulation
40243: 02/03/03: Rick Filipkiewicz: Re: Xilinx WebPack Simulation
40258: 02/03/03: Al Williams: Re: Xilinx WebPack Simulation
40237: 02/03/03: Yunhsianghsu: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
40256: 02/03/03: Kevin Brace: Re: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
40244: 02/03/03: Daniel Yap: thank you friends
40254: 02/03/03: Ray Morales: max3000a odd behavior -- is the bug in my vhdl code? help!
40257: 02/03/04: Jim Granville: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40271: 02/03/04: Ray Morales: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40285: 02/03/04: Ray Morales: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40287: 02/03/05: Jim Granville: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40281: 02/03/04: Mike Treseler: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40259: 02/03/04: Kevin Brace: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work
40262: 02/03/04: Paul: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work correctly?
40282: 02/03/04: Mike Treseler: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40312: 02/03/05: Russell Shaw: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40332: 02/03/05: Mike Treseler: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40342: 02/03/05: Kevin Brace: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40260: 02/03/03: Antonio: Constraining help required for clk_enable
40263: 02/03/04: David Hawke: Re: Constraining help required for clk_enable
40284: 02/03/04: Falk Brunner: Re: Constraining help required for clk_enable
40292: 02/03/05: Philip Freidin: Re: Constraining help required for clk_enable
40308: 02/03/05: David Hawke: Re: Constraining help required for clk_enable
40315: 02/03/05: Magnus Homann: Re: Constraining help required for clk_enable
40261: 02/03/03: Antonio: Other 2 constraining how to questions
40264: 02/03/04: David Hawke: Re: Other 2 constraining how to questions
40266: 02/03/04: Leon Qin: Is there a ver 7.1 of Sunplify?
40385: 02/03/06: S Ramirez: Re: Is there a ver 7.1 of Sunplify?
40459: 02/03/07: Bob Efram: Re: Is there a ver 7.1 of Sunplify?
40268: 02/03/04: Jarek: Atmel back annotation problems
40269: 02/03/04: satya: Asynchronous boundaries in FPGA
40283: 02/03/04: Peter Alfke: Re: Asynchronous boundaries in FPGA
40286: 02/03/04: Falk Brunner: Re: Asynchronous boundaries in FPGA
40306: 02/03/05: Ken Mac: Re: Asynchronous boundaries in FPGA
40376: 02/03/06: satya: Re: Asynchronous boundaries in FPGA
40270: 02/03/04: Giulio Ferro: quest for info
40275: 02/03/04: Ken Mac: phantom timing constraints in ISE 4.1
40280: 02/03/04: John_H: Re: phantom timing constraints in ISE 4.1
40309: 02/03/05: Ken Mac: Re: phantom timing constraints in ISE 4.1
40277: 02/03/04: Paul Butler: Minimum Size and Logic Sharing
40297: 02/03/04: Xilinx FAE from Insight SANKET: Re: Minimum Size and Logic Sharing
40300: 02/03/05: Ray Andraka: Re: Minimum Size and Logic Sharing
40288: 02/03/04: Chinmay: can "initial signal values" and other "for.....use" statements damage fpgas?
40291: 02/03/04: Rick Filipkiewicz: Re: can "initial signal values" and other "for.....use" statements
40294: 02/03/05: Kris Nichols: Xilinx EDA support for run-time reconfiguration
40577: 02/03/11: Ian Robertson: Re: Xilinx EDA support for run-time reconfiguration
40295: 02/03/04: ssy: convert_hex2ver can not generate the *.ver file
40299: 02/03/04: Mike Treseler: Re: convert_hex2ver can not generate the *.ver file
40298: 02/03/04: praveen: Converting VHDL netlist to EDN/EDF/XNF
40303: 02/03/05: Thomas Stanka: Re: Converting VHDL netlist to EDN/EDF/XNF
40325: 02/03/05: Praveen: Re: Converting VHDL netlist to EDN/EDF/XNF
40301: 02/03/05: Rob Finch: Clock dividing
40302: 02/03/04: Albert: Need Help
40337: 02/03/05: John_H: Re: Need Help
40304: 02/03/05: David de Andrés: Synthesizing with CORE Generator
40305: 02/03/05: Rick Filipkiewicz: Re: Synthesizing with CORE Generator
40321: 02/03/05: David de Andrés: Re: Synthesizing with CORE Generator
40311: 02/03/05: Paul: FPGA problems
40334: 02/03/05: Mike Treseler: Re: FPGA problems
40344: 02/03/05: Jay: Re: FPGA problems
40400: 02/03/06: Paul: Re: FPGA problems
40443: 02/03/07: Paul: Re: FPGA problems
40316: 02/03/05: Young-Su Kwon: Writing Synosys library for FPGA using LUT.
40357: 02/03/05: Muzaffer Kal: Re: Writing Synosys library for FPGA using LUT.
40317: 02/03/05: Matthias Wenzel: Array case expression must have a static subtype (VHDL)
40323: 02/03/05: Alan Fitch: Re: Array case expression must have a static subtype (VHDL)
40318: 02/03/05: M Schreiber: exceeding 2GB limits in xilinx
40322: 02/03/05: Austin Lesea: Re: exceeding 2GB limits in xilinx
40335: 02/03/05: Austin Lesea: Re: exceeding 2GB limits in xilinx
40354: 02/03/05: <istjohn@spamcop.net>: Re: exceeding 2GB limits in xilinx
40380: 02/03/06: Erwin Rol: Re: exceeding 2GB limits in xilinx
40384: 02/03/06: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40324: 02/03/05: emanuel stiebler: Re: exceeding 2GB limits in xilinx
40333: 02/03/05: Jay: Re: exceeding 2GB limits in xilinx
40339: 02/03/05: Ray Andraka: Re: exceeding 2GB limits in xilinx
40364: 02/03/05: Assaf Sarfati: Re: exceeding 2GB limits in xilinx
40365: 02/03/06: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40368: 02/03/06: Muzaffer Kal: Re: exceeding 2GB limits in xilinx
40370: 02/03/06: Lars Rzymianowicz: Re: exceeding 2GB limits in xilinx
40410: 02/03/06: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40426: 02/03/07: Peter Ormsby: Re: exceeding 2GB limits in xilinx
40435: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40442: 02/03/07: Nial Stewart: Re: exceeding 2GB limits in xilinx
40476: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40494: 02/03/08: Tim: Re: exceeding 2GB limits in xilinx
40519: 02/03/08: Petter Gustad: Re: exceeding 2GB limits in xilinx
40529: 02/03/08: Ray Andraka: Re: exceeding 2GB limits in xilinx
40532: 02/03/08: B. Joshua Rosen: Re: exceeding 2GB limits in xilinx
40533: 02/03/09: bob elkind: Re: exceeding 2GB limits in xilinx
40542: 02/03/09: Petter Gustad: Re: exceeding 2GB limits in xilinx
40544: 02/03/09: B. Joshua Rosen: Re: exceeding 2GB limits in xilinx
40552: 02/03/09: Petter Gustad: Re: exceeding 2GB limits in xilinx
40557: 02/03/10: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40574: 02/03/11: Erwin Rol: Re: exceeding 2GB limits in xilinx
40586: 02/03/11: Petter Gustad: Re: exceeding 2GB limits in xilinx
40639: 02/03/12: Erwin Rol: Re: exceeding 2GB limits in xilinx
40662: 02/03/12: Duane Clark: Re: exceeding 2GB limits in xilinx
40666: 02/03/12: Petter Gustad: Re: exceeding 2GB limits in xilinx
40787: 02/03/15: Peter Dudley: Re: exceeding 2GB limits in xilinx
40526: 02/03/08: glen herrmannsfeldt: Re: exceeding 2GB limits in xilinx
40386: 02/03/06: Johann Glaser: Re: exceeding 2GB limits in xilinx
40391: 02/03/06: Ray Andraka: Re: exceeding 2GB limits in xilinx
40406: 02/03/06: Rick Filipkiewicz: Re: exceeding 2GB limits in xilinx
40438: 02/03/07: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40428: 02/03/07: Allan Herriman: Re: exceeding 2GB limits in xilinx
40429: 02/03/07: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40450: 02/03/07: Tim: Re: exceeding 2GB limits in xilinx
40497: 02/03/08: Allan Herriman: Re: exceeding 2GB limits in xilinx
40541: 02/03/09: Rick Filipkiewicz: Re: exceeding 2GB limits in xilinx
40546: 02/03/09: Ray Andraka: Re: exceeding 2GB limits in xilinx
40640: 02/03/12: Allan Herriman: Re: exceeding 2GB limits in xilinx
40652: 02/03/12: Ray Andraka: Re: exceeding 2GB limits in xilinx
40436: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40523: 02/03/08: Jay: Re: exceeding 2GB limits in xilinx
40374: 02/03/06: Alan Fitch: Re: exceeding 2GB limits in xilinx
40392: 02/03/06: Petter Gustad: Re: exceeding 2GB limits in xilinx
40320: 02/03/05: Guy Eschemann: digital video PLL
40327: 02/03/05: Jay: Re: digital video PLL
40328: 02/03/05: Falk Brunner: Re: digital video PLL
40343: 02/03/05: Guy Eschemann: Re: digital video PLL
40345: 02/03/06: Jim Granville: Re: digital video PLL
40347: 02/03/05: Austin Lesea: Re: digital video PLL
40349: 02/03/05: John_H: Re: digital video PLL
40350: 02/03/05: Austin Lesea: Re: digital video PLL
40331: 02/03/05: Austin Lesea: Re: digital video PLL
40336: 02/03/05: John_H: Re: digital video PLL
40717: 02/03/13: Frank Vorstenbosch: Re: digital video PLL
40718: 02/03/13: John_H: Re: digital video PLL
40719: 02/03/13: Frank Vorstenbosch: Re: digital video PLL
40724: 02/03/14: John_H: Re: digital video PLL
40563: 02/03/10: Christopher Holmes: Re: digital video PLL
40338: 02/03/05: VhdlCohen: From Verif. Guild: Challenging the need for HVLs
40346: 02/03/05: Jan Gray: Xilinx announces Virtex-II Pro is shipping
40366: 02/03/06: rickman: Re: Xilinx announces Virtex-II Pro is shipping
40367: 02/03/06: Nicholas Weaver: Re: Xilinx announces Virtex-II Pro is shipping
40377: 02/03/06: Rick Filipkiewicz: Re: Xilinx announces Virtex-II Pro is shipping
40396: 02/03/06: Austin Lesea: Re: Xilinx announces Virtex-II Pro is shipping
40393: 02/03/06: Ray Andraka: Re: Xilinx announces Virtex-II Pro is shipping
40348: 02/03/05: Kevin Brace: Quartus II 2.0 fast fit option
40358: 02/03/06: Peter Ormsby: Re: Quartus II 2.0 fast fit option
40362: 02/03/05: Kevin Brace: Re: Quartus II 2.0 fast fit option
40378: 02/03/06: Nial Stewart: Re: Quartus II 2.0 fast fit option
40479: 02/03/07: Kevin Brace: Re: Quartus II 2.0 fast fit option
40483: 02/03/07: Ray Andraka: Re: Quartus II 2.0 fast fit option
40509: 02/03/08: Nial Stewart: Re: Quartus II 2.0 fast fit option
40422: 02/03/07: Russell Shaw: Re: Quartus II 2.0 fast fit option
40480: 02/03/07: Kevin Brace: Re: Quartus II 2.0 fast fit option
40495: 02/03/08: Russell Shaw: Re: Quartus II 2.0 fast fit option
40427: 02/03/07: Terry: Re: Quartus II 2.0 fast fit option
40473: 02/03/07: bob elkind: Re: Quartus II 2.0 fast fit option
40355: 02/03/05: Guillaume: FPGA exp with "timing constraint export"
40359: 02/03/05: Michol: Re: FPGA exp with "timing constraint export"
40356: 02/03/05: Steven Nowick: 2nd Call for Papers: IWLS-02 - IEEE/ACM Int. Wkshp. on Logic &
40360: 02/03/05: ssy: possible problem of asyn read of block ram in apex 20k device
40363: 02/03/05: duy: Block Ram
40395: 02/03/06: Matthias Scheerer: Re: Block Ram
40846: 02/03/16: Edwin Bland: Re: Block Ram
40407: 02/03/06: Peter Alfke: Re: FPGA wich supports LVDS
40580: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40581: 02/03/11: Austin Lesea: Re: FPGA which supports LVDS
40588: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40589: 02/03/11: Peter Alfke: Re: FPGA wich supports LVDS
40595: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40597: 02/03/11: Theron Hicks: Re: FPGA wich supports LVDS
40601: 02/03/11: Austin Lesea: Re: FPGA wich supports LVDS
40617: 02/03/12: Philip Freidin: Re: FPGA wich supports LVDS
40621: 02/03/11: Austin Lesea: Re: FPGA wich supports LVDS
40602: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40371: 02/03/06: <msauer@gmx.net>: FPGA which supports LVDS
40412: 02/03/06: Tom Burgess: Re: FPGA which supports LVDS
40373: 02/03/06: g. giachella: QPRO Virtex
40408: 02/03/06: Peter Alfke: Re: QPRO Virtex
40415: 02/03/06: Kevin Brace: Re: QPRO Virtex
40375: 02/03/06: F. Modderkolk: FPGA or DSP
40379: 02/03/06: Allan Herriman: Re: FPGA or DSP
40389: 02/03/06: Ray Andraka: Re: FPGA or DSP
40381: 02/03/06: F. Modderkolk: FPGA or DSP in a power supply?
40383: 02/03/06: Paul: Re: FPGA or DSP in a power supply?
40394: 02/03/06: F. Modderkolk: Re: FPGA or DSP in a power supply?
40409: 02/03/06: Peter Alfke: Re: FPGA or DSP in a power supply?
40413: 02/03/07: Jim Granville: Re: FPGA or DSP in a power supply?
40521: 02/03/08: Santiago de Pablo: Re: FPGA or DSP in a power supply?
40388: 02/03/06: Allan Herriman: Re: FPGA or DSP in a power supply?
40390: 02/03/06: Ray Andraka: Re: FPGA or DSP in a power supply?
40433: 02/03/07: F. Modderkolk: Re: FPGA or DSP in a power supply?
40437: 02/03/07: Jim Granville: Re: FPGA or DSP in a power supply?
40446: 02/03/07: Ray Andraka: Re: FPGA or DSP in a power supply?
40510: 02/03/08: F. Modderkolk: Re: FPGA or DSP in a power supply?
40511: 02/03/08: Paul: Re: FPGA or DSP in a power supply?
40512: 02/03/08: Ray Andraka: Re: FPGA or DSP in a power supply?
40514: 02/03/08: Peter Alfke: Re: FPGA or DSP in a power supply?
40515: 02/03/08: Ray Andraka: Re: FPGA or DSP in a power supply?
40452: 02/03/07: Peter Alfke: Re: FPGA or DSP in a power supply?
40520: 02/03/08: F. Modderkolk: Re: FPGA or DSP in a power supply?
40525: 02/03/08: Peter Alfke: Re: FPGA or DSP in a power supply?
40576: 02/03/11: F. Modderkolk: Re: FPGA or DSP in a power supply?
40382: 02/03/06: Martin Thompson: V-II DCM options
40397: 02/03/06: Austin Lesea: Re: V-II DCM options
40401: 02/03/06: Martin Thompson: Re: V-II DCM options
40472: 02/03/07: Jay: Re: V-II DCM options
40387: 02/03/06: Roberto Capobianco: Fast transmission
40418: 02/03/06: Peter Alfke: Re: Fast transmission
40447: 02/03/07: Roberto Capobianco: Re: Fast transmission
40470: 02/03/07: Jay: Re: Fast transmission
40398: 02/03/06: Kenny: MXE 5.5e speed
40419: 02/03/06: Cindy: Re: MXE 5.5e speed
40467: 02/03/07: Kamal: Re: MXE 5.5e speed
40399: 02/03/06: Kenny: How to create testbench (Verilog) easily ? Any tools ?
40417: 02/03/06: VhdlCohen: Re: How to create testbench (Verilog) easily ? Any tools ?
40402: 02/03/06: ICCAD Conference: ICCAD 2002 Call for Papers
40403: 02/03/06: Nahum Barnea: max frequency of obuf_lvdci_dv2_18
40455: 02/03/07: Austin Lesea: Re: max frequency of obuf_lvdci_dv2_18
40693: 02/03/12: Eric Smith: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40696: 02/03/12: Bob Perlman: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40709: 02/03/13: Austin Lesea: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40710: 02/03/13: Austin Lesea: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40404: 02/03/06: Chris Cowdery: Using a battery instead of Config device
40425: 02/03/07: Peter Alfke: Re: Using a battery instead of Config device
40469: 02/03/07: Jay: Re: Using a battery instead of Config device
40411: 02/03/06: Greg Neff: Mutual Clock Synchronization
40414: 02/03/06: John_H: Re: Mutual Clock Synchronization
40420: 02/03/06: Greg Neff: Re: Mutual Clock Synchronization
40421: 02/03/06: John_H: Re: Mutual Clock Synchronization
40465: 02/03/07: Greg Neff: Re: Mutual Clock Synchronization
40466: 02/03/07: John_H: Re: Mutual Clock Synchronization
40430: 02/03/07: Allan Herriman: Re: Mutual Clock Synchronization
40468: 02/03/07: Greg Neff: Re: Mutual Clock Synchronization
40475: 02/03/07: John_H: Re: Mutual Clock Synchronization
40694: 02/03/12: showbiz: Re: Mutual Clock Synchronization
40703: 02/03/13: Allan Herriman: Re: Mutual Clock Synchronization
40536: 02/03/08: bala iyer: Re: Mutual Clock Synchronization
40416: 02/03/06: Cindy: Virtex-II : Temperature Sensing Diodes
40456: 02/03/07: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40471: 02/03/07: Jay: Re: Virtex-II : Temperature Sensing Diodes
40474: 02/03/07: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40765: 02/03/14: Jon Elson: Re: Virtex-II : Temperature Sensing Diodes
40767: 02/03/14: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40423: 02/03/07: Nicholas Weaver: Announcement: Freely Available Rijndael Core for Virtex FPGAs.
40431: 02/03/06: ssy: high active and low active reset signal mixed in a design
40432: 02/03/07: Jim Granville: Re: high active and low active reset signal mixed in a design
40440: 02/03/07: ssy: Re: high active and low active reset signal mixed in a design
40445: 02/03/07: Phil Connor: Re: high active and low active reset signal mixed in a design
40449: 02/03/07: Muzaffer Kal: Re: high active and low active reset signal mixed in a design
40505: 02/03/08: ssy: Re: high active and low active reset signal mixed in a design
40543: 02/03/09: Rick Filipkiewicz: Re: high active and low active reset signal mixed in a design
40623: 02/03/11: Jay: Re: high active and low active reset signal mixed in a design
40697: 02/03/13: H.L: Re: high active and low active reset signal mixed in a design
40764: 02/03/14: Jon Elson: Re: high active and low active reset signal mixed in a design
40434: 02/03/07: sdfg: pipeline
40439: 02/03/07: MegaPowerStar: DPRAM implementation in altera
40558: 02/03/10: giga_super_man: Re: DPRAM implementation in altera
40673: 02/03/12: arpit.desai: Re: DPRAM implementation in altera
40680: 02/03/12: Mike Treseler: Re: DPRAM implementation in altera
40441: 02/03/07: David Brown: Converting old Mach 5 project from DSL to VHDL
40490: 02/03/08: Mikeandmax: Re: Converting old Mach 5 project from DSL to VHDL
40493: 02/03/08: Jim Granville: Re: Converting old Mach 5 project from DSL to VHDL
40506: 02/03/08: David Brown: Re: Converting old Mach 5 project from DSL to VHDL
40444: 02/03/07: dano: How can I install Xilinx ISE 4.1i under Linux?
40481: 02/03/07: Andy Main: Re: How can I install Xilinx ISE 4.1i under Linux?
40488: 02/03/08: dano: Re: How can I install Xilinx ISE 4.1i under Linux?
40482: 02/03/07: newman: Re: How can I install Xilinx ISE 4.1i under Linux?
40496: 02/03/08: Peter Ormsby: Re: How can I install Xilinx ISE 4.1i under Linux?
40559: 02/03/10: Utku Ozcan: Re: How can I install Xilinx ISE 4.1i under Linux?
40763: 02/03/14: Jon Elson: Re: How can I install Xilinx ISE 4.1i under Linux?
40451: 02/03/07: Salman Sheikh: Xilinx ISE 4.1
40463: 02/03/07: Falk Brunner: Re: Xilinx ISE 4.1
40498: 02/03/07: Xilinx FAE from Insight SANKET: Re: Xilinx ISE 4.1
40491: 02/03/08: Russell Shaw: Re: Xilinx ISE 4.1
40550: 02/03/09: Utku Ozcan: Re: Xilinx ISE 4.1
40551: 02/03/09: Utku Ozcan: Re: Xilinx ISE 4.1
40453: 02/03/07: Michael Amling: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
40454: 02/03/07: Flip Flippy: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
40458: 02/03/07: Kenny: Ports disappear after generating post place and route simulation model
40464: 02/03/07: Brian Philofsky: Re: Ports disappear after generating post place and route simulation
40461: 02/03/07: Joseph H Allen: Need XC2V4000/6000-4FF1152CES
40477: 02/03/07: Zak smith: Clamping Diode in the I/O !!!
40484: 02/03/07: Jay: Re: Clamping Diode in the I/O !!!
40485: 02/03/07: Austin Lesea: Re: Clamping Diode in the I/O !!!
40489: 02/03/08: Mikeandmax: Re: Clamping Diode in the I/O !!!
40478: 02/03/07: Niv: CLKDLL in Virtex
40487: 02/03/07: Peter Alfke: Re: CLKDLL in Virtex
40486: 02/03/07: Jon Schneider: Webpack/SpartanII maplib:93 error
40499: 02/03/07: MegaPowerStar: Re: Webpack/SpartanII maplib:93 error
40502: 02/03/08: Jon Schneider: Re: Webpack/SpartanII maplib:93 error
40500: 02/03/08: Peter Waldeck: Error in Foundation 4.1i
40762: 02/03/14: Jon Elson: Re: Error in Foundation 4.1i
40501: 02/03/07: dan doberstein: GATE ARRAY PROJECT
40516: 02/03/08: John_H: Re: GATE ARRAY PROJECT
40518: 02/03/08: Peter Alfke: Re: GATE ARRAY PROJECT
40503: 02/03/07: Peter Rauschert: Xilinx 32 Point FFT for post synthesis simulation ?
40504: 02/03/08: ssy: a simulation question about apex20ke_asynch_lcell
40507: 02/03/08: Nahum Barnea: suggestion to comp.arch.fpga
40513: 02/03/08: S Ramirez: Re: suggestion to comp.arch.fpga
40517: 02/03/08: VhdlCohen: Re: suggestion to comp.arch.fpga
40508: 02/03/08: sboe: hash arithmetic
40522: 02/03/08: Ryan Henderson: Sandwich board at ESC
40527: 02/03/08: S. Ramirez: Re: Sandwich board at ESC
40531: 02/03/08: Jay: Re: Sandwich board at ESC
40584: 02/03/11: James Horn: Re: Sandwich board at ESC
40530: 02/03/09: Hristo Stevic: Logic levels
40547: 02/03/09: Hristo Stevic: Re: Logic levels
40603: 02/03/11: John_H: Re: Logic levels
40534: 02/03/08: skldfb: BlockRam
40537: 02/03/09: Peter Alfke: Re: BlockRam
40538: 02/03/08: skldfb: Re: BlockRam
40540: 02/03/09: Ray Andraka: Re: BlockRam
40539: 02/03/08: skldfb: Re: BlockRam
40545: 02/03/09: Ray Andraka: Re: BlockRam
40535: 02/03/09: Tim: Xilinx Download Cable Connectors
40549: 02/03/09: Jeff Stout: Re: Xilinx Download Cable Connectors
40561: 02/03/10: Jim Kearney: Re: Xilinx Download Cable Connectors
40600: 02/03/11: rickman: Re: Xilinx Download Cable Connectors
40609: 02/03/11: In Memory of tecNovia: Re: Xilinx Download Cable Connectors
40611: 02/03/11: Jim Kearney: Re: Xilinx Download Cable Connectors
40616: 02/03/11: Tim: Re: Xilinx Download Cable Connectors
40548: 02/03/09: Jon Schneider: Instantiating BUFGSR goes tits up
40553: 02/03/10: Flora Cathy: 32-taps FIR !
40645: 02/03/12: Alan McKitterick: Re: 32-taps FIR !
40665: 02/03/12: Jacky Renaux: Re: 32-taps FIR !
40766: 02/03/14: Philippe: Re: 32-taps FIR !
40554: 02/03/09: David Lamb: Audio project with an FPGA?
40555: 02/03/10: Loi Tran: Re: Audio project with an FPGA?
40560: 02/03/10: Joey Nelson: Re: Audio project with an FPGA?
40568: 02/03/11: Andy Main: Re: Audio project with an FPGA?
40573: 02/03/11: Wolfgang Loewer: Re: Audio project with an FPGA?
40556: 02/03/09: Anbarasu: FPGA Synthesis ...new methodology
40562: 02/03/11: Mark: How to Align 7x DDR Data Input to a XC2V6000-5?
40585: 02/03/11: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40637: 02/03/12: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40664: 02/03/12: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40698: 02/03/13: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40714: 02/03/13: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40727: 02/03/14: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40564: 02/03/11: rickman: Spartan II E output voltage characteristics
40578: 02/03/11: Peter Alfke: Re: Spartan II E output voltage characteristics
40579: 02/03/11: Austin Lesea: Re: Spartan II E output voltage characteristics
40599: 02/03/11: rickman: Re: Spartan II E output voltage characteristics
40604: 02/03/11: Austin Lesea: Re: Spartan II E output voltage characteristics
40606: 02/03/11: Peter Alfke: Re: Spartan II E output voltage characteristics
40630: 02/03/12: rickman: Re: Spartan II E output voltage characteristics
40565: 02/03/10: Antonio: First steps with clock enable constraining
40583: 02/03/11: Peter Alfke: Re: First steps with clock enable constraining
40626: 02/03/12: Paul Taylor: Re: First steps with clock enable constraining
40566: 02/03/10: Antonio: floating pins
40610: 02/03/11: lsuser: Re: floating pins
40615: 02/03/11: Tim: Re: floating pins
40628: 02/03/11: Jonas Thor: Re: floating pins
40624: 02/03/11: Jay: Re: floating pins
40636: 02/03/11: Antonio: Re: floating pins
40653: 02/03/12: Ray Andraka: Re: floating pins
40669: 02/03/12: Jay: Re: floating pins
40567: 02/03/10: Antonio: MPPR question
40658: 02/03/12: Antonio: Re: MPPR question
40569: 02/03/11: Peter Rauschert: Cannot access header information - Modelsim Error with XilinxCoreLib ?
40570: 02/03/11: AT: JTAG & CPLD
40571: 02/03/11: X. Q.: MP3 decoder.
40591: 02/03/11: Falk Brunner: Re: MP3 decoder.
40572: 02/03/11: Utku Ozcan: promgen: unused area in with different values produce same checksum
40575: 02/03/11: David Brown: Newbie choosing a language - Verilog, VHDL, or ABEL
40587: 02/03/12: Jim Granville: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40605: 02/03/11: VhdlCohen: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40590: 02/03/11: Mike Treseler: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40592: 02/03/11: Falk Brunner: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40612: 02/03/11: Jay: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40638: 02/03/12: David Brown: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40667: 02/03/12: Mike Treseler: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40759: 02/03/14: Larry McKeogh: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40761: 02/03/15: Jim Granville: Re: Newbie choosing a language - Verilog, VHDL, or ABEL/CUPL
40582: 02/03/11: Sasa Bremec: SPI interface
40593: 02/03/11: Falk Brunner: Re: SPI interface
40598: 02/03/11: Theron Hicks: Re: SPI interface
40629: 02/03/12: Prasanth Kumar: Re: SPI interface
40594: 02/03/11: Theron Hicks: spartan2e startup module not being expanded
40620: 02/03/12: Georg Acher: Re: spartan2e startup module not being expanded
40596: 02/03/11: Theron Hicks: Has anyone used the LVDS or LVPECL I/O on spartan2e?
40607: 02/03/11: xchecker: FPGA download fails
40608: 02/03/11: Mark: Re: FPGA download fails
40644: 02/03/12: Neeraj: Re: FPGA download fails
40614: 02/03/11: Tim: Re: FPGA download fails
40641: 02/03/12: David Hawke: Re: FPGA download fails
40618: 02/03/11: Austin Franklin: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40619: 02/03/12: Phil Hays: Re: Article in March Embedded Systems - "The Death of Hardware
40622: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40627: 02/03/12: S. Ramirez: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40670: 02/03/12: Kevin Neilson: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40671: 02/03/12: S. Ramirez: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40674: 02/03/12: Nicholas Weaver: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40677: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40683: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40625: 02/03/11: wiy: a guide to digital design and synthesis
40632: 02/03/12: VhdlCohen: Re: a guide to digital design and synthesis
40649: 02/03/12: skdjf: Re: a guide to digital design and synthesis
40631: 02/03/12: rickman: Mystery two wire interface, or am I being dense?
40633: 02/03/12: Keith Brafford: Re: Mystery two wire interface, or am I being dense?
40685: 02/03/13: Rick Filipkiewicz: Re: Mystery two wire interface, or am I being dense?
40687: 02/03/13: Keith Brafford: Re: Mystery two wire interface, or am I being dense?
40634: 02/03/12: Jonathan Kirwan: Re: Mystery two wire interface, or am I being dense?
40635: 02/03/12: Jim Granville: Re: Mystery two wire interface, or am I being dense?
40643: 02/03/12: Phil Connor: Re: Mystery two wire interface, or am I being dense?
40648: 02/03/12: Christopher Saunter: Re: Mystery two wire interface, or am I being dense?
40650: 02/03/12: Allan Herriman: Re: Mystery two wire interface, or am I being dense?
40686: 02/03/13: michael brown: Re: Mystery two wire interface, or am I being dense?
40689: 02/03/13: Ray Andraka: Re: Mystery two wire interface, or am I being dense?
40691: 02/03/13: michael brown: Re: Mystery two wire interface, or am I being dense?
40701: 02/03/13: Tauno Voipio: Re: Mystery two wire interface, or am I being dense?
40651: 02/03/12: Jan Martin: Re: Mystery two wire interface, or am I being dense?
40656: 02/03/12: rickman: Re: Mystery two wire interface, or am I being dense?
40661: 02/03/12: Ned Konz: Re: Mystery two wire interface, or am I being dense?
40681: 02/03/12: Mark A. Odell: Re: Mystery two wire interface, or am I being dense?
40642: 02/03/12: Leon Qin: Where can I get a Ebbok <Writting Testbench>>
40647: 02/03/12: rg: Re: RTL/Gate-Level Simulation
40654: 02/03/12: Ray Andraka: Re: RTL/Gate-Level Simulation
40655: 02/03/12: Muthu: powerpc in virtex2pro
40660: 02/03/12: Peter Alfke: Re: powerpc in virtex2pro
40800: 02/03/15: Tim: Re: powerpc in virtex2pro
41486: 02/03/29: Cyrille de Brébisson: Re: powerpc in virtex2pro
41491: 02/03/30: Peter Alfke: Re: powerpc in virtex2pro
41520: 02/04/01: Ron Huizen: Re: powerpc in virtex2pro
41525: 02/04/01: Peter Alfke: Re: powerpc in virtex2pro
41568: 02/04/02: Jan Gray: Re: powerpc in virtex2pro
41583: 02/04/02: Austin Lesea: Re: powerpc in virtex2pro
41626: 02/04/03: jerry1111: Re: powerpc in virtex2pro
41627: 02/04/04: Jim Granville: Re: powerpc in virtex2pro
41628: 02/04/03: Austin Lesea: Re: powerpc in virtex2pro
41630: 02/04/03: Peter Alfke: Re: powerpc in virtex2pro
41631: 02/04/03: Jan Gray: Re: powerpc in virtex2pro
41632: 02/04/03: B. Joshua Rosen: Re: powerpc in virtex2pro
41633: 02/04/03: John_H: Re: powerpc in virtex2pro
41645: 02/04/04: Austin Lesea: Re: powerpc in virtex2pro
41657: 02/04/04: Falk Brunner: Re: powerpc in virtex2pro
41661: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41658: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41666: 02/04/04: Austin Lesea: Re: powerpc in virtex2pro
41668: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41678: 02/04/05: Ray Andraka: Re: powerpc in virtex2pro
41663: 02/04/04: Peter Alfke: Re: powerpc in virtex2pro
41667: 02/04/04: Steve Casselman: Re: powerpc in virtex2pro
41670: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41764: 02/04/07: Jan Gray: Re: powerpc in virtex2pro
41805: 02/04/08: Steve Casselman: Re: powerpc in virtex2pro
41675: 02/04/04: Kevin Brace: Re: powerpc in virtex2pro
41676: 02/04/04: Peter Alfke: Re: powerpc in virtex2pro
41655: 02/04/04: Falk Brunner: Re: powerpc in virtex2pro
41547: 02/04/01: Alan Calac: Re: powerpc in virtex2pro
41654: 02/04/04: Lasse Langwadt Christensen: Re: powerpc in virtex2pro
41659: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41662: 02/04/04: Ken McElvain: Re: powerpc in virtex2pro
41496: 02/03/30: Keith R. Williams: Re: powerpc in virtex2pro
41535: 02/04/01: Rick Filipkiewicz: Re: powerpc in virtex2pro
41544: 02/04/02: Ray Andraka: Re: powerpc in virtex2pro
41554: 02/04/01: Keith R. Williams: Re: powerpc in virtex2pro
41498: 02/03/30: Kevin Brace: Re: powerpc in virtex2pro
41519: 02/04/01: Utku Ozcan: Re: powerpc in virtex2pro
40657: 02/03/12: Diping: Pins levels on Spartan.
40663: 02/03/12: John_H: Re: Pins levels on Spartan.
40659: 02/03/12: Timmestein: nOOb: wants to start using an fpga
40668: 02/03/12: Jay: Re: nOOb: wants to start using an fpga
40723: 02/03/13: Kevin Brace: Re: nOOb: wants to start using an fpga
40672: 02/03/12: drake: cyphers
40675: 02/03/12: Vikram Pasham: Re: cyphers
40676: 02/03/12: Andy Main: Re: cyphers
40678: 02/03/12: Nicholas Weaver: Re: cyphers
41438: 02/03/29: Wesley J. Landaker: Re: cyphers
40679: 02/03/12: Prashant: Timing Simulations
40682: 02/03/12: Mike Treseler: Re: Timing Simulations
40684: 02/03/12: Kevin Brace: How do I infer a carry-chain parity generator in XST?
40688: 02/03/13: Ray Andraka: Re: How do I infer a carry-chain parity generator in XST?
40692: 02/03/12: Kevin Brace: Re: How do I infer a carry-chain parity generator in XST?
40713: 02/03/13: John_H: Re: How do I infer a carry-chain parity generator in XST?
40690: 02/03/13: Kelvin Hsu: How would I know somebody has copied my files in Unix?
40702: 02/03/13: Timmestein: Re: How would I know somebody has copied my files in Unix?
40738: 02/03/14: e.i.chester: Re: How would I know somebody has copied my files in Unix?
40695: 02/03/13: Kelvin Hsu: How can I program into the EEPROM?
40699: 02/03/13: Zak smith: Pointer Processor for OC192
40707: 02/03/13: <hamish@cloud.net.au>: Re: Pointer Processor for OC192
40700: 02/03/13: Zak smith: Any data about SFI 4 interface ?
40704: 02/03/13: Michael Boehnel: Single-event upsets in ROM
40705: 02/03/13: Saurabh Pal: DES implementation in Handel C
40776: 02/03/15: John: Re: DES implementation in Handel C
40706: 02/03/13: sfjg: EDA tools(from front to end)
40708: 02/03/13: Arash Salarian: Synthesis tools comparison?
40722: 02/03/13: S. Ramirez: Re: Synthesis tools comparison?
40735: 02/03/14: Arash Salarian: Re: Synthesis tools comparison?
40739: 02/03/14: Mike Treseler: Re: Synthesis tools comparison?
40753: 02/03/14: Jay: Re: Synthesis tools comparison?
40736: 02/03/14: Tim: Re: Synthesis tools comparison?
40746: 02/03/14: S. Ramirez: Re: Synthesis tools comparison?
40711: 02/03/13: Prashant: IP cores availability
40712: 02/03/13: Nahum Barnea: minimum value for clock to output
40771: 02/03/15: Rick Filipkiewicz: Re: minimum value for clock to output
40866: 02/03/17: Nahum Barnea: Re: minimum value for clock to output
40868: 02/03/17: Rick Filipkiewicz: Re: minimum value for clock to output
40986: 02/03/19: Nahum Barnea: Re: minimum value for clock to output
40715: 02/03/13: Dionissis Efstathiou: Universal FPGA Programmer
40716: 02/03/13: Falk Brunner: Re: Universal FPGA Programmer
40799: 02/03/15: Tim: Re: Universal FPGA Programmer
40720: 02/03/13: Kevin Brace: Is XST's Keep Hierarchy option broken?
40721: 02/03/13: Kevin Brace: XST duplicates unnecessary IOB OE FFs
40743: 02/03/14: Brian Drummond: Re: XST duplicates unnecessary IOB OE FFs
40760: 02/03/14: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40836: 02/03/16: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
40849: 02/03/16: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40870: 02/03/17: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
40964: 02/03/19: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
41340: 02/03/26: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
41423: 02/03/27: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40725: 02/03/13: Sniper Daryl: the server to access to this newgroup
40775: 02/03/15: Topo Gigio: Re: the server to access to this newgroup
41048: 02/03/20: piaoliuren: Re: the server to access to this newgroup
40726: 02/03/14: Martin Sauer: Difference between Virtex-II(E) und Virtex-E
40741: 02/03/14: Austin Lesea: Re: Difference between Virtex-II(E) und Virtex-E
40749: 02/03/14: Falk Brunner: Re: Difference between Virtex-II(E) und Virtex-E
40769: 02/03/14: Pete Fraser: Re: Difference between Virtex-II(E) und Virtex-E
40786: 02/03/15: Austin Lesea: 18X18, oh the possibilities!
40831: 02/03/16: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E
40833: 02/03/16: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E, correction
40856: 02/03/17: Ray Andraka: Re: Difference between Virtex-II(E) und Virtex-E
40754: 02/03/14: Jay: Re: Difference between Virtex-II(E) und Virtex-E
40900: 02/03/18: Pete Dudley: Re: Difference between Virtex-II(E) und Virtex-E
40902: 02/03/17: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E
40904: 02/03/18: rickman: Re: Difference between Virtex-II(E) und Virtex-E
40933: 02/03/18: Jason Daughenbaugh: Re: Difference between Virtex-II(E) und Virtex-E
40728: 02/03/14: H.L: Virtex BUFGDLL
40750: 02/03/14: Falk Brunner: Re: Virtex BUFGDLL
40778: 02/03/15: H.L: Re: Virtex BUFGDLL
40729: 02/03/13: Markus Meng: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40751: 02/03/14: Falk Brunner: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40827: 02/03/16: Markus Meng: Why do I want to do this ??
40832: 02/03/16: Hal Murray: Re: Why do I want to do this ??
40839: 02/03/16: Falk Brunner: Re: Why do I want to do this ??
40772: 02/03/15: Rick Filipkiewicz: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40777: 02/03/15: Georg Acher: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40779: 02/03/15: rickman: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40782: 02/03/15: Georg Acher: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40794: 02/03/15: Falk Brunner: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40829: 02/03/16: Markus Meng: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40730: 02/03/14: haim moshe: XILINX XC2V6000
40731: 02/03/14: Nahum Barnea: use virtex2 DCM as delay line
40742: 02/03/14: Austin Lesea: Re: use virtex2 DCM as delay line
40755: 02/03/14: Manfred Kraus: Re: use virtex2 DCM as delay line
40732: 02/03/14: Martin Sauer: Xilinix FPGA width 5V IO
40752: 02/03/14: Falk Brunner: Re: Xilinix FPGA width 5V IO
40756: 02/03/14: Manfred Kraus: Re: Xilinix FPGA width 5V IO
40758: 02/03/14: Falk Brunner: Re: Xilinix FPGA width 5V IO
40773: 02/03/15: Rick Filipkiewicz: Re: Xilinix FPGA width 5V IO
40784: 02/03/15: Austin Lesea: Re: Xilinix FPGA with 5V IO
40792: 02/03/15: Falk Brunner: Re: Xilinix FPGA with 5V IO
40808: 02/03/15: rickman: Re: Xilinix FPGA with 5V IO
40811: 02/03/15: Austin Lesea: Re: Xilinix FPGA with 5V IO
40733: 02/03/14: RSM: Where can I get the information on implementing CPU with FPGA?
40734: 02/03/14: Christian Plessl: Re: Where can I get the information on implementing CPU with FPGA?
40737: 02/03/14: Josh Pfrimmer: where to start with constraining..
40744: 02/03/14: Ray Andraka: Re: where to start with constraining..
40768: 02/03/14: Josh Pfrimmer: Re: where to start with constraining..
40774: 02/03/15: Rick Filipkiewicz: Re: where to start with constraining..
40789: 02/03/15: Magnus Homann: Re: where to start with constraining..
40797: 02/03/15: Jay: Re: where to start with constraining..
40740: 02/03/14: Nitin Chandrachoodan: Proto boards for labs
40745: 02/03/14: Christopher Saunter: Re: Proto boards for labs
40747: 02/03/14: Noddy: Re: Proto boards for labs
40757: 02/03/14: Manfred Kraus: Re: Proto boards for labs
40770: 02/03/14: Jason Moore: Re: Proto boards for labs
41013: 02/03/19: Nitin Chandrachoodan: Re: Proto boards for labs
40785: 02/03/15: Wolfgang Loewer: Re: Proto boards for labs
40830: 02/03/16: Hal Murray: Re: Proto boards for labs
41011: 02/03/19: Nitin Chandrachoodan: Re: Proto boards for labs
40748: 02/03/14: Tom: WTB: Coolrunner
40780: 02/03/15: Stefanos: VHDL:Problem with depuncturing unit
40781: 02/03/15: Stefanos: Re: VHDL:Problem with depuncturing unit
40783: 02/03/15: Dan: PCI design in a Spartan II which crashes in some wintel PCs
40793: 02/03/15: Eric Crabill: Re: PCI design in a Spartan II which crashes in some wintel PCs
40814: 02/03/15: Yury: Re: PCI design in a Spartan II which crashes in some wintel PCs
40818: 02/03/15: Dan: To Yury's post
40795: 02/03/15: Falk Brunner: Re: PCI design in a Spartan II which crashes in some wintel PCs
40807: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40820: 02/03/15: Dan: Reply to Kevin
40823: 02/03/16: Hal Murray: Re: Reply to Kevin
40855: 02/03/16: Kevin Brace: Re: Reply to Kevin
40817: 02/03/15: Dan: To Falk Brunner
40853: 02/03/16: Ray Andraka: Re: To Falk Brunner
40858: 02/03/16: Kevin Brace: Re: To Falk Brunner
40873: 02/03/17: Magnus Homann: Re: To Falk Brunner
40803: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40815: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40879: 02/03/17: ikauranen: Re: PCI design in a Spartan II which crashes in some wintel PCs
40788: 02/03/15: rickman: High speed clock routing
40790: 02/03/15: Magnus Homann: Re: High speed clock routing
40791: 02/03/15: rickman: Re: High speed clock routing
40802: 02/03/15: Magnus Homann: Re: High speed clock routing
40805: 02/03/16: Falk Brunner: Re: High speed clock routing
40834: 02/03/16: Magnus Homann: Re: High speed clock routing
40841: 02/03/16: Leon Heller: Re: High speed clock routing
40796: 02/03/15: Falk Brunner: Re: High speed clock routing
40810: 02/03/15: Austin Lesea: Re: High speed clock routing
40835: 02/03/16: Magnus Homann: Re: High speed clock routing
40837: 02/03/16: Falk Brunner: Re: High speed clock routing
40798: 02/03/15: rickman: Re: High speed clock routing
40801: 02/03/15: John_H: Re: High speed clock routing
40806: 02/03/15: rickman: Re: High speed clock routing
40809: 02/03/15: Austin Lesea: Re: High speed clock routing
40958: 02/03/19: rickman: Re: High speed clock routing
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