Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Nov 2001
36181: 01/11/01: Rick Filipkiewicz: XC18V04 serial EEPROM problem - 5V tolerance ?
36183: 01/11/01: digari: Altera Local Routing
36210: 01/11/02: Ray Andraka: Re: Altera Local Routing
36212: 01/11/02: Steve Fair: Re: Altera Local Routing
36229: 01/11/02: Ray Andraka: Re: Altera Local Routing
36255: 01/11/03: nitin: Re: Altera Local Routing
36324: 01/11/06: nitin: Re: Altera Local Routing
36184: 01/11/01: nitin: Registered as well as unregistered outputs?
36211: 01/11/02: Ray Andraka: Re: Registered as well as unregistered outputs?
36254: 01/11/03: nitin: Re: Registered as well as unregistered outputs?
36287: 01/11/05: Ray Andraka: Re: Registered as well as unregistered outputs?
36325: 01/11/06: digari: Re: Registered as well as unregistered outputs?
36187: 01/11/01: George Constantinides: Xilinx multiplier core - problem
36189: 01/11/01: George Constantinides: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
36198: 01/11/01: Dave Vanden Bout: Re: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
36190: 01/11/01: Jason T. Wright: Synplicity, Xilinx, & unwanted BUFGs
36196: 01/11/01: Alan Nishioka: Re: Synplicity, Xilinx, & unwanted BUFGs
36220: 01/11/02: Don Husby: Re: Synplicity, Xilinx, & unwanted BUFGs
36197: 01/11/01: Kevin Neilson: Re: Synplicity, Xilinx, & unwanted BUFGs
36208: 01/11/02: Michael Boehnel: Re: Synplicity, Xilinx, & unwanted BUFGs
36256: 01/11/03: Assaf Sarfati: Re: Synplicity, Xilinx, & unwanted BUFGs
36354: 01/11/07: <hamish@cloud.net.au>: Re: Synplicity, Xilinx, & unwanted BUFGs
36382: 01/11/07: Assaf Sarfati: Re: Synplicity, Xilinx, & unwanted BUFGs
36526: 01/11/11: <hamish@cloud.net.au>: Re: Synplicity, Xilinx, & unwanted BUFGs
36194: 01/11/01: Peter: Help with a 1996 XC3064 design!!
36201: 01/11/01: Falk Brunner: Re: Help with a 1996 XC3064 design!!
36204: 01/11/01: Peter Alfke: Re: Help with a 1996 XC3064 design!!
36266: 01/11/04: Peter: Re: Help with a 1996 XC3064 design!!
36269: 01/11/04: Peter Alfke: Re: Help with a 1996 XC3064 design!!
36205: 01/11/02: Peter Alfke: Re: Help with a 1996 XC3064 design!!
36202: 01/11/01: Pedro Alexandre: XC6000
36206: 01/11/02: Peter Alfke: Re: XC6000
36232: 01/11/02: glen herrmannsfeldt: Re: XC6000
36242: 01/11/03: Rick Filipkiewicz: Re: XC6000
36213: 01/11/02: Ray Andraka: Re: XC6000
36235: 01/11/02: Jim: Re: XC6000
36223: 01/11/02: Patrick Maheral: Open configuration bitstreams
36224: 01/11/02: Nicholas Weaver: Re: Open configuration bitstreams
36225: 01/11/02: Kevin Neilson: Re: Open configuration bitstreams
36226: 01/11/02: Austin Lesea: Re: Open configuration bitstreams
36227: 01/11/02: Kevin Neilson: Re: Open configuration bitstreams
36231: 01/11/02: Alex Rast: 64-bit PCI core for Lattice CPLD?
36233: 01/11/02: Speedy Zero Two: Re: 64-bit PCI core for Lattice CPLD?
36251: 01/11/03: Kevin Brace: Re: 64-bit PCI core for Lattice CPLD?
36339: 01/11/07: Alex Rast: Re: 64-bit PCI core for Lattice CPLD?
36259: 01/11/04: Philipp Krause: Re: 64-bit PCI core for Lattice CPLD?
36509: 01/11/10: clevin1234: Re: 64-bit PCI core for Lattice CPLD?
36234: 01/11/02: J. Reed Walker: JTAG problem
36236: 01/11/02: Jim: Re: JTAG problem
36281: 01/11/05: Jan Coombs: Re: JTAG problem
36238: 01/11/02: ikauranen: Implementing NIOS softcore in ACEX
36241: 01/11/03: C.Schlehaus: Re: Implementing NIOS softcore in ACEX
36248: 01/11/03: Peter Ormsby: Re: Implementing NIOS softcore in ACEX
36249: 01/11/03: C.Schlehaus: Re: Implementing NIOS softcore in ACEX
36240: 01/11/02: Tim Boescke: spartan synthesis with synopsis
36252: 01/11/03: newman: Re: spartan synthesis with synopsis
36253: 01/11/04: Peter Alfke: Re: spartan synthesis with synopsis
36291: 01/11/05: Brian Philofsky: Re: spartan synthesis with synopsis
36312: 01/11/06: Ray Andraka: Re: spartan synthesis with synopsis
36262: 01/11/04: Ray Andraka: Re: spartan synthesis with synopsis
36282: 01/11/05: newman: Re: spartan synthesis with synopsis
36247: 01/11/03: <bazaillion@yahoo.com>: How dense are FPGA/CPLD's
36267: 01/11/04: Rene Tschaggelar: Re: How dense are FPGA/CPLD's
36271: 01/11/04: Kevin Brace: Re: How dense are FPGA/CPLD's
36297: 01/11/05: Neil Franklin: Re: How dense are FPGA/CPLD's
36365: 01/11/07: Rene Tschaggelar: Re: How dense are FPGA/CPLD's
36377: 01/11/07: Kevin Brace: Re: How dense are FPGA/CPLD's
36399: 01/11/08: Russell Shaw: Re: How dense are FPGA/CPLD's
36412: 01/11/08: Ray Andraka: Re: How dense are FPGA/CPLD's
36415: 01/11/08: Peter Alfke: Re: How dense are FPGA/CPLD's
36439: 01/11/09: Russell Shaw: Re: How dense are FPGA/CPLD's
36442: 01/11/08: Peter Alfke: Re: How dense are FPGA/CPLD's
36257: 01/11/04: Leon Heller: Altera download problem
36258: 01/11/04: Kevin Brace: Re: Altera download problem
36336: 01/11/06: Leon Heller: Re: Altera download problem
36260: 01/11/04: Bigboss: Help on which FPGA development boards ?
36261: 01/11/04: ikauranen: A problem configuring APEX device
36298: 01/11/05: ikauranen: Re: A problem configuring APEX device
36263: 01/11/04: rickman: JBITS and modular FPGA configuration
36265: 01/11/04: Neil Franklin: Re: JBITS and modular FPGA configuration
36270: 01/11/05: <khtsoi@pc90026.cse.cuhk.edu.hk>: speed of adder in XC1000E-6
36313: 01/11/06: Ray Andraka: Re: speed of adder in XC1000E-6
36315: 01/11/06: <khtsoi@cse.cuhk.edu.hk>: Re: speed of adder in XC1000E-6
36330: 01/11/06: Ray Andraka: Re: speed of adder in XC1000E-6
36272: 01/11/04: Banana: Synplyfy to Xilinx pipe
36283: 01/11/05: Michael Boehnel: Re: Synplyfy to Xilinx pipe
36274: 01/11/04: Kevin Brace: Xilinx Floorplanner Effectiveness
36307: 01/11/06: Ray Andraka: Re: Xilinx Floorplanner Effectiveness
36316: 01/11/06: Rick Filipkiewicz: Re: Xilinx Floorplanner Effectiveness
36337: 01/11/06: Kevin Brace: Re: Xilinx Floorplanner Effectiveness
36333: 01/11/06: Kevin Neilson: Re: Xilinx Floorplanner Effectiveness
36340: 01/11/06: Kevin Brace: Re: Xilinx Floorplanner Effectiveness
36275: 01/11/04: Kevin Brace: Is There a Xilinx Floorplanner Tutorial?
36276: 01/11/05: Banana: Aldec question
36277: 01/11/05: wojtek: Re: Aldec question
36280: 01/11/05: Nick Mckay: Re : Xilinx multiplier core - problem
36284: 01/11/05: Adam Elbirt: Help with Synplify Warning
36292: 01/11/05: Andy Peters: Re: Help with Synplify Warning
36294: 01/11/05: Adam Elbirt: Re: Help with Synplify Warning
36286: 01/11/05: Banana: count and divide Idea needed
36305: 01/11/05: ikauranen: Re: count and divide Idea needed
36311: 01/11/06: Ray Andraka: Re: count and divide Idea needed
36390: 01/11/07: Banana: Re: count and divide Idea needed
36413: 01/11/08: Ray Andraka: Re: count and divide Idea needed
36288: 01/11/05: rickman: Virtex II introduction schedule
36296: 01/11/05: Rick Filipkiewicz: Re: Virtex II introduction schedule
36364: 01/11/07: Andreas Kugel: Re: Virtex II introduction schedule
36290: 01/11/05: Dave Brown: Xilinx ISE false timing errors?
36295: 01/11/05: Bob Perlman: Re: Xilinx ISE false timing errors?
36524: 01/11/11: Philip Freidin: Re: Xilinx ISE false timing errors?
36299: 01/11/05: Pete Fraser: Heatsink for Xilinx FF896 package?
36306: 01/11/06: Ray Andraka: Re: Heatsink for Xilinx FF896 package?
36300: 01/11/05: Dan Kuechle: Xilinx DLL clock question
36301: 01/11/05: Tullio Grassi: FPGA marketplace ?
36329: 01/11/06: Ray Andraka: Re: Xilinx DLL clock question
36310: 01/11/06: dfx2001: Counter detects both edge of clock?? (verilog)
36322: 01/11/06: Rick Filipkiewicz: Re: Counter detects both edge of clock?? (verilog)
36327: 01/11/06: Rob Finch: Re: Counter detects both edge of clock?? (verilog)
36328: 01/11/06: Eric Smith: Re: Counter detects both edge of clock?? (verilog)
36472: 01/11/09: Pallek, Andrew [CAR:CN34:EXCH]: Re: Counter detects both edge of clock?? (verilog)
36480: 01/11/09: Tim Hubberstey: Re: Counter detects both edge of clock?? (verilog)
36317: 01/11/06: <khtsoi@cse.cuhk.edu.hk>: RLOC for a block
36320: 01/11/06: <khtsoi@cse.cuhk.edu.hk>: Re: RLOC for a block
36331: 01/11/06: Ray Andraka: Re: RLOC for a block
36323: 01/11/06: Rene Doesburg: External clock for Altera UP1 Board
36326: 01/11/06: Assaf Sarfati: Virtex2 gate-level simulation: SDF and timing errors
36338: 01/11/07: Allan Herriman: Re: Virtex2 gate-level simulation: SDF and timing errors
36383: 01/11/07: Assaf Sarfati: Re: Virtex2 gate-level simulation: SDF and timing errors
36404: 01/11/08: Allan Herriman: Re: Virtex2 gate-level simulation: SDF and timing errors
36416: 01/11/08: Ray Andraka: Re: Virtex2 gate-level simulation: SDF and timing errors
36525: 01/11/11: Assaf Sarfati: Re: Virtex2 gate-level simulation: SDF and timing errors
36772: 01/11/19: Andy Peters: Re: Virtex2 gate-level simulation: SDF and timing errors
36792: 01/11/19: Assaf Sarfati: Re: Virtex2 gate-level simulation: SDF and timing errors
36332: 01/11/06: Jens-Christian Lache: placement for if (vhdl)
36334: 01/11/06: Ray Andraka: Re: placement for if (vhdl)
36360: 01/11/07: Jens-Christian Lache: Re: placement for if (vhdl)
36335: 01/11/06: Rick Filipkiewicz: Re: How can I use the instance of block RAM of Spartan2 in Synplify?
36341: 01/11/07: Russell Shaw: Fifo books
36350: 01/11/07: Edwin Naroska: Re: Fifo books
36352: 01/11/07: John Moore: Re: Fifo books
36397: 01/11/08: Russell Shaw: Re: Fifo books
36449: 01/11/09: Peter Alfke: Re: Fifo books
36462: 01/11/09: Russell Shaw: Re: Fifo books
36342: 01/11/07: Scott L. Burris: FPGA suppliers for hobbyists?
36345: 01/11/07: Ray Andraka: Re: FPGA suppliers for hobbyists?
36349: 01/11/07: Uwe Bonnes: Re: FPGA suppliers for hobbyists?
36357: 01/11/07: Leon Heller: Re: FPGA suppliers for hobbyists?
36370: 01/11/07: kryten_droid: Re: FPGA suppliers for hobbyists?
36343: 01/11/07: Su We: XST synthesis
36358: 01/11/07: Kevin Brace: Re: XST synthesis
36372: 01/11/08: Russell Shaw: Re: XST synthesis
36346: 01/11/07: duola: How can I use the instance of block RAM of Spartan2 in Synplify?
36347: 01/11/07: Rob Finch: FPGA Wish list
36368: 01/11/07: Peter Alfke: Re: FPGA Wish list
36376: 01/11/07: Pete Fraser: Re: FPGA Wish list
36427: 01/11/08: Nicholas Weaver: Re: FPGA Wish list
36430: 01/11/08: Tim: Re: FPGA Wish list
36432: 01/11/08: Nicholas Weaver: Re: FPGA Wish list
36431: 01/11/08: Falk Brunner: Re: FPGA Wish list
36433: 01/11/08: Nicholas Weaver: Re: FPGA Wish list
36379: 01/11/07: Rob Finch: Re: FPGA Wish list
36411: 01/11/08: Reinoud: Re: FPGA Wish list
36447: 01/11/08: Luke Roth: Re: FPGA Wish list
36348: 01/11/07: Banana: Encoder timin question
36351: 01/11/07: Jim: Re: Encoder timin question
36353: 01/11/07: Christopher Saunter: Modifying BlockRAM contents in a bitstream?
36366: 01/11/07: Neil Franklin: Re: Modifying BlockRAM contents in a bitstream?
36373: 01/11/07: Rick Filipkiewicz: Re: Modifying BlockRAM contents in a bitstream?
36355: 01/11/07: RS: FPGA BGA and decoupling
36361: 01/11/07: Mike Treseler: Re: FPGA BGA and decoupling
36363: 01/11/07: Keith R. Williams: Re: FPGA BGA and decoupling
36367: 01/11/07: Mike Treseler: Re: FPGA BGA and decoupling
36410: 01/11/08: Keith R. Williams: Re: FPGA BGA and decoupling
36362: 01/11/07: rafael plonka: Re: FPGA BGA and decoupling
36356: 01/11/07: Jonathan Bromley: Re: How can I implement such a counter in Verilog?
36359: 01/11/07: Steven Derrien: Xpower and vcd files
36492: 01/11/09: Petter Gustad: Re: Xpower and vcd files
36527: 01/11/11: <hamish@cloud.net.au>: Re: Xpower and vcd files
36686: 01/11/15: Dennis McCrohan: Re: Xpower and vcd files
36369: 01/11/07: Petter Gustad: Xilinx machine readable package info
36371: 01/11/07: Mike Treseler: Re: Xilinx machine readable package info
36434: 01/11/08: Petter Gustad: Re: Xilinx machine readable package info
36374: 01/11/08: Rick Filipkiewicz: Re: Xilinx machine readable package info
36426: 01/11/08: Petter Gustad: Re: Xilinx machine readable package info
36385: 01/11/08: Leon Heller: Re: Xilinx machine readable package info
36437: 01/11/08: Neil Franklin: Re: Xilinx machine readable package info
36448: 01/11/09: Petter Gustad: Re: Xilinx machine readable package info
36478: 01/11/09: Falk Brunner: Re: Xilinx machine readable package info
36386: 01/11/08: Leon Heller: Re: Xilinx machine readable package info
36425: 01/11/08: Petter Gustad: Re: Xilinx machine readable package info
36454: 01/11/09: Petter Gustad: Re: Xilinx machine readable package info
36375: 01/11/07: anon7864: Quadrature Encoder Sampling Time
36378: 01/11/08: Jim Granville: Re: Quadrature Encoder Sampling Time
36408: 01/11/08: Falser Klaus: Re: Quadrature Encoder Sampling Time
36436: 01/11/08: John_H: Re: Quadrature Encoder Sampling Time
36443: 01/11/09: John_H: A Quadrature Encoder to binary counter
36534: 01/11/11: kryten_droid: Re: Quadrature Encoder Sampling Time
36539: 01/11/12: Ray Andraka: Re: Quadrature Encoder Sampling Time
36541: 01/11/11: John Handwork: Re: Quadrature Encoder Sampling Time
36542: 01/11/12: Jim Granville: Re: Quadrature Encoder Sampling Time
36547: 01/11/12: Jonathan Bromley: Re: Quadrature Encoder Sampling Time
36567: 01/11/12: Manfred Kraus: Re: Quadrature Encoder Sampling Time
36570: 01/11/12: John_H: Re: Quadrature Encoder Sampling Time
36380: 01/11/07: Marty: Question about pipelining a design
36402: 01/11/08: Russell Shaw: Re: Question about pipelining a design
36438: 01/11/09: Russell Shaw: Re: Question about pipelining a design
36587: 01/11/12: Andy Peters: Re: Question about pipelining a design
36381: 01/11/07: Jaime Andres Aranguren Cardona: "Illegal assignment" message, NEED HELP, PLEASE!!!
36396: 01/11/08: Tim Hubberstey: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36398: 01/11/08: Nicolas Matringe: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36428: 01/11/08: Jaime Andres Aranguren Cardona: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36458: 01/11/09: Nicolas Matringe: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36384: 01/11/07: jesse: QuickLogic Programmer (s) for Sale
36389: 01/11/07: duola: How can I implement such a counter in Verilog?
36391: 01/11/07: Banana: Implementation of filter with three set of coeffs
36451: 01/11/08: Banana: Re: Implementation of filter with three set of coeffs
36501: 01/11/09: Ray Andraka: Re: Implementation of filter with three set of coeffs
36502: 01/11/09: Ray Andraka: Re: Implementation of filter with three set of coeffs
36392: 01/11/07: Banana: Can I enhance this Counter 4 and Counter 6 ???
36417: 01/11/08: Falk Brunner: Re: Can I enhance this Counter 4 and Counter 6 ???
36393: 01/11/08: Kuan Zhou: Can Xilinx recognize the critical path in the design
36418: 01/11/08: Falk Brunner: Re: Can Xilinx recognize the critical path in the design
36520: 01/11/10: Kuan Zhou: Re: Can Xilinx recognize the critical path in the design
36521: 01/11/10: Jim: Re: Can Xilinx recognize the critical path in the design
36394: 01/11/08: Noddy: Bit scaling
36395: 01/11/08: wrth: about ise4.1 solaris install
36414: 01/11/08: Kamal Patel: Re: about ise4.1 solaris install
36400: 01/11/08: Andrew Gray: Hex numbers in VHDL
36403: 01/11/08: Panu H: Re: Hex numbers in VHDL
36405: 01/11/08: Alan Fitch: Re: Hex numbers in VHDL
36420: 01/11/08: Tony Benham: Re: Hex numbers in VHDL
36421: 01/11/08: Tim Hubberstey: Re: Hex numbers in VHDL
36422: 01/11/08: Tony Benham: Re: Hex numbers in VHDL
36540: 01/11/11: Chua Kah Hean: Re: Hex numbers in VHDL
36575: 01/11/12: Edwin Naroska: Re: Hex numbers in VHDL
36627: 01/11/13: David Rogoff: Re: Hex numbers in VHDL
36629: 01/11/13: Mike Treseler: Re: Hex numbers in VHDL
36528: 01/11/11: <hamish@cloud.net.au>: Re: Hex numbers in VHDL
36457: 01/11/09: Alan Fitch: Re: Hex numbers in VHDL
36459: 01/11/09: Jonathan Bromley: Re: Hex numbers in VHDL
36809: 01/11/20: Sanjay Parekh: Re: Hex numbers in VHDL
36401: 01/11/08: Andrew Gray: VHDL testbench question
36406: 01/11/08: Srinivasan Venkataramanan: Re: VHDL testbench question
36512: 01/11/10: Clyde R. Shappee: Re: VHDL testbench question
36407: 01/11/08: Francisco Camarero: ITU G.273.1 Codec in Virtex XCV400E ?
36409: 01/11/08: Andrew Gray: Maxplus error
36440: 01/11/09: Russell Shaw: Re: Maxplus error
36446: 01/11/09: Srinivasan Venkataramanan: Re: Maxplus error
36467: 01/11/09: C.Schlehaus: Re: Maxplus error
36419: 01/11/08: jakab tanko: Xilinx dedicated IO pins
36423: 01/11/08: Magnus Homann: Re: Xilinx dedicated IO pins
36429: 01/11/08: Jens-Christian Lache: Re: Xilinx dedicated IO pins
36435: 01/11/08: jakab tanko: Re: Xilinx dedicated IO pins
36461: 01/11/09: Magnus Homann: Re: Xilinx dedicated IO pins
36586: 01/11/12: Andy Peters: Re: Xilinx dedicated IO pins
36424: 01/11/08: Jon Schneider: Testing of EPX780QC132 needed
36441: 01/11/09: Dean Armstrong: Multiple levels of reset in CPLD
36585: 01/11/12: Andy Peters: Re: Multiple levels of reset in CPLD
36444: 01/11/09: Kenneth: How to set timing constraint in Xilinx VirtexII device when using DCM
36445: 01/11/09: Kenneth: Re: How to set timing constraint in Xilinx VirtexII device when using
37025: 01/11/28: Kate Meilicke: Re: How to set timing constraint in Xilinx VirtexII device when using
37113: 01/11/30: <hamish@cloud.net.au>: Re: How to set timing constraint in Xilinx VirtexII device when using DCM
36529: 01/11/11: <hamish@cloud.net.au>: Re: How to set timing constraint in Xilinx VirtexII device when using DCM
36450: 01/11/09: Emil Blaschek: reply
36452: 01/11/09: nitin: Is ALtera using segmented routing in Mecury?
36453: 01/11/09: nitin: Carry chain in Virtex II
36519: 01/11/10: Neil Franklin: Re: Carry chain in Virtex II
36550: 01/11/12: nitin: Re: Carry chain in Virtex II
36578: 01/11/12: Neil Franklin: Re: Carry chain in Virtex II
36674: 01/11/15: nitin: Re: Carry chain in Virtex II
36455: 01/11/09: <khtsoi@cse.cuhk.edu.hk>: RLOC on RAMB4_Sn_Sn
36470: 01/11/09: Kevin Neilson: Re: RLOC on RAMB4_Sn_Sn
36486: 01/11/09: Ray Andraka: Re: RLOC on RAMB4_Sn_Sn
36456: 01/11/09: Michael Boehnel: Unknown Timing Sim Warnings
36477: 01/11/09: Falk Brunner: Re: Unknown Timing Sim Warnings
36545: 01/11/12: Michael Boehnel: Re: Unknown Timing Sim Warnings
36460: 01/11/09: Nicolas Matringe: Xilinx unconnected logic
36468: 01/11/09: Austin Lesea: Re: Xilinx unconnected logic - always connected!
36479: 01/11/09: Nicolas Matringe: Re: Xilinx unconnected logic - always connected!
36487: 01/11/09: Ray Andraka: Re: Xilinx unconnected logic
36463: 01/11/09: Philippe Robert: Decoupling capacitors on Virtex II
36473: 01/11/09: rickman: Re: Decoupling capacitors on Virtex II
36481: 01/11/09: Austin Lesea: Re: Decoupling capacitors on Virtex II
36499: 01/11/09: Tim: Re: Decoupling capacitors on Virtex II
36847: 01/11/22: William L Hunter Jr: Re: Decoupling capacitors on Virtex II
36475: 01/11/09: Falk Brunner: Re: Decoupling capacitors on Virtex II
36753: 01/11/19: Ian Dedic: Re: Decoupling capacitors on Virtex II
36754: 01/11/19: rickman: Re: Decoupling capacitors on Virtex II
36766: 01/11/19: John_H: Re: Decoupling capacitors on Virtex II
36844: 01/11/22: Rick Filipkiewicz: Re: Decoupling capacitors on Virtex II
36852: 01/11/21: rickman: Re: Decoupling capacitors on Virtex II
36864: 01/11/22: Martin Thompson: Re: Decoupling capacitors on Virtex II
36879: 01/11/22: John Larkin: Re: Decoupling capacitors on Virtex II
36889: 01/11/23: Martin Thompson: Re: Decoupling capacitors on Virtex II
36898: 01/11/23: John Larkin: Re: Decoupling capacitors on Virtex II
36921: 01/11/26: Martin Thompson: Re: Decoupling capacitors on Virtex II
36858: 01/11/22: Philippe Robert: Re: Decoupling capacitors on Virtex II
36490: 01/11/09: pete dudley: Re: Decoupling capacitors on Virtex II
36503: 01/11/10: Russell Shaw: Re: Decoupling capacitors on Virtex II
36563: 01/11/12: Austin Lesea: Re: Decoupling capacitors on Virtex II
36592: 01/11/13: Russell Shaw: Re: Decoupling capacitors on Virtex II
36680: 01/11/15: Philippe Robert: Re: Decoupling capacitors on Virtex II
36681: 01/11/15: Martin Thompson: Re: Decoupling capacitors on Virtex II
36684: 01/11/15: Keith R. Williams: Re: Decoupling capacitors on Virtex II
36685: 01/11/15: Austin Lesea: Re: Decoupling capacitors on Virtex II
36738: 01/11/18: Rick Filipkiewicz: Re: Decoupling capacitors on Virtex II
36758: 01/11/19: Austin Lesea: Re: Decoupling capacitors on Virtex II
36548: 01/11/12: Martin Thompson: Re: Decoupling capacitors on Virtex II
36464: 01/11/09: Russell Shaw: Log2(x) for vhdl?
36465: 01/11/09: Allan Herriman: Re: Log2(x) for vhdl?
36466: 01/11/09: Ray Andraka: Re: Log2(x) for vhdl?
36505: 01/11/10: Russell Shaw: Re: Log2(x) for vhdl?
36507: 01/11/10: Ray Andraka: Re: Log2(x) for vhdl?
36553: 01/11/12: Ian Smith: Re: Log2(x) for vhdl?
36796: 01/11/20: Jos De Laender: Re: Log2(x) for vhdl?
36469: 01/11/09: Austin Franklin: Virtex 2 parts availability???
36488: 01/11/09: pete dudley: Re: Virtex 2 parts availability???
36489: 01/11/09: Austin Lesea: Re: Virtex 2 parts availability???
36496: 01/11/09: Austin Franklin: Re: Virtex 2 parts availability???
36497: 01/11/09: Austin Franklin: Re: Virtex 2 parts availability???
36564: 01/11/12: Austin Lesea: Re: Virtex 2 parts shipping = receiving
36571: 01/11/12: Austin Franklin: Re: Virtex 2 parts shipping = receiving
36572: 01/11/12: Jim Bittman: Re: Virtex 2 parts shipping = receiving
36588: 01/11/12: Austin Franklin: Re: Virtex 2 parts shipping = receiving
36600: 01/11/13: James C. Schwalbe: Re: Virtex 2 parts availability???
36608: 01/11/13: Petter Gustad: Re: Virtex 2 parts availability???
36617: 01/11/13: Austin Lesea: Place your orders....
36621: 01/11/13: Petter Gustad: Re: Place your orders....
36636: 01/11/13: Tim Hubberstey: Re: Place your orders....
36639: 01/11/13: Austin Lesea: Re: Place your orders....
36643: 01/11/14: Ray Andraka: Re: Place your orders....
36717: 01/11/17: <hamish@cloud.net.au>: Re: Virtex 2 parts availability???
36720: 01/11/17: Peter Alfke: Re: Virtex 2 parts availability???
36471: 01/11/09: JianYong Niu: How to convert unsigned integer into std_logic_vector in VHDL design?
36476: 01/11/09: Falk Brunner: Re: How to convert unsigned integer into std_logic_vector in VHDL design?
36491: 01/11/09: Ray Andraka: Re: How to convert unsigned integer into std_logic_vector in VHDL
36484: 01/11/09: Mike Treseler: Re: How to convert unsigned integer into std_logic_vector in VHDL
36495: 01/11/09: Juergen Otterbach: Re: How to convert unsigned integer into std_logic_vector in VHDL
36474: 01/11/09: Dave Brown: Location constraint error message?
36482: 01/11/09: Falk Brunner: Re: Location constraint error message?
36494: 01/11/09: Dave Brown: Re: Location constraint error message?
36483: 01/11/09: Samuel Bogale: ideas
36500: 01/11/09: Ray Andraka: Re: ideas
36583: 01/11/12: Andy Peters: Re: ideas
36597: 01/11/13: Ray Andraka: Re: ideas
36598: 01/11/12: rk: Re: ideas
36616: 01/11/13: John Larkin: Re: ideas
36485: 01/11/09: Seb: speed of HW JPEG implementations
36493: 01/11/09: Falk Brunner: Re: speed of HW JPEG implementations
36508: 01/11/09: Jay: Re: speed of HW JPEG implementations
36666: 01/11/15: Vincenzo Liguori: Re: speed of HW JPEG implementations
36498: 01/11/09: Tim Stewart: 18V8Z and Philips SNAP compiler
36510: 01/11/10: Jim Granville: Re: 18V8Z and Philips SNAP compiler
36504: 01/11/09: Dave Brown: XIlinx SLOW configuration option
36506: 01/11/09: Dave Brown: Re: XIlinx SLOW configuration option
36514: 01/11/10: Falk Brunner: Re: XIlinx SLOW configuration option
36511: 01/11/10: McMeikan: ZX81 production run, is there any interest?
36517: 01/11/10: Andrew Owen: Re: ZX81 production run, is there any interest?
36518: 01/11/10: Peter Alfke: Re: ZX81 production run, is there any interest?
36530: 01/11/11: Peter Liebert-Adelt: Re: ZX81 production run, is there any interest?
36535: 01/11/11: kryten_droid: Re: ZX81 production run, is there any interest?
36536: 01/11/11: Andrew Owen: Re: ZX81 production run, is there any interest?
36561: 01/11/12: Hans Summers: Re: ZX81 production run, is there any interest?
36566: 01/11/13: McMeikan: Re: ZX81 production run, is there any interest?
36579: 01/11/12: Speedy Zero Two: Re: ZX81 production run, is there any interest?
36610: 01/11/13: McMeikan: Re: ZX81 production run, is there any interest?
36641: 01/11/14: kryten_droid: Re: ZX81 production run, is there any interest?
36653: 01/11/14: McMeikan: Re: ZX81 production run, is there any interest?
36513: 01/11/10: I. Servan Uzun: mixed language synthesis with Synplify
36515: 01/11/11: Russell Shaw: Funny voltage levels
36516: 01/11/11: Russell Shaw: Re: Funny voltage levels
36557: 01/11/12: Nial Stewart: Re: Funny voltage levels
36559: 01/11/13: Russell Shaw: Re: Funny voltage levels
36569: 01/11/12: Nial Stewart: Re: Funny voltage levels
36573: 01/11/12: Peter Alfke: Re: Funny voltage levels
36593: 01/11/13: Russell Shaw: Re: Funny voltage levels
36603: 01/11/13: Nial Stewart: Re: Funny voltage levels
36522: 01/11/10: Ramnath: Reconfigrable Routers
36532: 01/11/11: Jim: Re: Reconfigrable Routers
36523: 01/11/10: Mohap: 8031 on board Xilinx XC4000XL
36531: 01/11/11: srinas: Interleaver and Reed Solomon Encoder example
36552: 01/11/12: Edwin Naroska: Re: Interleaver and Reed Solomon Encoder example
36584: 01/11/12: FredInAShed: Re: Interleaver and Reed Solomon Encoder example
36628: 01/11/13: Kevin Neilson: Re: Interleaver and Reed Solomon Encoder example
36533: 01/11/12: Russell Shaw: Type of counter
36549: 01/11/12: Alan Fitch: Re: Type of counter
36554: 01/11/12: Russell Shaw: Re: Type of counter
36562: 01/11/12: Alan Fitch: Re: Type of counter
36537: 01/11/11: Kevin Brace: What is the optimal number of fanouts?
36538: 01/11/12: Peter Alfke: Re: What is the optimal number of fanouts?
36543: 01/11/11: Banana: State of the art for my counters/dividers x3 , x4 , x6
36546: 01/11/12: #BASUKI ENDAH PRIYANTO#: Clock Divider or Multiplier ???
36568: 01/11/12: Falk Brunner: Re: Clock Divider or Multiplier ???
36718: 01/11/17: <hamish@cloud.net.au>: Re: Clock Divider or Multiplier ???
36721: 01/11/17: Peter Alfke: Re: Clock Divider or Multiplier ???
36725: 01/11/17: Falk Brunner: Re: Clock Divider or Multiplier ???
36739: 01/11/18: Rick Filipkiewicz: Re: Clock Divider or Multiplier ???
36611: 01/11/13: John Adair: Re: Clock Divider or Multiplier ???
36551: 01/11/12: Markus Fras: PLL in Altera's Apex20K
36565: 01/11/12: Austin Lesea: Re: PLL in Altera's Apex20K
36601: 01/11/13: James C. Schwalbe: Re: PLL in Altera's Apex20K
36555: 01/11/12: Russell Shaw: Incrementing counter from state-machine
36558: 01/11/12: Thomas Stanka: Re: Incrementing counter from state-machine
36589: 01/11/13: Russell Shaw: Re: Incrementing counter from state-machine
36604: 01/11/13: Srinivasan Venkataramanan: Re: Incrementing counter from state-machine
36607: 01/11/13: Thomas Stanka: Re: Incrementing counter from state-machine
36619: 01/11/13: Jerry: Re: Incrementing counter from state-machine
36645: 01/11/14: Russell Shaw: Re: Incrementing counter from state-machine
36580: 01/11/12: Andy Peters: Re: Incrementing counter from state-machine
36590: 01/11/13: Russell Shaw: Re: Incrementing counter from state-machine
36581: 01/11/12: Mike Treseler: Re: Incrementing counter from state-machine
36591: 01/11/13: Russell Shaw: Re: Incrementing counter from state-machine
36599: 01/11/13: Jim: Re: Incrementing counter from state-machine
36618: 01/11/13: Nial Stewart: Re: Incrementing counter from state-machine
36646: 01/11/14: Russell Shaw: Re: Incrementing counter from state-machine
36658: 01/11/14: Mike Treseler: Re: Incrementing counter from state-machine
36665: 01/11/15: Russell Shaw: Re: Incrementing counter from state-machine
36671: 01/11/15: Martin Thompson: Re: Incrementing counter from state-machine
36765: 01/11/19: Andy Peters: Re: Incrementing counter from state-machine
36776: 01/11/20: Russell Shaw: Re: Incrementing counter from state-machine
36808: 01/11/20: Andy Peters: Re: Incrementing counter from state-machine
36556: 01/11/12: Brian Davis: Floorplanner Package Pin View
36560: 01/11/12: JianYong Niu: fixed-point number convert
36574: 01/11/12: Jim Bittman: Xilinx s/w upgrade 4.1 problems
36620: 01/11/13: Falk Brunner: Re: Xilinx s/w upgrade 4.1 problems
36635: 01/11/13: Jim Bittman: Re: Xilinx s/w upgrade 4.1 problems
36651: 01/11/14: Rick Filipkiewicz: Re: Xilinx s/w upgrade 4.1 problems
36654: 01/11/14: Jim Bittman: Re: Xilinx s/w upgrade 4.1 problems
36667: 01/11/14: Mark: Re: Xilinx s/w upgrade 4.1 problems
36576: 01/11/12: Alex Rast: Xilinx F 2.1i files incompatible with 4.1i
36577: 01/11/12: Eduardo Augusto Bezerra: Jpeg 2000
36606: 01/11/13: Wolfgang Loewer: Re: Jpeg 2000
36582: 01/11/12: Sul Weh: CASE vs. IF statements
36594: 01/11/13: Russell Shaw: Re: CASE vs. IF statements
36596: 01/11/13: Sul Weh: Re: CASE vs. IF statements
36732: 01/11/18: Tom Verbeure: Re: CASE vs. IF statements
36595: 01/11/12: G: Timing constraints for multiple clock logic paths
36623: 01/11/13: Rick Filipkiewicz: Re: Timing constraints for multiple clock logic paths
36602: 01/11/13: Thomas Wambera: Fast Fourier Transformation - camera data
36876: 01/11/22: Jay: Re: Fast Fourier Transformation - camera data
36896: 01/11/23: Ray Andraka: Re: Fast Fourier Transformation - camera data
36605: 01/11/13: <khtsoi@cse.cuhk.edu.hk>: Synopsys+Xilinx vs Synplicity
36657: 01/11/14: Mark: Re: Synopsys+Xilinx vs Synplicity
36683: 01/11/15: Lee Weston: Re: Synopsys+Xilinx vs Synplicity
36767: 01/11/19: Andy Peters: Re: Synopsys+Xilinx vs Synplicity
36770: 01/11/19: Ray Andraka: Re: Synopsys+Xilinx vs Synplicity
36780: 01/11/19: ssy: Re: Synopsys+Xilinx vs Synplicity
36609: 01/11/13: Madhura: FPGA synthesis
36613: 01/11/13: Petter Gustad: Re: FPGA synthesis
36749: 01/11/19: Madhura: Re: FPGA synthesis
36750: 01/11/19: <khtsoi@cse.cuhk.edu.hk>: Re: FPGA synthesis
36759: 01/11/19: Madhura: Re: FPGA synthesis
36760: 01/11/19: <khtsoi@cse.cuhk.edu.hk>: Re: FPGA synthesis
36612: 01/11/13: fede: Elliptic Curves
36810: 01/11/20: Nicholas Weaver: Re: Elliptic Curves
36821: 01/11/21: Simmler Harald: Re: Elliptic Curves
36833: 01/11/21: Noel Klonsky: Re: Elliptic Curves
36614: 01/11/13: Kris Nichols: Xilinx port warnings
36615: 01/11/13: Kris Nichols: 'Timing' simulation in ModelSIM
36624: 01/11/13: Mike Treseler: Re: 'Timing' simulation in ModelSIM
36625: 01/11/13: Brian Philofsky: Re: 'Timing' simulation in ModelSIM
36631: 01/11/13: Kris Nichols: Re: 'Timing' simulation in ModelSIM
36768: 01/11/19: Andy Peters: Re: 'Timing' simulation in ModelSIM
36663: 01/11/14: Austin Franklin: Re: 'Timing' simulation in ModelSIM
36740: 01/11/18: Rick Filipkiewicz: Re: 'Timing' simulation in ModelSIM
36978: 01/11/27: Brian Philofsky: Re: 'Timing' simulation in ModelSIM
36622: 01/11/14: #BASUKI ENDAH PRIYANTO#: Clock Skew
36633: 01/11/13: Falk Brunner: Re: Clock Skew
36634: 01/11/13: Kris Nichols: Xilinx problems using constants in the input ports of entities
36637: 01/11/13: Brian Philofsky: Re: Xilinx problems using constants in the input ports of entities
36638: 01/11/13: Kris Nichols: Re: Xilinx problems using constants in the input ports of entities
36640: 01/11/13: Matt Koepnick: Displaying Verilog variables when simulating in Max+Plus II
36642: 01/11/13: Arguo: SDRAM Module vs. SDRAM
36644: 01/11/13: Keith R. Williams: Re: SDRAM Module vs. SDRAM
36669: 01/11/14: Assaf Sarfati: Re: SDRAM Module vs. SDRAM
36647: 01/11/14: mehmeto: interleaver delay question
36649: 01/11/14: Allan Herriman: Re: interleaver delay question
36677: 01/11/15: Rene Tschaggelar: Re: interleaver delay question
36679: 01/11/15: Andrew MacCormack: Re: interleaver delay question
36650: 01/11/14: John Adair: Re: interleaver delay question
36670: 01/11/15: mehmeto: Re: interleaver delay question
36659: 01/11/14: Jacky Renaux: Re: interleaver delay question
36660: 01/11/14: Kevin Neilson: Re: interleaver delay question
36648: 01/11/14: Damir Danijel Zagar: ASRC (asynchronus sample rate conversion)
36655: 01/11/14: robert bristow-johnson: Re: ASRC (asynchronus sample rate conversion)
36661: 01/11/14: Jon Harris: Re: ASRC (asynchronus sample rate conversion)
36682: 01/11/15: Brad Evans: Re: ASRC (asynchronus sample rate conversion)
36656: 01/11/14: Muzaffer Kal: Re: ASRC (asynchronus sample rate conversion)
36652: 01/11/14: David Eadie: Prototyping Board
36672: 01/11/15: Maf: Re: Prototyping Board
36708: 01/11/16: John Jakson: Re: Prototyping Board
36751: 01/11/19: John Adair: Re: Prototyping Board
36839: 01/11/21: Andy Peters: Re: Prototyping Board
36668: 01/11/14: nitin: ALTDIG & DIG ?
36673: 01/11/15: VR: High Speed PWM?
36675: 01/11/15: Rene Tschaggelar: Re: High Speed PWM?
36676: 01/11/15: Jim Granville: Re: High Speed PWM?
36678: 01/11/15: Francisco Camarero: Re: High Speed PWM?
36691: 01/11/15: Peter Alfke: Re: High Speed PWM?
36692: 01/11/15: VR: Re: High Speed PWM?
36693: 01/11/15: Peter Alfke: Re: High Speed PWM?
36701: 01/11/16: Theron Hicks: Re: High Speed PWM?
36714: 01/11/17: VR: Re: High Speed PWM?
36716: 01/11/17: Peter Alfke: Re: High Speed PWM?
36696: 01/11/15: Eric: Re: High Speed PWM?
36687: 01/11/15: Tadesa: CAM
36688: 01/11/15: Peter Alfke: Re: CAM
36699: 01/11/16: Tadesa: Re: CAM
36700: 01/11/16: Kamal Patel: Re: CAM
36709: 01/11/16: Peter Ormsby: Re: CAM
36711: 01/11/16: Samuel Bogale: Re: CAM
36689: 01/11/15: duola: How can I solve the "clock" warning of synplify.
36747: 01/11/19: phil: Re: How can I solve the "clock" warning of synplify.
36877: 01/11/22: Jay: Re: How can I solve the "clock" warning of synplify.
36690: 01/11/15: duola: Why can not I find the 2S200PQ208 in the aldec's Spartan2 familly?
36694: 01/11/16: Daniel Nilsson: jtag programming xilinx cpld
36698: 01/11/16: Jim: Re: jtag programming xilinx cpld
36823: 01/11/21: Falser Klaus: Re: jtag programming xilinx cpld
36830: 01/11/21: Alan Nishioka: Re: jtag programming xilinx cpld
36697: 01/11/16: Gunther May: Pinning in Lattice Design Expert
36702: 01/11/17: #BASUKI ENDAH PRIYANTO#: Xilinx and Multirate clock ??
36719: 01/11/17: Lasse Langwadt Christensen: Re: Xilinx and Multirate clock ??
36722: 01/11/17: Peter Alfke: Re: Xilinx and Multirate clock ??
36755: 01/11/19: rickman: Re: Xilinx and Multirate clock ??
36777: 01/11/19: Peter Alfke: Re: Xilinx and Multirate clock ??
36769: 01/11/19: Andy Peters: Re: Xilinx and Multirate clock ??
36884: 01/11/23: Lasse Langwadt Christensen: Re: Xilinx and Multirate clock ??
36703: 01/11/16: Zdravko: OrCAD footprints for CoolRunner
36707: 01/11/16: Javi Diaz: Spartan2 - 5 V tolerance question
36710: 01/11/16: Kamal Patel: Re: Spartan2 - 5 V tolerance question
36712: 01/11/16: Peter Alfke: Re: Spartan2 - 5 V tolerance question
36715: 01/11/16: dgjk: unsetenv LANG
36723: 01/11/17: BigSlamu: Webpack and gate synthesis
36724: 01/11/17: Kris Nichols: Problem sythesizing libraries in Xilinx 4.1i
36726: 01/11/17: Rob Finch: Xilinx Student edition F1.5 and Webpack compatible ?
36727: 01/11/17: apple88888: Does anybody knows where have a free(open hardware) FPGA PCI Development board whith PCB data.....?
36783: 01/11/19: ssy: Re: Does anybody knows where have a free(open hardware) FPGA PCI Development board whith PCB data.....?
36728: 01/11/17: Alex Sherstuk: Q: XILINX binary .bit file header - ?
36729: 01/11/17: Lasse Langwadt Christensen: Re: Q: XILINX binary .bit file header - ?
36730: 01/11/18: Philip Freidin: Re: Q: XILINX binary .bit file header - ?
36731: 01/11/18: <khtsoi@cse.cuhk.edu.hk>: Re: Q: XILINX binary .bit file header - ?
36733: 01/11/17: Pablo Bleyer Kocik: WebPACK 4.1 under Win95
36734: 01/11/18: Simon Gornall: Re: WebPACK 4.1 under Win95
36736: 01/11/18: Leon Heller: Re: WebPACK 4.1 under Win95
36735: 01/11/18: Mouli: fft instantiation in foundation tools
36737: 01/11/18: Austin Franklin: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36741: 01/11/18: Austin Franklin: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36794: 01/11/20: <hamish@cloud.net.au>: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36806: 01/11/20: Austin Franklin: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36742: 01/11/18: Pablo Bleyer Kocik: WebPACK 4.1 under Win95 : solved
36743: 01/11/19: Daniel Nilsson: jtag programming xilinx xc9572 cpld
36744: 01/11/19: Jim: Re: jtag programming xilinx xc9572 cpld
36745: 01/11/19: hitajian: Problems of Amplify about Modular Design
36746: 01/11/19: Jonas Weiss: Virtex-II Pin-Incompatibility
36756: 01/11/19: rickman: Re: Virtex-II Pin-Incompatibility
36748: 01/11/19: ssy: how to limit the fanout in APEX20K400E
36757: 01/11/19: daniel: Re: how to limit the fanout in APEX20K400E
36752: 01/11/20: Tony Burch: Ann: Low cost Spartan2 FPGA board
36841: 01/11/21: kryten_droid: Re: Low cost Spartan2 FPGA board
36761: 01/11/19: Seb: modelsim: free, evaluation or full !?
36781: 01/11/19: ssy: Re: modelsim: free, evaluation or full !?
36762: 01/11/19: Andrew Gray: Modelsim
36774: 01/11/20: Arthur Sharp: Re: Modelsim
36775: 01/11/20: Andrew Gray: Re: Modelsim
36779: 01/11/20: Ray Andraka: Re: Modelsim
36787: 01/11/20: Leon Heller: Re: Modelsim
36788: 01/11/20: Leon Heller: Re: Modelsim
36802: 01/11/20: Theron Hicks: Re: Modelsim
37068: 01/11/29: Ed Browne, Precision Electronic Solutions: Re: Modelsim
37110: 01/11/30: JohnM: Re: Modelsim
37121: 01/11/30: Andy Peters: Re: Modelsim
37188: 01/12/03: Santiago de Pablo: Re: Modelsim
37197: 01/12/03: Seb: Re: Modelsim
37433: 01/12/10: Asher C. Martin: Re: Modelsim
37436: 01/12/11: Russell Shaw: Re: Modelsim
37434: 01/12/10: Asher C. Martin: Re: Modelsim
36763: 01/11/19: nurit eliram: DLL cycle-to-cycle jitter
36764: 01/11/19: Austin Lesea: Re: DLL cycle-to-cycle jitter
37000: 01/11/28: <Nurit.Eliram@mailandnews.com>: Re: DLL cycle-to-cycle jitter
37005: 01/11/28: Austin Lesea: Re: DLL cycle-to-cycle jitter
37044: 01/11/29: <Nurit.Eliram@mailandnews.com>: Re: DLL cycle-to-cycle jitter
37061: 01/11/29: Austin Lesea: Re: DLL cycle-to-cycle jitter
37083: 01/11/29: Rick Filipkiewicz: Re: DLL cycle-to-cycle jitter
37087: 01/11/29: Austin Lesea: Re: DLL cycle-to-cycle jitter
36771: 01/11/19: Ray Andraka: Re: DLL cycle-to-cycle jitter
36773: 01/11/20: Jas: AHDL to VHDL
36905: 01/11/24: Alexey Borisov: Re: AHDL to VHDL
36778: 01/11/19: Jason Berringer: ISA interface
36832: 01/11/21: rickman: Re: ISA interface
36782: 01/11/19: ssy: how to imply CAM in APEX20K
36795: 01/11/20: Wolfgang Loewer: Re: how to imply CAM in APEX20K
36784: 01/11/19: ssy: what is the price of XC2V2000?
36785: 01/11/20: Tim: Re: what is the price of XC2V2000?
36786: 01/11/19: Bharathi: Synthesis in Active-VHDL
36797: 01/11/20: Edwin Naroska: Re: Synthesis in Active-VHDL
36791: 01/11/19: Antonio: Synplify use question
36803: 01/11/20: Ray Andraka: Re: Synplify use question
36824: 01/11/21: Symon: Re: Synplify use question
36793: 01/11/20: VR: Synplicity and BlockRAM?
36799: 01/11/20: Tom Dillon: Re: Synplicity and BlockRAM?
36816: 01/11/21: VR: Re: Synplicity and BlockRAM?
36822: 01/11/21: Symon: Re: Synplicity and BlockRAM?
36834: 01/11/21: VR: Re: Synplicity and BlockRAM?
36880: 01/11/22: Andrew Barnish: Re: Synplicity and BlockRAM?
36798: 01/11/20: Utku Ozcan: Altera: diff betw. MAX3000 and MAX7000?
36807: 01/11/20: Victor Schutte: Re: Altera: diff betw. MAX3000 and MAX7000?
36800: 01/11/20: Erik Lins: Foundation ISE 4.1
36829: 01/11/21: Kamal Patel: Re: Foundation ISE 4.1
36801: 01/11/20: JianYong Niu: Implementation problem with the codes generated from Xilinx System Generator
36804: 01/11/20: George: I need a Xilinx Spartan PCI Development Board
36818: 01/11/20: Kevin Brace: Re: I need a Xilinx Spartan PCI Development Board
37217: 01/12/04: sdfjsd: Re: I need a Xilinx Spartan PCI Development Board
37218: 01/12/04: Ray Andraka: Re: I need a Xilinx Spartan PCI Development Board
37273: 01/12/06: sdfjsd: Re: I need a Xilinx Spartan PCI Development Board
37312: 01/12/06: Mike Johnson: Re: I need a Xilinx Spartan PCI Development Board
37321: 01/12/07: Ray Andraka: Re: I need a Xilinx Spartan PCI Development Board
37323: 01/12/06: Kevin Brace: Re: I need a Xilinx Spartan PCI Development Board
37352: 01/12/07: Ray Andraka: Re: I need a Xilinx Spartan PCI Development Board
37365: 01/12/08: Rick Filipkiewicz: Re: I need a Xilinx Spartan PCI Development Board
37366: 01/12/08: Duane Clark: Re: I need a Xilinx Spartan PCI Development Board
37383: 01/12/08: Eric Smith: Re: I need a Xilinx Spartan PCI Development Board
37393: 01/12/09: Duane Clark: Re: I need a Xilinx Spartan PCI Development Board
37397: 01/12/09: Duane Clark: Re: I need a Xilinx Spartan PCI Development Board
37370: 01/12/08: Ray Andraka: Re: I need a Xilinx Spartan PCI Development Board
37373: 01/12/08: Duane Clark: Re: I need a Xilinx Spartan PCI Development Board
37382: 01/12/09: Ray Andraka: Re: I need a Xilinx Spartan PCI Development Board
37389: 01/12/09: Duane Clark: Re: I need a Xilinx Spartan PCI Development Board
37385: 01/12/09: Kevin Brace: Re: I need a Xilinx Spartan PCI Development Board
36805: 01/11/20: Tobias Stumber: Altera & Actel prices
36813: 01/11/21: rafael plonka: Re: Altera & Actel prices
36871: 01/11/22: Ben Popoola: Re: Altera & Actel prices
36811: 01/11/20: Theron Hicks: don't cares and X's in a case statement?
36812: 01/11/20: Peter Alfke: Re: don't cares and X's in a case statement?
37010: 01/11/28: Theron Hicks: Re: don't cares and X's in a case statement?
36815: 01/11/20: Peter Alfke: Re: don't cares and X's in a case statement?
36826: 01/11/21: <hamish@cloud.net.au>: Re: don't cares and X's in a case statement?
36831: 01/11/21: rickman: Re: don't cares and X's in a case statement?
37075: 01/11/29: Don Husby: Re: don't cares and X's in a case statement?
36814: 01/11/21: Russell Shaw: Bit-serial efficiency
36817: 01/11/21: Ray Andraka: Re: Bit-serial efficiency
36825: 01/11/21: John: XC4000EX Logiblox Clock Distribution
36827: 01/11/21: John: XC4000EX Logiblox Clock Distribution
36828: 01/11/21: Adrian: Viewing generated VHDL
36838: 01/11/21: Andy Peters: Re: Viewing generated VHDL
36854: 01/11/21: Adrian: Re: Viewing generated VHDL
36867: 01/11/22: Dave Vanden Bout: Re: Viewing generated VHDL
36868: 01/11/22: Ramnath: Re: Viewing generated VHDL
36897: 01/11/23: Nick Macias: Re: Viewing generated VHDL
36835: 01/11/21: jfh: slew rate of virtex output buffers figures
36836: 01/11/21: Austin Lesea: Re: slew rate of virtex output buffers figures
36837: 01/11/21: Magnus Homann: Re: slew rate of virtex output buffers figures
36840: 01/11/21: Speedy Zero Two: Re: slew rate of virtex output buffers figures
36843: 01/11/21: Austin Lesea: Re: slew rate of virtex output buffers figures
36845: 01/11/22: Rick Filipkiewicz: Re: slew rate of virtex output buffers figures
36850: 01/11/22: Peter Alfke: Re: slew rate of virtex output buffers figures
36878: 01/11/22: Rick Filipkiewicz: Re: slew rate of virtex output buffers figures
36926: 01/11/26: Austin Lesea: Re: slew rate of virtex output buffers figures
36875: 01/11/22: Jay: Re: slew rate of virtex output buffers figures
36842: 01/11/21: Dave Brown: read only version register usinga generic
36846: 01/11/22: Kevin Neilson: Re: read only version register usinga generic
36866: 01/11/22: Dave Brown: Re: read only version register usinga generic
36869: 01/11/22: Johnsonw10: Re: read only version register usinga generic
36848: 01/11/21: ssy: too large a 32 entry 3 read 2 write register file
36874: 01/11/22: Jay: Re: too large a 32 entry 3 read 2 write register file
36849: 01/11/21: Colin O'Flynn: PCMCIA interface and CPLD
36853: 01/11/21: Douglas: The Xilinx Practical Designer Lab Book
36855: 01/11/21: Adrian: Creating a jitter free clock
36900: 01/11/23: Speedy Zero Two: Re: Creating a jitter free clock
36949: 01/11/27: Adrian: Re: Creating a jitter free clock
37014: 01/11/28: Tom Burgess: Re: Creating a jitter free clock
37020: 01/11/28: Austin Lesea: Re: Creating a jitter free clock
36965: 01/11/27: John_H: Re: Creating a jitter free clock
36968: 01/11/27: Peter Alfke: Re: Creating a jitter free clock
36970: 01/11/27: Austin Lesea: Re: Creating a jitter free clock
36973: 01/11/28: Jim Granville: Re: Creating a jitter free clock
36974: 01/11/27: Austin Lesea: Re: Creating a jitter free clock
36980: 01/11/28: Allan Herriman: Re: Creating a jitter free clock
36981: 01/11/27: Austin Lesea: Re: Creating a jitter free clock
36984: 01/11/28: Tim: Re: Creating a jitter free clock
36985: 01/11/28: Allan Herriman: Re: Creating a jitter free clock
36987: 01/11/27: Peter Alfke: Re: Creating a jitter free clock
36969: 01/11/27: Austin Lesea: Re: Creating a jitter free clock
36997: 01/11/28: adrian: Re: Creating a jitter free clock
37011: 01/11/28: John_H: Re: Creating a jitter free clock
37021: 01/11/29: Jim Granville: Re: Creating a jitter free clock
&nbs