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Authors (R)
R A Felton:
13286: 98/11/24: Report problems
R Allen:
35670: 01/10/13: Re: Block RAMs
R Sefton:
28166: 00/12/23: spartan-II power supply sequencing problem
29811: 01/03/12: Re: Again Spartan II power
29831: 01/03/13: Re: Again Spartan II power
R! Tafas Jr:
104173: 06/06/20: Re: Google FPGA Designer beta release
R!SC:
77282: 05/01/03: problem with edk
77307: 05/01/04: LEON2 or microblaze
77889: 05/01/19: jvm on microblaze
82349: 05/04/11: xilinx virtex 4 download cable
84917: 05/06/01: problem with edk 7.1
<r-m-w@web.de>:
103236: 06/05/29: JTAG in-system programming of PROM devices
r. bansal:
1512: 95/07/06: VHDL/FPGAs/PLDs help
R. Colin Johnson:
6511: 97/05/29: Convener, where are you?
R. D. Davis:
2515: 95/12/22: Re: [q][Reverse Engineering Protection]
R. Lamberts:
9413: 98/03/11: Announcing: Open Design Circuits
R. Mark Gogolewski:
9203: 98/03/02: Re: The case for Linux and EDA
9244: 98/03/04: Re: The case for Linux and EDA
9255: 98/03/05: Re: The case for Linux and EDA
9261: 98/03/05: Re: The case for Linux and EDA
9288: 98/03/05: Re: The case for Linux and EDA
17299: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
17306: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
R. Scheuerer:
7834: 97/10/21: Save your 49c402 microcode investment
R. T. Finch:
22214: 00/05/02: new2fpga
22476: 00/05/09: Xilinx Student Edition 1.5 License.dat
22527: 00/05/11: Re: Xilinx Student Edition 1.5 License.dat
22804: 00/05/25: Verilog assignment
23009: 00/06/08: Re: Xilinx foundation Student Edition problem.
23473: 00/06/26: Re: Different ?
23501: 00/06/27: Re: Different ?
23523: 00/06/28: Re: I cant stand it any more.
24250: 00/08/01: clock quadrupling
R. T. Wurth:
5223: 97/01/31: Re: Steven K. Knapp - no such article
6546: 97/06/02: Re: New Reconfigurable Computing newsgroup?
<r.kinkead@gmail.com>:
91908: 05/11/16: Lattice XP flash memory access.....
91925: 05/11/16: Re: Lattice XP flash memory access.....
<(r.m.muench+ieee.org)>:
5660: 97/03/05: Re: What kind of functions mostly implemented using FPGAs?
R.Sriram:
36029: 01/10/26: Bi directional pin
51015: 02/12/26: Interested in FPGA design
R.W. DeHoedt:
5922: 97/03/26: Re: BIT SERIAL MULTIPLY
<ra_arce@yahoo.com>:
79968: 05/02/27: Resource (FMAPs) use when using block RAMs
Raanan:
13314: 98/11/25: Synchronous SRAM design wanted
<raarce@gmail.com>:
103017: 06/05/24: Report for routing resource usage?
Raban:
131312: 08/04/18: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
<rabbiaqamar@yahoo.com>:
129082: 08/02/13: i need ur help
129083: 08/02/13: i need fpga board with 10 Gig interface and pcie interface
RAcoops:
41830: 02/04/09: Xilinx Prototype Platforms
41836: 02/04/09: Re: Xilinx Prototype Platforms
radarman:
89514: 05/09/16: Looking for info on the V8/Arclite MicroRISC 8-bit core
90050: 05/10/03: Re: for...generate loop with generics, constants (vhdl)
96942: 06/02/13: Problem programming Altera flex 10k100 & EPC2
96985: 06/02/14: Re: Problem programming Altera flex 10k100 & EPC2
96989: 06/02/14: Re: is there a way to initialize signals to a value
98637: 06/03/13: Coregen in ISE 8.1i webpack not working quite right
98693: 06/03/14: Re: Coregen in ISE 8.1i webpack not working quite right
99035: 06/03/19: Re: Support software for XC3042
99234: 06/03/21: Re: Support software for XC3042
99352: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
100067: 06/04/02: Re: Hierarchical FSM?
100613: 06/04/13: Re: Spartan 3E Starter Kit is finally here!
100791: 06/04/18: Re: PLD610
100870: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
100871: 06/04/19: =?iso-8859-1?q?Re:_ow_to_connect_FPGA_and_=B5C?=
100872: 06/04/19: Re: C# and Spartan 3 Starter Kit
100887: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
100908: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
101011: 06/04/24: Re: Reliability CPLD/FPGA vs Microcontroller
101532: 06/05/02: Re: RESET pin on NIOS II processor
101954: 06/05/08: Re: Spartan 3e starter kit & Multimedia
101959: 06/05/08: Re: Xilinx 3s8000?
101990: 06/05/09: Re: Spartan 3e starter kit & Multimedia
102006: 06/05/09: Re: Xilinx 3s8000?
102050: 06/05/09: Re: Xilinx 3s8000?
102073: 06/05/10: Re: Xilinx 3s8000?
102670: 06/05/18: Spartan 3e sample: pack power control with M(1)?
102735: 06/05/19: Re: Spartan 3e sample: pack power control with M(1)?
102782: 06/05/20: Re: Why do the electronics manufacturers have to spam me?
102811: 06/05/21: Re: JTAG chaining of two different Xilinx Spartan 3E boards
103125: 06/05/25: Altium Livedesign eval boards - can you add a configuration prom?
103189: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103436: 06/06/01: XIlinx 7.1i ISE problem with Spartan 3e design
103443: 06/06/01: Re: XIlinx 7.1i ISE problem with Spartan 3e design
103465: 06/06/02: Problem with Xilinx ISE 7.1i core generator
103497: 06/06/04: Re: Problem with Xilinx ISE 7.1i core generator
103653: 06/06/07: Re: Anyone with Xilinx SP305-board ?
103766: 06/06/10: Re: Anyone with Xilinx SP305-board ?
104370: 06/06/26: Re: newbie wants to do VHDL on an FPGA
104604: 06/06/30: Re: How to control the uart
104605: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104617: 06/07/01: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104640: 06/07/03: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104742: 06/07/05: Re: "Large" memory array in VHDL
105017: 06/07/11: Re: Development Boards -Your chance to suggest features
105421: 06/07/22: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105466: 06/07/24: Re: Hardware book like "Code Complete"?
105480: 06/07/24: Re: Hardware book like "Code Complete"?
105728: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
106004: 06/08/04: How to implement large ROM's from binary sources?
106070: 06/08/07: Re: verilog versus vhdl
106342: 06/08/11: Re: Dio5 interface with ps2 port
106513: 06/08/14: Any interest in a v8 uRISC/Arclite clone?
106576: 06/08/15: Re: Alternative for Mentor''s HDL Designer
106688: 06/08/17: Re: Alternative for Mentor''s HDL Designer
106807: 06/08/19: Re: Speed vs Area Optimisation
106853: 06/08/21: Re: CPU design
106901: 06/08/22: Re: CPU design
106902: 06/08/22: Re: CPU design
108164: 06/09/06: Re: Qestion about the ability of synthesis
108301: 06/09/07: Re: Qestion about the ability of synthesis
108306: 06/09/07: Re: Synchronous Clocks
108309: 06/09/07: Re: Why No Process Shrink On Prior FPGA Devices ?
108393: 06/09/10: Re: Can a FPGA work like a microprocessor ?
108613: 06/09/13: Re: Spartan3E availability
108637: 06/09/14: Re: uclinux on spartan-3e starter kit
108918: 06/09/19: Re: USB programming cables
109095: 06/09/20: Re: Old vs. New FPGAs
109855: 06/10/06: Re: Spartan 3 Starter Kit I/O ports
109951: 06/10/08: Re: Antifuse, lower cost?
109979: 06/10/09: Re: Antifuse, lower cost?
110012: 06/10/09: Re: Quartus II 6.0: System clock has been set back
110089: 06/10/10: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
110116: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110166: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110167: 06/10/11: Re: Antifuse, lower cost?
110227: 06/10/12: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
111398: 06/11/02: Re: EDK software development
111461: 06/11/03: Re: digilent spartan-3 board sram timing
111493: 06/11/03: Re: reset
112319: 06/11/20: Parallax Stratix Smartpack accessories?
112342: 06/11/20: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112373: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
113001: 06/12/04: Can you configure an Altera Stratix without the nStatus line?
113005: 06/12/04: Re: Can you configure an Altera Stratix without the nStatus line?
113042: 06/12/05: Re: Can you configure an Altera Stratix without the nStatus line?
113476: 06/12/14: Re: what are your current SoC design for ?
113899: 06/12/28: Re: ChipScope - impact on design or not?
113902: 06/12/28: Re: moving from xlinx 8.1 to 8.2 or better wait ?
113937: 06/12/29: Re: ChipScope - impact on design or not?
113942: 06/12/29: Re: ChipScope - impact on design or not?
113944: 06/12/29: Re: moving from xlinx 8.1 to 8.2 or better wait ?
114678: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
115178: 07/02/01: EDK tri-state control
116041: 07/02/28: Can write, can't read with OPB_SPI 1.00e
116050: 07/02/28: Re: Can write, can't read with OPB_SPI 1.00e
117273: 07/03/27: (Xilinx) OPB watchdog timer fails to release RESET
117426: 07/03/30: Re: (Xilinx) OPB watchdog timer fails to release RESET
117501: 07/04/02: Does the XC3S250E-VQ100 exist?
117587: 07/04/04: Re: Does the XC3S250E-VQ100 exist?
118783: 07/05/03: Re: Unused Pin setting on per-pin basis
118793: 07/05/03: Re: Unused Pin setting on per-pin basis
119010: 07/05/09: Re: ML405 LCD
120700: 07/06/13: Re: custom peripheral registers
120754: 07/06/15: Re: Stolen Spartan 3E-1600 Development Board
121523: 07/07/06: Re: I need relocate my program outside bram...
121718: 07/07/11: Flex 10k100 & EPC2 redux - forgot the special ingredient?
126245: 07/11/17: Altera webpack for Linux?
126306: 07/11/19: Re: Altera webpack for Linux?
128118: 08/01/15: Re: Where has Xilnet gone?
129319: 08/02/20: Interrupt Handler page missing in from software platform settings in
130126: 08/03/15: Re: ISSI SRAM.
130981: 08/04/07: Modify POF with new ESB (ROM) content?
131063: 08/04/09: Re: Disable optimisation - Ring oscillator
Radboud Verberne:
23158: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
<raderrl@my-deja.com>:
17527: 99/08/06: Xilinx vs. Lucent vs. XX FPGA comparison
19228: 99/12/07: tool command language (TCL)
RADHIKA:
29334: 01/02/14: Re: XILINX FPGA programming through JTAG
radhika:
29305: 01/02/13: Configuration of FPGA using SPROM
29308: 01/02/13: Configuration of FPGA using SPROM
29339: 01/02/14: Re: Configuration of FPGA using SPROM
29386: 01/02/17: Re: Configuration of FPGA using SPROM
29387: 01/02/17: Re: Configuration of FPGA using SPROM
29427: 01/02/20: Re: Configuration of FPGA using SPROM
Radioman:
90837: 05/10/22: Re: MAC Architectures
RadioShox:
109839: 06/10/06: Instantiating Altera M4K block without MegaWizard
Radosalw Gasiorek:
17122: 99/07/01: 82XX INTEL
Radoslaw Gasiorek:
20827: 00/02/23: IEC 1131-3 i NEED HELP
Radoslaw Mitura:
44876: 02/07/03: Jtag extest
Radó Zoltán:
35515: 01/10/09: VHDL code
35849: 01/10/20: I search a free 8086 core...
Rafa:
83550: 05/05/03: JTAG without parallel port
Rafael Antunes Nobrega:
45692: 02/08/01: FPGA needed
Rafael Arce:
80091: 05/03/01: Re: Resource (FMAPs) use when using block RAMs
Rafael Deliano:
124353: 07/09/19: Re: FPGA history
130268: 08/03/19: Re: A Challenge for serialized processor design and implementation
Rafael Gadea Girones:
18472: 99/10/26: BlockRAM of VIRTEX
rafael plonka:
35009: 01/09/17: Altera Quartus II: Ouput skew ;-(
35391: 01/10/02: Implementation of Quartus Megafunctions in Mentor HDS???
35854: 01/10/21: Re: Verilog vs. VHDL
36362: 01/11/07: Re: FPGA BGA and decoupling
36813: 01/11/21: Re: Altera & Actel prices
<rafaelcns@gmail.com>:
90215: 05/10/06: matrix inversion in hardware
Rafal Jastrzebski:
73794: 04/09/29: Re: what to do with the DCM locked signal?
Rafal Kielbik:
15156: 99/03/10: LUT
<rafeeqs@excite.com>:
19080: 99/11/27: Re: Virtex: Getting flip-flops into the pads
Rafiki Kim Hofmans:
3112: 96/04/04: addressing PCI-interface
3201: 96/04/24: so little posts about PCI :(
3239: 96/05/02: Mr. Holmes D.
3295: 96/05/10: socket wanted for xilinx or other way to plug in
3360: 96/05/20: Re: PCI fpga
3420: 96/05/28: how to use memgen
3783: 96/07/31: assigning LOC in XACT
3857: 96/08/09: XACT:error301 with flow engine
3876: 96/08/13: Re: XACT:error301 with flow engine
3890: 96/08/15: XACT6.0:prosim and routed design
3909: 96/08/18: Re: XACT6.0:prosim and routed design
3964: 96/08/26: XC4010E en downloading bitstream
4027: 96/09/04: Re: Xilinx Foundation w/64Mb RAM
4055: 96/09/06: Re: PCI Bus Protocal & FPGA vendors
4070: 96/09/07: Re: Help with XACT 6.0 ProSim Problem
4331: 96/10/16: xc4000 and 2 clocks
Raghavendra:
61211: 03/09/30: Re: Implementing Bidirectional pins
65435: 04/01/29: what is back annotation
65436: 04/01/29: Power extimation?
69098: 04/04/27: Re: ASIC RTL and FPGA RTL
75162: 04/10/27: Re: unstable fpga design
74461: 04/10/11: DCM for generating higher frequencies.
77159: 04/12/26: Doubt on DDR SDRAM read/write operation sequence.
77405: 05/01/06: Refresh rate in DDR-SDRAM
Raghavendra G Jorapur:
3605: 96/07/03: Re: LCA to Schematic
3718: 96/07/21: Re: FPGA - RAM interfacing
3793: 96/08/02: Re: assigning LOC in XACT
raghu:
110843: 06/10/24: Please Help
Raghu:
110632: 06/10/18: Learner
<raghunandan85@gmail.com>:
131572: 08/04/25: PLB Master Example
131679: 08/04/28: Re: PLB Master Example
131846: 08/05/03: Re: PLB Master Example
<raghurash@rediffmail.com>:
87067: 05/07/14: Re: ise 7.1 Input clk is never used.
ragon:
17718: 99/08/27: Short path check in Virtex M2.1i
Rah:
51227: 03/01/07: Spartan II:Bidirectional IO interfacing 5V CMOS ?
Rahul:
52057: 03/01/29: Huffman Encoder and Decoder in verilog/ vhdl
rahul joshi:
47333: 02/09/24: querries regarding cpld
Rahul Khanna:
64113: 03/12/16: What is this ASMBL thing from Xilinx?
RAI:
126648: 07/11/28: Re: An error occured while using Dual Port Block Memory
Rain One:
48838: 02/10/25: PCI burst reads w/ Spartan
Rainer Becker:
7908: 97/10/29: Configuration of XC4000 FPGAs with JTAG
27000: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5
26999: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5a
Rainer Buchty:
26883: 00/11/02: Re: OT: Xilinx T-Shirt
57556: 03/07/02: Re: Xilinx ISE drops support for more parts
57644: 03/07/03: Re: Xilinx ISE drops support for more parts
66741: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
67834: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
75757: 04/11/14: Re: Obsolete processors resurected in FPGAs
75766: 04/11/14: Re: Obsolete processors resurected in FPGAs
82692: 05/04/16: Re: Xilinx tools on Linux
82694: 05/04/16: Re: salary ballpark please guys
82873: 05/04/19: Re: salary ballpark please guys
95018: 06/01/20: Re: OT:Shooting Ourselves in the Foot
97224: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
97234: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
98092: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
101293: 06/04/28: Re: Opteron HT coprocessors
104968: 06/07/11: Programming the Spartan-3E Starter Kit using Linux?
105031: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
121728: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121997: 07/07/17: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
129731: 08/03/04: Re: my Spartan-4 wishlist
Rainer Dorsch:
14867: 99/02/21: Re: Free circuit design
Rainer M. Malzbender:
2173: 95/10/25: US-CO-Boulder Digital Designer (EE) Job Opening
2999: 96/03/11: US-CO-Digital Hardware Designers Wanted
Rainer Malzbender:
594: 95/01/14: FPGA tools that run on SGI ?
1478: 95/06/27: OrCAD support for Xilinx 5200 series ??
1766: 95/08/29: Re: Actel PCI App Note
1927: 95/09/20: Re: Fast FPGA's?
Rainer Scharnow:
3496: 96/06/11: Xtal Osc. at XC31xxA
3510: 96/06/12: Re: Xtal Osc. at XC31xxA
3554: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3686: 96/07/15: Atmel EEPROMs 17C65: again
3687: 96/07/15: Re: Atmel EEPROMs 17C65: again
3689: 96/07/16: Re: Atmel EEPROMs 17C65: again
3714: 96/07/19: IMPORTANT! ATMEL 17C65
3767: 96/07/29: Re: Question about books for FPGA
3804: 96/08/05: Re: Question about books for FPGA
4107: 96/09/11: XChecker and WinNT or OS/2
Rainer Schmidt:
52360: 03/02/07: Partial Reconfiguration - Virtex-E
52370: 03/02/07: Re: Partial Reconfiguration - Virtex-E
53798: 03/03/24: Difference between static and active partial reconfiguration of Xilinx
Rainer Storn:
29983: 01/03/20: Book on FPGA-Design with Xilinx chips
29984: 01/03/20: Packing density of Xilinx FPGAs
Rainier:
101561: 06/05/03: How to open an ISE 8.1 project in ISE 7.1?
rAinStorms:
34922: 01/09/14: Help!
54368: 03/04/09: Re: Altera not supplying Leonardo any more
54402: 03/04/10: Altera Serial Configuration - ST Serial Flash?
54893: 03/04/22: Re: Complex FIR in FPGA
54894: 03/04/22: Re: spartan2e vs cyclone
54917: 03/04/22: Re: spartan2e vs cyclone
64422: 04/01/04: Re: please help! state machine
67301: 04/03/10: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
67314: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67527: 04/03/14: Re: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
Raintech Consulting Limited:
29982: 01/03/20: Jobs....?
Raivo Nael:
65092: 04/01/20: Re: WTD: info on AMD palce22v10
65258: 04/01/22: Re: WTD: info on AMD palce22v10
65278: 04/01/23: Re: WTD: info on AMD palce22v10
65438: 04/01/29: Is FPGA fully static?
67343: 04/03/10: Re: licence for Xilinx 2.1i
raj:
69116: 04/04/27: Xpower Static Current
69283: 04/05/04: synthsizing multi-dimensional array XST
69481: 04/05/11: VHDL-Verilog Co-Simulation
69641: 04/05/16: load on a clock signal in FPGA
70253: 04/06/10: Reading Back Configuration of Slice/LUT
71661: 04/07/26: configuration SRAM cells in Xilinx/Altera FPGAs
71693: 04/07/27: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71729: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
72617: 04/08/26: Re: Xilinx Command Prompt
89073: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
Raj B Krishnamurthy:
24159: 00/07/27: compact PCI Xilinx virtex FPGA card
Raj Kumar Nagarajan:
51361: 03/01/11: Re: MicroBlaze MDK2.2 opb_timer
Raj Nagarajan:
63718: 03/12/01: Re: debugging microblaze with xmd
Raj Patel:
3728: 96/07/22: Xilinx XC6200 Information
raja:
20039: 00/01/25: global clock distribution
20090: 00/01/27: CARRY CHAIN CIRCUIT in ORCA 3T
20175: 00/01/30: Re: Xilinx vs Altera
20566: 00/02/15: Re: LUT & VHDL
21249: 00/03/14: Re: Testbench for a modulator and a demodulator
Raja Neogi:
2437: 95/12/05: final call for paper (ICSE'96)
rajan:
65551: 04/02/02: Comparison of the Co-verification tools for SoC/ASIC
<rajashekar_798@yahoo.com>:
94836: 06/01/18: xilmfs on flash
94894: 06/01/18: Re: xilmfs on flash
94912: 06/01/19: Re: xilmfs on flash
94981: 06/01/19: Re: xilmfs on flash
Rajat Karol:
43699: 02/05/29: Engineering Samples for free?
43784: 02/06/02: Engineering Samples for free?
Rajeev:
46633: 02/09/04: Viewing Xilinx netlist
46670: 02/09/05: Re: Viewing Xilinx netlist
46706: 02/09/06: Re: Viewing Xilinx netlist
46708: 02/09/06: Re: Viewing Xilinx netlist
46937: 02/09/12: Xilinx LogicCore Pipelined Divider Clock Cycles
46938: 02/09/12: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
46972: 02/09/13: Re: 2-D resistor array
47157: 02/09/19: Re: GCLK pin used like an standard input
47165: 02/09/19: Re: VHDL : Lookup Table
47439: 02/09/25: Virtex2 Block Multiplier: Faster, Faster
47465: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
47483: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
47817: 02/10/04: Re: Finding nets in hierarchy
48379: 02/10/16: Standing on the shores of Stratix-land
48582: 02/10/21: Re: Standing on the shores of Stratix-land
48650: 02/10/22: Re: Transferring Design from XILINX --> ALTERA
48855: 02/10/25: Re: Please recommend a FPGA chip!
48857: 02/10/25: 3.3V Device Programmer Suggestions ?
48971: 02/10/28: Re: 3.3V Device Programmer Suggestions ?
49046: 02/10/30: Re: 3.3V Device Programmer Suggestions ?
53921: 03/03/27: Tristate pins + Inputs => External Pullup ?
54197: 03/04/04: Re: Xilinx Divider Core
54200: 03/04/04: Re: Spartan vs. Cyclone for arithmetic functions
54203: 03/04/04: Re: PCI specification
54286: 03/04/07: Re: Tristate pins + Inputs => External Pullup ?
54326: 03/04/08: Re: price of fpga chips
54477: 03/04/11: Buying FPGAs from parts brokers
54563: 03/04/14: Re: Buying FPGAs from parts brokers
54566: 03/04/14: Re: 2.5V switching regulator for Spartan 2
54714: 03/04/16: Re: 2.5V switching regulator for Spartan 2
59387: 03/08/18: Altera JTAG verification
59434: 03/08/19: Re: Altera JTAG verification
59500: 03/08/20: Re: Altera JTAG verification
67647: 04/03/16: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
67703: 04/03/17: Re: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
67704: 04/03/17: Re: Answering Machine RAM
67749: 04/03/18: Re: clock rising edge alignment
67814: 04/03/19: Altera DSP Builder
67959: 04/03/23: Re: Apparent Altera Cyclone JTAG problem
68095: 04/03/26: Re: study verilog or vhdl?
68171: 04/03/28: Re: counter design
68238: 04/03/30: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
68246: 04/03/30: Re: FIFO Depth(Length) Calculation
68282: 04/03/31: Re: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
68446: 04/04/05: VHDL: Use of literal '1' on an input port ?
68494: 04/04/06: Re: Quartus removes Tristate Buffer
68495: 04/04/06: Re: VHDL: Use of literal '1' on an input port ?
68641: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68648: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68716: 04/04/15: Re: Yet Another Altera Online Support Is USELESS Rant...
68718: 04/04/15: Re: System Generator HDL co-simulatin problem
68860: 04/04/20: Re: Trouble with rising edge signals in functional simulation
68886: 04/04/21: Re: What does a "background check" mean? ...
68887: 04/04/21: Re: Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...
68933: 04/04/22: Re: calculate the number of logic gate in FPGA
69322: 04/05/06: Re: costal loop question
69438: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69621: 04/05/15: Re: best fpga development board?
69942: 04/05/25: Re: Driving fpga pin out over long cable
70143: 04/06/04: Re: VHDL test bench in Quartus
70210: 04/06/09: Re: comp.arch.fpga: reset strategy
70363: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
70373: 04/06/14: Stratix DSP Block: Choosing which FFs are enabled
70422: 04/06/16: Re: Stratix DSP Block: Choosing which FFs are enabled
70649: 04/06/22: Re: Initializing data in EAB ram
70674: 04/06/23: Re: Trying to remember how to use Quartus
70949: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
71019: 04/07/05: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71068: 04/07/07: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71138: 04/07/09: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71226: 04/07/12: Re: Same bitstream files give different behavior.
71286: 04/07/13: Re: extending a signal pulse
71773: 04/07/29: Re: FPGA vs CPLD
71806: 04/07/30: Re: FPGA vs CPLD
72967: 04/09/09: Re: vhdl error ?? - [code included]
81186: 05/03/18: Re: Which HDL?
81191: 05/03/18: Re: LVDS as general differential input ?
81192: 05/03/18: Re: Spartan 3 to tempsensor interface
81193: 05/03/18: Re: Using DSP Builder with Quartus
81739: 05/03/30: Re: LVDS as general differential input ?
108679: 06/09/14: ispDesignExpert available for download anywhere ?
108692: 06/09/15: Re: ispDesignExpert available for download anywhere ?
108733: 06/09/15: Re: ispDesignExpert available for download anywhere ?
108965: 06/09/19: Re: VHDL oddity
109986: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
129570: 08/02/27: Using dma_sg_v2_01_a component with plb_ipif
rajeev:
104513: 06/06/28: NCO Clock driven Designs in FPGA
Rajeev Jayaraman:
25351: 00/09/07: Re: Slow routing of PWR/GND (Virtex)
35504: 01/10/08: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
42430: 02/04/23: Re: Maximum Usage in a Virtex FPGA
67879: 04/03/21: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000 FPGA.
Rajeev Mishra:
15745: 99/04/11: URGENT! Need VHDL code for ADPCM decompression on Xilinx FPGA
rajendra:
70524: 04/06/18: Programming FPGA in Xilinx Virtex 2 pro board
114269: 07/01/10: ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
Rajendra:
104141: 06/06/19: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
rajendra k singh:
72390: 04/08/17: linux on virtex 2 pro board
72414: 04/08/18: Re: linux on virtex 2 pro board
Rajesh Bawankule:
29394: 01/02/19: Verilog FAQ : February 2001
30358: 01/04/04: Verilog FAQ: April 2001
31633: 01/06/01: Verilog FAQ: June 1, 2001
32170: 01/06/17: Verilog FAQ : Jun 17, 2001
32597: 01/07/01: FAQ: Verilog FAQ : July 1, 2001
32658: 01/07/04: Third issue of Chip-Guru is ready: July 2001
49400: 02/11/11: FAQ: Verilog FAQ : November 15, 2002
Rajesh Kumar E.V:
33631: 01/08/01: VIRTEX E FPGA Configuration through SelectMap
Rajesh Murugesan:
67250: 04/03/09: How to use BUFGMUX in SPARTAN 2 device????
67251: 04/03/09: Reg..How to use BUFGMUX in Spartan 2 family
69392: 04/05/10: Can I use an internal reset signal in DLL?
69680: 04/05/18: DLL - Change in input frequency (CLKIN)
69922: 04/05/24: Re: DLL - Change in input frequency (CLKIN) ---help needed
70061: 04/06/01: DLL- Change in input clock source --Suggestions plz
Rajesh Pathak:
68976: 04/04/23: Verilog RTL of a Galois Field Multiplier
rajesh52:
23182: 00/06/16: Verilog FAQ
<rajesh52@hotmail.com>:
13774: 98/12/24: Version 8 of Verilog FAQ released
14150: 99/01/15: Re: Verilog Book --- Me too!
14569: 99/02/04: Re: Verilog ROM Models
14757: 99/02/15: Verilog FAQ
14769: 99/02/16: Verilog FAQ
14974: 99/03/01: Verilog FAQ
15225: 99/03/15: Verilog FAQ
16100: 99/05/03: Verilog FAQ
16660: 99/06/01: Verilog FAQ
17295: 99/07/19: Verilog FAQ
17483: 99/07/30: Verilog FAQ.
17632: 99/08/16: Verilog FAQ
17887: 99/09/15: verilog FAQ
17996: 99/09/22: Re: FPGA Compiler II/FPGA Express User's Manual
18330: 99/10/15: Verilog FAQ
19141: 99/12/02: Re: HDL editor?
19142: 99/12/02: Verilog FAQ
19911: 00/01/17: Verilog FAQ
20603: 00/02/16: Verilog FAQ
22205: 00/05/01: Verilog FAQ
25206: 00/08/30: Verilog FAQ
28327: 01/01/07: FYI: chip-guru online chip design magazine
28947: 01/01/30: Verilog FAQ : Jan 2001
<rajesh52@my-dejanews.com>:
14089: 99/01/12: Re: programming language interface
14322: 99/01/25: Re: Needed: PCI interface
<rajesh@comit.com>:
6580: 97/06/04: Alternate Verilog FAQ : New release
7870: 97/10/26: Verilog FAQ version 5 released
8114: 97/11/18: Free verilog models , examples
9889: 98/04/11: Verilog FAQ version released
10108: 98/04/27: Alt. Verilog FAQ released.
10312: 98/05/11: Re: available eda environments
11303: 98/08/03: Verilog FAQ Version 7 published
11304: 98/08/03: Verilog FAQ Version 7 published
<rajesh@NoSPAM-1606.comit.com>:
8731: 98/01/22: Re: MAX+II software from Altera.
Rajeshwary:
62585: 03/11/02: Spartan II with Digilab board, IO communication
62731: 03/11/05: ISE : Synthesis process hangs
rajiv:
68896: 04/04/21: liberary component
120215: 07/06/03: Synchronization of instruction with clock
121546: 07/07/07: verilog code for read write in Bram block
121557: 07/07/08: verilog code for read write in bram block
121579: 07/07/09: Adding a bram block to a user defined bram controller
<rajivc53@gmail.com>:
120705: 07/06/14: c code to initialize a peripheral
121448: 07/07/04: read/write in bram block
Rajkumar:
128415: 08/01/24: Re: How to choose an FPGA for High speed applications
128580: 08/01/31: Re: I need a SDRAM controller
Rajkumar Kadam:
119442: 07/05/19: Re: How do I constraint multiple clock cycle in Altera?
<rajkumar@gdatech.com>:
12137: 98/10/01: Re: Which FPGA tool is better
22099: 00/04/22: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
25399: 00/09/09: Re: Mealy vs Moore FSM model
raju:
116139: 07/03/02: Re: Where can i get free CAN VHDL core
<raju.penum@gmail.com>:
116071: 07/02/28: Where can i get free CAN VHDL core
raju_lingala:
97305: 06/02/20: SDRAM Reading problem
Rajul Maheshwari:
16841: 99/06/14: site for reconfigurable computing
RaKa:
87129: 05/07/15: Re: Why cann't this block be synthesized in top level
116211: 07/03/04: Ideas for Masters Project.
126029: 07/11/13: Asynchronous FIFO Latency.
rakesh:
90517: 05/10/15: Problem with Xilinx Impact under windowsXP
Rakesh Sharma:
74008: 04/10/02: How to generate a signal on Xilinx Spartan II
74901: 04/10/21: Xilinx translate error : Cannot find signal "clk"
Rakesh YC:
71134: 04/07/09: configuration for a mixed mode VHDL-verilog lang
Ralf:
43794: 02/06/03: Lattice Synario Service Pack
84535: 05/05/20: ALTERA EPXA1 SDRAM BUG
Ralf =?iso-8859-1?Q?Oberl=E4nder?=:
30239: 01/03/29: Encryption Bitstrems
30706: 01/04/25: Failed to configure Spartan2
Ralf A. Eckhardt:
28687: 01/01/21: xc95108 funny behaviour
28691: 01/01/21: Re: xc95108 funny behaviour
28717: 01/01/22: Re: xc95108 funny behaviour
28730: 01/01/22: Re: xc95108 funny behaviour
42527: 02/04/26: Re: XC9500XL problem
48947: 02/10/28: Re: cpld I/O modes
Ralf Duschef:
82529: 05/04/13: Re: "The ISE 7.1 Experience"
Ralf Hildebrandt:
42963: 02/05/08: Re: State machine synthesis
49439: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
51174: 03/01/05: Re: conversions and some assistance please
55777: 03/05/19: Re: about simulation
56847: 03/06/17: Re: An All Digital Phase Lock Loop
57006: 03/06/20: Re: Quartus bug or wrong VHDL?
57480: 03/07/01: Re: FPGA vs. DSP.
59921: 03/09/01: Re: What does + synthesize to?
65227: 04/01/22: Re: How can I have multiple drivers of one inout port?
66550: 04/02/22: Re: Comparator and minimum value address
66558: 04/02/22: Re: Comparator and minimum value address
69695: 04/05/18: Re: std_logic_vector vs unsigned
82964: 05/04/20: Re: Unconstrained ports for synthesis
92761: 05/12/06: Re: Info on packing regular tree-like structures into rectangles?
97973: 06/03/02: Re: Help wanted
97982: 06/03/02: Re: Help wanted
98681: 06/03/14: Re: VHDL
98728: 06/03/15: Re: About Altera FPGA Board
98787: 06/03/16: Re: About Altera FPGA Board
98789: 06/03/16: Re: Urgent Help Needed!!!!!
98870: 06/03/17: Re: About Altera FPGA Board
98873: 06/03/17: Re: Urgent Help Needed!!!!!
98969: 06/03/18: Re: Microblaze FSL peripheral problem
98976: 06/03/18: Re: Urgent Help Needed!!!!!
99001: 06/03/18: Re: About Altera FPGA Board
99133: 06/03/20: Re: Urgent Help Needed!!!!!
99359: 06/03/23: Re: XST takes unusually long
99441: 06/03/24: Re: XST takes unusually long
99611: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
100250: 06/04/05: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
100414: 06/04/08: Re: Compiler to FPSLIC
100484: 06/04/10: Re: How to handle the high fanout
101437: 06/05/01: Re: Question about the ip I developed
101710: 06/05/05: Re: RFID chip has battary in it or not
101828: 06/05/07: Re: flashing a led
102328: 06/05/15: Re: difference of variable and signal
104216: 06/06/21: Re: xst can, but vcomp can't
104282: 06/06/22: Re: xst can, but vcomp can't
104316: 06/06/23: Re: xst can, but vcomp can't
104317: 06/06/23: Re: stimulus for FPGA
104340: 06/06/24: Re: stimulus for FPGA
105090: 06/07/13: Re: how to implement multi-port memory
105677: 06/07/28: Re: Verilog case statements
105681: 06/07/28: Re: Verilog case statements
105711: 06/07/29: Re: Verilog case statements
105712: 06/07/29: Re: "This design element is inferred rather than instantiated" (newbie)
105770: 06/07/31: Re: Verilog case statements
105899: 06/08/02: Re: generating sine-like waveforms
106011: 06/08/05: Re: How to implement large ROM's from binary sources?
106080: 06/08/07: Re: verilog versus vhdl
106356: 06/08/12: Re: Embedded clocks
106357: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
106917: 06/08/22: Re: hex format 16 bit?
107815: 06/09/01: Re: Higher voltages input, quick check....
108274: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108936: 06/09/19: Re: BUF component
109294: 06/09/23: Re: please tell me how to learn testbench?
110684: 06/10/19: Re: Meeting Timing Constraint
111540: 06/11/05: Re: Integration of modules
112755: 06/11/28: Re: pre-synthezis simulation in ModelSim for Actel
112829: 06/11/29: Re: pre-synthezis simulation in ModelSim for Actel
112832: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
112833: 06/11/29: Re: FPGA application field
112892: 06/11/30: Re: FPGA application field
112950: 06/12/02: Re: FPGA application field
113920: 06/12/29: Re: SPI slave problem
114494: 07/01/17: Re: Process on both edges
114568: 07/01/19: Re: Generation of Divided-by-3 clock
115887: 07/02/23: Re: porting virtex2-pro into virtex4. Performance!!
115888: 07/02/23: Re: 2x technique
116287: 07/03/06: Re: VHDL and Latch
116766: 07/03/17: Re: What official function should I call to genertate a sum of products
117737: 07/04/09: Re: Clocking data into a shift register on positive AND negative
118016: 07/04/16: Re: combinatorial vs sequential
119027: 07/05/09: Re: 'EVENT (or rising_edge) static prefix requirement....
120212: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than
122052: 07/07/18: Re: Latches
122067: 07/07/18: Re: or1200 uses more than 100% of resources. how to reduce?
122142: 07/07/20: Re: Counter ?
123693: 07/09/02: Re: flip-flop enable
128046: 08/01/14: Re: sine and cosine wave generation
129313: 08/02/20: Re: From ASIC RTL to FPGA, what are the things I should take care
Ralf Koehler:
6271: 97/05/07: universal PCI-Interface with FPGA?
Ralph:
47597: 02/09/30: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
93911: 06/01/03: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94143: 06/01/06: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
ralph:
42402: 02/04/23: Re: Post-synthesis simulation
94061: 06/01/05: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
Ralph Friedrich:
27871: 00/12/13: Configuration : XC4000
87335: 05/07/21: Re: General-purpose STAPL Composer?
Ralph Hartley:
109491: 06/09/27: Re: An algorithm with Minimum vertex cover without considering its
Ralph Malph:
64523: 04/01/06: Re: Spartan3 availability
64637: 04/01/09: Re: Anybody know what the REAL story is? Jim figured it out.
64649: 04/01/10: Re: Anybody know what the REAL story is? Jim figured it out.
64670: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
64680: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
64681: 04/01/11: Re: Spartan3 prices again...
64703: 04/01/11: Re: Altera Cyclone data is incomplete or messy
64721: 04/01/12: Re: fpga database?
64814: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64815: 04/01/14: Re: Open source ARM, Version 0.1
64828: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64833: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64901: 04/01/15: Re: Spartan-IIE as an ASYNC RAM?
64943: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
65059: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65060: 04/01/19: Re: Spartan3 prices again...
65062: 04/01/19: Re: Which version of ISE Webpack has FPGA Editor on it?
65063: 04/01/19: Re: WTD: info on AMD palce22v10
65064: 04/01/19: Re: QUES: Where can I find Xilinx M1 tools
65177: 04/01/21: Re: WTD: info on AMD palce22v10
65222: 04/01/22: Re: WTD: info on AMD palce22v10
65224: 04/01/22: Re: Soft failures (?) 9536XL
65252: 04/01/22: Re: OT: liability insurance
65253: 04/01/22: Re: xilinx 70% tracking rule
65256: 04/01/22: Re: Why is router software not multi-threaded?
65263: 04/01/22: Re: WTD: info on AMD palce22v10
65311: 04/01/24: Re: WTD: info on AMD palce22v10
65312: 04/01/24: Re: xilinx 70% tracking rule
65406: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65412: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
Ralph Mason:
20184: 00/01/30: Which FPGA to learn with?
32169: 01/06/18: Verilog or VHDL?
48595: 02/10/22: Newbie Questions - Jan Gray XSOC
48614: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
48642: 02/10/22: Webpac Simulation
48680: 02/10/23: Re: Webpac Simulation
48683: 02/10/23: Re: Webpac Simulation
48685: 02/10/23: Re: Newbie Questions - Jan Gray XSOC
48883: 02/10/26: #1's in verilog
48921: 02/10/27: Couple of Questions
49025: 02/10/30: Re: filters on fpgas
49165: 02/11/04: Learner ? - Open Collector in Verilog
49264: 02/11/07: Instruction sets to implement instruction sets
49324: 02/11/09: Re: Instruction sets to implement instruction sets
49423: 02/11/12: Re: CLB numbers for various ops?
49658: 02/11/19: Some Basic Understanding - RTL
50207: 02/12/05: Re: ISA bus VGA
50370: 02/12/10: Tiny Forth Processors
50421: 02/12/11: Re: Tiny Forth Processors
50448: 02/12/11: Re: Tiny Forth Processors
50960: 02/12/24: Re: Combinatorial clock source question
51975: 03/01/28: Re: GNU C for custom processor
52403: 03/02/08: XC9536XL - ISP
52536: 03/02/13: Setting CPLD options (Webpac)
52965: 03/02/27: xc9500 Low power mode
52991: 03/02/28: Re: xc9500 Low power mode
53272: 03/03/10: Re: Clocking a spartanIIE with a 5V signal?
53602: 03/03/18: Re: new XC95xx global clock
53610: 03/03/18: Re: new XC95xx global clock
53820: 03/03/25: Re: Xilinx FPGAs available?
54065: 03/04/02: Re: XC9572XL Macrocell power
54073: 03/04/02: Re: XC9572XL Macrocell power
54110: 03/04/03: Re: XC9572XL Macrocell power
55108: 03/04/27: Re: Xilinx of Linux HOWTO has been updated
55526: 03/05/12: Re: help on FPGA-programming tutorial for students
55578: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55695: 03/05/16: Re: smallest embedded cpu.
55697: 03/05/16: Re: smallest embedded cpu.
55714: 03/05/17: Re: smallest embedded cpu.
55929: 03/05/24: Re: CLKDLL: Dividing
55966: 03/05/25: Re: Newbie CPLD question
55967: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
56036: 03/05/28: Re: 2 Questions about VHDL
56058: 03/05/28: Re: FIFO Controller
56090: 03/05/29: Re: FIFO Controller
56163: 03/05/30: FPGA's an Flash
56177: 03/05/30: Re: FPGA's an Flash
56433: 03/06/05: Re: Xilinx Block RAM
56747: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
57295: 03/06/27: Xlilin xc9572XL Default register values
57302: 03/06/27: Re: Xlilin xc9572XL Default register values
57378: 03/06/29: Re: Xlilin xc9572XL Default register values
57403: 03/06/30: Re: Xlilin xc9572XL Default register values
57441: 03/07/01: Re: Xlilin xc9572XL Default register values
57402: 03/06/30: Re: Xlilin xc9572XL Default register values
57582: 03/07/03: Re: Xlilin xc9572XL Default register values
59154: 03/08/11: Re: FPGA for a Newcomer
59161: 03/08/11: Re: Upgrading OS or WebPack
60068: 03/09/05: Re: New to FPGA, seeking advice
62439: 03/10/30: Re: Xilinx Spartan3: Price
62694: 03/11/05: Re: FPGA Prototyping Board
62878: 03/11/11: Re: Home grown CPU core legal?
Ralph Reinhold:
6911: 97/07/08: Re: Generating Sine/Cosine digitally
Ralph Remme:
3076: 96/03/27: Re: LOG/iC Installation Problem
3312: 96/05/13: Re: Looking for free FPGA softw./Xilinx
Ralph Watson:
1925: 95/09/20: Re: Anyone using Altera 8820A ?
2464: 95/12/08: Re: Median filter
3384: 96/05/23: Re: Fitting problems with Altera MAX9560
Ralph Weir:
20882: 00/02/25: Re: MRP systems
30109: 01/03/23: Re: Virtex Em on a board?
30363: 01/04/04: Re: DSP Volume-control in FPGA
ralphie:
110392: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110395: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
ralstef:
115184: 07/02/01: DDR SDRAM controller for virtex 2 pro
Ram:
60214: 03/09/08: FPGA: Interfacing external NVRAM
60819: 03/09/23: PPC access to PROM using Virtex @ pro
60923: 03/09/24: on the fly Reconfig
68083: 04/03/25: Re: xilinx PPC map file
78712: 05/02/06: problem with xilinx platform studio 6.2i
78792: 05/02/07: Re: problem with xilinx platform studio 6.2i
78849: 05/02/08: virtex4 distributed RAM
78861: 05/02/09: Beginner: running EDK 6.3 in linux
78897: 05/02/09: Re: Beginner: running EDK 6.3 in linux
78902: 05/02/09: Re: virtex4 distributed RAM
78903: 05/02/09: Re: virtex4 distributed RAM
78906: 05/02/09: Re: virtex4 distributed RAM
88947: 05/09/01: FS: Lot of 60 XCV1000 FPGAs
88978: 05/09/01: Re: Lot of 60 XCV1000 FPGAs
89287: 05/09/11: Which JTAG cable for Xilinx & Linux?
89318: 05/09/12: ISE 7.1i & Linux / reg code question
89321: 05/09/12: Microblaze & Memory DMA operation
89348: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89349: 05/09/13: Re: Microblaze & Memory DMA operation
89367: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89370: 05/09/13: Re: Microblaze & Memory DMA operation
89555: 05/09/19: Re: Reading a PAL fusemap with a microscope
89591: 05/09/20: ISE 7.1i & Linux / reg code question
89870: 05/09/28: Re: a ISE installation problem on linux
89871: 05/09/28: Pricing for V2-Pro / V4-FX ?
89872: 05/09/28: Req to Xilinx: eCos port for Microblaze
90004: 05/10/01: Re: Req to Xilinx: eCos port for Microblaze
91402: 05/11/05: Re: FPGA : PCI-CORE
ram:
8212: 97/11/29: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
12651: 98/10/21: Re: Schematic entry?
14454: 99/01/30: Re: No. of CLBs in Xilinx nearly 100% can't implement.
60043: 03/09/04: Memory
60094: 03/09/04: Re: Memory
61052: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61910: 03/10/14: Re: Universities that focus on IC design
61912: 03/10/14: Partial Reconfiguration
61916: 03/10/14: Partial/ Dynamic Reconfiguration Virtex 2 pro- does it have any help at all
61918: 03/10/14: Re: Xilinx "Programming failed" message
61932: 03/10/15: Re: newbie linker script question
61986: 03/10/15: Re: Partial Reconfiguration
62015: 03/10/16: Re: explain the vhdl code
62016: 03/10/16: xilinx System ACE solution
62099: 03/10/19: Re: To our future engineers, smart and otherwise...
62216: 03/10/22: PPC boot
62219: 03/10/22: EMC/SDRAM
62451: 03/10/29: Questions that question????
62555: 03/11/01: Re: data recorder examples?
62981: 03/11/11: Re: How to visit the files in CF cards
63208: 03/11/17: Re: How to visit the files in CF cards
64437: 04/01/04: System Ace - Flash card formatting
64838: 04/01/14: Re: Can i get a sample XSVF file?
64840: 04/01/14: Re: Microblaze simulation
65161: 04/01/21: EDK - Desinging system with C++
65334: 04/01/24: Re: Spirit on Mars
65995: 04/02/10: Building a NN using FPGA
66060: 04/02/11: Re: Xilinx Platform Flash Prom
66061: 04/02/11: Re: XC2V2000 + System Ace + Reconfig
66522: 04/02/20: Re: Power supply for the Xilinx Virtex Pro FF1152 Proto Board
66828: 04/02/26: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
66996: 04/03/02: V2pro + A/D + IrDA + RS232 board???
66997: 04/03/02: Re: Xilinx iMPACT error: "Done did not go high"
67489: 04/03/12: Re: System Ace: can not program Avnet V2P7 board
67533: 04/03/13: Re: Virtex 2 P -> PPC write to block RAM
67534: 04/03/13: Re: any body help me about xc4010e board
67557: 04/03/14: Board with all modules
67733: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67734: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67860: 04/03/21: Re: What's the flow V2P SysAce handles the software inside the ACE file
68027: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
68034: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
68160: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
68311: 04/03/31: Re: Virtex 2 PRO Eval/Development platforms
68313: 04/03/31: newbie - TCP/IP
68643: 04/04/12: system C - streams C
68960: 04/04/22: Re: FPGA within demonstration
68961: 04/04/22: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68962: 04/04/22: Re: liberary component
68963: 04/04/22: Re: documents
69202: 04/04/29: Re: basic question, virtex 2 pro
69207: 04/04/29: Is this a best approach- FPGA ANN
69361: 04/05/07: OPB IPIF user logic
70342: 04/06/13: Re: Xilinx .bit to .svf...
71219: 04/07/12: Re: Need some help regarding dynamic reconfiguring of the pin connections
72345: 04/08/16: Re: Using SDRAM on Xilinx AFX V2P board
75473: 04/11/06: what's the scenario out there
112350: 06/11/20: timing constraints
112351: 06/11/20: timing constraints
112482: 06/11/22: query
112530: 06/11/24: types of FPGA
112574: 06/11/24: query
112575: 06/11/24: query
112631: 06/11/26: query in constraining timing
112638: 06/11/26: Re: query in constraining timing
112639: 06/11/26: Re: query in constraining timing
112643: 06/11/26: Re: query in constraining timing
112653: 06/11/27: tips for P&R in FPGA(quartus)
112869: 06/11/30: help
112947: 06/12/01: Hi
113014: 06/12/05: Re: Hi
113071: 06/12/05: query in gate level simulationin quartus s/w 6.0
113200: 06/12/07: query regarding capacitance of pins of cyclone device
113466: 06/12/14: query
113506: 06/12/14: Query
113507: 06/12/14: Re: Query
115242: 07/02/04: query in P&R of FPGA
115243: 07/02/04: Re: query in P&R of FPGA
116187: 07/03/03: regarding power and timing
116315: 07/03/07: Re: A Very good VLSI Chip design website
117710: 07/04/08: query
121338: 07/07/02: cosimulation
122474: 07/07/28: query in byte blaster/signal topic logic analyser
Ram Meenakshisundaram:
17554: 99/08/10: Newbie - what are the limitations of the student edition
17556: 99/08/10: Emulating a transputer on FPGA
17565: 99/08/10: Re: Emulating a transputer on FPGA
19868: 00/01/14: XACT where is it??
Ram Prabhakar:
6595: 97/06/04: Re: Alternate Verilog FAQ : New release
Ramakrishnan:
45753: 02/08/04: Controller for a Architecture
45789: 02/08/05: Re: Controller for a Architecture
45805: 02/08/06: Re: Controller for a Architecture
45947: 02/08/12: Reconfiguration in Xilinx FPGA
45958: 02/08/12: Re: Reconfiguration in Xilinx FPGA
45981: 02/08/13: Re: Reconfiguration in Xilinx FPGA
46091: 02/08/17: Re: Reconfiguration in Xilinx FPGA
46104: 02/08/19: onboard reconfiguration of Xilinx FPGA
46125: 02/08/19: Re: onboard reconfiguration of Xilinx FPGA
46155: 02/08/20: Re: onboard reconfiguration of Xilinx FPGA
46241: 02/08/22: Downloading bit streams in Xilinx
46272: 02/08/23: Re: Downloading bit streams in Xilinx
93156: 05/12/14: Xst Error
<ramakrishnan.vijayakumar@gmail.com>:
111151: 06/10/30: Programming Virtex II Pro Eval Board
Raman Arora:
38405: 02/01/14: Re: speech recognition - active noise cancellation
Raman Narayan:
24007: 00/07/20: Re: 104 Page Collective DAC'00 Trip Report Up
Ramanathan:
27772: 00/12/07: Test Bench
Ramanathan S:
29687: 01/03/05: URGENT HELP REQ......
Rambutwa Gooberundi:
9492: 98/03/18: Re: Xilinx XACT 6.01 crack
ramesh:
95646: 06/01/24: porting linux on ml403
96588: 06/02/07: Re: porting linux on ml403
97031: 06/02/15: can i use gcc of EDK?
Ramesh C. Tekumalla:
5468: 97/02/18: Re: Mealy/Moore state machines
Ramesh Narayanaswamy:
2597: 96/01/10: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
7133: 97/08/04: Re: Simulating large VHDL design (FPGA backannotated)
<ramesh_z@my-deja.com>:
22914: 00/06/02: view synthesis 7.0
23086: 00/06/14: ASIC DESIGN
23657: 00/07/04: silicon
Rami:
26042: 00/10/01: Begineer
Rami Gideoni:
7614: 97/09/28: Re: vme vs compact pci
7615: 97/09/28: Re: vme vs compact pci
Raminder S Bajwa:
982: 95/04/06: Re: Aptix (Field Programmable Interconnect) ??
1048: 95/04/20: VMEbus interface using fpgas
Ramnath:
35851: 01/10/20: Xilinx Libraries
35852: 01/10/20: Fpga Synthesis Process
35859: 01/10/21: FPGA based IPv6 router -- hi
36522: 01/11/10: Reconfigrable Routers
36868: 01/11/22: Re: Viewing generated VHDL
36888: 01/11/23: Re: Fpga Synthesis Process
37483: 01/12/12: Constraints Some basics
37539: 01/12/13: Relation between net delay & Period
ramshankar:
33233: 01/07/19: foundation series 2.1i
Ramtilak:
71182: 04/07/11: Need some help regarding dynamic reconfiguring of the pin connections
71514: 04/07/20: Area constraint on a sub-module
72326: 04/08/14: Hardware/Software Communication in Virtex-2p
Ramy:
24516: 00/08/11: Re: Xilinx chip not programming correctly
24678: 00/08/16: Re: Xilinx chip not programming correctly
24679: 00/08/16: Permanently programming FPGAs
ramy:
24484: 00/08/10: Help with Xilinx
79546: 05/02/20: does anyone have a c compiler for the picoblaze
79547: 05/02/20: Re: Question about microblaze C complier
79688: 05/02/23: Re: C compiler for Picoblaze
ran:
77058: 04/12/21: MAP failes after inserting ILA and ICON cores to the design
77093: 04/12/21: Re: MAP failes after inserting ILA and ICON cores to the design
77111: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design
77442: 05/01/06: Re: MAP failes after inserting ILA and ICON cores to the design
ranbow:
64051: 03/12/14: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64086: 03/12/15: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64115: 03/12/17: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64137: 03/12/18: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
Randal Kuramoto:
37625: 01/12/17: Re: ISP by JTAG using a microcontroller
45221: 02/07/16: Re: Spartan PROMs...
Randall Holman:
45110: 02/07/12: PCMCIA host
Randall Logan:
14043: 99/01/08: Anyone have an Altera LP6 interface card FS?
<randallchaas@sbcglobal.net>:
129538: 08/02/27: Re: Viewing RTL schematic in Xilinx ISE
<randombit@my-deja.com>:
19640: 00/01/05: Re: Design security
19641: 00/01/05: Re: Design security
19642: 00/01/05: Re: Design security
randomdude@gmail.com:
82271: 05/04/10: A PCI FPGA card I found on ebay
82276: 05/04/10: Re: A PCI FPGA card I found on ebay
82288: 05/04/10: Re: A PCI FPGA card I found on ebay
84364: 05/05/17: VHDL array question
84376: 05/05/18: Re: VHDL array question
84395: 05/05/18: Re: VHDL array question
<randomdude@gmail.com>:
121032: 07/06/22: Reshipping spartan3 PCIE board to England
121064: 07/06/24: Re: Reshipping spartan3 PCIE board to England
122289: 07/07/25: Re: Beginners question
122763: 07/08/06: Re: Need suggestion for my project
<randraka@ids.net>:
452: 94/11/21: RE: Looking for VHDL & VIEWLOGIC FPGA Experts/Consult
568: 95/01/06: RE: Fpga programming
579: 95/01/10: Lee Fadden, what is your address?
595: 95/01/15: Re: ViewLogic simulation without master reset
617: 95/01/19: Re: ViewLogic simulation without master reset
629: 95/01/23: Re: ViewLogic simulation without master reset
677: 95/02/03: re:Inefficiency(?)
681: 95/02/05: Re: "on-fly" reprogrammable devices/research
729: 95/02/18: Re: Can I implement a digital PLL in an FPGA??
776: 95/02/28: Re: Can I implement a digital PLL in an FPGA??
786: 95/03/02: Re: Can I implement a digital PLL in an FPGA??
800: 95/03/03: RE: FPGA Custom Computing Machine
836: 95/03/09: Re:FPGA bit serial multipliers, correction
1095: 95/04/27: Re: Need help about conference chip
1185: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1310: 95/05/31: Re: Any company for conversion FPGA to ASIC?
1535: 95/07/11: RE: Xilinx 5200 Software
1646: 95/08/10: RE: Xilinx FPGAs ---> Xilinx EPLDs
1689: 95/08/16: Re: Xilinx xc4013 routing problems ??
1884: 95/09/15: Re: Fast FPGA's?
1926: 95/09/20: Re: Fast FPGA's?
<randraka@my-dejanews.com>:
13026: 98/11/12: Re: placement&routing problems
Randy:
32606: 01/07/02: Re: Converting character to integer in VHDL
Randy Bickford:
8549: 98/01/07: seeking example for PWM using PLDs
Randy Bolling:
704: 95/02/10: Asset
38605: 02/01/18: Re: VirtexII ES configuration
38606: 02/01/18: Re: I2C multiplexer
Randy Given:
23973: 00/07/19: Experts-Exchange
Randy Nachtrieb:
27800: 00/12/08: FS: ADVICE RTOS In Circuit Emulator
Randy Robinson:
9989: 98/04/21: Re: Xilinx FPGAs: Usable Pins on XS Boards (Help)
10330: 98/05/12: Re: How to use LogiBlox Components in FPGA Express?
10385: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
10386: 98/05/15: Re: Xilinx FGA Express
14508: 99/02/02: Re: Opinions requested : Minc/Synario alternatives
14575: 99/02/04: Re: Synplify/Xilinx4085XLA question
17507: 99/08/03: Re: Xilinx Virtex configuration in chunks
113675: 06/12/19: Re: unexplainable Problem on Spartan 3
Randy Tietz:
4799: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
9503: 98/03/19: Re: Looking for space qualified FPGAs/ASICs
Randy Yates:
11739: 98/09/05: Re: professional autorouters
14274: 99/01/22: Re: Can we get back to DSP again? Was Re: Who cares what DSP
19632: 00/01/04: Re: synthesis opportunities
66451: 04/02/19: Re: Dual-stack (Forth) processors
66624: 04/02/24: Re: Dual-stack (Forth) processors
87440: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software
87465: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software
87545: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software
87601: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software
87668: 05/07/28: Re: Best Practices to Manage Complexity in Hardward/Software
87708: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software
87739: 05/07/30: Re: Best Practices to Manage Complexity in Hardward/Software
89463: 05/09/15: Re: Looking for a DIgital Systems book with JPEG example code
<randy97>:
6935: 97/07/10: http://www.love.com
randyjg:
84968: 05/06/01: Re: how to use GCC compiler
RANGA REDDY:
51031: 02/12/27: RAMDAC implementation in FPGA
51071: 02/12/30: Re: RAMDAC implementation in FPGA
51131: 03/01/02: Re: Latch inferring : Async OR Sync ?
51369: 03/01/12: schematic to VHDL conversion???
69979: 04/05/25: SDRAM
69984: 04/05/26: SDRAM controller
70292: 04/06/11: Re: SDRAM
<ranjeeta.patil@gmail.com>:
81866: 05/04/02: EDK:Question regarding opb_uart
rao:
105107: 06/07/13: issue on on using Xilinx PROMS in conjugation with System ACE;
105818: 06/08/01: Re: Information requested on FPGAs and ARM evaluation boards
114160: 07/01/05: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114169: 07/01/05: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
115797: 07/02/20: Re: Xilinx MIG DDR2 Documentation
Raoul:
57951: 03/07/10: XILINX COREGEN FFT CORE 2.0
raph:
90863: 05/10/24: SoC Processor design at gate level for edu
raphael:
100287: 06/04/06: ddr in virtex2
Raphael BELLEC:
4737: 96/12/09: Fpga, Epld, cpld....
raphfrk:
122279: 07/07/25: verilog parser question about `defines
122582: 07/07/31: Re: verilog parser question about `defines
Raquette Eric:
2024: 95/10/03: Re: FPGA for a 20k gates micro-controller.
raravan:
17046: 99/06/27: Re: newbie -- What's the best way to get started?
<rarteaga@gmail.com>:
84048: 05/05/11: Slice Virtex II = Equivalent gates ??
Ras Sim:
35571: 01/10/10: I need free PCI-Core (vhdl)!!
Rascal:
23456: 00/06/26: Xilinx XC5200 implementation with F2.1i
23490: 00/06/27: Re: First time user Spartan problem