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Authors (R)
R A Felton:
13286: 98/11/24: Report problems
R Allen:
35670: 01/10/13: Re: Block RAMs
R Sefton:
28166: 00/12/23: spartan-II power supply sequencing problem
29811: 01/03/12: Re: Again Spartan II power
29831: 01/03/13: Re: Again Spartan II power
R! Tafas Jr:
104173: 06/06/20: Re: Google FPGA Designer beta release
R!SC:
77282: 05/01/03: problem with edk
77307: 05/01/04: LEON2 or microblaze
77889: 05/01/19: jvm on microblaze
82349: 05/04/11: xilinx virtex 4 download cable
84917: 05/06/01: problem with edk 7.1
<r-m-w@web.de>:
103236: 06/05/29: JTAG in-system programming of PROM devices
r. bansal:
1512: 95/07/06: VHDL/FPGAs/PLDs help
R. Colin Johnson:
6511: 97/05/29: Convener, where are you?
R. D. Davis:
2515: 95/12/22: Re: [q][Reverse Engineering Protection]
R. Hofman:
132407: 08/05/26: How to update a row and a column at the same clock cycle?
R. Lamberts:
9413: 98/03/11: Announcing: Open Design Circuits
R. Mark Gogolewski:
9203: 98/03/02: Re: The case for Linux and EDA
9244: 98/03/04: Re: The case for Linux and EDA
9255: 98/03/05: Re: The case for Linux and EDA
9261: 98/03/05: Re: The case for Linux and EDA
9288: 98/03/05: Re: The case for Linux and EDA
17299: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
17306: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
R. Scheuerer:
7834: 97/10/21: Save your 49c402 microcode investment
R. T. Finch:
22214: 00/05/02: new2fpga
22476: 00/05/09: Xilinx Student Edition 1.5 License.dat
22527: 00/05/11: Re: Xilinx Student Edition 1.5 License.dat
22804: 00/05/25: Verilog assignment
23009: 00/06/08: Re: Xilinx foundation Student Edition problem.
23473: 00/06/26: Re: Different ?
23501: 00/06/27: Re: Different ?
23523: 00/06/28: Re: I cant stand it any more.
24250: 00/08/01: clock quadrupling
R. T. Wurth:
5223: 97/01/31: Re: Steven K. Knapp - no such article
6546: 97/06/02: Re: New Reconfigurable Computing newsgroup?
<r.fridolin@gmx.de>:
140493: 09/05/14: XILINX license model restricts longtime availability
<r.kinkead@gmail.com>:
91908: 05/11/16: Lattice XP flash memory access.....
91925: 05/11/16: Re: Lattice XP flash memory access.....
<(r.m.muench+ieee.org)>:
5660: 97/03/05: Re: What kind of functions mostly implemented using FPGAs?
R.Sriram:
36029: 01/10/26: Bi directional pin
51015: 02/12/26: Interested in FPGA design
R.W. DeHoedt:
5922: 97/03/26: Re: BIT SERIAL MULTIPLY
<ra_arce@yahoo.com>:
79968: 05/02/27: Resource (FMAPs) use when using block RAMs
Raanan:
13314: 98/11/25: Synchronous SRAM design wanted
<raarce@gmail.com>:
103017: 06/05/24: Report for routing resource usage?
Raban:
131312: 08/04/18: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
<rabbiaqamar@yahoo.com>:
129082: 08/02/13: i need ur help
129083: 08/02/13: i need fpga board with 10 Gig interface and pcie interface
RAcoops:
41830: 02/04/09: Xilinx Prototype Platforms
41836: 02/04/09: Re: Xilinx Prototype Platforms
radarman:
89514: 05/09/16: Looking for info on the V8/Arclite MicroRISC 8-bit core
90050: 05/10/03: Re: for...generate loop with generics, constants (vhdl)
96942: 06/02/13: Problem programming Altera flex 10k100 & EPC2
96985: 06/02/14: Re: Problem programming Altera flex 10k100 & EPC2
96989: 06/02/14: Re: is there a way to initialize signals to a value
98637: 06/03/13: Coregen in ISE 8.1i webpack not working quite right
98693: 06/03/14: Re: Coregen in ISE 8.1i webpack not working quite right
99035: 06/03/19: Re: Support software for XC3042
99234: 06/03/21: Re: Support software for XC3042
99352: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
100067: 06/04/02: Re: Hierarchical FSM?
100613: 06/04/13: Re: Spartan 3E Starter Kit is finally here!
100791: 06/04/18: Re: PLD610
100870: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
100871: 06/04/19: =?iso-8859-1?q?Re:_ow_to_connect_FPGA_and_=B5C?=
100872: 06/04/19: Re: C# and Spartan 3 Starter Kit
100887: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
100908: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
101011: 06/04/24: Re: Reliability CPLD/FPGA vs Microcontroller
101532: 06/05/02: Re: RESET pin on NIOS II processor
101954: 06/05/08: Re: Spartan 3e starter kit & Multimedia
101959: 06/05/08: Re: Xilinx 3s8000?
101990: 06/05/09: Re: Spartan 3e starter kit & Multimedia
102006: 06/05/09: Re: Xilinx 3s8000?
102050: 06/05/09: Re: Xilinx 3s8000?
102073: 06/05/10: Re: Xilinx 3s8000?
102670: 06/05/18: Spartan 3e sample: pack power control with M(1)?
102735: 06/05/19: Re: Spartan 3e sample: pack power control with M(1)?
102782: 06/05/20: Re: Why do the electronics manufacturers have to spam me?
102811: 06/05/21: Re: JTAG chaining of two different Xilinx Spartan 3E boards
103125: 06/05/25: Altium Livedesign eval boards - can you add a configuration prom?
103189: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103436: 06/06/01: XIlinx 7.1i ISE problem with Spartan 3e design
103443: 06/06/01: Re: XIlinx 7.1i ISE problem with Spartan 3e design
103465: 06/06/02: Problem with Xilinx ISE 7.1i core generator
103497: 06/06/04: Re: Problem with Xilinx ISE 7.1i core generator
103653: 06/06/07: Re: Anyone with Xilinx SP305-board ?
103766: 06/06/10: Re: Anyone with Xilinx SP305-board ?
104370: 06/06/26: Re: newbie wants to do VHDL on an FPGA
104604: 06/06/30: Re: How to control the uart
104605: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104617: 06/07/01: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104640: 06/07/03: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104742: 06/07/05: Re: "Large" memory array in VHDL
105017: 06/07/11: Re: Development Boards -Your chance to suggest features
105421: 06/07/22: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105466: 06/07/24: Re: Hardware book like "Code Complete"?
105480: 06/07/24: Re: Hardware book like "Code Complete"?
105728: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
106004: 06/08/04: How to implement large ROM's from binary sources?
106070: 06/08/07: Re: verilog versus vhdl
106342: 06/08/11: Re: Dio5 interface with ps2 port
106513: 06/08/14: Any interest in a v8 uRISC/Arclite clone?
106576: 06/08/15: Re: Alternative for Mentor''s HDL Designer
106688: 06/08/17: Re: Alternative for Mentor''s HDL Designer
106807: 06/08/19: Re: Speed vs Area Optimisation
106853: 06/08/21: Re: CPU design
106901: 06/08/22: Re: CPU design
106902: 06/08/22: Re: CPU design
108164: 06/09/06: Re: Qestion about the ability of synthesis
108301: 06/09/07: Re: Qestion about the ability of synthesis
108306: 06/09/07: Re: Synchronous Clocks
108309: 06/09/07: Re: Why No Process Shrink On Prior FPGA Devices ?
108393: 06/09/10: Re: Can a FPGA work like a microprocessor ?
108613: 06/09/13: Re: Spartan3E availability
108637: 06/09/14: Re: uclinux on spartan-3e starter kit
108918: 06/09/19: Re: USB programming cables
109095: 06/09/20: Re: Old vs. New FPGAs
109855: 06/10/06: Re: Spartan 3 Starter Kit I/O ports
109951: 06/10/08: Re: Antifuse, lower cost?
109979: 06/10/09: Re: Antifuse, lower cost?
110012: 06/10/09: Re: Quartus II 6.0: System clock has been set back
110089: 06/10/10: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
110116: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110166: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110167: 06/10/11: Re: Antifuse, lower cost?
110227: 06/10/12: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
111398: 06/11/02: Re: EDK software development
111461: 06/11/03: Re: digilent spartan-3 board sram timing
111493: 06/11/03: Re: reset
112319: 06/11/20: Parallax Stratix Smartpack accessories?
112342: 06/11/20: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112373: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
113001: 06/12/04: Can you configure an Altera Stratix without the nStatus line?
113005: 06/12/04: Re: Can you configure an Altera Stratix without the nStatus line?
113042: 06/12/05: Re: Can you configure an Altera Stratix without the nStatus line?
113476: 06/12/14: Re: what are your current SoC design for ?
113899: 06/12/28: Re: ChipScope - impact on design or not?
113902: 06/12/28: Re: moving from xlinx 8.1 to 8.2 or better wait ?
113937: 06/12/29: Re: ChipScope - impact on design or not?
113942: 06/12/29: Re: ChipScope - impact on design or not?
113944: 06/12/29: Re: moving from xlinx 8.1 to 8.2 or better wait ?
114678: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
115178: 07/02/01: EDK tri-state control
116041: 07/02/28: Can write, can't read with OPB_SPI 1.00e
116050: 07/02/28: Re: Can write, can't read with OPB_SPI 1.00e
117273: 07/03/27: (Xilinx) OPB watchdog timer fails to release RESET
117426: 07/03/30: Re: (Xilinx) OPB watchdog timer fails to release RESET
117501: 07/04/02: Does the XC3S250E-VQ100 exist?
117587: 07/04/04: Re: Does the XC3S250E-VQ100 exist?
118783: 07/05/03: Re: Unused Pin setting on per-pin basis
118793: 07/05/03: Re: Unused Pin setting on per-pin basis
119010: 07/05/09: Re: ML405 LCD
120700: 07/06/13: Re: custom peripheral registers
120754: 07/06/15: Re: Stolen Spartan 3E-1600 Development Board
121523: 07/07/06: Re: I need relocate my program outside bram...
121718: 07/07/11: Flex 10k100 & EPC2 redux - forgot the special ingredient?
126245: 07/11/17: Altera webpack for Linux?
126306: 07/11/19: Re: Altera webpack for Linux?
128118: 08/01/15: Re: Where has Xilnet gone?
129319: 08/02/20: Interrupt Handler page missing in from software platform settings in
130126: 08/03/15: Re: ISSI SRAM.
130981: 08/04/07: Modify POF with new ESB (ROM) content?
131063: 08/04/09: Re: Disable optimisation - Ring oscillator
132151: 08/05/15: Re: xilinx spi core question (microblaze)
136959: 08/12/15: Re: Terasic DE1 board commentary
140530: 09/05/15: Cheap Ethernet PHY boards?
140641: 09/05/20: Re: Cheap Ethernet PHY boards?
140874: 09/05/27: Cyclone III == Spartan ?
140950: 09/05/30: Re: Cyclone3 and AT45DB serial flash
140958: 09/05/31: GMII pinning issue
141213: 09/06/11: Re: XILINX WEB SERVER DEMO
141319: 09/06/17: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141597: 09/06/29: Re: usefulness of Virtex-II devices
144732: 09/12/29: Re: EPCS vs SPI Flash
145003: 10/01/19: Re: working with ADC and DAC together
146158: 10/03/06: Re: Actel is now the only FPGA vendor with hard-core processor in the
146726: 10/03/26: PCB routing issues for sync SRAM
146761: 10/03/27: Re: PCB routing issues for sync SRAM
146803: 10/03/29: Re: PCB routing issues for sync SRAM
146809: 10/03/29: Re: PCB routing issues for sync SRAM
147417: 10/04/26: Re: Quartus II under Windows7?
147738: 10/05/20: Re: I'd rather switch than fight!
147816: 10/05/25: Re: Last Xilinx Webpack that was big-brother free?
Radboud Verberne:
23158: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
<raderrl@my-deja.com>:
17527: 99/08/06: Xilinx vs. Lucent vs. XX FPGA comparison
19228: 99/12/07: tool command language (TCL)
Radha:
135681: 08/10/12: Good reference for Static Timing Analysis
RADHIKA:
29334: 01/02/14: Re: XILINX FPGA programming through JTAG
radhika:
29305: 01/02/13: Configuration of FPGA using SPROM
29308: 01/02/13: Configuration of FPGA using SPROM
29339: 01/02/14: Re: Configuration of FPGA using SPROM
29386: 01/02/17: Re: Configuration of FPGA using SPROM
29387: 01/02/17: Re: Configuration of FPGA using SPROM
29427: 01/02/20: Re: Configuration of FPGA using SPROM
Radioman:
90837: 05/10/22: Re: MAC Architectures
RadioShox:
109839: 06/10/06: Instantiating Altera M4K block without MegaWizard
Radosalw Gasiorek:
17122: 99/07/01: 82XX INTEL
Radoslaw Gasiorek:
20827: 00/02/23: IEC 1131-3 i NEED HELP
Radoslaw Mitura:
44876: 02/07/03: Jtag extest
Radó Zoltán:
35515: 01/10/09: VHDL code
35849: 01/10/20: I search a free 8086 core...
Rafa:
83550: 05/05/03: JTAG without parallel port
Rafael:
134174: 08/07/28: code for slipway + abits
Rafael Antunes Nobrega:
45692: 02/08/01: FPGA needed
Rafael Arce:
80091: 05/03/01: Re: Resource (FMAPs) use when using block RAMs
Rafael Deliano:
124353: 07/09/19: Re: FPGA history
130268: 08/03/19: Re: A Challenge for serialized processor design and implementation
Rafael Gadea Girones:
18472: 99/10/26: BlockRAM of VIRTEX
rafael plonka:
35009: 01/09/17: Altera Quartus II: Ouput skew ;-(
35391: 01/10/02: Implementation of Quartus Megafunctions in Mentor HDS???
35854: 01/10/21: Re: Verilog vs. VHDL
36362: 01/11/07: Re: FPGA BGA and decoupling
36813: 01/11/21: Re: Altera & Actel prices
<rafaelcns@gmail.com>:
90215: 05/10/06: matrix inversion in hardware
Rafal Jastrzebski:
73794: 04/09/29: Re: what to do with the DCM locked signal?
Rafal Kielbik:
15156: 99/03/10: LUT
<rafeeqs@excite.com>:
19080: 99/11/27: Re: Virtex: Getting flip-flops into the pads
Rafiki Kim Hofmans:
3112: 96/04/04: addressing PCI-interface
3201: 96/04/24: so little posts about PCI :(
3239: 96/05/02: Mr. Holmes D.
3295: 96/05/10: socket wanted for xilinx or other way to plug in
3360: 96/05/20: Re: PCI fpga
3420: 96/05/28: how to use memgen
3783: 96/07/31: assigning LOC in XACT
3857: 96/08/09: XACT:error301 with flow engine
3876: 96/08/13: Re: XACT:error301 with flow engine
3890: 96/08/15: XACT6.0:prosim and routed design
3909: 96/08/18: Re: XACT6.0:prosim and routed design
3964: 96/08/26: XC4010E en downloading bitstream
4027: 96/09/04: Re: Xilinx Foundation w/64Mb RAM
4055: 96/09/06: Re: PCI Bus Protocal & FPGA vendors
4070: 96/09/07: Re: Help with XACT 6.0 ProSim Problem
4331: 96/10/16: xc4000 and 2 clocks
Raghavendra:
61211: 03/09/30: Re: Implementing Bidirectional pins
65435: 04/01/29: what is back annotation
65436: 04/01/29: Power extimation?
69098: 04/04/27: Re: ASIC RTL and FPGA RTL
75162: 04/10/27: Re: unstable fpga design
74461: 04/10/11: DCM for generating higher frequencies.
77159: 04/12/26: Doubt on DDR SDRAM read/write operation sequence.
77405: 05/01/06: Refresh rate in DDR-SDRAM
Raghavendra G Jorapur:
3605: 96/07/03: Re: LCA to Schematic
3718: 96/07/21: Re: FPGA - RAM interfacing
3793: 96/08/02: Re: assigning LOC in XACT
raghu:
110843: 06/10/24: Please Help
140424: 09/05/13: Connect two bidirectional pins in FPGA
Raghu:
110632: 06/10/18: Learner
<raghunandan85@gmail.com>:
131572: 08/04/25: PLB Master Example
131679: 08/04/28: Re: PLB Master Example
131846: 08/05/03: Re: PLB Master Example
132389: 08/05/25: EDK 10.1 Map Error
132432: 08/05/27: Re: EDK 10.1 Map Error
132433: 08/05/27: Re: XILINX core generator question
132473: 08/05/28: Re: EDK 10.1 Map Error
132923: 08/06/10: Re: Cheating the FPGA clock speed
<raghurash@rediffmail.com>:
87067: 05/07/14: Re: ise 7.1 Input clk is never used.
ragon:
17718: 99/08/27: Short path check in Virtex M2.1i
Ragu:
134219: 08/07/31: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
Rah:
51227: 03/01/07: Spartan II:Bidirectional IO interfacing 5V CMOS ?
Rahul:
52057: 03/01/29: Huffman Encoder and Decoder in verilog/ vhdl
rahul joshi:
47333: 02/09/24: querries regarding cpld
Rahul Khanna:
64113: 03/12/16: What is this ASMBL thing from Xilinx?
RAI:
126648: 07/11/28: Re: An error occured while using Dual Port Block Memory
Rai:
141773: 09/07/08: Multipliers and CORDIC cores
141798: 09/07/09: Re: Multipliers and CORDIC cores
141800: 09/07/09: Re: Multipliers and CORDIC cores
141806: 09/07/10: Re: Multipliers and CORDIC cores
141842: 09/07/12: Re: Multipliers and CORDIC cores
Rain One:
48838: 02/10/25: PCI burst reads w/ Spartan
Rainer Becker:
7908: 97/10/29: Configuration of XC4000 FPGAs with JTAG
27000: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5
26999: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5a
Rainer Buchty:
26883: 00/11/02: Re: OT: Xilinx T-Shirt
57556: 03/07/02: Re: Xilinx ISE drops support for more parts
57644: 03/07/03: Re: Xilinx ISE drops support for more parts
66741: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
67834: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
75757: 04/11/14: Re: Obsolete processors resurected in FPGAs
75766: 04/11/14: Re: Obsolete processors resurected in FPGAs
82692: 05/04/16: Re: Xilinx tools on Linux
82694: 05/04/16: Re: salary ballpark please guys
82873: 05/04/19: Re: salary ballpark please guys
95018: 06/01/20: Re: OT:Shooting Ourselves in the Foot
97224: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
97234: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
98092: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
101293: 06/04/28: Re: Opteron HT coprocessors
104968: 06/07/11: Programming the Spartan-3E Starter Kit using Linux?
105031: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
121728: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121997: 07/07/17: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
129731: 08/03/04: Re: my Spartan-4 wishlist
139458: 09/03/30: Re: Toolchain for programming Mach211SP PLD.
141659: 09/07/02: Re: FPGA as FM RADIO transmitter
142465: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142472: 09/08/12: Re: Spartan-6 Boards - Your Wish List
143047: 09/09/17: 82S153 Fuse Map / Disassembler
143054: 09/09/17: Re: 82S153 Fuse Map / Disassembler
143079: 09/09/18: Re: 82S153 Fuse Map / Disassembler
143098: 09/09/20: Re: 82S153 Fuse Map / Disassembler
Rainer Dorsch:
14867: 99/02/21: Re: Free circuit design
Rainer M. Malzbender:
2173: 95/10/25: US-CO-Boulder Digital Designer (EE) Job Opening
2999: 96/03/11: US-CO-Digital Hardware Designers Wanted
Rainer Malzbender:
594: 95/01/14: FPGA tools that run on SGI ?
1478: 95/06/27: OrCAD support for Xilinx 5200 series ??
1766: 95/08/29: Re: Actel PCI App Note
1927: 95/09/20: Re: Fast FPGA's?
Rainer Scharnow:
3496: 96/06/11: Xtal Osc. at XC31xxA
3510: 96/06/12: Re: Xtal Osc. at XC31xxA
3554: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3686: 96/07/15: Atmel EEPROMs 17C65: again
3687: 96/07/15: Re: Atmel EEPROMs 17C65: again
3689: 96/07/16: Re: Atmel EEPROMs 17C65: again
3714: 96/07/19: IMPORTANT! ATMEL 17C65
3767: 96/07/29: Re: Question about books for FPGA
3804: 96/08/05: Re: Question about books for FPGA
4107: 96/09/11: XChecker and WinNT or OS/2
Rainer Schmidt:
52360: 03/02/07: Partial Reconfiguration - Virtex-E
52370: 03/02/07: Re: Partial Reconfiguration - Virtex-E
53798: 03/03/24: Difference between static and active partial reconfiguration of Xilinx
Rainer Storn:
29983: 01/03/20: Book on FPGA-Design with Xilinx chips
29984: 01/03/20: Packing density of Xilinx FPGAs
Rainier:
101561: 06/05/03: How to open an ISE 8.1 project in ISE 7.1?
rAinStorms:
34922: 01/09/14: Help!
54368: 03/04/09: Re: Altera not supplying Leonardo any more
54402: 03/04/10: Altera Serial Configuration - ST Serial Flash?
54893: 03/04/22: Re: Complex FIR in FPGA
54894: 03/04/22: Re: spartan2e vs cyclone
54917: 03/04/22: Re: spartan2e vs cyclone
64422: 04/01/04: Re: please help! state machine
67301: 04/03/10: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
67314: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67527: 04/03/14: Re: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
Raintech Consulting Limited:
29982: 01/03/20: Jobs....?
Raivo Nael:
65092: 04/01/20: Re: WTD: info on AMD palce22v10
65258: 04/01/22: Re: WTD: info on AMD palce22v10
65278: 04/01/23: Re: WTD: info on AMD palce22v10
65438: 04/01/29: Is FPGA fully static?
67343: 04/03/10: Re: licence for Xilinx 2.1i
raj:
69116: 04/04/27: Xpower Static Current
69283: 04/05/04: synthsizing multi-dimensional array XST
69481: 04/05/11: VHDL-Verilog Co-Simulation
69641: 04/05/16: load on a clock signal in FPGA
70253: 04/06/10: Reading Back Configuration of Slice/LUT
71661: 04/07/26: configuration SRAM cells in Xilinx/Altera FPGAs
71693: 04/07/27: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71729: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
72617: 04/08/26: Re: Xilinx Command Prompt
89073: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
133513: 08/07/01: real time FIR implementation in FPGA
133519: 08/07/02: Re: real time FIR implementation in FPGA
133539: 08/07/03: synthesis in xilinx
133806: 08/07/16: unified protocol
133817: 08/07/16: Re: unified protocol
133839: 08/07/17: Re: unified protocol
133895: 08/07/18: Re: unified protocol
136587: 08/11/23: distributed dual port RAM with asynchronous read in ACTEL Smartgen
137215: 09/01/03: time limited netlist generation
137228: 09/01/04: Re: time limited netlist generation
Raj B Krishnamurthy:
24159: 00/07/27: compact PCI Xilinx virtex FPGA card
Raj Kumar Nagarajan:
51361: 03/01/11: Re: MicroBlaze MDK2.2 opb_timer
Raj Nagarajan:
63718: 03/12/01: Re: debugging microblaze with xmd
Raj Patel:
3728: 96/07/22: Xilinx XC6200 Information
raja:
20039: 00/01/25: global clock distribution
20090: 00/01/27: CARRY CHAIN CIRCUIT in ORCA 3T
20175: 00/01/30: Re: Xilinx vs Altera
20566: 00/02/15: Re: LUT & VHDL
21249: 00/03/14: Re: Testbench for a modulator and a demodulator
Raja Neogi:
2437: 95/12/05: final call for paper (ICSE'96)
rajan:
65551: 04/02/02: Comparison of the Co-verification tools for SoC/ASIC
<rajashekar_798@yahoo.com>:
94836: 06/01/18: xilmfs on flash
94894: 06/01/18: Re: xilmfs on flash
94912: 06/01/19: Re: xilmfs on flash
94981: 06/01/19: Re: xilmfs on flash
Rajat Karol:
43699: 02/05/29: Engineering Samples for free?
43784: 02/06/02: Engineering Samples for free?
Rajeev:
46633: 02/09/04: Viewing Xilinx netlist
46670: 02/09/05: Re: Viewing Xilinx netlist
46706: 02/09/06: Re: Viewing Xilinx netlist
46708: 02/09/06: Re: Viewing Xilinx netlist
46937: 02/09/12: Xilinx LogicCore Pipelined Divider Clock Cycles
46938: 02/09/12: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
46972: 02/09/13: Re: 2-D resistor array
47157: 02/09/19: Re: GCLK pin used like an standard input
47165: 02/09/19: Re: VHDL : Lookup Table
47439: 02/09/25: Virtex2 Block Multiplier: Faster, Faster
47465: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
47483: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
47817: 02/10/04: Re: Finding nets in hierarchy
48379: 02/10/16: Standing on the shores of Stratix-land
48582: 02/10/21: Re: Standing on the shores of Stratix-land
48650: 02/10/22: Re: Transferring Design from XILINX --> ALTERA
48855: 02/10/25: Re: Please recommend a FPGA chip!
48857: 02/10/25: 3.3V Device Programmer Suggestions ?
48971: 02/10/28: Re: 3.3V Device Programmer Suggestions ?
49046: 02/10/30: Re: 3.3V Device Programmer Suggestions ?
53921: 03/03/27: Tristate pins + Inputs => External Pullup ?
54197: 03/04/04: Re: Xilinx Divider Core
54200: 03/04/04: Re: Spartan vs. Cyclone for arithmetic functions
54203: 03/04/04: Re: PCI specification
54286: 03/04/07: Re: Tristate pins + Inputs => External Pullup ?
54326: 03/04/08: Re: price of fpga chips
54477: 03/04/11: Buying FPGAs from parts brokers
54563: 03/04/14: Re: Buying FPGAs from parts brokers
54566: 03/04/14: Re: 2.5V switching regulator for Spartan 2
54714: 03/04/16: Re: 2.5V switching regulator for Spartan 2
59387: 03/08/18: Altera JTAG verification
59434: 03/08/19: Re: Altera JTAG verification
59500: 03/08/20: Re: Altera JTAG verification
67647: 04/03/16: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
67703: 04/03/17: Re: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
67704: 04/03/17: Re: Answering Machine RAM
67749: 04/03/18: Re: clock rising edge alignment
67814: 04/03/19: Altera DSP Builder
67959: 04/03/23: Re: Apparent Altera Cyclone JTAG problem
68095: 04/03/26: Re: study verilog or vhdl?
68171: 04/03/28: Re: counter design
68238: 04/03/30: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
68246: 04/03/30: Re: FIFO Depth(Length) Calculation
68282: 04/03/31: Re: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
68446: 04/04/05: VHDL: Use of literal '1' on an input port ?
68494: 04/04/06: Re: Quartus removes Tristate Buffer
68495: 04/04/06: Re: VHDL: Use of literal '1' on an input port ?
68641: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68648: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68716: 04/04/15: Re: Yet Another Altera Online Support Is USELESS Rant...
68718: 04/04/15: Re: System Generator HDL co-simulatin problem
68860: 04/04/20: Re: Trouble with rising edge signals in functional simulation
68886: 04/04/21: Re: What does a "background check" mean? ...
68887: 04/04/21: Re: Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...
68933: 04/04/22: Re: calculate the number of logic gate in FPGA
69322: 04/05/06: Re: costal loop question
69438: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69621: 04/05/15: Re: best fpga development board?
69942: 04/05/25: Re: Driving fpga pin out over long cable
70143: 04/06/04: Re: VHDL test bench in Quartus
70210: 04/06/09: Re: comp.arch.fpga: reset strategy
70363: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
70373: 04/06/14: Stratix DSP Block: Choosing which FFs are enabled
70422: 04/06/16: Re: Stratix DSP Block: Choosing which FFs are enabled
70649: 04/06/22: Re: Initializing data in EAB ram
70674: 04/06/23: Re: Trying to remember how to use Quartus
70949: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
71019: 04/07/05: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71068: 04/07/07: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71138: 04/07/09: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71226: 04/07/12: Re: Same bitstream files give different behavior.
71286: 04/07/13: Re: extending a signal pulse
71773: 04/07/29: Re: FPGA vs CPLD
71806: 04/07/30: Re: FPGA vs CPLD
72967: 04/09/09: Re: vhdl error ?? - [code included]
81186: 05/03/18: Re: Which HDL?
81191: 05/03/18: Re: LVDS as general differential input ?
81192: 05/03/18: Re: Spartan 3 to tempsensor interface
81193: 05/03/18: Re: Using DSP Builder with Quartus
81739: 05/03/30: Re: LVDS as general differential input ?
108679: 06/09/14: ispDesignExpert available for download anywhere ?
108692: 06/09/15: Re: ispDesignExpert available for download anywhere ?
108733: 06/09/15: Re: ispDesignExpert available for download anywhere ?
108965: 06/09/19: Re: VHDL oddity
109986: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
129570: 08/02/27: Using dma_sg_v2_01_a component with plb_ipif
rajeev:
104513: 06/06/28: NCO Clock driven Designs in FPGA
Rajeev Jayaraman:
25351: 00/09/07: Re: Slow routing of PWR/GND (Virtex)
35504: 01/10/08: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
42430: 02/04/23: Re: Maximum Usage in a Virtex FPGA
67879: 04/03/21: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000 FPGA.
Rajeev Mishra:
15745: 99/04/11: URGENT! Need VHDL code for ADPCM decompression on Xilinx FPGA
rajendra:
70524: 04/06/18: Programming FPGA in Xilinx Virtex 2 pro board
114269: 07/01/10: ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
Rajendra:
104141: 06/06/19: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
rajendra k singh:
72390: 04/08/17: linux on virtex 2 pro board
72414: 04/08/18: Re: linux on virtex 2 pro board
rajesh:
137126: 08/12/24: Generation of WR and RD signal for ASYNC FIFO
137136: 08/12/27: Re: Generation of WR and RD signal for ASYNC FIFO
137160: 08/12/29: Re: Generation of WR and RD signal for ASYNC FIFO
Rajesh Bawankule:
29394: 01/02/19: Verilog FAQ : February 2001
30358: 01/04/04: Verilog FAQ: April 2001
31633: 01/06/01: Verilog FAQ: June 1, 2001
32170: 01/06/17: Verilog FAQ : Jun 17, 2001
32597: 01/07/01: FAQ: Verilog FAQ : July 1, 2001
32658: 01/07/04: Third issue of Chip-Guru is ready: July 2001
49400: 02/11/11: FAQ: Verilog FAQ : November 15, 2002
Rajesh Gandhi:
142320: 09/08/04: AES encryption of bitstream - is my design secure?
142324: 09/08/04: Re: AES encryption of bitstream - is my design secure?
142325: 09/08/04: Re: AES encryption of bitstream - is my design secure?
142326: 09/08/04: Re: AES encryption of bitstream - is my design secure?
142328: 09/08/04: Re: AES encryption of bitstream - is my design secure?
142334: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142342: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142354: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142369: 09/08/06: Re: AES encryption of bitstream - is my design secure?
142370: 09/08/06: Re: AES encryption of bitstream - is my design secure?
142453: 09/08/11: Re: AES encryption of bitstream - is my design secure?
142454: 09/08/11: Re: AES encryption of bitstream - is my design secure?
Rajesh Kumar E.V:
33631: 01/08/01: VIRTEX E FPGA Configuration through SelectMap
Rajesh Murugesan:
67250: 04/03/09: How to use BUFGMUX in SPARTAN 2 device????
67251: 04/03/09: Reg..How to use BUFGMUX in Spartan 2 family
69392: 04/05/10: Can I use an internal reset signal in DLL?
69680: 04/05/18: DLL - Change in input frequency (CLKIN)
69922: 04/05/24: Re: DLL - Change in input frequency (CLKIN) ---help needed
70061: 04/06/01: DLL- Change in input clock source --Suggestions plz
Rajesh Pathak:
68976: 04/04/23: Verilog RTL of a Galois Field Multiplier
rajesh52:
23182: 00/06/16: Verilog FAQ
<rajesh52@hotmail.com>:
13774: 98/12/24: Version 8 of Verilog FAQ released
14150: 99/01/15: Re: Verilog Book --- Me too!
14569: 99/02/04: Re: Verilog ROM Models
14757: 99/02/15: Verilog FAQ
14769: 99/02/16: Verilog FAQ
14974: 99/03/01: Verilog FAQ
15225: 99/03/15: Verilog FAQ
16100: 99/05/03: Verilog FAQ
16660: 99/06/01: Verilog FAQ
17295: 99/07/19: Verilog FAQ
17483: 99/07/30: Verilog FAQ.
17632: 99/08/16: Verilog FAQ
17887: 99/09/15: verilog FAQ
17996: 99/09/22: Re: FPGA Compiler II/FPGA Express User's Manual
18330: 99/10/15: Verilog FAQ
19141: 99/12/02: Re: HDL editor?
19142: 99/12/02: Verilog FAQ
19911: 00/01/17: Verilog FAQ
20603: 00/02/16: Verilog FAQ
22205: 00/05/01: Verilog FAQ
25206: 00/08/30: Verilog FAQ
28327: 01/01/07: FYI: chip-guru online chip design magazine
28947: 01/01/30: Verilog FAQ : Jan 2001
<rajesh52@my-dejanews.com>:
14089: 99/01/12: Re: programming language interface
14322: 99/01/25: Re: Needed: PCI interface
<rajesh@comit.com>:
6580: 97/06/04: Alternate Verilog FAQ : New release
7870: 97/10/26: Verilog FAQ version 5 released
8114: 97/11/18: Free verilog models , examples
9889: 98/04/11: Verilog FAQ version released
10108: 98/04/27: Alt. Verilog FAQ released.
10312: 98/05/11: Re: available eda environments
11303: 98/08/03: Verilog FAQ Version 7 published
11304: 98/08/03: Verilog FAQ Version 7 published
<rajesh@NoSPAM-1606.comit.com>:
8731: 98/01/22: Re: MAX+II software from Altera.
<rajeshobli@yahoo.co.in>:
133447: 08/06/29: FIR filter with integer coefficients
Rajeshwary:
62585: 03/11/02: Spartan II with Digilab board, IO communication
62731: 03/11/05: ISE : Synthesis process hangs
rajiv:
68896: 04/04/21: liberary component
120215: 07/06/03: Synchronization of instruction with clock
121546: 07/07/07: verilog code for read write in Bram block
121557: 07/07/08: verilog code for read write in bram block
121579: 07/07/09: Adding a bram block to a user defined bram controller
<rajivc53@gmail.com>:
120705: 07/06/14: c code to initialize a peripheral
121448: 07/07/04: read/write in bram block
Rajkumar:
128415: 08/01/24: Re: How to choose an FPGA for High speed applications
128580: 08/01/31: Re: I need a SDRAM controller
135815: 08/10/16: Re: Xilinx SPI PROM programming via JTAG
Rajkumar Kadam:
119442: 07/05/19: Re: How do I constraint multiple clock cycle in Altera?
<rajkumar@gdatech.com>:
12137: 98/10/01: Re: Which FPGA tool is better
22099: 00/04/22: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
25399: 00/09/09: Re: Mealy vs Moore FSM model
rajsinghdua:
141401: 09/06/23: Interfacing microblaze with External RAM
raju:
116139: 07/03/02: Re: Where can i get free CAN VHDL core
<raju.penum@gmail.com>:
116071: 07/02/28: Where can i get free CAN VHDL core
raju_lingala:
97305: 06/02/20: SDRAM Reading problem
Rajul Maheshwari:
16841: 99/06/14: site for reconfigurable computing
RaKa:
87129: 05/07/15: Re: Why cann't this block be synthesized in top level
116211: 07/03/04: Ideas for Masters Project.
126029: 07/11/13: Asynchronous FIFO Latency.
rakesh:
90517: 05/10/15: Problem with Xilinx Impact under windowsXP
Rakesh Sharma:
74008: 04/10/02: How to generate a signal on Xilinx Spartan II
74901: 04/10/21: Xilinx translate error : Cannot find signal "clk"
Rakesh YC:
71134: 04/07/09: configuration for a mixed mode VHDL-verilog lang
Ralf:
43794: 02/06/03: Lattice Synario Service Pack
84535: 05/05/20: ALTERA EPXA1 SDRAM BUG
Ralf =?iso-8859-1?Q?Oberl=E4nder?=:
30239: 01/03/29: Encryption Bitstrems
30706: 01/04/25: Failed to configure Spartan2
Ralf A. Eckhardt:
28687: 01/01/21: xc95108 funny behaviour
28691: 01/01/21: Re: xc95108 funny behaviour
28717: 01/01/22: Re: xc95108 funny behaviour
28730: 01/01/22: Re: xc95108 funny behaviour
42527: 02/04/26: Re: XC9500XL problem
48947: 02/10/28: Re: cpld I/O modes
Ralf Duschef:
82529: 05/04/13: Re: "The ISE 7.1 Experience"
Ralf Hildebrandt:
42963: 02/05/08: Re: State machine synthesis
49439: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
51174: 03/01/05: Re: conversions and some assistance please
55777: 03/05/19: Re: about simulation
56847: 03/06/17: Re: An All Digital Phase Lock Loop
57006: 03/06/20: Re: Quartus bug or wrong VHDL?
57480: 03/07/01: Re: FPGA vs. DSP.
59921: 03/09/01: Re: What does + synthesize to?
65227: 04/01/22: Re: How can I have multiple drivers of one inout port?
66550: 04/02/22: Re: Comparator and minimum value address
66558: 04/02/22: Re: Comparator and minimum value address
69695: 04/05/18: Re: std_logic_vector vs unsigned
82964: 05/04/20: Re: Unconstrained ports for synthesis
92761: 05/12/06: Re: Info on packing regular tree-like structures into rectangles?
97973: 06/03/02: Re: Help wanted
97982: 06/03/02: Re: Help wanted
98681: 06/03/14: Re: VHDL
98728: 06/03/15: Re: About Altera FPGA Board
98787: 06/03/16: Re: About Altera FPGA Board
98789: 06/03/16: Re: Urgent Help Needed!!!!!
98870: 06/03/17: Re: About Altera FPGA Board
98873: 06/03/17: Re: Urgent Help Needed!!!!!
98969: 06/03/18: Re: Microblaze FSL peripheral problem
98976: 06/03/18: Re: Urgent Help Needed!!!!!
99001: 06/03/18: Re: About Altera FPGA Board
99133: 06/03/20: Re: Urgent Help Needed!!!!!
99359: 06/03/23: Re: XST takes unusually long
99441: 06/03/24: Re: XST takes unusually long
99611: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
100250: 06/04/05: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
100414: 06/04/08: Re: Compiler to FPSLIC
100484: 06/04/10: Re: How to handle the high fanout
101437: 06/05/01: Re: Question about the ip I developed
101710: 06/05/05: Re: RFID chip has battary in it or not
101828: 06/05/07: Re: flashing a led
102328: 06/05/15: Re: difference of variable and signal
104216: 06/06/21: Re: xst can, but vcomp can't
104282: 06/06/22: Re: xst can, but vcomp can't
104316: 06/06/23: Re: xst can, but vcomp can't
104317: 06/06/23: Re: stimulus for FPGA
104340: 06/06/24: Re: stimulus for FPGA
105090: 06/07/13: Re: how to implement multi-port memory
105677: 06/07/28: Re: Verilog case statements
105681: 06/07/28: Re: Verilog case statements
105711: 06/07/29: Re: Verilog case statements
105712: 06/07/29: Re: "This design element is inferred rather than instantiated" (newbie)
105770: 06/07/31: Re: Verilog case statements
105899: 06/08/02: Re: generating sine-like waveforms
106011: 06/08/05: Re: How to implement large ROM's from binary sources?
106080: 06/08/07: Re: verilog versus vhdl
106356: 06/08/12: Re: Embedded clocks
106357: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
106917: 06/08/22: Re: hex format 16 bit?
107815: 06/09/01: Re: Higher voltages input, quick check....
108274: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108936: 06/09/19: Re: BUF component
109294: 06/09/23: Re: please tell me how to learn testbench?
110684: 06/10/19: Re: Meeting Timing Constraint
111540: 06/11/05: Re: Integration of modules
112755: 06/11/28: Re: pre-synthezis simulation in ModelSim for Actel
112829: 06/11/29: Re: pre-synthezis simulation in ModelSim for Actel
112832: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
112833: 06/11/29: Re: FPGA application field
112892: 06/11/30: Re: FPGA application field
112950: 06/12/02: Re: FPGA application field
113920: 06/12/29: Re: SPI slave problem
114494: 07/01/17: Re: Process on both edges
114568: 07/01/19: Re: Generation of Divided-by-3 clock
115887: 07/02/23: Re: porting virtex2-pro into virtex4. Performance!!
115888: 07/02/23: Re: 2x technique
116287: 07/03/06: Re: VHDL and Latch
116766: 07/03/17: Re: What official function should I call to genertate a sum of products
117737: 07/04/09: Re: Clocking data into a shift register on positive AND negative
118016: 07/04/16: Re: combinatorial vs sequential
119027: 07/05/09: Re: 'EVENT (or rising_edge) static prefix requirement....
120212: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than
122052: 07/07/18: Re: Latches
122067: 07/07/18: Re: or1200 uses more than 100% of resources. how to reduce?
122142: 07/07/20: Re: Counter ?
123693: 07/09/02: Re: flip-flop enable
128046: 08/01/14: Re: sine and cosine wave generation
129313: 08/02/20: Re: From ASIC RTL to FPGA, what are the things I should take care
144153: 09/11/14: Re: An incomplete Mux and Latch?
144726: 09/12/29: Re: fsm coding question
147689: 10/05/16: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
Ralf Koehler:
6271: 97/05/07: universal PCI-Interface with FPGA?
Ralph:
47597: 02/09/30: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
93911: 06/01/03: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94143: 06/01/06: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
ralph:
42402: 02/04/23: Re: Post-synthesis simulation
94061: 06/01/05: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
Ralph Friedrich:
27871: 00/12/13: Configuration : XC4000
87335: 05/07/21: Re: General-purpose STAPL Composer?
Ralph Hartley:
109491: 06/09/27: Re: An algorithm with Minimum vertex cover without considering its
Ralph Malph:
64523: 04/01/06: Re: Spartan3 availability
64637: 04/01/09: Re: Anybody know what the REAL story is? Jim figured it out.
64649: 04/01/10: Re: Anybody know what the REAL story is? Jim figured it out.
64670: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
64680: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
64681: 04/01/11: Re: Spartan3 prices again...
64703: 04/01/11: Re: Altera Cyclone data is incomplete or messy
64721: 04/01/12: Re: fpga database?
64814: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64815: 04/01/14: Re: Open source ARM, Version 0.1
64828: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64833: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64901: 04/01/15: Re: Spartan-IIE as an ASYNC RAM?
64943: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
65059: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65060: 04/01/19: Re: Spartan3 prices again...
65062: 04/01/19: Re: Which version of ISE Webpack has FPGA Editor on it?
65063: 04/01/19: Re: WTD: info on AMD palce22v10
65064: 04/01/19: Re: QUES: Where can I find Xilinx M1 tools
65177: 04/01/21: Re: WTD: info on AMD palce22v10
65222: 04/01/22: Re: WTD: info on AMD palce22v10
65224: 04/01/22: Re: Soft failures (?) 9536XL
65252: 04/01/22: Re: OT: liability insurance
65253: 04/01/22: Re: xilinx 70% tracking rule
65256: 04/01/22: Re: Why is router software not multi-threaded?
65263: 04/01/22: Re: WTD: info on AMD palce22v10
65311: 04/01/24: Re: WTD: info on AMD palce22v10
65312: 04/01/24: Re: xilinx 70% tracking rule
65406: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65412: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
Ralph Mason:
20184: 00/01/30: Which FPGA to learn with?
32169: 01/06/18: Verilog or VHDL?
48595: 02/10/22: Newbie Questions - Jan Gray XSOC
48614: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
48642: 02/10/22: Webpac Simulation
48680: 02/10/23: Re: Webpac Simulation
48683: 02/10/23: Re: Webpac Simulation
48685: 02/10/23: Re: Newbie Questions - Jan Gray XSOC
48883: 02/10/26: #1's in verilog
48921: 02/10/27: Couple of Questions
49025: 02/10/30: Re: filters on fpgas
49165: 02/11/04: Learner ? - Open Collector in Verilog
49264: 02/11/07: Instruction sets to implement instruction sets
49324: 02/11/09: Re: Instruction sets to implement instruction sets
49423: 02/11/12: Re: CLB numbers for various ops?
49658: 02/11/19: Some Basic Understanding - RTL
50207: 02/12/05: Re: ISA bus VGA
50370: 02/12/10: Tiny Forth Processors
50421: 02/12/11: Re: Tiny Forth Processors
50448: 02/12/11: Re: Tiny Forth Processors
50960: 02/12/24: Re: Combinatorial clock source question
51975: 03/01/28: Re: GNU C for custom processor
52403: 03/02/08: XC9536XL - ISP
52536: 03/02/13: Setting CPLD options (Webpac)
52965: 03/02/27: xc9500 Low power mode
52991: 03/02/28: Re: xc9500 Low power mode
53272: 03/03/10: Re: Clocking a spartanIIE with a 5V signal?
53602: 03/03/18: Re: new XC95xx global clock
53610: 03/03/18: Re: new XC95xx global clock
53820: 03/03/25: Re: Xilinx FPGAs available?
54065: 03/04/02: Re: XC9572XL Macrocell power
54073: 03/04/02: Re: XC9572XL Macrocell power
54110: 03/04/03: Re: XC9572XL Macrocell power
55108: 03/04/27: Re: Xilinx of Linux HOWTO has been updated
55526: 03/05/12: Re: help on FPGA-programming tutorial for students
55578: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55695: 03/05/16: Re: smallest embedded cpu.
55697: 03/05/16: Re: smallest embedded cpu.
55714: 03/05/17: Re: smallest embedded cpu.
55929: 03/05/24: Re: CLKDLL: Dividing
55966: 03/05/25: Re: Newbie CPLD question
55967: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
56036: 03/05/28: Re: 2 Questions about VHDL
56058: 03/05/28: Re: FIFO Controller
56090: 03/05/29: Re: FIFO Controller
56163: 03/05/30: FPGA's an Flash
56177: 03/05/30: Re: FPGA's an Flash
56433: 03/06/05: Re: Xilinx Block RAM
56747: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
57295: 03/06/27: Xlilin xc9572XL Default register values
57302: 03/06/27: Re: Xlilin xc9572XL Default register values
57378: 03/06/29: Re: Xlilin xc9572XL Default register values
57403: 03/06/30: Re: Xlilin xc9572XL Default register values
57441: 03/07/01: Re: Xlilin xc9572XL Default register values
57402: 03/06/30: Re: Xlilin xc9572XL Default register values
57582: 03/07/03: Re: Xlilin xc9572XL Default register values
59154: 03/08/11: Re: FPGA for a Newcomer
59161: 03/08/11: Re: Upgrading OS or WebPack
60068: 03/09/05: Re: New to FPGA, seeking advice
62439: 03/10/30: Re: Xilinx Spartan3: Price
62694: 03/11/05: Re: FPGA Prototyping Board
62878: 03/11/11: Re: Home grown CPU core legal?
Ralph Reinhold:
6911: 97/07/08: Re: Generating Sine/Cosine digitally
Ralph Remme:
3076: 96/03/27: Re: LOG/iC Installation Problem
3312: 96/05/13: Re: Looking for free FPGA softw./Xilinx
Ralph Watson:
1925: 95/09/20: Re: Anyone using Altera 8820A ?
2464: 95/12/08: Re: Median filter
3384: 96/05/23: Re: Fitting problems with Altera MAX9560
Ralph Weir:
20882: 00/02/25: Re: MRP systems
30109: 01/03/23: Re: Virtex Em on a board?
30363: 01/04/04: Re: DSP Volume-control in FPGA
ralphie:
110392: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110395: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
ralstef:
115184: 07/02/01: DDR SDRAM controller for virtex 2 pro
Ram:
60214: 03/09/08: FPGA: Interfacing external NVRAM
60819: 03/09/23: PPC access to PROM using Virtex @ pro
60923: 03/09/24: on the fly Reconfig
68083: 04/03/25: Re: xilinx PPC map file
78712: 05/02/06: problem with xilinx platform studio 6.2i
78792: 05/02/07: Re: problem with xilinx platform studio 6.2i
78849: 05/02/08: virtex4 distributed RAM
78861: 05/02/09: Beginner: running EDK 6.3 in linux
78897: 05/02/09: Re: Beginner: running EDK 6.3 in linux
78902: 05/02/09: Re: virtex4 distributed RAM
78903: 05/02/09: Re: virtex4 distributed RAM
78906: 05/02/09: Re: virtex4 distributed RAM
88947: 05/09/01: FS: Lot of 60 XCV1000 FPGAs
88978: 05/09/01: Re: Lot of 60 XCV1000 FPGAs
89287: 05/09/11: Which JTAG cable for Xilinx & Linux?
89318: 05/09/12: ISE 7.1i & Linux / reg code question
89321: 05/09/12: Microblaze & Memory DMA operation
89348: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89349: 05/09/13: Re: Microblaze & Memory DMA operation
89367: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89370: 05/09/13: Re: Microblaze & Memory DMA operation
89555: 05/09/19: Re: Reading a PAL fusemap with a microscope
89591: 05/09/20: ISE 7.1i & Linux / reg code question
89870: 05/09/28: Re: a ISE installation problem on linux
89871: 05/09/28: Pricing for V2-Pro / V4-FX ?
89872: 05/09/28: Req to Xilinx: eCos port for Microblaze
90004: 05/10/01: Re: Req to Xilinx: eCos port for Microblaze
91402: 05/11/05: Re: FPGA : PCI-CORE
ram:
8212: 97/11/29: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
12651: 98/10/21: Re: Schematic entry?
14454: 99/01/30: Re: No. of CLBs in Xilinx nearly 100% can't implement.
60043: 03/09/04: Memory
60094: 03/09/04: Re: Memory
61052: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61910: 03/10/14: Re: Universities that focus on IC design
61912: 03/10/14: Partial Reconfiguration
61916: 03/10/14: Partial/ Dynamic Reconfiguration Virtex 2 pro- does it have any help at all
61918: 03/10/14: Re: Xilinx "Programming failed" message
61932: 03/10/15: Re: newbie linker script question
61986: 03/10/15: Re: Partial Reconfiguration
62015: 03/10/16: Re: explain the vhdl code
62016: 03/10/16: xilinx System ACE solution
62099: 03/10/19: Re: To our future engineers, smart and otherwise...
62216: 03/10/22: PPC boot
62219: 03/10/22: EMC/SDRAM
62451: 03/10/29: Questions that question????
62555: 03/11/01: Re: data recorder examples?
62981: 03/11/11: Re: How to visit the files in CF cards
63208: 03/11/17: Re: How to visit the files in CF cards
64437: 04/01/04: System Ace - Flash card formatting
64838: 04/01/14: Re: Can i get a sample XSVF file?
64840: 04/01/14: Re: Microblaze simulation
65161: 04/01/21: EDK - Desinging system with C++
65334: 04/01/24: Re: Spirit on Mars
65995: 04/02/10: Building a NN using FPGA
66060: 04/02/11: Re: Xilinx Platform Flash Prom
66061: 04/02/11: Re: XC2V2000 + System Ace + Reconfig
66522: 04/02/20: Re: Power supply for the Xilinx Virtex Pro FF1152 Proto Board
66828: 04/02/26: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
66996: 04/03/02: V2pro + A/D + IrDA + RS232 board???
66997: 04/03/02: Re: Xilinx iMPACT error: "Done did not go high"
67489: 04/03/12: Re: System Ace: can not program Avnet V2P7 board
67533: 04/03/13: Re: Virtex 2 P -> PPC write to block RAM
67534: 04/03/13: Re: any body help me about xc4010e board
67557: 04/03/14: Board with all modules
67733: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67734: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67860: 04/03/21: Re: What's the flow V2P SysAce handles the software inside the ACE file
68027: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
68034: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
68160: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
68311: 04/03/31: Re: Virtex 2 PRO Eval/Development platforms
68313: 04/03/31: newbie - TCP/IP
68643: 04/04/12: system C - streams C
68960: 04/04/22: Re: FPGA within demonstration
68961: 04/04/22: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68962: 04/04/22: Re: liberary component
68963: 04/04/22: Re: documents
69202: 04/04/29: Re: basic question, virtex 2 pro
69207: 04/04/29: Is this a best approach- FPGA ANN
69361: 04/05/07: OPB IPIF user logic
70342: 04/06/13: Re: Xilinx .bit to .svf...
71219: 04/07/12: Re: Need some help regarding dynamic reconfiguring of the pin connections
72345: 04/08/16: Re: Using SDRAM on Xilinx AFX V2P board
75473: 04/11/06: what's the scenario out there
112350: 06/11/20: timing constraints
112351: 06/11/20: timing constraints
112482: 06/11/22: query
112530: 06/11/24: types of FPGA
112574: 06/11/24: query
112575: 06/11/24: query
112631: 06/11/26: query in constraining timing
112638: 06/11/26: Re: query in constraining timing
112639: 06/11/26: Re: query in constraining timing
112643: 06/11/26: Re: query in constraining timing
112653: 06/11/27: tips for P&R in FPGA(quartus)
112869: 06/11/30: help
112947: 06/12/01: Hi
113014: 06/12/05: Re: Hi
113071: 06/12/05: query in gate level simulationin quartus s/w 6.0
113200: 06/12/07: query regarding capacitance of pins of cyclone device
113466: 06/12/14: query
113506: 06/12/14: Query
113507: 06/12/14: Re: Query
115242: 07/02/04: query in P&R of FPGA
115243: 07/02/04: Re: query in P&R of FPGA
116187: 07/03/03: regarding power and timing
116315: 07/03/07: Re: A Very good VLSI Chip design website
117710: 07/04/08: query
121338: 07/07/02: cosimulation
122474: 07/07/28: query in byte blaster/signal topic logic analyser
Ram Meenakshisundaram:
17554: 99/08/10: Newbie - what are the limitations of the student edition
17556: 99/08/10: Emulating a transputer on FPGA
17565: 99/08/10: Re: Emulating a transputer on FPGA
19868: 00/01/14: XACT where is it??
Ram Prabhakar:
6595: 97/06/04: Re: Alternate Verilog FAQ : New release
Ramakrishnan:
45753: 02/08/04: Controller for a Architecture
45789: 02/08/05: Re: Controller for a Architecture
45805: 02/08/06: Re: Controller for a Architecture
45947: 02/08/12: Reconfiguration in Xilinx FPGA
45958: 02/08/12: Re: Reconfiguration in Xilinx FPGA
45981: 02/08/13: Re: Reconfiguration in Xilinx FPGA
46091: 02/08/17: Re: Reconfiguration in Xilinx FPGA
46104: 02/08/19: onboard reconfiguration of Xilinx FPGA
46125: 02/08/19: Re: onboard reconfiguration of Xilinx FPGA
46155: 02/08/20: Re: onboard reconfiguration of Xilinx FPGA
46241: 02/08/22: Downloading bit streams in Xilinx
46272: 02/08/23: Re: Downloading bit streams in Xilinx
93156: 05/12/14: Xst Error
<ramakrishnan.vijayakumar@gmail.com>:
111151: 06/10/30: Programming Virtex II Pro Eval Board
Raman Arora:
38405: 02/01/14: Re: speech recognition - active noise cancellation
Raman Narayan:
24007: 00/07/20: Re: 104 Page Collective DAC'00 Trip Report Up
Ramanathan:
27772: 00/12/07: Test Bench
Ramanathan S:
29687: 01/03/05: URGENT HELP REQ......
Rambutwa Gooberundi:
9492: 98/03/18: Re: Xilinx XACT 6.01 crack
ramesh:
95646: 06/01/24: porting linux on ml403
96588: 06/02/07: Re: porting linux on ml403
97031: 06/02/15: can i use gcc of EDK?
Ramesh C. Tekumalla:
5468: 97/02/18: Re: Mealy/Moore state machines
Ramesh Narayanaswamy:
2597: 96/01/10: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
7133: 97/08/04: Re: Simulating large VHDL design (FPGA backannotated)
<ramesh_z@my-deja.com>:
22914: 00/06/02: view synthesis 7.0
23086: 00/06/14: ASIC DESIGN
23657: 00/07/04: silicon
Rami:
26042: 00/10/01: Begineer
Rami Gideoni:
7614: 97/09/28: Re: vme vs compact pci
7615: 97/09/28: Re: vme vs compact pci
Raminder S Bajwa:
982: 95/04/06: Re: Aptix (Field Programmable Interconnect) ??
1048: 95/04/20: VMEbus interface using fpgas
Ramnath:
35851: 01/10/20: Xilinx Libraries
35852: 01/10/20: Fpga Synthesis Process
35859: 01/10/21: FPGA based IPv6 router -- hi
36522: 01/11/10: Reconfigrable Routers
36868: 01/11/22: Re: Viewing generated VHDL
36888: 01/11/23: Re: Fpga Synthesis Process
37483: 01/12/12: Constraints Some basics
37539: 01/12/13: Relation between net delay & Period
ramshankar:
33233: 01/07/19: foundation series 2.1i
Ramtilak:
71182: 04/07/11: Need some help regarding dynamic reconfiguring of the pin connections
71514: 04/07/20: Area constraint on a sub-module
72326: 04/08/14: Hardware/Software Communication in Virtex-2p
Ramy:
24516: 00/08/11: Re: Xilinx chip not programming correctly
24678: 00/08/16: Re: Xilinx chip not programming correctly
24679: 00/08/16: Permanently programming FPGAs
ramy:
24484: 00/08/10: Help with Xilinx
79546: 05/02/20: does anyone have a c compiler for the picoblaze
79547: 05/02/20: Re: Question about microblaze C complier
79688: 05/02/23: Re: C compiler for Picoblaze
ran:
77058: 04/12/21: MAP failes after inserting ILA and ICON cores to the design
77093: 04/12/21: Re: MAP failes after inserting ILA and ICON cores to the design
77111: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design
77442: 05/01/06: Re: MAP failes after inserting ILA and ICON cores to the design
rana:
140947: 09/05/30: time constraining asynchronous fifo
147996: 10/06/11: how to interface a ddr2 memory controller to a processor
148001: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
148002: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
ranbow:
64051: 03/12/14: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64086: 03/12/15: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64115: 03/12/17: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64137: 03/12/18: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
Randal Kuramoto:
37625: 01/12/17: Re: ISP by JTAG using a microcontroller
45221: 02/07/16: Re: Spartan PROMs...
Randall Holman:
45110: 02/07/12: PCMCIA host
Randall Logan:
14043: 99/01/08: Anyone have an Altera LP6 interface card FS?
<randallchaas@sbcglobal.net>:
129538: 08/02/27: Re: Viewing RTL schematic in Xilinx ISE
<randombit@my-deja.com>:
19640: 00/01/05: Re: Design security
19641: 00/01/05: Re: Design security
19642: 00/01/05: Re: Design security
randomdude@gmail.com:
82271: 05/04/10: A PCI FPGA card I found on ebay
82276: 05/04/10: Re: A PCI FPGA card I found on ebay
82288: 05/04/10: Re: A PCI FPGA card I found on ebay
84364: 05/05/17: VHDL array question
84376: 05/05/18: Re: VHDL array question
84395: 05/05/18: Re: VHDL array question
<randomdude@gmail.com>:
121032: 07/06/22: Reshipping spartan3 PCIE board to England
121064: 07/06/24: Re: Reshipping spartan3 PCIE board to England
122289: 07/07/25: Re: Beginners question
122763: 07/08/06: Re: Need suggestion for my project
134786: 08/08/31: FPGA on a DIMM module, performing encryption
134788: 08/08/31: Re: FPGA on a DIMM module, performing encryption
134798: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134802: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134824: 08/09/02: Re: FPGA on a DIMM module, performing encryption
<randraka@ids.net>:
452: 94/11/21: RE: Looking for VHDL & VIEWLOGIC FPGA Experts/Consult
568: 95/01/06: RE: Fpga programming
579: 95/01/10: Lee Fadden, what is your address?
595: 95/01/15: Re: ViewLogic simulation without master reset
617: 95/01/19: Re: ViewLogic simulation without master reset
629: 95/01/23: Re: ViewLogic simulation without master reset
677: 95/02/03: re:Inefficiency(?)
681: 95/02/05: Re: "on-fly" reprogrammable devices/research
729: 95/02/18: Re: Can I implement a digital PLL in an FPGA??
776: 95/02/28: Re: Can I implement a digital PLL in an FPGA??
786: 95/03/02: Re: Can I implement a digital PLL in an FPGA??
800: 95/03/03: RE: FPGA Custom Computing Machine
836: 95/03/09: Re:FPGA bit serial multipliers, correction
1095: 95/04/27: Re: Need help about conference chip
1185: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1310: 95/05/31: Re: Any company for conversion FPGA to ASIC?
1535: 95/07/11: RE: Xilinx 5200 Software
1646: 95/08/10: RE: Xilinx FPGAs ---> Xilinx EPLDs
1689: 95/08/16: Re: Xilinx xc4013 routing problems ??
1884: 95/09/15: Re: Fast FPGA's?
1926: 95/09/20: Re: Fast FPGA's?
<randraka@my-dejanews.com>:
13026: 98/11/12: Re: placement&routing problems
randy:
138603: 09/03/01: timequest error
138991: 09/03/18: PLL inclk error
Randy:
32606: 01/07/02: Re: Converting character to integer in VHDL
Randy Bickford:
8549: 98/01/07: seeking example for PWM using PLDs
Randy Bolling:
704: 95/02/10: Asset
38605: 02/01/18: Re: VirtexII ES configuration
38606: 02/01/18: Re: I2C multiplexer
Randy Given:
23973: 00/07/19: Experts-Exchange
Randy Nachtrieb:
27800: 00/12/08: FS: ADVICE RTOS In Circuit Emulator
Randy Robinson:
9989: 98/04/21: Re: Xilinx FPGAs: Usable Pins on XS Boards (Help)
10330: 98/05/12: Re: How to use LogiBlox Components in FPGA Express?
10385: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
10386: 98/05/15: Re: Xilinx FGA Express
14508: 99/02/02: Re: Opinions requested : Minc/Synario alternatives
14575: 99/02/04: Re: Synplify/Xilinx4085XLA question
17507: 99/08/03: Re: Xilinx Virtex configuration in chunks
113675: 06/12/19: Re: unexplainable Problem on Spartan 3
Randy Tietz:
4799: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
9503: 98/03/19: Re: Looking for space qualified FPGAs/ASICs
Randy Yates:
11739: 98/09/05: Re: professional autorouters
14274: 99/01/22: Re: Can we get back to DSP again? Was Re: Who cares what DSP
19632: 00/01/04: Re: synthesis opportunities
66451: 04/02/19: Re: Dual-stack (Forth) processors
66624: 04/02/24: Re: Dual-stack (Forth) processors
87440: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software
87465: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software
87545: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software
87601: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software
87668: 05/07/28: Re: Best Practices to Manage Complexity in Hardward/Software
87708: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software
87739: 05/07/30: Re: Best Practices to Manage Complexity in Hardward/Software
89463: 05/09/15: Re: Looking for a DIgital Systems book with JPEG example code
132732: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132809: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132825: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132861: 08/06/09: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
135669: 08/10/11: Re: XMOS XC-1 kits are shipping
141764: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
146738: 10/03/26: Multipliers in CoolRunner Series?
146739: 10/03/26: Re: Multipliers in CoolRunner Series?
146747: 10/03/27: Re: Multipliers in CoolRunner Series?
146754: 10/03/27: Re: Multipliers in CoolRunner Series?
146755: 10/03/27: Re: Multipliers in CoolRunner Series?
146759: 10/03/27: Re: Multipliers in CoolRunner Series?
146766: 10/03/28: Maximum output rate
146784: 10/03/28: Re: Maximum output rate
146816: 10/03/29: Re: Maximum output rate
148083: 10/06/19: Xilinx DCM Block Stability Issues
148085: 10/06/19: Re: Xilinx DCM Block Stability Issues
148092: 10/06/21: Re: Xilinx DCM Block Stability Issues
148093: 10/06/21: Re: Xilinx DCM Block Stability Issues
148095: 10/06/21: Re: Xilinx DCM Block Stability Issues
148110: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
<randy97>:
6935: 97/07/10: http://www.love.com
randyddr:
141786: 09/07/08: Virtex 4 and 5
randyjg:
84968: 05/06/01: Re: how to use GCC compiler
RANGA REDDY:
51031: 02/12/27: RAMDAC implementation in FPGA
51071: 02/12/30: Re: RAMDAC implementation in FPGA
51131: 03/01/02: Re: Latch inferring : Async OR Sync ?
51369: 03/01/12: schematic to VHDL conversion???
69979: 04/05/25: SDRAM
69984: 04/05/26: SDRAM controller
70292: 04/06/11: Re: SDRAM
<ranjeeta.patil@gmail.com>:
81866: 05/04/02: EDK:Question regarding opb_uart
rao:
105107: 06/07/13: issue on on using Xilinx PROMS in conjugation with System ACE;
105818: 06/08/01: Re: Information requested on FPGAs and ARM evaluation boards
114160: 07/01/05: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114169: 07/01/05: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
115797: 07/02/20: Re: Xilinx MIG DDR2 Documentation
134994: 08/09/09: IDELAYCTRL Locking problem with ISE10.1i
135014: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
135382: 08/09/29: Problem with mpmc(4.02.a) simulation -- DDR never initializes
135387: 08/09/29: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
Raoul:
57951: 03/07/10: XILINX COREGEN FFT CORE 2.0
raph:
90863: 05/10/24: SoC Processor design at gate level for edu
136913: 08/12/12: BUFGMUX placement
136957: 08/12/15: Re: BUFGMUX placement
137011: 08/12/18: Re: LEON3 processor
137012: 08/12/18: Re: BUFGMUX placement
raphael:
100287: 06/04/06: ddr in virtex2
Raphael BELLEC:
4737: 96/12/09: Fpga, Epld, cpld....
raphfrk:
122279: 07/07/25: verilog parser question about `defines
122582: 07/07/31: Re: verilog parser question about `defines
Raquette Eric:
2024: 95/10/03: Re: FPGA for a 20k gates micro-controller.
raravan:
17046: 99/06/27: Re: newbie -- What's the best way to get started?
<rarteaga@gmail.com>:
84048: 05/05/11: Slice Virtex II = Equivalent gates ??
Ras Sim:
35571: 01/10/10: I need free PCI-Core (vhdl)!!
Rascal:
23456: 00/06/26: Xilinx XC5200 implementation with F2.1i
23490: 00/06/27: Re: First time user Spartan problem
23543: 00/06/29: Re: Xilinx XC5200 implementation with F2.1i
26440: 00/10/16: Re: PROM 17512
26491: 00/10/18: Re: source PROM 17512
26973: 00/11/06: Re: Need help locking pins for Spartan XL
Rashid:
105163: 06/07/16: An idea for a product (FPGA/ASIC based)
105165: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
Rashid Karimov:
37989: 01/12/28: Re: Look for FPGA Starterkit
38001: 01/12/29: Re: How to set block ram contents ?
<rashid.karimov@gmail.com>:
104272: 06/06/22: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
<rashidk@home.net>:
85152: 05/06/06: Re: Basics FPGA
rasic:
111996: 06/11/14: sending data across a 32 bit bus
raso:
104702: 06/07/04: ADPLL (50Hz to 2kHz)
105521: 06/07/25: 2Khz clock signal from 50Hz main frequency with ADPLL
105530: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105553: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105554: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105618: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
Rasquinha:
71304: 04/07/14: Quartus SOPC Builder doesnt Recgnize my .elf file
<rasti123@eunet.yu>:
62942: 03/11/11: Re: Reverse engineering an EDIF file?
Rastislav Struharik:
20143: 00/01/28: Spartan XL
62889: 03/11/10: Reverse engineering an EDIF file?
<rastr@lan.novsu.ac.ru>:
3412: 96/05/27: We can HELP ALTERA user for Remote_simulation projects E-mail:rastr@lan.novsu.ac.ru
rat:
69373: 04/05/09: is it possible to design usb only with fpga?
69524: 04/05/13: program flash memory through JTAG on FPGA
70032: 04/05/28: how can I merge 66mhz pci clock to 33mhz clock?
70773: 04/06/28: How to add clock delay in CPLD?
70786: 04/06/28: Re: How to add clock delay in CPLD?
70845: 04/06/30: a question in the pci interface design
70882: 04/07/01: Re: a question in the pci interface design
ratemonotonic:
124739: 07/10/02: Re: Basic VHDL Development kit
124750: 07/10/03: Re: Basic VHDL Development kit
125888: 07/11/08: P160 Communication Module 3
125890: 07/11/08: Re: P160 Communication Module 3
125935: 07/11/09: Re: P160 Communication Module 3
126939: 07/12/06: Using FSL with Interrupts
126975: 07/12/07: Re: Using FSL with Interrupts
127129: 07/12/12: Newbee Microblaze system BRAM utlization confusion
127184: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127185: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127186: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127253: 07/12/15: Re: Newbee Microblaze system BRAM utlization confusion
127639: 08/01/04: XPS MPMC
127643: 08/01/04: Re: XPS MPMC
127676: 08/01/05: MPMC On EDK
127677: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
127730: 08/01/06: Re: MPMC On EDK
127756: 08/01/07: Re: MPMC On EDK
127919: 08/01/10: XAPP924 Doesnt work
127979: 08/01/11: opb_emc_v1_10_b
128000: 08/01/12: Re: opb_emc_v1_10_b
128003: 08/01/12: Re: opb_emc_v1_10_b
128004: 08/01/12: Re: XAPP924 Doesnt work
128034: 08/01/14: Where has Xilnet gone?
128207: 08/01/18: Re: Where has Xilnet gone?
128941: 08/02/11: FSL version compatability with Microblaze version
131299: 08/04/18: New to FPGA : Timing Closure
132181: 08/05/16: Resetting FPGA Without watch dog timer
132227: 08/05/19: Re: Resetting FPGA Without watch dog timer
132228: 08/05/19: Re: Resetting FPGA Without watch dog timer
132252: 08/05/19: Re: Resetting FPGA Without watch dog timer
132381: 08/05/24: Microblaze Cache and FSL problem
Rathna Rao:
22089: 00/04/20: jobs
ratztafaz:
130272: 08/03/19: ISE 10.0 finally with multi-threading and SV support ?
130284: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
130514: 08/03/26: Re: ISE 10.0 finally with multi-threading and SV support ?
raul:
89733: 05/09/23: Re: Modelsim XE, what's the latest version?
89735: 05/09/23: Re: Modelsim XE, what's the latest version?
90731: 05/10/19: Re: Best Async FIFO Implementation
90757: 05/10/20: Re: Best Async FIFO Implementation
90808: 05/10/21: Re: Best Async FIFO Implementation
92976: 05/12/10: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
<rauletta@erebor.cudenver.edu>:
8532: 98/01/05: ASIC 1998 CFP
8825: 98/01/29: 1998 DAC University Booth (First Call for Participation)
RaulGonz:
145468: 10/02/11: Actel FPGA corePWM IP
145493: 10/02/11: Re: Actel FPGA corePWM IP
raulizahi@gmail.com:
90852: 05/10/23: Re: Best Async FIFO Implementation
91075: 05/10/28: Re: locking hdl to a particular fpga
<raullim7@hotmail.com>:
125692: 07/11/01: can i use dual edge or two clocks?
125700: 07/11/01: Re: can i use dual edge or two clocks?
125732: 07/11/01: Re: can i use dual edge or two clocks?
125736: 07/11/02: Re: can i use dual edge or two clocks?
125784: 07/11/04: Global Variables
125855: 07/11/06: Time Delay in FPGA
125857: 07/11/07: FPGA Clock signal
125924: 07/11/08: Re: FPGA Clock signal
129450: 08/02/25: XEM3010
raven:
119598: 07/05/23: Xilinx ML405 / VxWorks 6.3 Bootloader
raven1322:
143373: 09/10/07: Re: Virtex 5 HDMI
Raven76:
70199: 04/06/08: handel-c library file
70269: 04/06/10: Xilinx Floorplanner
Ravi:
74535: 04/10/13: Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool
ravi:
11470: 98/08/17: Job opportunities in Bay area for ASIC/ FPGA designers / Application Engg.
Ravi Bhat:
21669: 00/03/28: Test: Please ignore...
54815: 03/04/18: test
Ravi Bhormish:
52269: 03/02/05: A forum for SystemC
Ravi Chandra Anantha:
19016: 99/11/24: Re: Hierarchical Scan Insertion
Ravi Ramakrishnan:
1838: 95/09/07: Re: verilog to fpga ?
2428: 95/12/04: Re: Vendors For Verilog On The PC
Ravi Sankar K.:
70450: 04/06/17: Synplify_pro
Ravi Singh:
18179: 99/10/05: Board Designers required
ravihma:
148211: 10/06/29: error in XPS
ravikumar:
24910: 00/08/21: urgent help fr a beginer
Ravindra Divekar:
2985: 96/03/08: x86 using FPGAs ..
3012: 96/03/13: 8085A using FPGAs....
ravindra kalla:
87759: 05/07/31: FPGA
87808: 05/08/01: circular read address generator
87900: 05/08/03: hi stefen
88045: 05/08/07: circular buffer(its urgent)
88195: 05/08/11: use of memory in verilog(uegent please)
92009: 05/11/19: input in spartan kit(its urgent)
92328: 05/11/27: hi
<ravipativishnu@yahoo.co.in>:
116671: 07/03/15: doubt in verilog coding
116679: 07/03/15: Re: doubt in verilog coding
116684: 07/03/15: Re: doubt in verilog coding
117112: 07/03/23: problem while using if or case statements
ravisguptaji:
143005: 09/09/14: Everything in single clock cycle.
143010: 09/09/14: Re: Everything in single clock cycle.
Ravishankar S:
121117: 07/06/26: Trace capturing
121119: 07/06/26: Amontec chameleon
121166: 07/06/27: Re: Trace capturing
121167: 07/06/27: Re: Amontec chameleon
121261: 07/06/29: Re: Trace capturing
<raxpeter@gmail.com>:
119997: 07/05/30: XS40 Download Cable
Ray:
22469: 00/05/10: Re: Xilinx fpga board schematics?
60283: 03/09/09: Power-on slope :Spartan IIE
114058: 07/01/03: FPGA ROUTING
114064: 07/01/03: Re: FPGA ROUTING
Ray Almond:
17859: 99/09/14: Opinions Wanted
Ray Anderson:
71675: 04/07/27: Re: New WinFilter Digital Filter design freeware tool release available.
Ray Andraka:
1979: 95/09/27: Re: FPGA for a 20k gates micro-controller.
2007: 95/10/01: Re: FFT in FPGAs ?
2303: 95/11/18: Re: Industry Trends
2331: 95/11/20: Re: [q][Reverse Engineering Protection]
2468: 95/12/09: Re: CRC-32 implementation
2490: 95/12/18: Re: Gated Clock Problem in Xilinx FPGA Implementation
2491: 95/12/18: Re: WAnted: correlator!!!!!
2492: 95/12/18: Re: WAnted: correlator!!!!!
2829: 96/02/13: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2908: 96/02/27: Re: Floating Point and Reconfigurable Architectures
2964: 96/03/07: Re: [NEWBIE] FPGA Project?
3087: 96/03/28: Re: Low-power FPGA or EPLD
3129: 96/04/09: Re: Q: Multiplier & Subtractor in Xilinx 5204 FPGA ?
3449: 96/06/01: Re: Xilinx and Viewlogic
3568: 96/06/26: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3582: 96/07/01: Re: REQ:Old Picture of Bus
3647: 96/07/08: Re: FPGA Companies
3698: 96/07/17: Re: What about the XC6200 ?
3699: 96/07/17: Re: What about the XC6200 ?
3700: 96/07/17: Hardware sort?
3819: 96/08/07: Re: Xilinx/FPGA Timing Problems
3960: 96/08/24: Re: XC6200 FPGAs
3978: 96/08/28: Re: USB Host Core for FPGA/Gate Array
4012: 96/09/03: Re: FPGA vs. Custom design
4064: 96/09/06: Re: FPGA design project
4104: 96/09/10: Re: FPGA design project
4139: 96/09/17: Re: How can I make my XILINX design faster?
4193: 96/09/24: Re: manchester clock recovery
4194: 96/09/24: Re: XilinX XC5200 address pointer based FIFO
4202: 96/09/25: Re: 4800 baud serial input to xc4000
4231: 96/10/02: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4252: 96/10/04: Re: Q on Xilinx/Viewsim macros
4253: 96/10/04: Re: Reconfigurable hardware
4310: 96/10/13: Re: Async with FPGA?
4345: 96/10/18: Re: What are I/O's doing prior to configuration?
4585: 96/11/18: Re: GEC Plessey, Toshiba, PlusLogic FPGAs?
4689: 96/11/29: Re: Reconfigurable FPGAs in Networking
4767: 96/12/12: Re: Anyone tried a FFT in a FPGA?
4778: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
4789: 96/12/15: Re: ASICs Vs. FPGA in Safety Critical Apps.
4825: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
4836: 96/12/18: Re: Help: FPGA for fast digital signal processing
4850: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
4851: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
5058: 97/01/17: Re: advice request
5103: 97/01/23: Altera PCI experience anyone?
5126: 97/01/24: Re: FPGA & division
5212: 97/01/30: Re: What is the different between FPGA and CPLD?
5228: 97/01/31: Re: Steven K. Knapp - no such article
5230: 97/01/31: Re: What is the different between FPGA and CPLD?
5231: 97/01/31: Re: Reconfigurable Logic Query
5336: 97/02/07: Re: FPGA power dissipation
5362: 97/02/10: Re: FPGAs with internal Tri-state busses ?
5377: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
5390: 97/02/12: Re: DES Challenge
5392: 97/02/12: Re: bonding of XC4025
5445: 97/02/16: Re: Mealy/Moore state machines
5571: 97/02/25: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
5699: 97/03/07: Re: Xilinx config pins M0..M2
5717: 97/03/10: Re: Xilinx FPGA & SIMMs
5850: 97/03/20: Re: Is this really possible?
5882: 97/03/22: Re: 8-bit divider in FPGA
5744: 97/03/11: Re: ACTEL RAM BASED FPGAs
6163: 97/04/20: Re: Exponential function architecture
6199: 97/04/24: Re: prep benchmarks for FPGAs
6220: 97/04/29: Re: Low power PLD?
6319: 97/05/14: Re: Anyone using Actel software?
6330: 97/05/15: Re: What's FPGA?
6370: 97/05/19: Re: Fast comparator
6600: 97/06/04: Re: New Reconfigurable Computing newsgroup?
6770: 97/06/26: Re: Any designs to avoid in FPGAs
6685: 97/06/13: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6686: 97/06/13: Re: Power consumption (Xilinx FPGA) questions
6716: 97/06/18: Re: Help, FPGA Information
6717: 97/06/18: Re: PC Keyboard Controller in a Xilinx...
6786: 97/06/27: Re: Generating Sine/Cosine digitally
6814: 97/06/30: Re: Smart Card Design and Interface. How?
6916: 97/07/08: Re: Generating Sine/Cosine digitally
6951: 97/07/14: Re: Generating Sine/Cosine digitally
6895: 97/07/07: Re: Does FAQ for this group exist? (empty)
7420: 97/09/08: Re: HELP: FIFO's on an FPGA
7425: 97/09/09: Re: HELP: FIFO's on an FPGA
7435: 97/09/10: Re: HELP: FIFO's on an FPGA
7624: 97/09/29: Re: fifos design for fpga
7715: 97/10/06: Re: bidirectional bus problem
7744: 97/10/09: Re: bidirectional bus problem
7797: 97/10/16: Re: I looked up Altera in an Italian dictionary.....
7798: 97/10/16: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
7814: 97/10/17: Re: Xilinx delay reports?
7815: 97/10/17: [Reposted due to Enlow UCE cancel]: Re: Xilinx delay reports?
7879: 97/10/26: Re: Xilinx Adder Trees in Viewlogic
7924: 97/10/30: Re: Pin compatible
7938: 97/11/01: Re: Complex Multiplier
7990: 97/11/05: Re: Digital reverberator on FPGA
8013: 97/11/07: Re: Digital reverberator on FPGA
8020: 97/11/07: Re: Division using FPGAs
8039: 97/11/10: Re: FPGA basics please ?
8071: 97/11/14: Re: Looking for dynamically reprogrammable FPGA's
8087: 97/11/16: Re: Oneshot for Atmel 6K series
8117: 97/11/19: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8135: 97/11/20: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8152: 97/11/21: Re: Dr watson & M1
8163: 97/11/23: Re: Need info on runtime configurable FPGAs
8164: 97/11/23: Re: what is metastability time of a flip_flop
8187: 97/11/25: Re: Q: Xilinx foundation V1.3 optimizes out my WHOLE design !?!?
8412: 97/12/12: Re: combinational multipliers
8588: 98/01/11: Re: Xilinx Stock
8678: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8691: 98/01/20: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8748: 98/01/23: Re: DSP vs FPGA
8760: 98/01/23: Re: ALtera Devices.
8839: 98/01/31: Re: VHDL vs schematics
8840: 98/01/31: Re: How to design 3-staged pipelined multiplier in VHDL for Xilinx 4000XL
8997: 98/02/12: Re: Walace tree???
9170: 98/02/27: Re: Correlation implementation...
9172: 98/02/27: Re: DES: beginner FPGA questions.
9173: 98/02/27: Re: PLL design with Xilinx 4kseries
9174: 98/02/27: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
9344: 98/03/06: Re: Correlation implementation...
9210: 98/03/02: Re: Correlation implementation...
9350: 98/03/06: Re: PLL design with Xilinx 4kseries
9211: 98/03/02: Re: Correlation--Multichannel
9345: 98/03/06: Re: Die Size Comparison of competing FPGAs
9505: 98/03/19: Re: Looking for space qualified FPGAs/ASICs
9549: 98/03/23: Re: Dual port
9608: 98/03/25: Re: Partially reconfigurable FPGA
9624: 98/03/26: Re: Dual port
9646: 98/03/27: Re: Q: Random number generator
9660: 98/03/28: Re: XactStep6 - The cure for a dongle
9705: 98/03/31: Re: Floating point representation in FPGA
9830: 98/04/08: Re: XactStep6 - The cure for a dongle
9888: 98/04/11: Re: XactStep6 - The cure for a dongle
9887: 98/04/11: Re: FLEX 10K : FPGA or CPLD
9991: 98/04/21: Re: Could you help me save CLB's?
10025: 98/04/22: Re: Arbiter help !!!
10045: 98/04/23: Re: XC4000XL and Ground Bouncing
10088: 98/04/26: Re: Make a delay in Xilinx FPGAs (more Details)?
10242: 98/05/06: Re: Arbiter help !!!
10211: 98/05/04: Re: DSP in an Altera or Xilinx?
10230: 98/05/05: Re: DSP in an Altera or Xilinx?
10231: 98/05/05: Re: Radix-4 CORDIC pipeline -- which chip?
10267: 98/05/08: Re: Xilinx Routing Delay
10456: 98/05/19: Re: Building signal delays inside an FPGA
10457: 98/05/19: Re: Minimal ALU instruction set.
10563: 98/05/29: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
10757: 98/06/16: Re: Wallace trees
10867: 98/06/26: Re: High Speed Digital Designers...
10868: 98/06/26: Re: synthesis and simulation
10870: 98/06/26: Re: Xilinx Foundation simulator problem?
10913: 98/06/30: Re: complete testing
10959: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10960: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10961: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10962: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10963: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10964: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11016: 98/07/10: Re: is the code for XC4000E burned on it or in EEPROM ?
11057: 98/07/15: Re: Shift Invarient Bit Transform
11058: 98/07/15: Re: Shift Invarient Bit Transform
11062: 98/07/16: Re: Shift Invarient Bit Transform
11065: 98/07/16: Re: Floorplanning Intro?
11072: 98/07/17: Re: Floorplanning Intro?
11076: 98/07/17: Re: Shift Invarient Bit Transform
11085: 98/07/17: Re: Floorplanning Intro?
11087: 98/07/17: Re: Partial reprogramming
11117: 98/07/20: Re: Xilinx Dynatext and NTFS ?
11122: 98/07/20: Re: Need info -> implementing high-speed multipliers
11123: 98/07/20: Re: Old Contace Information
11124: 98/07/20: Re: Partial reprogramming
11148: 98/07/21: Re: How to write a VHDL counter of up & down
11170: 98/07/22: Re: How to write a VHDL counter of up & down
11171: 98/07/22: Re: unknown speedgrade question
11172: 98/07/22: Re: unknown speedgrade question
11181: 98/07/22: Re: Schematic Symbol Generation
11294: 98/08/02: Re: how much ? prices of Xilinx chips
11319: 98/08/04: Re: [Q] motor control onto an FPGA
11337: 98/08/05: Re: [Q] motor control onto an FPGA
11338: 98/08/05: Re: fast 8x8-Multiplyer
11411: 98/08/11: Re: Security
11415: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
11432: 98/08/12: Re: Newbie seeks cheap fun w/FPGAs
11451: 98/08/14: Re: Combinatoric Divide-by-3 Algorithm
11452: 98/08/14: Re: FFT-Speed
11513: 98/08/20: Re: vector product minimization problem
11522: 98/08/20: Re: Video 256 colors interface HELP!
11525: 98/08/20: Re: half full flag in a xilinx async fifo?
11587: 98/08/25: Re: FPGA vendors
11588: 98/08/25: Re: half full flag in a xilinx async fifo?
11604: 98/08/26: Re: How to design a PLL
11638: 98/08/27: Re: half full flag in a xilinx async fifo?
11673: 98/08/30: Re: CPLD/FPGA software
11675: 98/08/31: Re: Video 256 colors interface HELP!
11681: 98/08/31: Re: A Johnson counter
11705: 98/09/02: Re: half full flag in a xilinx async fifo?
11768: 98/09/08: Re: Altera 10K20 Register File Implementation??
11792: 98/09/09: Re: 22V10 programming
11813: 98/09/10: Re: Xilinx Spartan vs. 4K series
11815: 98/09/10: Re: Need Permutation generator
11826: 98/09/11: Multiplication hardware
11914: 98/09/18: Re: sync or async SRAM?
11915: 98/09/18: Re: measuring junction temperature
11916: 98/09/18: Re: Design Security Question
11917: 98/09/18: Re: ASIC -> FPGA async issues
11929: 98/09/19: Re: sync or async SRAM?
11996: 98/09/23: Re: sync or async SRAM?
12005: 98/09/23: Re: Efficient max-function architecture?
12037: 98/09/25: Re: Design Security Question
12054: 98/09/25: Re: Efficient max-function architecture?
12055: 98/09/25: Re: Efficient max-function architecture?
12086: 98/09/28: Re: Faster 32_bit integer multiplier required !!
12098: 98/09/28: Re: Fastest Add
12116: 98/09/29: Re: Maxplus2 Timing Analyzer
12135: 98/09/30: Re: Fastest Add
12136: 98/09/30: Re: FIR Filter Design
12150: 98/10/01: Re: FIR Filter Design
12160: 98/10/01: Re: Fastest Add
12224: 98/10/05: Re: FIR Filter Design
12237: 98/10/06: Re: FIR Filter Design
12267: 98/10/07: Re: FIR Filter Design
12325: 98/10/08: Re: FIR Filter Design
12226: 98/10/05: Re: RAM Implementation in Altera Flex10K100A
12359: 98/10/09: Re: Xilinx may not support schematics for Virtex?????
12361: 98/10/09: Re: Help Desperately Needed with Altera Microprocessor Design.
12386: 98/10/10: Re: Help Desperately Needed with Altera Microprocessor Design.
12394: 98/10/11: Re: FIR Filter Design
12400: 98/10/11: Re: Xilinx may not support schematics for Virtex?????
12402: 98/10/11: Re: FIR Filter Design
12466: 98/10/12: Re: FOCUS FOCUS FOCUS (Xilinx not supporting viewlogic sim)
12467: 98/10/12: Re: Digital Sine Generator
12468: 98/10/12: Re: FPGA info..
12587: 98/10/19: Re: Viewsim bashing 101
12588: 98/10/19: Re: Schematic entry?
12589: 98/10/19: Re: 100 MHz FPGA
12590: 98/10/19: Re: optimized fpga
12591: 98/10/19: Re: gray code counter in a Xilinx fpga???
12593: 98/10/19: Re: FIR Filter Design
12625: 98/10/20: Re: gray code counter in a Xilinx fpga???
12657: 98/10/22: Re: Schematic entry?
12658: 98/10/22: Re: Evaluation
12673: 98/10/22: Re: Schematic entry?
12687: 98/10/23: Re: gray code counter in a Xilinx fpga???
12688: 98/10/23: Re: Fast multiplier, FPGA & ASIC
12704: 98/10/23: Re: gray code counter in a Xilinx fpga???
12705: 98/10/23: Re: 3.3V FPGAs on the ISA bus?????
12706: 98/10/23: Re: DynaText **!?!?
12707: 98/10/23: Re: Xilinx F1.5/FPGA Express wackiness (& Floorplanner)
12709: 98/10/23: Re: Fast multiplier, FPGA & ASIC
12733: 98/10/26: Re: FPGA Decouple Capacitor values
12771: 98/10/29: Re: State machines in VHDL/Verilog
12772: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
12773: 98/10/29: Re: !Recommendation wanted! Which CAD for shematic entry of Xilinx FPGA'based devices choose
12778: 98/10/29: Re: FPGA Decouple Capacitor values
12779: 98/10/29: Re: Schematic entry?
12795: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
12796: 98/10/29: Re: Xilinx mode pins.
12805: 98/10/30: Re: Digital Sine Generator
12829: 98/10/30: Re: Xilinx mode pins.
12992: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12999: 98/11/10: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12989: 98/11/09: Re: Why doesn't Xilinx's simulator work?
12990: 98/11/09: Re: placement&routing problems
12991: 98/11/09: Re: design multipier?
13016: 98/11/11: Re: FPGA VGA interface
13053: 98/11/13: Re: VHDL project
13054: 98/11/13: Re: placement&routing problems
13057: 98/11/13: Re: Affordable boundary scan (JTAG) interconnect testing software any
13128: 98/11/16: Re: Example of clock circuit needed !
13130: 98/11/16: Re: newbie question about timing
13159: 98/11/17: Re: Is there an alternative to Altera EPM5128 OTP?
13165: 98/11/18: Re: Synthesizeablel fifo
13181: 98/11/18: Re: XNF issue
13182: 98/11/18: Re: Serial EPROMs
13190: 98/11/18: Re: Synthesizeablel fifo
13212: 98/11/20: Re: Synthesizeablel fifo
13213: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13214: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13225: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13240: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13241: 98/11/21: Re: Synthesizeablel fifo
13263: 98/11/22: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13266: 98/11/22: Re: Combining busses Xilinx
13267: 98/11/22: Re: Synthesizeablel fifo
13279: 98/11/23: Re: VHDL project
13280: 98/11/23: Re: Combining busses Xilinx
13281: 98/11/23: Re: Anyone use XChecker cable with 3.3V Xilinx parts?
13282: 98/11/23: Re: Synthesizeablel fifo
13300: 98/11/24: Re: Integer divide algorithms
13315: 98/11/25: Re: Add-in board with FPGA Secondary Processor
13688: 98/12/18: Re: Xilinx Foundation vs. Altera Max Plus II
13367: 98/11/30: Re: PCB rules for Xilinx ICs
13368: 98/11/30: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13492: 98/12/05: Re: A short digression...
13499: 98/12/06: Re: A short digression...
13510: 98/12/07: Re: A short digression...
13583: 98/12/10: Re: A short digression...
13601: 98/12/11: Re: HELP, Tool selection
13449: 98/12/03: Re: Minimum clock freq reqd
13447: 98/12/03: Re: Xilinx FPGA configuration problems... Help!
13473: 98/12/04: Re: package/footprint/layout
13517: 98/12/07: Re: New FPGA Brd: FPGA+PowerPC+Ethernet+TCP/IP
13518: 98/12/07: Re: computer requirements for CAE systems
13547: 98/12/08: Re: What are the 'rules' for assigning large buses to fpga's
13602: 98/12/11: Re: Need basic info on FPGA!
13610: 98/12/12: Re: XESS FPGA Board?
13633: 98/12/15: Re: FAQ Address Please
13634: 98/12/15: Re: Parallel Port Pass Through Specs?
13713: 98/12/19: Re: Atmel's PLD
13714: 98/12/19: Re: Async Fifo Core or Macro for Xilinx FPGA
13719: 98/12/20: Re: Async Fifo Core or Macro for Xilinx FPGA
13763: 98/12/22: Re: Xilinx - Viewlogic Virtex Support
14080: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
14081: 99/01/11: Re: smallest DCT algorithm?
13958: 99/01/05: Re: Bit-Serial Multiplier
13965: 99/01/05: Re: FPGA development system
13966: 99/01/05: Re: Dynamic reconfig
14005: 99/01/06: Re: which FPGA to choose ?
14008: 99/01/07: Re: fpga socket
14012: 99/01/07: Re: fpga socket
14021: 99/01/07: Re: fpga socket
14110: 99/01/13: Re: 1-wire
14135: 99/01/14: Re: DFF/Couter behavior with clock and control signals change
14147: 99/01/15: Re: General FPGA introduction needed
14202: 99/01/19: Re: Q:Hardware debugging with Xilinx M1.4
14226: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
14241: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
14245: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
14252: 99/01/21: Re: Q: Counting GHz pulses - ?
14253: 99/01/21: Re: hdl vs. schematics - was <snip>
14259: 99/01/22: Re: hdl vs. schematics - was <snip>
14265: 99/01/22: Re: decoder Viterbi
14317: 99/01/25: Re: PLL in FPGA
14319: 99/01/25: Re: 8x8 (x8 -> 11) DCT Implementation Results?
14340: 99/01/26: Re: FPGA architecture
14349: 99/01/26: Re: Xilinx - Questions on clock & Async delays.
14369: 99/01/27: Re: SWAP Home RF 4-FSK Demodulator
14407: 99/01/28: Re: No. of CLBs in Xilinx nearly 100% can't implement.
14436: 99/01/29: Re: Hazard
14457: 99/01/30: Re: Q:Installing Xilinx F1.4 license server
14596: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14600: 99/02/05: Re: Hazard
14617: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14618: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14696: 99/02/11: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14776: 99/02/16: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14620: 99/02/06: Re: routability of FPGA - is this an issue?
14646: 99/02/08: Re: routability of FPGA - is this an issue?
14699: 99/02/11: Re: Parity and flex10k
14700: 99/02/11: Re: reconfiguring Logiblox ROM's
14712: 99/02/12: Re: asyncronous finite state machines on FPGAs?
14713: 99/02/12: Re: reconfiguring Logiblox ROM's
14777: 99/02/16: Re: xnf de-compiler
14791: 99/02/17: Re: Xilinx Spartan and pin-locking
14844: 99/02/19: Re: P&R times for Altera10K200E and Virtex
14931: 99/02/25: Re: High Fanout Signals
14932: 99/02/25: Re: Xilinx Virtex
14955: 99/02/26: Re: Virtex multiplication
14956: 99/02/26: Re: JTAG HANG UP......
14957: 99/02/27: Re: Virtex multiplication
14971: 99/03/01: Re: JTAG HANG UP......
15086: 99/03/05: Re: High Fanout Signals
15112: 99/03/07: Re: Your view on this article?
14977: 99/03/01: Re: graphic Lcd control core
15001: 99/03/02: Re: Getting started in programmable logic
15002: 99/03/02: Re: Student edition!
15057: 99/03/04: Re: combining multiple xilinx designs into one
15094: 99/03/05: Re: Getting started in programmable logic
15147: 99/03/09: Re: Xilinx Foundation Timing
15174: 99/03/10: Re: Current State of FPGA-based PCI Interfaces?
15236: 99/03/15: Re: Want to learn about FPGA.
15237: 99/03/15: Re: Clock multiplier
15239: 99/03/15: Re: Possible problem with die shrink of xc4010
15240: 99/03/15: Re: multiport register file--Altera Flex10k20 ?
15281: 99/03/17: Re: help!
15282: 99/03/17: Re: How can I improve an adder?
15313: 99/03/18: Re: Xilinx Spartan configuration troubles
15324: 99/03/18: Re: Xilinx Spartan configuration troubles
15356: 99/03/19: Re: FPGA vendor comparison
15357: 99/03/19: Re: Placement control in ALtera devices
15358: 99/03/19: Re: Power Estimiation
15375: 99/03/21: Re: FPGA vendor comparison
15377: 99/03/21: Re: From VHDL to FPGA?
15378: 99/03/21: Re: From VHDL to FPGA?
15386: 99/03/21: Re: From VHDL to FPGA?
15397: 99/03/22: Re: From VHDL to FPGA?
15425: 99/03/23: Re: viterbi coder/decoder
15459: 99/03/24: Re: Info about FPGA/PLD
15460: 99/03/24: Re: Booth or Wallace Trees Multipliers
15465: 99/03/25: keeping an Altera EAB register in synplicity
15471: 99/03/25: Re: keeping an Altera EAB register in synplicity
15472: 99/03/25: Re: Info about VHDL syntesis
15473: 99/03/25: Re: keeping an Altera EAB register in synplicity
15496: 99/03/26: Re: keeping an Altera EAB register in synplicity
15504: 99/03/26: Re: keeping an Altera EAB register in synplicity
15517: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
15518: 99/03/28: Re: Info about FPGA/PLD
15549: 99/03/30: Re: From VHDL to FPGA?
15586: 99/04/01: Re: Schematic Capture & FPGA synthesis
15598: 99/04/02: Re: Schematic Capture & FPGA synthesis
15606: 99/04/02: Re: Schematic Capture & FPGA synthesis
15648: 99/04/06: Re: FPGAs with ECL-compatible I/Os
15740: 99/04/11: Re: FPGAs with ECL-compatible I/Os
15746: 99/04/12: Re: FPGAs with ECL-compatible I/Os
15597: 99/04/02: Re: Does any one want to talk about Dynamic Configuration?
15603: 99/04/02: Re: How to implement Matched Filter in FPGA?
15604: 99/04/02: Re: How to implement Matched Filter in FPGA?
15616: 99/04/02: Re: How to implement Matched Filter in FPGA?
15621: 99/04/03: Re: XILINX CLB architecture
15649: 99/04/06: Re: FIFO
15652: 99/04/06: Re: newbie: FPGA suggestion
15653: 99/04/06: Re: Levels of logic
15656: 99/04/06: Re: How to implement Matched Filter in FPGA?
15657: 99/04/06: Re: How to implement Matched Filter in FPGA?
15676: 99/04/07: Re: Best FPGA for High Speed DSP Logic?
15687: 99/04/08: Re: Best FPGA for High Speed DSP Logic?
15688: 99/04/08: Re: FPGA testing board
15699: 99/04/08: Re: Illegal States in 1 Hot State Machines
15719: 99/04/09: Re: Levels of logic
15723: 99/04/10: Re: Best FPGA for High Speed DSP Logic?
15724: 99/04/10: Re: Levels of logic
15814: 99/04/15: Re: craig
15862: 99/04/17: Re: High speed reconfigurability
15863: 99/04/17: Re: XC4000 LUT on the fly programming
15864: 99/04/17: Re: High speed reconfigurability
15874: 99/04/17: Re: XC4000 LUT on the fly programming
15875: 99/04/17: Re: XC4000 LUT on the fly programming
15876: 99/04/17: Re: High speed reconfigurability
15901: 99/04/20: Re: texture mapping hardware
15907: 99/04/20: Re: Virtex based PCI cards
15911: 99/04/20: Re: Okay, a really dumb Xilinx FPGA question.
15912: 99/04/20: Re: What's the best way to learn about fpga's?
15947: 99/04/22: Re: High speed reconfigurability
15970: 99/04/23: Re: on using EAB of FLEX10k
15971: 99/04/23: Re: Xilinx Spartan experience?
15972: 99/04/23: Re: Using Embedded RAM in Xilinx Virtex Chips
15985: 99/04/25: Re: Using Embedded RAM in Xilinx Virtex Chips
16010: 99/04/27: Re: Storage of 32Bit-Vectors
16032: 99/04/28: Re: floating point converter
16064: 99/04/30: Re: High speed PLL inside FPGA
16065: 99/04/30: Re: Double Port ram for Altera EPF10K20
16066: 99/04/30: Re: Xilinx Implementation error
16067: 99/04/30: Re: Source code Ethernet, E1 Framer, HDLC Contr.
16068: 99/04/30: Re: IRQ Controller
16069: 99/04/30: Re: P I/O core
16082: 99/04/30: Re: Double Port ram for Altera EPF10K20
16083: 99/04/30: Re: Storage of 32Bit-Vectors
16084: 99/04/30: Re: High speed PLL inside FPGA
16457: 99/05/23: Re: Virtex based PCI cards
16463: 99/05/24: Re: Virtex based PCI cards
16108: 99/05/03: Re: Anyone use 27256 for config?
16124: 99/05/05: Re: 10KE dual port RAM help ?
16129: 99/05/05: Re: Reciprocator in VHDL
16135: 99/05/05: Re: Anyone use 27256 for config?
16150: 99/05/06: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
16170: 99/05/07: Re: DSP in FPGA
16171: 99/05/07: Re: BGA Prototyping ?
16260: 99/05/12: Re: Synchronizer design?
16261: 99/05/12: Re: Synchronizer design?
16262: 99/05/12: Re: How synthesize tools concern with size of the design?
16279: 99/05/13: Re: Reciprocator in VHDL
16293: 99/05/13: Re: How synthesize tools concern with size of the design?
16318: 99/05/15: Re: How synthesize tools concern with size of the design?
16454: 99/05/23: Re: 4062XL problems and solutions
16455: 99/05/23: Re: Case study: Viewlogic's IntelliFlow
16456: 99/05/23: Re: Is schmitt trigger possible with Xilinx 9536?
16458: 99/05/23: Re: Request FAQ
16530: 99/05/26: Re: High Speed Reconfigurability
16551: 99/05/27: Re: High Speed Reconfigurability
16563: 99/05/28: Re: High speed with VHDL
16565: 99/05/28: Re: virtex vs apex20k family comparison for DSP ?
16578: 99/05/28: Re: High Speed Reconfigurability
16579: 99/05/28: Re: RAM for external/internal use
16580: 99/05/28: Re: Dynamically reconfigurable devices
16591: 99/05/28: Re: RAM for external/internal use
16592: 99/05/28: Re: Dynamically reconfigurable devices
16623: 99/05/31: Re: Printing to picture files
16624: 99/05/31: Re: Printing to picture files
16684: 99/06/02: Re: Printing to picture files
16690: 99/06/02: Re: Evolutionary computation
16650: 99/06/01: Re: Fixed delay in FSM
16668: 99/06/01: Re: FPGA Introduction is needed, right?
16707: 99/06/03: Re: Initial Values, Xilinx Virtex
16759: 99/06/07: Re: Initial Values, Xilinx Virtex
16795: 99/06/08: Re: LINE DELAYS USING RAMS
16802: 99/06/09: Re: LINE DELAYS USING RAMS
16838: 99/06/12: Re: Digital filters in VHDL
16876: 99/06/15: Re: newbie -- What's the best way to get started?
16877: 99/06/15: Re: delay line in FPGA / ASIC with VHDL
16878: 99/06/15: Re: Digital filters in VHDL/FPGA
16910: 99/06/16: Re: FPGA board for ISA bus wanted
16911: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
16913: 99/06/16: Re: Xilinx DP RAM SPO Output
16914: 99/06/16: Re: aobut analog
16915: 99/06/16: Re: vhdl and viewlogic problem
16919: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
16953: 99/06/18: Re: vhdl and viewlogic problem
16999: 99/06/22: Re: combining multiple xilinx designs into one
17009: 99/06/23: Re: Purchase of Spartan chips on the internet
17021: 99/06/25: www.reconfig.com
17029: 99/06/25: Re: fast counter in 4013XL?
17030: 99/06/25: Re: 100 Billion operations per sec.!
17071: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17080: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17081: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17088: 99/06/29: Re: FGPA Servo Motor Controller
17109: 99/06/30: Re: FPGAs v/s DSPs in Cell phones
17110: 99/06/30: Re: uLaw and ALaw conversion in an FPGA
17126: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
17190: 99/07/07: Re: 100 Billion operations per sec.!
17119: 99/07/01: Re: Heat disspa
17162: 99/07/06: Re: Xilink FPGA
17169: 99/07/06: Re: Need informations (articles, on-line) about fast adders and multipliers
17170: 99/07/06: Re: Floating point on fpga, Counters?
17189: 99/07/07: Re: Floating point on fpga, Counters?
17238: 99/07/13: Re: Dongle problems.
17248: 99/07/14: Re: Dongle problems.
17249: 99/07/14: Re: Dongle problems.
17250: 99/07/14: Re: ISA PnP core
17261: 99/07/15: Re: Dongle problems.
17269: 99/07/15: Re: Dongle problems.
17270: 99/07/15: Re: Dongle problems.
17271: 99/07/15: Re: ISA PnP core
17273: 99/07/15: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17285: 99/07/17: Re: Digital modulator? Synthesisable Sin(x) funct.
17287: 99/07/17: Re: fpga 10k50 and up prototype with a/d d/a
17296: 99/07/19: Re: Frequency multiplier in XC4000
17305: 99/07/19: Re: Xilinx/Synopsys License Problem
17337: 99/07/21: Re: C language to programmable logic
17341: 99/07/21: Re: fpga 10k50 and up prototype with a/d d/a
17350: 99/07/22: Re: Solaris vs. NT
17366: 99/07/22: Re: tiles-rus 8405
17377: 99/07/23: Re: Designing a Virtex board
17386: 99/07/23: Re: What does a SpartanXL look like prior to configuration?
17387: 99/07/23: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
17393: 99/07/23: Re: Hardware FFT Design?
17427: 99/07/27: Re: XACT vs. Workview office
17428: 99/07/27: Re: NRZ Deserializing in Virtex
17449: 99/07/28: Re: Digital modulator? Synthesisable Sin(x) funct.
17456: 99/07/29: Re: Partial Reconfiguration?
17466: 99/07/29: Re: Partial Reconfiguration?
17472: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
17473: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
17487: 99/07/30: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17488: 99/07/31: Re: Digital modulator? Synthesisable Sin(x) funct.
17493: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
17499: 99/08/02: Re: Semi-deterministic behaviour in FPGA's
17506: 99/08/03: Re: Digital modulator? Synthesisable Sin(x) funct.
17521: 99/08/05: Re: serial multiplier with LogiCore scaled 1/2 accumulator
17528: 99/08/06: Re: serial multiplier with LogiCore scaled 1/2 accumulator
17529: 99/08/06: Re: Xilinx vs. Lucent vs. XX FPGA comparison
17530: 99/08/06: Re: carry logic for implementing wide logic functions
17570: 99/08/10: Re: Emulating a transputer on FPGA
17581: 99/08/11: Re: Emulating a transputer on FPGA
17583: 99/08/11: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17591: 99/08/11: Re: Emulating a transputer on FPGA
17595: 99/08/12: Re: Foundation F1.5i Floorplanner document - ?
17729: 99/08/27: Re: Feasibility of 200 MHz, 12K design on FPGA
17730: 99/08/27: Re: constrain into one XC4000 CLB
17731: 99/08/27: Re: multiplier Virtex
17732: 99/08/27: Re: microcontroller vs FPGA
17733: 99/08/27: Re: looking for image processing hardware
17741: 99/08/28: Re: PLL cascading in VIRTEX
17770: 99/09/01: Re: Feasibility of 200 MHz, 12K design on FPGA
17771: 99/09/01: Re: Dissolve hierarchy or not?
17798: 99/09/05: Re: Newbie question: Reading FPGA programming?
17846: 99/09/13: Re: differences between ALTERA-XILINX
17847: 99/09/13: Re: Relative Location attribute
17851: 99/09/13: Re: A mix is best
17855: 99/09/14: Re: Virtex Interconnect
17865: 99/09/14: Re: free/demo/low cost verilog synthesis tools available?
17916: 99/09/16: Re: Xilinx development board > XVC400
17943: 99/09/18: Re: speeding up place and route
17944: 99/09/18: Re: Xilinx XC4005E
17945: 99/09/18: Re: DSP in FPGA
17946: 99/09/18: Re: Question about Alliance 2.1i
17953: 99/09/19: Re: Loadable arithmetic in Virtex
17954: 99/09/19: Re: Virtex global set/reset
17960: 99/09/19: Re: Loadable arithmetic in Virtex
17963: 99/09/19: Re: Loadable arithmetic in Virtex
17965: 99/09/19: Re: Loadable arithmetic in Virtex
17974: 99/09/20: Re: Programming Spartan XL
17992: 99/09/21: Re: [Q] simple Queue implementation with external RAM
18004: 99/09/22: Re: Virtex questions
18028: 99/09/24: Re: Synopsys inside Foundation 2.1i does not infer fast-adder
18073: 99/09/27: Re: New Xilinx Virtex-E is out!
18091: 99/09/29: Re: Performance of reprogrammable FPGA´s?
18099: 99/09/29: Re: Verilog or VHSIC HDL ?
18100: 99/09/29: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
18102: 99/09/29: Re: Fine grain vs. Coarse grain
18113: 99/09/30: Re: Are all SRAM based FPGAs -Reconfigurable devices.
18125: 99/10/01: Re: Slice (or CLB) count
18135: 99/10/02: Re: Reconfigurable FPGAs-- A query on this..
18136: 99/10/02: Re: Producing 60/40 clock in vhdl
18137: 99/10/02: Re: Reconfigurable FPGAs-- A query on this..
18138: 99/10/03: Re: Producing 60/40 clock in vhdl
18139: 99/10/03: Re: Producing 60/40 clock in vhdl
18140: 99/10/03: Re: Reconfigurable FPGAs-- A query on this..
18145: 99/10/03: Re: ATM srambler
18146: 99/10/03: Re: What are the Virtex REV connections?
18150: 99/10/03: Re: Producing 60/40 clock in vhdl
18158: 99/10/04: Re: ATM srambler
18159: 99/10/04: Re: Clock multiplexing in Virtex
18169: 99/10/04: Re: ABEL for CPLD Design
18171: 99/10/04: Re: I need a Link
18175: 99/10/05: Re: Multiplierless FIR filters in FPGAs
18183: 99/10/05: Re: Producing 60/40 clock in vhdl
18185: 99/10/05: Re: Multiplierless FIR filters in FPGAs
18191: 99/10/06: Re: ATM srambler
18210: 99/10/07: Re: Multiplierless FIR filters in FPGAs
18221: 99/10/08: Re: RAM in xilinx FPGAs.
18244: 99/10/08: Re: RAM in xilinx FPGAs.
18301: 99/10/13: Re: Interconnecting LUTs on a Virtex
18311: 99/10/13: Re: Xilinx FPGA Programmer
18320: 99/10/14: Re: Virtex Board
18321: 99/10/14: Re: Need info about a FAST adders. How built it? (0)
18341: 99/10/16: Re: Interconnecting LUTs on a Virtex
18342: 99/10/16: Re: VITERBI
18343: 99/10/16: Re: VITERBI
18362: 99/10/19: Re: Question on Jbits(Xilinx product) for Xc4000 series
18388: 99/10/21: Re: Xilinx Orientation Question
18392: 99/10/21: Re: Xilinx Orientation Question
18412: 99/10/23: Re: VHDL carry chain RPMs
18413: 99/10/23: Re: Xilinx Orientation Question
18419: 99/10/23: Re: Seeking for FPGA/CPLD (Starter) kit
18420: 99/10/23: Re: Static power consumption
18423: 99/10/23: Re: floating point synthesis
18431: 99/10/23: Re: floating point synthesis
18513: 99/10/28: Re: Comparison between Altera and Xilinx
18514: 99/10/28: Re: FPGA
18515: 99/10/28: Re: schematics ==> www
18516: 99/10/28: Re: schematics ==> www
18526: 99/10/28: Re: Comparison between Altera and Xilinx
18527: 99/10/28: Re: FPGA
18533: 99/10/28: Re: schematics ==> www
18547: 99/10/29: Re: StateCAD versus Viewdraw
18551: 99/10/30: Re: Comparison between Altera and Xilinx
18554: 99/10/30: Re: Comparison between Altera and Xilinx
18561: 99/10/31: Re: Comparison between Altera and Xilinx
18583: 99/11/01: Re: Comparison between Altera and Xilinx
18585: 99/11/02: Re: XNF file formats ???
18590: 99/11/02: Re: 16 bit counter in Abel
18613: 99/11/03: Re: High Speed Enough!?
18614: 99/11/03: Re: Xlinx FPGA
18615: 99/11/03: Re: Why DSP in a FPGA?
18622: 99/11/03: Re: Input metastability
18623: 99/11/03: Re: Xlinx FPGA
18643: 99/11/04: Re: High Speed Enough!?
18644: 99/11/04: Re: Price of FPGA
18650: 99/11/04: Re: Xilinx M2.1i SP2?
18669: 99/11/05: Re: Xlinx FPGA
18673: 99/11/06: Re: Why DSP in a FPGA?
18684: 99/11/07: Re: ROM or SRAM !?
18688: 99/11/07: Re: Input metastability
18690: 99/11/07: Re: Downloading Xilinx FPGA with just .bit file???
18696: 99/11/08: Re: ROM or SRAM !?
18734: 99/11/10: Re: orcad synthesis for simplepld
18743: 99/11/11: Re: fast programmable divider using xilinx xc4002xl
18752: 99/11/11: Re: fast programmable divider using xilinx xc4002xl
18753: 99/11/11: Re: Simulation of FPGA design. Please Help!
18758: 99/11/12: Re: Pin locking problem in Altera fpga
18833: 99/11/18: Re: How to use GSR-net in Virtex?
18834: 99/11/18: Re: How to use multiple resets?
18835: 99/11/18: Re: How many bits in an FPGA bitstream?
18849: 99/11/18: Re: analog capabilities?
18850: 99/11/18: Re: Not complett multipier LUT in FPGA
18851: 99/11/18: Re: Need advice on interfacing SDRAM modules
18864: 99/11/19: Re: How to use multiple resets?
18865: 99/11/19: Re: How to use GSR-net in Virtex?
18866: 99/11/19: Re: implementing TCP/IP on PLD
18889: 99/11/19: Re: How to use GSR-net in Virtex?
18918: 99/11/21: Re: Why not Lucent ORCA FGPAs?
18944: 99/11/22: Re: Why not Lucent ORCA FGPAs?
18959: 99/11/22: Re: VHDL vs. schematic entry
18961: 99/11/22: Virtex mapper won't pack register with F5 combinatorial
18965: 99/11/22: Re: VHDL vs. schematic entry
18983: 99/11/23: Re: VHDL vs. schematic entry
19000: 99/11/23: Re: VHDL vs. schematic entry
19001: 99/11/23: Re: How to use GSR-net in Virtex?
19002: 99/11/23: Re: Why not Lucent ORCA FGPAs?
19003: 99/11/23: Re: How to use multiple resets?
19094: 99/11/29: Re: LOC's RLOC's and Virtex
19098: 99/11/29: Re: VHDL vs. schematic entry
19102: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
19114: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
19115: 99/11/29: Re: VHDL vs. schematic entry
19119: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
19124: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
19125: 99/11/30: Re: Xilinx FPGA Editor guessing games solved!
19133: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
19134: 99/12/01: Re: Timing constraint not met
19135: 99/12/01: Re: data serializer/decoder FPGA solution
19169: 99/12/03: Re: Tristate bidirectional pads with Xilinx
19174: 99/12/03: Re: Problems with routing Virtex device
19176: 99/12/03: Re: Problems with routing Virtex device
19180: 99/12/03: Re: Help with ROM in Xilinx Virtex
19183: 99/12/03: Re: Solution: ROM in Xilinx Virtex
19218: 99/12/06: Re: TIme Delay 1us-100ms
19235: 99/12/07: Re: TIme Delay 1us-100ms
19249: 99/12/08: Re: constraints between clock domains: can't advance
19264: 99/12/09: Re: JTAG on PCI slot
19266: 99/12/09: Re: Passing attributes from VHDL with FPGA Express for Xilinx
19274: 99/12/09: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19307: 99/12/12: Re: Lattice ispLSI Security
19335: 99/12/14: Re: Lattice ispLSI Security
19378: 99/12/17: Re: Xilinx FPGA Editor...does it really work?
19379: 99/12/17: Re: CIC Filters in FPGA
19387: 99/12/17: Re: Speed grade
19392: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
19395: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
19402: 99/12/19: Re: Speed grade
19409: 99/12/20: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19410: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
19419: 99/12/20: Re: Speed grade
19420: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
19429: 99/12/21: Re: fpga cost
19433: 99/12/21: Re: Dumb question springing from a discussion about chess on a chip...
19444: 99/12/21: Re: Speed grade
19446: 99/12/21: Re: fpga cost
19447: 99/12/21: Re: M1 timings
19449: 99/12/21: Re: M1 timings
19461: 99/12/22: Re: XC4000E
19469: 99/12/23: Crossing clock domain boundaries[ was Speed grade]
19476: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
19480: 99/12/24: Re: Dumb question springing from a discussion about chess on a chip...
19481: 99/12/24: Re: viewlogic problem
19588: 00/01/03: Re: Design security
19589: 00/01/03: Re: Virtex Config Help
19590: 00/01/03: Re: IRDY/TRDY Dedicated or Special Pin Name
19591: 00/01/03: Re: FG and H function in Xilinx FPGA
19600: 00/01/03: Re: Design security
19633: 00/01/04: Re: fpga cost
19634: 00/01/04: Re: STARTUP
19643: 00/01/05: Re: Design security
19655: 00/01/07: Re: Lucent Orca designs
19662: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
19684: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
19686: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
19687: 00/01/08: Re: Virtex real time debugging
19693: 00/01/08: Re: 100 MHz counters
19699: 00/01/08: Re: Optimizing VHDL for Altera
19700: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19702: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19701: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19703: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19704: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19705: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19706: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19707: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19708: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19709: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19710: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19711: 00/01/09: Re: Optimizing VHDL for Altera
19721: 00/01/09: Re: How to upgrade Foundation 1.4 to build Spartan-XL code?
19722: 00/01/09: Re: Optimizing VHDL for Altera
19723: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19735: 00/01/10: Re: XC4000 Configuration Bitstream structure
19736: 00/01/10: Re: Virtex Temperature Sensing diode pins DXP, DXN
19743: 00/01/11: Re: Optimizing VHDL for Altera
19744: 00/01/11: Re: THANX: Disable clockbuffer for only a single flip-flop
19757: 00/01/11: Re: SDRAM controller ?
19764: 00/01/11: Re: XC4000 Configuration Bitstream structure
19775: 00/01/11: Re: 100 MHz counters
19803: 00/01/12: Re: Xilinx Spartan2
19804: 00/01/12: Re: 100 MHz counters
19813: 00/01/13: Re: Reliability of programming SRAM FPGAs
19825: 00/01/13: Re: Design security
19826: 00/01/13: Re: fastest 32 bit RISC
19848: 00/01/14: Re: fpga board
19849: 00/01/14: Re: DDC Core for FPGA
19862: 00/01/14: Re: fastest 32 bit RISC
19878: 00/01/15: Re: XACT & XC4000E - Need help
19888: 00/01/16: Re: Partly reprogrammable FPGAs
19889: 00/01/16: Re: XACT & XC4000E - Need help
19894: 00/01/16: Re: Random Number Generator
19895: 00/01/16: Re: timing diagrams
19899: 00/01/17: Re: Random Number Generator
19908: 00/01/17: Re: Viterbi decoder in FPGA
19909: 00/01/17: Re: Random Number Generator
19922: 00/01/18: Re: Random Number Generator
19933: 00/01/19: Re: Random Number Generator
19937: 00/01/19: Re: Need advice on timing problem
19944: 00/01/19: Re: looping FIFO?
19952: 00/01/20: help: signal stuck at 'U' inside generate statement
19969: 00/01/20: Re: Xilinx vs. other FPGAs manufactrers
19978: 00/01/21: Re: odd behavior of Virtex RAM Block model
19993: 00/01/21: Re: help: signal stuck at 'U' inside generate statement
19994: 00/01/21: Re: help: signal stuck at 'U' inside generate statement
20000: 00/01/22: Re: Transmeta CM & Conf. Comp?
20028: 00/01/24: Re: How to access standard sdram ?
20029: 00/01/24: Re: Polynomial calculation on FPGA ???
20030: 00/01/24: Re: Xilinx vs. other FPGAs manufactrers
20031: 00/01/24: Re: FPGA to manage serial DAQ?
20078: 00/01/26: Re: EEPROM based FPGAs
20080: 00/01/26: GSR in HDL on instantiated flip-flop primitives
20089: 00/01/26: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20108: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
20109: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
20110: 00/01/27: Re: What has happened to freecore.com ?
20111: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20112: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20126: 00/01/28: Re: GSR in HDL on instantiated flip-flop primitives
20128: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20149: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20167: 00/01/29: Re: ADC to DSP... FIFO?
20174: 00/01/30: Re: Can Foundation import Viewlogic?
20199: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20200: 00/01/31: Re: Which FPGA to learn with?
20173: 00/01/30: Re: looping FIFO?
20206: 00/01/31: Re: Virtex DLL inoperability
20214: 00/02/01: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20229: 00/02/01: Re: Xilinx Tools
20230: 00/02/01: Re: Count 1's algorithm...
20288: 00/02/04: Re: Count 1's algorithm...
20289: 00/02/04: Re: Spartan 2 & Foundation
20158: 00/01/29: Re: Spartan II availability and pricing
20302: 00/02/04: Re: Spartan 2 & Foundation
20321: 00/02/04: Xilinx "WebCD" gripes
20322: 00/02/04: Re: Spartan 2 & Foundation
20323: 00/02/04: Re: Conditional compilation in VHDL?
20325: 00/02/05: Re: Conditional compilation in VHDL?
20334: 00/02/05: Re: Xilinx "WebCD" gripes
20354: 00/02/07: Re: Xilinx "WebCD" gripes
20355: 00/02/07: Re: Xilinx "WebCD" gripes
20384: 00/02/08: Re: ADC to DSP... FIFO?
20411: 00/02/09: Re: Why does Virtex has no EPROM support like XC4000
20520: 00/02/13: Re: launching a FPGA cores start-up
20521: 00/02/13: Re: FPGA IP complexity
20522: 00/02/13: Re: Xilinx Virtex Reset
20523: 00/02/13: Re: A FPGA hickup
20524: 00/02/13: Re: [NEED HELP] Carry Select Adder?
20544: 00/02/14: Re: launching a FPGA cores start-up
20545: 00/02/14: Re: LUT & VHDL
20546: 00/02/14: Re: CIC Question
20564: 00/02/14: Re: Xilinx Virtex Reset
20568: 00/02/15: Re: Advice please
20577: 00/02/15: Re: MULTIRATE DESIGN
20579: 00/02/15: Re: launching a FPGA cores start-up
20617: 00/02/16: Re: 100% slice utilization in Virtex FPGA
20618: 00/02/16: Re: Virtex DLL inoperability
20619: 00/02/16: Re: multiplier
20638: 00/02/16: Re: CIC Question
20658: 00/02/17: Re: Choosing the correct size FPGA
20660: 00/02/17: Re: Request for Info
20661: 00/02/17: Re: launching a FPGA cores start-up
20671: 00/02/17: Re: CLAy 31 datasheet
20687: 00/02/17: Re: Xilinx hold time problems...
20688: 00/02/17: Re: multiplier
20689: 00/02/17: Re: coregen-bug produces bad blockram > 16 bit
20690: 00/02/17: Re: RECONFIGURABLE board for image processign
20694: 00/02/18: Re: multiplier
20695: 00/02/18: Re: Xilinx M2.1 Floorplanner Question
20696: 00/02/18: Re: Using a programable logic device to search a huge number field
20697: 00/02/18: Re: Using a programable logic device to search a huge number field
20698: 00/02/18: Re: Suggested prototyping boards < $200
20718: 00/02/18: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20728: 00/02/19: Re: BEHAVIOURAL VHDL
20729: 00/02/19: Re: x18 FIFO's in Virtex
20731: 00/02/19: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20735: 00/02/20: Distributed Arithmetic De-mystified
20736: 00/02/20: Re: BEHAVIOURAL VHDL
20738: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20740: 00/02/20: Re: Spartan and timing analyzer: clock nets using non-dedicated
20741: 00/02/20: Re: multiplier
20742: 00/02/20: Re: Xilinx M2.1 Floorplanner Question
20746: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20747: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20754: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20755: 00/02/20: Re: Divider
20761: 00/02/21: Re: Passing multi-cycle timing constrains from Synplify to M1
20769: 00/02/21: Re: multiplier
20770: 00/02/21: Re: Passing multi-cycle timing constrains from Synplify to M1
20795: 00/02/22: Re: Distributed Arithmetic De-mystified
20808: 00/02/23: Re: Xchecker schematic?
20809: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20849: 00/02/24: Re: Bit Serial Arithmetic De-mystified
20850: 00/02/24: Re: Xchecker schematic?
20863: 00/02/24: Re: Design security
20907: 00/02/26: Re: MRP systems
20999: 00/03/02: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
21040: 00/03/03: Re: BEHAVIOURAL VHDL
20990: 00/03/02: Re: Xilinx Tools Vs Altera tools
20991: 00/03/02: Re: AMS board design advice asked
20965: 00/03/01: Re: AMS board simple questions
20976: 00/03/01: Re: Xilinx Tools Vs Altera tools
21009: 00/03/03: Re: Comment on Atmel AT40K ?
21036: 00/03/03: Re: Comment on Atmel AT40K ?
21037: 00/03/03: Re: SpartanXL route and place
21039: 00/03/03: Re: SpartanXL route and place
21042: 00/03/04: Re: EDA tools
21046: 00/03/04: Re: Comment on Atmel AT40K ?
21052: 00/03/04: Re: Comment on Atmel AT40K ?
21057: 00/03/04: Re: Comment on Atmel AT40K ?
21059: 00/03/05: Re: Xilinx Tools Question
21061: 00/03/05: Re: Xilinx Tools Question
21080: 00/03/06: Re: about multipliers
21088: 00/03/06: Re: Comment on Atmel AT40K ?
21109: 00/03/07: Re: SpartanXL route and place
21110: 00/03/07: Re: SpartanXL route and place
21113: 00/03/07: Re: SpartanXL route and place
21146: 00/03/08: Re: SpartanXL route and place
21169: 00/03/09: Re: SpartanXL route and place
21171: 00/03/09: Re: ModelSim 2.1i ?
21185: 00/03/09: Re: SpartanXL route and place
21189: 00/03/09: Re: ModelSim 2.1i ?
21203: 00/03/10: Re: SpartanXL route and place
21204: 00/03/10: Re: FPGA board
21205: 00/03/10: Re: SpartanXL route and place
21213: 00/03/10: Re: SpartanXL route and place
21214: 00/03/10: Re: SpartanXL route and place
21216: 00/03/10: Re: ModelSim 2.1i ?
21217: 00/03/10: Re: Spartan 2 Industrial temp range versions
21233: 00/03/11: Re: Xilinx IP Protection
21239: 00/03/12: Re: Xilinx Foundation Series and FSM designs
21246: 00/03/13: Re: DSP with FPGA
21250: 00/03/14: Re: DSP with FPGA
21265: 00/03/14: Re: Virtex IOB T register
21278: 00/03/15: Re: Atmel censors web access
21279: 00/03/15: Re: Virtex IOB T register
21280: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
21322: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21378: 00/03/21: Re: How I can DLL function unsing VHDL in Virtex?
21421: 00/03/22: Re: Virtex DLL inoperability
21448: 00/03/22: Re: Virtex DLL inoperability
21452: 00/03/22: Re: No- FPGA openness
21462: 00/03/23: Re: FPGA openness
21482: 00/03/23: Re: FPGA openness
21493: 00/03/23: Re: FPGA openness
21509: 00/03/23: Re: FPGA openness
21527: 00/03/24: Re: No- FPGA openness
21528: 00/03/24: Re: No- FPGA openness
21529: 00/03/24: Re: FPGA openness
21530: 00/03/24: Re: FPGA openness
21567: 00/03/25: Re: FPGA openness
21597: 00/03/26: Re: FPGA openness
21598: 00/03/26: Re: FPGA openness
21602: 00/03/26: Re: FPGA openness
21626: 00/03/27: Re: FPGA openness
21628: 00/03/27: Re: FPGA openness
21637: 00/03/27: Re: FPGA & single point failure
21647: 00/03/28: Re: FPGA & single point failure
21665: 00/03/28: Re: Digital Filters - Help me!!
21681: 00/03/29: Re: FPGA openness
21688: 00/03/29: Re: VHDL at RTL level vs. floorplanning.
21691: 00/03/29: Re: FPGA openness
21702: 00/03/29: Re: FPGA openness
21703: 00/03/29: Re: FPGA openness
21704: 00/03/29: Re: FPGA openness
21753: 00/03/30: Re: 10 gbit/s input
21754: 00/03/30: Re: FPGA openness
21755: 00/03/30: Re: FPGA openness
21756: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
21757: 00/03/30: Re: Memory cores
21758: 00/03/30: Re: What's so good about antifuse???
21759: 00/03/30: Re: What's so good about antifuse???
21768: 00/03/31: Re: FPGA openness
21786: 00/03/31: Re: FPGA openness
21787: 00/03/31: Re: ANTIFUSE AND XILINX
21788: 00/03/31: Re: 82C54
21627: 00/03/27: Re: FPGA openness
21812: 00/04/01: Re: FPGA openness
21892: 00/04/05: Re: Memory cores
21907: 00/04/06: Re: Memory cores
21875: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
21876: 00/04/05: Re: Clocks and BUFGP
21888: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
21908: 00/04/06: Re: JTAG programming
21909: 00/04/06: Re: Spartan on chip oscillator
21910: 00/04/06: Re: Warnings during mapping
21920: 00/04/07: Re: FPGA Openness/ Summary
21933: 00/04/07: Re: multiprocessor support of IC design tools
21946: 00/04/07: Re: multiprocessor support of IC design tools
21955: 00/04/09: Re: multiprocessor support of IC design tools
21962: 00/04/10: Re: multiprocessor support of IC design tools
21974: 00/04/10: Re: Distributed Arithmetic
21975: 00/04/10: Re: setup and hold time violation
21980: 00/04/11: Re: Programator for xilinx
22002: 00/04/11: Re: Is there any DSP and FPGA based board suitable to motor drive
22003: 00/04/11: Re: Clock Dividers
22009: 00/04/12: Re: Multiple Clock design, setup & hold time violation
22049: 00/04/16: Re: FPGA/PLD design tools?
22207: 00/05/01: Re: Why are there no "cheap" FPGAs?
22233: 00/05/02: Re: Why are there no "cheap" FPGAs?
22274: 00/05/04: Re: Why are there no "cheap" FPGAs?
22275: 00/05/04: Re: How to Prevent theft of FPGA design
22279: 00/05/04: Re: How to Prevent theft of FPGA design
22327: 00/05/05: Re: How to Prevent theft of FPGA design
22353: 00/05/05: Re: How to Prevent theft of FPGA design
22354: 00/05/05: Re: How to Prevent theft of FPGA design
22382: 00/05/07: Re: How to Prevent theft of FPGA design
22502: 00/05/10: Re: ? economical SPROM programmer for Xilinx
22734: 00/05/21: Re: Why are there no "cheap" FPGAs?
22231: 00/05/02: Re: random integer
22473: 00/05/10: Re: pipeline shiftreg in virtex
22474: 00/05/10: Re: HELP - what to choose?
22522: 00/05/11: Re: appropriate ASIC Prototyping Board
22524: 00/05/11: Re: HELP - what to choose?
22525: 00/05/11: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
22542: 00/05/11: Re: appropriate ASIC Prototyping Board
22543: 00/05/11: Re: Info on using Reconfig feature of Virtex?
22544: 00/05/11: Re: FPGA emulators?
22560: 00/05/12: Re: Reccomend an ASIC emulation board
22561: 00/05/12: Re: pipeline shiftreg in virtex
22575: 00/05/12: Re: Do you know xilinx FPGAs well?
22576: 00/05/12: Re: asic vs fpga
22577: 00/05/12: Re: Xilinx Virtex SRL16
22604: 00/05/13: Re: Do you know xilinx FPGAs well?
22605: 00/05/13: Re: pipeline shiftreg in virtex
22663: 00/05/17: Re: SMT 7 segment display ??
22686: 00/05/17: Re: Spartan II availability and pricing
22688: 00/05/18: Re: Spartan II availability and pricing
22691: 00/05/18: Re: Spartan II availability and pricing
22714: 00/05/19: Re: FPGA emultaion of a microprocessor
22740: 00/05/21: Re: Help for a novice of Xilinx Foundation
22750: 00/05/22: Re: US-IL-In desperate need of FPGA engineer
22772: 00/05/23: Re: Xilinx Logic Cell counts and carry chains
22777: 00/05/24: Re: Xilinx Logic Cell counts and carry chains
22778: 00/05/24: Re: ISA interface on FPGA or CPLD
22801: 00/05/25: Re: Xilinx Logic Cell counts and carry chains
22802: 00/05/25: Re: Implementation in FPGA
22803: 00/05/25: Re: 8087 in FPGA?
22830: 00/05/25: Re: 8087 in FPGA?
22844: 00/05/27: Re: 8087 in FPGA?
22871: 00/05/29: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22881: 00/05/29: Re: Help with Coregen
22907: 00/05/31: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22941: 00/06/05: Re: Help with Coregen
22971: 00/06/06: Re: Help with Coregen
22911: 00/06/01: Re: Microprocessors in FPGA
22992: 00/06/08: Re: Xilinx Spartan; CLB's run out
23007: 00/06/09: Re: TTL device Libraries
23026: 00/06/09: Re: Simulation of VIRTEX BLOCKRAM
23037: 00/06/10: Re: XILINX RAM Useless
23048: 00/06/10: Re: XILINX RAM Useless
23065: 00/06/12: Re: Altera vs Xilinx
23070: 00/06/13: Re: Altera vs Xilinx
23071: 00/06/13: Re: Altera vs Xilinx
23109: 00/06/14: Re: for my students
23186: 00/06/16: Re: Virtex ".FFX" contraint???
23187: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog
23188: 00/06/16: Re: Block level incremental synthesis (?)
23189: 00/06/16: Re: SV: Xilinx config over parallel port ?
23191: 00/06/16: Re: Hand soldering a PQ208 - It looks tough to do.
23213: 00/06/17: Re: Virtex ".FFX" contraint???
23214: 00/06/17: Re: Problem copying text from the Spartan II data sheet
23217: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23224: 00/06/18: Re: Xilinx config over parallel port ?
23236: 00/06/18: Re: Xilinx config over parallel port ?
23271: 00/06/20: Re: Wanted: Xilinx VirtexE
23355: 00/06/23: Re: dual processor PC for PPR - are they worth the extra cost?
23450: 00/06/26: Re: How to speed it up?
23108: 00/06/14: Re: FS: FpgaGuru.com DOMAIN
23707: 00/07/06: Re: FFT/IFFT for FPGA
23702: 00/07/05: Re: How to augment the output of a Xilinx lfsr in verilog??
23705: 00/07/06: Re: Viewlogic schematic from Synplify edif output?
23706: 00/07/06: Re: VHDL code for LFSR
23708: 00/07/06: Re: BIST in FPGAs?
23828: 00/07/12: Re: Xilinx buys LavaLogic
23948: 00/07/17: Re: XC2018 development system xact5 or xact6 sale?
24042: 00/07/24: Re: Routing Resources for Xilinx BlockRAM
24044: 00/07/24: Re: Routing Resources for Xilinx BlockRAM
24045: 00/07/24: Re: XC4000 select ram
24046: 00/07/24: Re: IP CORE, 8250 core with 16byte fifo which only uses 100CLB's
24047: 00/07/24: Re: Xilinx Logic Cell counts and carry chains
24048: 00/07/24: Re: New Xilinx Student Edition
24049: 00/07/24: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24053: 00/07/25: Re: 17 clocks in a Virtex
24069: 00/07/26: Re: Routing Resources for Xilinx BlockRAM
24070: 00/07/26: Re: Spartan II Pin
24071: 00/07/26: Re: Silicon Valley Housing Nightmare?
24072: 00/07/26: Re: Xilinx Logic Cell counts and carry chains
24092: 00/07/26: Re: Variable shifting
24110: 00/07/27: Re: Variable shifting
24111: 00/07/27: Re: Variable shifting
24112: 00/07/27: Re: Pad trireg in XLA FPGA
24148: 00/07/27: Re: Variable shifting
24150: 00/07/27: Re: Implementation
24189: 00/07/29: Re: Variable shifting
24193: 00/07/29: Re: LFSR as a divider
24200: 00/07/29: Re: Variable shifting
24208: 00/07/29: Re: Variable shifting
24220: 00/07/30: Re: LFSR as a divider
24221: 00/07/30: Re: Viewlogic Licensing
24236: 00/07/31: Re: Viewlogic Licencing
24237: 00/07/31: Re: Spartan-II / Virtex-E / DC linear regulators
24261: 00/08/01: Re: Look-up tables in Altera
24290: 00/08/02: Re: Viewlogic Licensing
24260: 00/08/01: Re: Desperatly needing a SpartanII
24277: 00/08/02: Re: Desperatly needing a SpartanII
24278: 00/08/02: Re: Desperatly needing a SpartanII
24279: 00/08/02: Re: FPGA selection
24291: 00/08/02: Re: 32-input AND and 100-input OR - can I do it fast?
24323: 00/08/04: Re: Who needs all those printed ac parameters?
24349: 00/08/04: Re: FPGA selection
24466: 00/08/10: Re: XST?
24467: 00/08/10: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA
24479: 00/08/10: Re: some basic rules on FPGA design
24537: 00/08/12: Re: Comparing Xilinx FPGAs
24549: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24564: 00/08/14: Re: state encoding in Synplify!!!
24591: 00/08/14: Re: Help!!! Bit serial Baugh-Wooley multiplier
24602: 00/08/15: Re: Help! Troubles using async FIFO cores in Virtex
24658: 00/08/16: Re: Help!!! Bit serial Baugh-Wooley multiplier
24659: 00/08/16: Re: fifo;s
24697: 00/08/17: Re: Permanently programming FPGAs
24729: 00/08/17: Re: Permanently programming FPGAs
24743: 00/08/17: Re: Permanently programming FPGAs
24745: 00/08/17: Re: Clock recovery in FPGA
24763: 00/08/17: Re: state encoding in Synplify!!!
24765: 00/08/17: Re: Clock recovery in FPGA
24773: 00/08/18: Re: state encoding in Synplify!!!
24805: 00/08/19: Re: Xilinx Xact & Alliance
24806: 00/08/19: Virtex BEL constraints--do they really do anything?
24812: 00/08/19: Re: Xilinx Student Edition Floorplanning
24830: 00/08/20: Re: Further FPGA metastability questions
24860: 00/08/21: Re: Metastability and antifuze
24861: 00/08/21: Re: Further FPGA metastability questions
24862: 00/08/21: Re: timing simulation vs functional one
24866: 00/08/21: Re: Further FPGA metastability questions
24867: 00/08/21: Re: Metastability measurement
24887: 00/08/21: Looks like Xilinx is at it again!
24897: 00/08/21: Re: Usage of ROC (Foundation 2.1i)
24898: 00/08/21: Re: timing simulation vs functional one
24899: 00/08/21: Re: Looks like Xilinx is at it again!
24900: 00/08/21: Re: Looks like Xilinx is at it again!
24905: 00/08/21: Re: Looks like Xilinx is at it again!
24906: 00/08/22: Re: Verilog multiplier in Xilinx...
24945: 00/08/23: Re: Looks like Xilinx is at it again!
24975: 00/08/23: Re: create a RAM in a Virtex
24977: 00/08/23: Re: timing simulation vs functional one
25007: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25012: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25033: 00/08/24: Re: run time doubled with Xilinx 3.1i upgrade - Problem Fixed!!
25038: 00/08/24: Re: largest fpga in the industry
25045: 00/08/24: Re: largest fpga in the industry
25050: 00/08/24: Re: largest fpga in the industry
25054: 00/08/25: Re: create a RAM in a Virtex
25072: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other
25073: 00/08/25: Re: DLL Properties on Xilinx Virtex/VirtexE
25074: 00/08/25: Re: create a RAM in a Virtex
25097: 00/08/25: Re: create a RAM in a Virtex
25099: 00/08/25: Re: Large amout of Interconnect between FPGAs
25100: 00/08/25: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25105: 00/08/25: Re: Is there any way to configure the Virtex BRAM outputs as direct,
25129: 00/08/27: Re: Balls!
25166: 00/08/29: Re: largest fpga in the industry
25187: 00/08/30: Re: Spartan II vs. Virtex
25270: 00/09/03: Re: Balls!
25278: 00/09/04: Re: Balls!
25254: 00/09/01: Re: Xilinx block Ram Verilog model
25279: 00/09/04: Re: Slow routing of PWR/GND (Virtex)
25288: 00/09/05: Re: XC4013 available
25290: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
25291: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
25301: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
25307: 00/09/06: Re: Slow routing of PWR/GND (Virtex)
25308: 00/09/06: Re: Model for 8101 - 8104
25324: 00/09/06: Re: floorplanning
25335: 00/09/06: Re: bga->dip?
25353: 00/09/07: Re: floorplanning
25364: 00/09/08: Re: XC3000A Configuration data
25372: 00/09/08: Re: DCT implementation using FPGA
25382: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25468: 00/09/12: Re: Is this practical?
25480: 00/09/12: Re: Is this practical?
25481: 00/09/12: Re: computing difference between Gray values?
25514: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25532: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25533: 00/09/13: Re: Is this practical?
25534: 00/09/13: Re: Is this practical?
25545: 00/09/13: Re: virtex shape
25554: 00/09/13: Re: Is this practical?
25625: 00/09/15: Re: FPGA Express Strikes Again!
25627: 00/09/15: Re: Guide to useing Atmel FPGA (at40k)
25708: 00/09/18: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25709: 00/09/18: Re: Clock skew in XILINX CPLD
25711: 00/09/18: Re: Reassurance on Xilinx Sought
25727: 00/09/18: Re: Clock skew in XILINX CPLD
25743: 00/09/19: Re: Freelance Designer Needed: Protel & FPGA
25760: 00/09/19: Re: PCB side of this
25770: 00/09/20: Re: Adders in FPGA?
25788: 00/09/20: Re: Complaint: Xilinx functional simulation libraries
25802: 00/09/20: Re: Safe voltage regulator for Xilinx XC2S150 part?
25803: 00/09/21: Re: Synthesiser comparisons (was: FPGA Express strikes again)
25804: 00/09/21: Re: Complaint: Xilinx functional simulation libraries
25834: 00/09/22: Re: Announce: Free HC11 CPU Core
25855: 00/09/23: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
25857: 00/09/23: Re: CORDIC COS/SIN with FPGA implementation
25864: 00/09/23: Re: dp ram
25870: 00/09/23: Re: Reassurance on Xilinx Sought
25876: 00/09/24: Re: CORDIC COS/SIN with FPGA implementation
26014: 00/09/30: Re: FPGA Express strikes again! Xilinx response
26013: 00/09/30: Re: atmel verses altera
26019: 00/10/01: Re: FPGA Express strikes again! Xilinx response
26021: 00/10/01: Re: atmel verses altera
26027: 00/10/01: Re: atmel verses altera
26020: 00/10/01: Re: multi-input adders in virtex ?
26026: 00/10/01: Re: multi-input adders in virtex ?
26029: 00/10/01: Re: Xilinx XC2018 Design tools
26039: 00/10/01: Re: multi-input adders in virtex ?
26040: 00/10/01: Re: multi-input adders in virtex ?
26058: 00/10/02: Re: multi-input adders in virtex ?
26059: 00/10/02: Re: Multiplication
26091: 00/10/03: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26092: 00/10/03: Re: Pwr/Gnd ( again)
26114: 00/10/04: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26115: 00/10/04: Re: Pwr/Gnd ( again)
26141: 00/10/05: Re: Pwr/Gnd ( again)
26154: 00/10/05: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26170: 00/10/06: Re: Multiplication
26253: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26254: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26269: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26297: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26433: 00/10/16: Re: clk'event
26435: 00/10/16: Re: 5V compatible Virtex
26437: 00/10/16: Re: const coeff multiplier w/ LUTs
26438: 00/10/16: Re: Sinusoidal PWM on Xilinx FPGA
26439: 00/10/16: Re: LUT to CLB assignment
26447: 00/10/16: Re: 5V compatible Virtex
26456: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26457: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26458: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26459: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26463: 00/10/17: Re: 5V compatible Virtex
26474: 00/10/17: Re: VHDL vs Verilog
26476: 00/10/17: Re: VHDL vs Verilog
26481: 00/10/18: Re: VHDL vs Verilog
26484: 00/10/18: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26498: 00/10/18: Re: Q: Xilinx unified libraries and synthesis
26499: 00/10/18: Re: Virtex pull-up/down resistors question
26507: 00/10/18: Re: Spartan II ?
26511: 00/10/18: Re: Off subjuct, VHDL question
26512: 00/10/18: Re: two complement multiplier
26513: 00/10/18: Re: XILINX Download cable with USB
26521: 00/10/19: Re: Off subjuct, VHDL question
26525: 00/10/19: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26540: 00/10/19: Re: How safe is the algorithm implemented with FPGA?
26541: 00/10/19: Re: DS2401 security from pirating an FPGA
26550: 00/10/20: Re: Very Lucrative FPGA Jobs
26563: 00/10/20: Re: DS2401 security from pirating an FPGA
26571: 00/10/20: Re: "Number of logic levels" in xilinx PAR reports
26590: 00/10/21: Re: xilinx floor planner issues
26591: 00/10/21: Re: VHDL vs Verilog
26592: 00/10/21: Re: Cheapy FPGA sw
26614: 00/10/22: Re: Xilinx 4000 reset
26615: 00/10/22: Re: xilinx floor planner issues
26620: 00/10/23: Re: UCF Question
26672: 00/10/24: Re: How safe is the algorithm implemented with FPGA?
26706: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26732: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
26633: 00/10/23: Re: Typical toggle rates for power estimation ...
26640: 00/10/23: Re: Typical toggle rates for power estimation ...
26648: 00/10/23: Re: XILINX Download cable with USB
26673: 00/10/24: Re: New PACT 50 GOP Reconfigurable Processor
26674: 00/10/24: Re: Virtex Dual Port RAM simulation failure in Modelsim
26677: 00/10/24: Re: How to reduce Tco?
26690: 00/10/25: Re: Design theft story in EDN. New security ?
26694: 00/10/25: Re: log2 function in VHDL
26717: 00/10/25: Re: ROC (reset on configuration) on Virtex ?
26731: 00/10/26: Re: Fpga vs. ASIC
26739: 00/10/26: Re: High fan out CE signal.
26740: 00/10/26: Re: what's meaning?
26764: 00/10/27: Re: Using previous version as floorplan (2.1i vs 3.1i)
26765: 00/10/27: Re: High fan out CE signal.
26810: 00/10/30: Re: High fan out CE signal.
26811: 00/10/30: Re: Long Island Verilog and VHDL people wanted!!
26815: 00/10/31: Re: High fan out CE signal.
26818: 00/10/31: Re: Long Island Verilog and VHDL people wanted!!
26825: 00/10/31: Re: High fan out CE signal.
26826: 00/10/31: Re: Using previous version as floorplan (2.1i vs 3.1i)
26833: 00/10/31: Re: High fan out CE signal.
26834: 00/10/31: Re: Alliance 3.2i
26846: 00/11/01: Re: High fan out CE signal.
26920: 00/11/03: Re: Alliance under Linux?
26941: 00/11/04: Re: Group behaviour (was: Alliance under Linux)
26969: 00/11/06: Re: High fan out CE signal.
26903: 00/11/02: Re: Need a PCB speaker driven by XCV100
26906: 00/11/03: Re: OT: Xilinx T-Shirt
27005: 00/11/07: Re: Need help locking pins for Spartan XL
27077: 00/11/09: Re: Non routable design
27086: 00/11/10: Re: Non routable design
27091: 00/11/10: Re: Non routable design
27099: 00/11/10: Re: Pull-up
27105: 00/11/10: Re: Virtex 32x1 RAM - Prevent usage
27108: 00/11/11: Re: Non routable design
27118: 00/11/11: Re: Number Format in DSP implementations
27129: 00/11/12: Re: CRC, LFSR and scramblers
27159: 00/11/13: Re: XC4000 maps better than Spartan2
27175: 00/11/13: Re: XC4000 maps better than Spartan2
27246: 00/11/16: Re: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
27247: 00/11/16: Re: Need help locking pins for Spartan XL
27268: 00/11/16: Re: Can FPGA perform float point calculation?
27274: 00/11/16: Re: Xilinx coregen problems
27281: 00/11/17: Re: Xilinx coregen problems
27305: 00/11/17: Re: Can FPGA perform float point calculation?
27307: 00/11/17: Re: reset pulse ?
27309: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27324: 00/11/18: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27325: 00/11/18: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27326: 00/11/18: Re: reset pulse ?
27355: 00/11/19: Re: Xilinx FPGA: SRAM based, but is it dependant upon SEEPROM?
27358: 00/11/19: Re: Synthesis & Routing speed
27366: 00/11/20: Re: Virtex circuit tricks -- add/mux in one LUT per bit
27367: 00/11/20: Re: LUT and EDIF
27384: 00/11/20: Re: Hardware suggestions for evolutionary experiments
27538: 00/11/28: Re: Clock Skew : Does Xilinx know what they're doing?
27612: 00/11/30: Re: Selfmade Cores or something similar (Xilinx)
27644: 00/12/01: Re: Synplify Benchmarks
27659: 00/12/01: Re: Synplify Benchmarks
27660: 00/12/01: Re: Synplify Benchmarks
27662: 00/12/01: Re: Synplify Benchmarks
27721: 00/12/05: Re: Synplify Benchmarks
27680: 00/12/02: Re: Synplify Benchmarks
27663: 00/12/01: Re: DLLs driving DLLs in Virtex.
27811: 00/12/09: Re: dual port ram for altera
27848: 00/12/12: Re: dual port ram for altera
27856: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27962: 00/12/18: Re: ActiveHDL 4.1?
27963: 00/12/18: Re: CSD OR DISTRIBUTED ARITHMETIC?
27964: 00/12/18: Re: Verilog or VHDL
27965: 00/12/18: Re: Setup violation
27981: 00/12/18: Re: Setup violation
28091: 00/12/20: Re: dual port ram for altera
28092: 00/12/20: Re: 3V -> 5V clock signal level conversion
28150: 00/12/23: Re: Question about programming xcv100
28858: 01/01/26: Re: really fast counter in SpartanXL?
28229: 01/01/03: Re: Question about programming xcv100
28252: 01/01/03: Re: Fixing pins on Spartan II
28265: 01/01/04: Re: XILINX SRL16E - FIFO
28305: 01/01/05: Re: Fixing pins on Spartan II
28306: 01/01/05: Re: XILINX SRL16E - FIFO
28346: 01/01/08: Re: Spartan-II DLL Usage
28347: 01/01/08: Re: FPGA for radar digital downconversion
28372: 01/01/10: Re: VIRTEX : pad location
28415: 01/01/11: Re: grey code counters
28416: 01/01/11: Re: How to do simulation on Synopsys FPGA Express
28453: 01/01/13: Re: Virtex counter speed
28459: 01/01/13: Re: I wanna Model Sim cracked
28493: 01/01/15: Re: Looking for prototyping board
28494: 01/01/15: Re: fifo
28495: 01/01/15: Re: Virtex-II officially launched
28600: 01/01/18: Re: CMOS or TTL
28601: 01/01/18: Re: FSM encoding
28604: 01/01/18: Re: FAQ for this news group? (or What is an FPGA?)
28629: 01/01/18: Re: FPGA for radar digital downconversion
28664: 01/01/20: Re: spartanII chip availability
28665: 01/01/20: Re: FPGAs with a partial reconfiguration
28666: 01/01/20: Re: FSM encoding
28667: 01/01/20: Re: FSM encoding
28668: 01/01/20: Re: Best design for asyn. interface DSP <-> FPGA?
28669: 01/01/20: Re: Synplicity newsgroup?
28714: 01/01/22: Re: Virtex-II officially launched
28738: 01/01/23: Re: Virtex-II officially launched
28739: 01/01/23: Xilinx XCell is not on-line?
28740: 01/01/23: Re: FPGAs with a partial reconfiguration
28762: 01/01/23: Re: Xilinx XCell is not on-line?
28763: 01/01/23: Re: Xilinx XCell is not on-line?
28767: 01/01/24: Re: Virtex counter speed
28768: 01/01/24: Re: multiplier architecture
28781: 01/01/24: Re: Fixing pins on Spartan II
28782: 01/01/24: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28783: 01/01/24: Re: Virtex-II officially launched
28801: 01/01/24: Re: Virtex counter speed
28805: 01/01/24: Re: Virtex counter speed
28868: 01/01/26: Re: Advice on FPGA board.
28869: 01/01/26: Re: mutiplier !!
28870: 01/01/26: Re: CORDIC ALGORITHM
28876: 01/01/26: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28885: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28888: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28892: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28916: 01/01/29: Re: Is it a timing constraint problem?
28925: 01/01/29: Re: Q: VIRTEX experience, multipliers
28932: 01/01/30: Re: Is it a timing constraint problem?
28963: 01/01/31: Re: CORDI C PROCESSOR!
28964: 01/01/31: Re: Standard Deviation Moving Window
28965: 01/01/31: Re: Xilinx fast carry counter question
28974: 01/01/31: Re: Xilinx fast carry counter question
28980: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
29563: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
29572: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
29573: 01/02/27: Re: Virtex USB solution
29574: 01/02/27: Re: Spartan II power
29575: 01/02/27: Re: I want to learn sth about FPGA
29577: 01/02/27: Re: DLL jitter "bake-off" vs. PLL
29590: 01/02/27: Re: programmable coefficient fir filter?
29630: 01/03/02: Re: What about speed-grade?
29635: 01/03/02: Re: What about speed-grade?
29653: 01/03/03: Re: Metastability, Asynchronous Signals, & Asynchronous design
29667: 01/03/04: Re: Metastability, Asynchronous Signals, & Asynchronous design
29679: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29722: 01/03/06: Re: Actel's FPGA : A54SX32A
29762: 01/03/08: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
29773: 01/03/08: Re: Problem with Xilinx 3.3-sp7
29793: 01/03/10: Re: Metastability
29808: 01/03/12: Re: Configuration devices
29820: 01/03/12: Re: clock divider by 1.5
29927: 01/03/18: Re: FFT in FPGAs
29947: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29951: 01/03/19: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29952: 01/03/19: Re: about placement and routing
29971: 01/03/19: Re: TOA measurement
29974: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29975: 01/03/20: Re: TOA measurement
29998: 01/03/20: Re: TOA measurement
29999: 01/03/20: Re: TOA measurement
30000: 01/03/20: Re: Book on FPGA-Design with Xilinx chips
30001: 01/03/20: Re: Packing density of Xilinx FPGAs
30004: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30024: 01/03/21: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30037: 01/03/21: Re: Do I need to tie unused CPLD pins to GND?
30051: 01/03/21: Re: TOA measurement
30055: 01/03/22: Re: reduced precision floating point
30064: 01/03/22: Re: reduced precision floating point
30065: 01/03/22: Re: TOA measurement
30066: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
30067: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30077: 01/03/22: Virtex Em on a board?
30087: 01/03/22: Re: frequency measurement?
30088: 01/03/23: Re: Virtex Em on a board?
30137: 01/03/25: Re: Accumulator - Core in XC4K
30138: 01/03/25: Re: How to find out where par placed things?
30160: 01/03/26: Re: Asynchronus Mashine States
30184: 01/03/27: Re: Asynchronus Mashine States
30197: 01/03/27: Re: frequency measurement?
30208: 01/03/28: Re: speech
30234: 01/03/29: Re: Books for trade
30303: 01/04/02: Re: pseudo random numbers
30304: 01/04/02: Re: adding std_logic_vectors
30315: 01/04/02: Re: pseudo random numbers
30316: 01/04/02: Re: pseudo random numbers
30327: 01/04/03: Re: pseudo random numbers
30338: 01/04/03: Re: Timing Error
30339: 01/04/03: Re: pseudo random numbers
30348: 01/04/03: Re: pseudo random numbers
30351: 01/04/04: Re: pseudo random numbers
30353: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
30367: 01/04/04: Re: salary info for FPGA/HardwareEng's
30368: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
30372: 01/04/04: Re: pseudo random numbers
30379: 01/04/05: Re: QPSK phase rotator implementation in FPGA ?
30390: 01/04/05: Re: How to specify Spartan2 GSR/GTS for Synthesis
30391: 01/04/05: Re: URGENT: Using SpartanII DLL to multiply clock freq
30427: 01/04/07: Re: pseudo random numbers
30428: 01/04/07: Re: XCV1000BG560: onchip ram
30461: 01/04/09: Re: MicroBlaze
30503: 01/04/11: Re: How to specify Spartan2 GSR/GTS for Synthesis
30509: 01/04/11: Re: Introductory Question - LSB to MSB Conversion.
30650: 01/04/21: Re: Wanted: ISA bus implementation for Xilinx
30671: 01/04/23: Re: looking for comment on implementation
30672: 01/04/23: Re: looking for comment on implementation
30673: 01/04/23: Re: looking for comment on implementation
30674: 01/04/23: Re: looking for comment on implementation
30676: 01/04/23: Re: CIC interpolate by 3 & filter
30677: 01/04/23: Re: Frequency of FPGA
30686: 01/04/24: Re: Something about the counter
30695: 01/04/24: Re: CIC interpolate by 3 & filter
30730: 01/04/26: Re: manufacturer's of FIR chips
30765: 01/04/27: Re: Comparison of FPGA and DSP
30921: 01/05/03: Re: Comparison of FPGA and DSP
31081: 01/05/11: Re: Need Advice on what Xilinx Tools to purchase
31279: 01/05/17: Re: Xilinx and Actel
31303: 01/05/18: Re: Fine phase shift in Virtex2
31370: 01/05/21: Re: free simulator
31394: 01/05/21: Re: free simulator
31413: 01/05/22: Re: Counter problem
31419: 01/05/23: Re: Counter problem
31444: 01/05/24: Re: frequency ramp
31572: 01/05/30: Re: Help: RAM clear in one clock cycle
31592: 01/05/31: Re: Help: RAM clear in one clock cycle
31593: 01/05/31: Re: RLOC'in Virtex-II FDCs???
31944: 01/06/08: Re: Virtex LUT4 problems in FPGA Express
32013: 01/06/11: Re: [Xilinx] Spartan II Devices ..internal tristate busses ...
32064: 01/06/12: Re: Virtex LUT4 problems in FPGA Express
32065: 01/06/12: Re: Virtex LUT4 problems in FPGA Express
32074: 01/06/12: Re: Virtex, Routing Error
32075: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
32154: 01/06/16: Re: Virtex II multiplier question
32191: 01/06/19: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
32235: 01/06/20: Re: Pin locking in Maxplus2
32251: 01/06/21: Re: Pin locking in Maxplus2
32253: 01/06/21: Re: FFT limited size input
32254: 01/06/21: Re: Xilinx Software free
32263: 01/06/21: synplicity 6.2.4 'optimizing' instantiated designs
32265: 01/06/21: Re: NT vs W2K (WAS Re: Pin locking in Maxplus2)
32266: 01/06/21: Re: Pin locking in Maxplus2
32275: 01/06/21: Re: synplicity 6.2.4 'optimizing' instantiated designs
32276: 01/06/21: Re: FFT limited size input
32285: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32286: 01/06/22: Re: LFSR Taps for 64 bit registers?
32288: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32307: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32308: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32316: 01/06/22: Re: FFT limited size input
32328: 01/06/23: Re: Unisim Library Question?
32332: 01/06/23: Re: what tools run OK on windows 2000?
32385: 01/06/25: Re: synplicity 6.2.4 'optimizing' instantiated designs
32397: 01/06/25: Re: Register balancing in FPGA Express
32398: 01/06/26: Re: IOB FF in Synplicity
32399: 01/06/26: Re: Unisim Library Question?
32400: 01/06/26: Re: black box instantiation in Spartan II Design
32402: 01/06/26: Re: Xilinx logic usage
32416: 01/06/26: Re: Alpha Particle
32431: 01/06/26: Re: Xilinx System Generator Simulation Problem
32460: 01/06/27: Re: Unisim Library Question?
32462: 01/06/27: Re: Xilinx unified library
32517: 01/06/28: Re: IOB FF in Synplicity
32518: 01/06/28: Re: Xc4k parallel-parallel multiplier
32543: 01/06/29: Re: Error to execute vcom.do in ModelSim XE5.3d
32621: 01/07/03: Re: Asynchronous design in Virtex FPGA => sleepless nights
32650: 01/07/04: Re: poor man's floating point...
32651: 01/07/04: Re: Asynchronous design in Virtex FPGA => sleepless nights
32652: 01/07/04: Re: Are these typical VirtexE timing values?
32687: 01/07/05: Re: How to estimate the number of CLBs ?
32709: 01/07/05: Re: How to estimate the number of CLBs ?
32715: 01/07/05: Re: Arc Tangente and Square Root algorithms
32716: 01/07/05: Re: AMS Wildstar Board
32747: 01/07/06: Re: Floating Point SQRT
32756: 01/07/07: Re: Problems with Virtex Block Ram Propagation Delay
32771: 01/07/09: Re: Shift and Add Multiplier With Signed Numbers
32772: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx
32857: 01/07/10: Re: Online threshold limit counter
32858: 01/07/10: Re: Simulation problems with BlockRAM's INIT values !
32859: 01/07/10: Re: Adder/Subtracter Core???
32860: 01/07/10: Re: How do I distribute cores?
32879: 01/07/11: Re: How do I distribute cores?
32880: 01/07/11: Re: Online threshold limit counter
32882: 01/07/11: Re: Online threshold limit counter
32883: 01/07/11: Re: Online threshold limit counter
32884: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
32897: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
32899: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
32960: 01/07/13: Re: Shift and Add Multiplier With Signed Numbers
32979: 01/07/13: Re: Design entry
32980: 01/07/13: Re: How do I distribute cores?
33023: 01/07/15: Re: Which Chip Family?
33024: 01/07/15: Re: Shift and Add Multiplier With Signed Numbers
33053: 01/07/16: Re: Fixing routing in a Virtex FPGA
33055: 01/07/16: Re: Which Chip Family?
33111: 01/07/17: Re: Working Design - Anyone
33116: 01/07/17: Re: Which Chip Family?
33146: 01/07/18: Re: FPGAs in Safety Involved Applications
33149: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33167: 01/07/18: Re: Xilinx WebPACK - ROM
33169: 01/07/18: Re: Working Design - Anyone
33176: 01/07/18: Re: Xilinx WebPACK - ROM
33187: 01/07/19: Re: Spartan2XC2S30 vs ACEXEP1K30
33207: 01/07/19: Re: Spartan2XC2S30 vs ACEXEP1K30
33209: 01/07/19: Re: Taking 4MSB a problem in 2's complement?
33263: 01/07/21: Re: regarding the constraints while writing VHDL code
33264: 01/07/21: Re: Modulator Sizing Questions
33265: 01/07/21: Re: Modulator Sizing Questions
33279: 01/07/22: Re: Measuring power consumption
33354: 01/07/24: Re: Soldering Ceramic BGA's
33367: 01/07/24: Re: Register Chain
33481: 01/07/27: Re: SRL16
33525: 01/07/29: Re: Digital Mixer
33526: 01/07/29: Re: SRL16
33535: 01/07/29: Re: Jitter Added by FPGA counter
33536: 01/07/29: Re: finite defect statistics
33555: 01/07/30: Re: Modulator Sizing Questions
33558: 01/07/30: Re: finite defect statistics
33578: 01/07/31: Re: SRL16
33579: 01/07/31: Re: Xilinx/Altera "behavioral" verilog
33588: 01/07/31: Re: finite defect statistics
33590: 01/07/31: Re: How to add carry optimizations
33611: 01/07/31: Re: finite defect statistics
33613: 01/07/31: Re: computer science Vs Computer Enginnering
33619: 01/08/01: Re: finite defect statistics
33620: 01/08/01: Re: Xilinx/Altera "behavioral" verilog
33643: 01/08/01: Re: Xilinx/Altera "behavioral" verilog
33644: 01/08/01: Re: computer science Vs Computer Enginnering
33656: 01/08/01: Re: DLL useage
33670: 01/08/02: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
33711: 01/08/02: Re: finite defect statistics
33712: 01/08/02: Re: Spartan II and asynchronous memory interface
33727: 01/08/03: Re: Clock skew with Xilinx DLLs...
33748: 01/08/03: Re: finite defect statistics
33750: 01/08/03: Re: Spartan II and asynchronous memory interface
33751: 01/08/03: Re: Clock skew with Xilinx DLLs...
33765: 01/08/03: Re: Spartan II and asynchronous memory interface
33766: 01/08/03: Re: Clock skew with Xilinx DLLs...
33827: 01/08/06: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
33828: 01/08/06: Re: Cordic NCO questions
33829: 01/08/06: Re: how to give timing constraint in an hierarchy des
33830: 01/08/06: Re: I needs a saturable adder.
33831: 01/08/06: Re: May I connect two pins to the same net?
33854: 01/08/06: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
33864: 01/08/07: Re: Polyphase and VHDL questions
33865: 01/08/07: Re: I needs a saturable adder.
33871: 01/08/07: Re: 200MHz, 28 bit counter in Spartan ii
33874: 01/08/07: Re: What to do if a constrain is not met ???
33878: 01/08/07: Re: Polyphase and VHDL questions
33879: 01/08/07: Re: Cordic NCO questions
33916: 01/08/08: Re: Wildcard and Foundation tools
33931: 01/08/08: Re: LUT as Buffer?
33938: 01/08/09: Re: Generate constants with a function
33951: 01/08/09: Re: LUT as Buffer?
33952: 01/08/09: Re: Cordic NCO questions
33954: 01/08/09: Re: What to do if a constrain is not met ???
33955: 01/08/09: Re: Problem with fft16 generated by Xilinx Core Gen 3.1i
33957: 01/08/09: Re: Wildcard and Foundation tools
33986: 01/08/09: Re: Generate constants with a function
33987: 01/08/09: Re: multplier
33997: 01/08/10: Re: Anyone using Xilinx System Generator yet???
34533: 01/08/29: Re: new to fpga
34537: 01/08/29: Re: Slowing PCI for FPGA
34611: 01/08/30: Re: Big SR in Virtex-E
34625: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34639: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34670: 01/09/03: Re: DSP in OTP
34672: 01/09/03: Re: Virtex Architecture: Interconnect
34678: 01/09/03: Re: Segmented interconnects
34694: 01/09/04: Re: Open collector outputs
34711: 01/09/04: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34743: 01/09/06: Re: Virtex II sizing rule of thumb
34745: 01/09/06: Re: Virtex-2 engineering samples
34763: 01/09/06: Re: Missing bits
34766: 01/09/06: Re: Segmented interconnects
34793: 01/09/08: Re: Actel FPGA glitches
34795: 01/09/08: Re: Clock division in Xilinx Vertex-E.
34796: 01/09/08: Re: Missing bits
34797: 01/09/08: Re: Selection of a suitable FPGA board
34799: 01/09/08: Re: Clock division in Xilinx Vertex-E.
34805: 01/09/08: Re: SOS : A Question about synthesizng ROM
34806: 01/09/08: Re: Missing bits
34811: 01/09/08: Re: Xilinx dev. kit for Linux?
34812: 01/09/09: Re: To mix frequency with a FPGA
34816: 01/09/09: Re: Selection of a suitable FPGA board
34829: 01/09/10: Re: Actel FPGA glitches
34954: 01/09/15: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34987: 01/09/17: Re: QPSK modulator with no multipliers
34989: 01/09/17: Re: Problems with Xilinx VirtexE (Newbie)
34990: 01/09/17: Re: Block RAM initialization
34991: 01/09/17: Re: Block RAM initialization
34992: 01/09/17: Re: Carry Chain: Delay
34993: 01/09/17: Re: INIT attribute of SRL16E
34995: 01/09/17: Re: Virtex-2 availability
34996: 01/09/17: Re: Altera survey
35025: 01/09/18: Re: Virtex-2 variable DPS availability
35026: 01/09/18: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
35038: 01/09/18: Re: QPSK modulator with no multipliers
35077: 01/09/20: Re: Synplicity logic replication
35108: 01/09/21: Re: Synplicity logic replication
35109: 01/09/21: Re: Increase routing delay in XILINX FPGA editor
35120: 01/09/21: Re: problem with location constraints in Verilog
35125: 01/09/22: Re: Virtex Clock Enable and Synplify
35139: 01/09/23: Re: problem with location constraints in Verilog
35140: 01/09/23: Re: how to simulate virtex components?
35158: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35159: 01/09/24: Re: Synplicity logic replication
35198: 01/09/25: Re: FPGA with embedded Memory
35200: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
35205: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
35227: 01/09/26: Re: how to simulate virtex components?
35263: 01/09/27: Re: Timing constraints...
35276: 01/09/27: Re: Logical constraints of LUT
35282: 01/09/27: Re: Logical constraints of LUT
35286: 01/09/27: Re: System DSP Generator on Xilinx
35297: 01/09/28: Re: Fastest way to become a Verilog samurai?
35298: 01/09/28: Re: fir filter
35299: 01/09/28: Re: verification problems please help
35318: 01/09/28: Re: how to dublicate logic?
35320: 01/09/28: Re: Active-HDL back annotated simulation and PC memory usage
35321: 01/09/28: Re: Meta-stability
35327: 01/09/29: Re: Forcing a LUT logic function (was Synplicity logic replication)
35364: 01/10/01: Re: future Xilinx products wish list ...
35365: 01/10/01: Re: Forcing a LUT logic function (was Synplicity logic replication)
35374: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
35376: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
35397: 01/10/02: Re: Barrel Shifter
35402: 01/10/03: Re: comp.arch.fpga : Unusual clock divider ckt
35417: 01/10/04: Re: Barrel Shifter
35429: 01/10/04: Re: comp.arch.fpga : Unusual clock divider ckt
35430: 01/10/04: Re: multipliers in virtex-II
35456: 01/10/05: Re: ROM based FSMs
35459: 01/10/05: Re: Video processing
35463: 01/10/06: Re: ROM based FSMs
35469: 01/10/06: Re: ROM based FSMs
35476: 01/10/07: Re: ROM based FSMs
35480: 01/10/07: Re: ROM based FSMs
35481: 01/10/07: Re: ROM based FSMs
35484: 01/10/07: Re: ROM based FSMs
35549: 01/10/10: Re: qpsk clock recovery
35562: 01/10/10: Re: 155MHz to DLL in Spartan II
35563: 01/10/10: Re: Virtex-2 maximum clock speed
35593: 01/10/11: Re: FPGA reset
35594: 01/10/11: Re: High level synthesis will never work well :)
35605: 01/10/11: Re: High level synthesis will never work well :)
35640: 01/10/12: Re: High level synthesis will never work well :)
35641: 01/10/12: Re: I need free PCI-Core (vhdl)!!
35642: 01/10/12: Re: PWM Signal in VHDL ?
35643: 01/10/12: Re: Small FPGA proto boards
35689: 01/10/13: Re: FPGA Asynchronous Design
35703: 01/10/14: Re: FPGA Asynchronous Design
35704: 01/10/14: Re: Instantiating Virtex II library macros.
35734: 01/10/16: Re: System Gates
35751: 01/10/16: Re: 1024 point non-complex FFT on a SPARTAN2
35752: 01/10/16: Re: Instantiating Virtex II library macros.
35869: 01/10/22: Re: Verilog vs. VHDL
35911: 01/10/23: Re: Verilog vs. VHDL
35912: 01/10/23: Re: Verilog vs. VHDL
35924: 01/10/24: Re: RLOC under VHDL
35973: 01/10/25: Re: Recommend a book
35977: 01/10/25: Re: How to make an implementable big counter?
35978: 01/10/25: Re: transferring data between related clocks
35997: 01/10/25: Re: How to make an implementable big counter?
35998: 01/10/25: Re: Cheap programming of XC2018?
36010: 01/10/26: Re: DSP on FPGA Opinions Needed->Earn $100
36028: 01/10/26: Re: How to make an implementable big counter?
36033: 01/10/26: Re: S/PDIF interface for FPGA
36051: 01/10/27: Re: How to make an implementable big counter?
36056: 01/10/27: Re: fir filter
36063: 01/10/27: Re: Digital image input for simulation on Altera FPGA
36064: 01/10/27: Re: DSP on FPGA Opinions Needed->Those are good questions.
36070: 01/10/27: Re: How to make an implementable big counter?
36076: 01/10/28: Re: FIR >14 taps
36077: 01/10/28: Re: How to make an implementable big counter?
36161: 01/10/31: Re: Second Scenario: BRAM usage reduction in FIFO design
36162: 01/10/31: Re: one SPROM for 2 XCS30XLs?
36175: 01/11/01: Re: Leonardo bugs
36210: 01/11/02: Re: Altera Local Routing
36211: 01/11/02: Re: Registered as well as unregistered outputs?
36213: 01/11/02: Re: XC6000
36229: 01/11/02: Re: Altera Local Routing
36230: 01/11/02: Re: Guided Design, Xilinx Virtex-E
36262: 01/11/04: Re: spartan synthesis with synopsis
36285: 01/11/05: Re: Implementing Filter
36287: 01/11/05: Re: Registered as well as unregistered outputs?
36306: 01/11/06: Re: Heatsink for Xilinx FF896 package?
36307: 01/11/06: Re: Xilinx Floorplanner Effectiveness
36311: 01/11/06: Re: count and divide Idea needed
36312: 01/11/06: Re: spartan synthesis with synopsis
36313: 01/11/06: Re: speed of adder in XC1000E-6
36314: 01/11/06: Re: Can anyone guide me in selecting an FPGA?
36329: 01/11/06: Re: Xilinx DLL clock question
36330: 01/11/06: Re: speed of adder in XC1000E-6
36331: 01/11/06: Re: RLOC for a block
36334: 01/11/06: Re: placement for if (vhdl)
36345: 01/11/07: Re: FPGA suppliers for hobbyists?
36412: 01/11/08: Re: How dense are FPGA/CPLD's
36413: 01/11/08: Re: count and divide Idea needed
36416: 01/11/08: Re: Virtex2 gate-level simulation: SDF and timing errors
36466: 01/11/09: Re: Log2(x) for vhdl?
36486: 01/11/09: Re: RLOC on RAMB4_Sn_Sn
36487: 01/11/09: Re: Xilinx unconnected logic
36491: 01/11/09: Re: How to convert unsigned integer into std_logic_vector in VHDL
36500: 01/11/09: Re: ideas
36501: 01/11/09: Re: Implementation of filter with three set of coeffs
36502: 01/11/09: Re: Implementation of filter with three set of coeffs
36507: 01/11/10: Re: Log2(x) for vhdl?
36539: 01/11/12: Re: Quadrature Encoder Sampling Time
36597: 01/11/13: Re: ideas
36643: 01/11/14: Re: Place your orders....
36770: 01/11/19: Re: Synopsys+Xilinx vs Synplicity
36771: 01/11/19: Re: DLL cycle-to-cycle jitter
36779: 01/11/20: Re: Modelsim
36803: 01/11/20: Re: Synplify use question
36817: 01/11/21: Re: Bit-serial efficiency
36895: 01/11/23: Re: fix LOC on LUT1
36896: 01/11/23: Re: Fast Fourier Transformation - camera data
36938: 01/11/26: Re: FFT with Distributed Arithmatic
36941: 01/11/27: Re: Which vendor to choose
37167: 01/12/02: Re: What do you like/dislike about place and route tools?
37168: 01/12/02: Re: 128-bit scrambling and CRC computations
37208: 01/12/04: Re: What do you like/dislike about place and route tools?
37218: 01/12/04: Re: I need a Xilinx Spartan PCI Development Board
37285: 01/12/06: Re: Where can I find the implemention of block float multiplier?
37310: 01/12/06: Re: where is designed FPGA for apple II computer...?
37316: 01/12/07: Re: Where can I find the implemention of block float multiplier?
37320: 01/12/07: Re: where is designed FPGA for apple II computer...?
37321: 01/12/07: Re: I need a Xilinx Spartan PCI Development Board
37351: 01/12/07: Re: For Sale: Huge Xilinx FPGA lots
37352: 01/12/07: Re: I need a Xilinx Spartan PCI Development Board
37361: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37370: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
37371: 01/12/08: Re: Xilinx multiplier and block ram error
37382: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
37465: 01/12/11: Re: What do you like/dislike about place and route tools?
37473: 01/12/12: Re: DCM error
37475: 01/12/12: Re: how do i implement it?
37477: 01/12/12: Re: Altera pin drivers
37478: 01/12/12: Re: Altera pin drivers
37479: 01/12/12: Re: Initialization of RAM
37506: 01/12/13: Re: Initialization of RAM
37508: 01/12/13: Re: Crosstalk on clocks
37547: 01/12/14: Re: Dual-port ram templates
37553: 01/12/14: Re: Fondation 4.1 and SpartanXL
37556: 01/12/14: Re: Dual-port ram templates
37564: 01/12/15: Re: Dual-port ram templates
37662: 01/12/18: Re: is it OK?
37664: 01/12/18: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37679: 01/12/19: Re: You take the low road and I'll ......
37688: 01/12/19: Re: You take the low road and I'll ......
37689: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37695: 01/12/19: Re: Xilinx Foundation - Routing constraints/prohibit
37740: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37741: 01/12/19: Re: You take the low road and I'll ......
37765: 01/12/20: Re: Virtex 2 & Trace
37766: 01/12/20: Re: Hardware FPGA questions
37799: 01/12/20: Re: The speedest FPGA
37805: 01/12/20: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37817: 01/12/20: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37818: 01/12/20: Re: You take the low road and I'll ......
37819: 01/12/20: Re: annoying problem and "simple and clever solution"
37867: 01/12/22: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37881: 01/12/22: Re: Beginners question: several circuits in one chip
37895: 01/12/23: Re: Default Should Be "Inputs and Outputs" For IOBs - please respond???
37896: 01/12/23: Re: Kindergarten Stuff
38015: 01/12/31: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for
38023: 01/12/31: Re: CRC-32 48bit(width)
38112: 02/01/06: Re: RNS
38113: 02/01/06: Re: A Fast counter in VHDL?
38194: 02/01/08: Re: 128 bit compare delay kill me!
38203: 02/01/08: Re: ROM synthesis question
38254: 02/01/10: Re: ROM synthesis question
38255: 02/01/10: Re: distributed ram bits in XCVxxxx series
38256: 02/01/10: Re: bufg instantiation in ISE 4.1
38257: 02/01/10: Re: bufg instantiation in ISE 4.1
38258: 02/01/10: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38269: 02/01/10: Re: FPGA Synthesis and implementation
38271: 02/01/10: Re: FPGA Synthesis and implementation
38299: 02/01/11: Re: The speedest FPGA
38300: 02/01/11: Re: multiply (*) 11000000000
38301: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38304: 02/01/11: Re: asic vs. fpga
38328: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38331: 02/01/11: Re: Picking an FPGA
38332: 02/01/11: Re: APEX-II vs VIRTEX-II
38335: 02/01/11: Re: How to constrain the inputs of a multi-level parity generator and
38350: 02/01/12: Re: speech recognition - active noise cancellation
38352: 02/01/12: Re: Picking an FPGA
38353: 02/01/12: Re: Picking an FPGA
38354: 02/01/12: Re: multiply (*) 11000000000
38355: 02/01/12: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38372: 02/01/12: Re: speech recognition - active noise cancellation
38391: 02/01/13: Re: Homebrew computers using FPGA?
38392: 02/01/13: Re: speech recognition - active noise cancellation
38475: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
38536: 02/01/16: Re: Signal processing using FPGAs
38537: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
38538: 02/01/16: Re: Leonardo + Xilinx tools help
38543: 02/01/17: Re: Repost: Should clock skew be included for setup time analysis?
38567: 02/01/17: Re: Image Processing on FPGAs. Dose System Generator help??
38598: 02/01/18: Re: Audio time delay circuit
38624: 02/01/19: Re: Shift Register question
38625: 02/01/19: Re: Audio time delay circuit
38627: 02/01/19: Re: Audio time delay circuit
38628: 02/01/19: Re: Simple shift register not working
38629: 02/01/19: Re: Should clock skew be included for setup time analysis?
38669: 02/01/21: Re: Signal processing using FPGAs
38683: 02/01/22: Re: Signal processing using FPGAs
38694: 02/01/22: Re: Q: can ROM content affect logic syn result
38698: 02/01/22: Re: CRC-32 48bit(width)
38706: 02/01/22: Re: analog input via serial connection
38712: 02/01/23: Re: input source to feed 20 filters! how to decrease the load
38721: 02/01/23: Re: Virtex-II Programming Highs and Lows
38736: 02/01/23: Re: CRC-32 48bit(width)
38737: 02/01/23: Re: Q: can ROM content affect logic syn result
38738: 02/01/23: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38741: 02/01/23: Re: Internal tri state buffer..
38764: 02/01/24: Re: Internal tri state buffer..
38765: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
38773: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
38776: 02/01/24: Re: Synthsis Tools for Xilinx
38781: 02/01/25: Re: Audio time delay circuit
38785: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
38816: 02/01/26: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38827: 02/01/26: Re: Mapping between Xlinx 4K and Spartan-II
38828: 02/01/26: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38893: 02/01/28: Re: Simple shift register not working (update)
38915: 02/01/28: Re: tri-state vs. Mux
38918: 02/01/28: Re: Pin assignment on ACEX1K
38919: 02/01/28: Re: Xilinx webpack
38933: 02/01/28: Re: Books on DSP
38935: 02/01/28: Re: Simple shift register not working (update)
38947: 02/01/28: Re: Xilinx webpack
38988: 02/01/29: Re: Books on DSP
38992: 02/01/29: Re: dll error message in ModelSim XE/Starter 5.5b
39030: 02/01/30: Re: The LUT puzzle, Iam on the way
39033: 02/01/30: Re: Dont care simulation
39035: 02/01/30: Re: Books on DSP
39040: 02/01/30: Re: function synthesis.
39047: 02/01/30: Re: 9 or 8 bits for image processing ?
39051: 02/01/30: Re: Signal assignment mismatch with Aldec 5.1 problem
39053: 02/01/30: Re: 9 or 8 bits for image processing ?
39057: 02/01/30: Re: RLOCS with combinatorial logic
39058: 02/01/30: Re: The LUT puzzle, Iam on the way
39059: 02/01/30: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39089: 02/01/31: Re: The LUT puzzle, Iam on the way
39090: 02/01/31: Re: Memory Question on Virtex
39140: 02/02/01: Re: The LUT puzzle, Iam on the way
39147: 02/02/01: Re: Linking IP
39159: 02/02/02: Re: Linking IP
39205: 02/02/04: Re: solutions manuals, and no they are not for school
39206: 02/02/04: Re: ClkEnable vs gated clock
39208: 02/02/04: Re: RAM question
39209: 02/02/04: Re: Virtex-II and SDRAM Controller at 133MHz
39220: 02/02/04: Re: RAM question
39226: 02/02/04: Re: par and carry chains not allowing manual floorplanning
39241: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
39248: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
39313: 02/02/06: Re: ClkEnable vs gated clock
39315: 02/02/06: Re: Virtex 2 rect->pol conversion
39326: 02/02/06: Re: Pseudorandom Bitstream
39358: 02/02/07: Re: Virtex-II and SDRAM Controller at 133MHz
39359: 02/02/07: Re: Pseudorandom Bitstream
39360: 02/02/07: Re: CLKDLL x4 problem
39362: 02/02/07: Re: MC6800 vhdl design
39368: 02/02/07: Re: Pseudorandom Bitstream
39369: 02/02/07: Re: Which PC for ALTERA development tools ?
39370: 02/02/07: Re: Multiple clock domein synchronization.
39386: 02/02/07: Re: Pseudorandom Bitstream
39418: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39420: 02/02/08: Re: CLKDLL x4 problem
39421: 02/02/08: Re: Pseudorandom Bitstream
39429: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
39430: 02/02/08: Re: Multiple clock domein synchronization.
39457: 02/02/10: Re: Multiple clock domein synchronization.
39459: 02/02/10: Re: Multiple clock domein synchronization.
39460: 02/02/10: Re: par and carry chains not allowing manual floorplanning
39463: 02/02/11: Re: par and carry chains not allowing manual floorplanning
39479: 02/02/11: Re: Altera's new family Stratix
39480: 02/02/11: Re: Multiple clock domein synchronization.
39488: 02/02/11: Re: Altera's new family Stratix
39489: 02/02/11: Re: I think it's a synthesis bug
39491: 02/02/12: Re: Xilinx EDIF to BIT transation
39493: 02/02/12: Re: par and carry chains not allowing manual floorplanning
39497: 02/02/12: Re: Altera's new family Stratix
39505: 02/02/12: Re: Pseudorandom Bitstream
39507: 02/02/12: Re: Multiple clock domein synchronization.
39508: 02/02/12: Re: Making Altera development quicker
39531: 02/02/12: Re: Newbie SpartanII Block Ram question
39532: 02/02/12: Re: Power estimation for Virtex-2 device
39539: 02/02/12: Re: Spartan Program/Verify
39541: 02/02/13: Re: Pseudorandom Bitstream
39543: 02/02/13: Re: Making Altera development quicker
39559: 02/02/13: Re: Suggestions on distributing a module...
39560: 02/02/13: Re: RAM CORE settings for maximum speed
39561: 02/02/13: Re: Pseudorandom Bitstream
39562: 02/02/13: Re: par and carry chains not allowing manual floorplanning
39564: 02/02/13: Re: Making Altera development quicker
39565: 02/02/13: Re: Foundation 4.1 vs. ISE 4.1?
39615: 02/02/14: Re: Spartan-II becomes Vertex.
39616: 02/02/14: Re: RAM CORE settings for maximum speed
39619: 02/02/14: Re: Power estimation for Virtex-2 device
39620: 02/02/14: Re: Foundation 4.1 vs. ISE 4.1?
39654: 02/02/15: Re: Spartan-II becomes Vertex.
39656: 02/02/15: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
39657: 02/02/15: Re: par and carry chains not allowing manual floorplanning
39670: 02/02/15: Re: oscillation
39675: 02/02/15: Re: Spartan-II becomes Vertex.
39691: 02/02/16: Re: oscillation
39696: 02/02/16: Re: FPGA choices and questions
39801: 02/02/20: Re: Xilinx ISE 3.3 upgrade to 4.1
39802: 02/02/20: Re: Xilinx IP Core multiplier performance
39822: 02/02/20: Re: Virtex-II and SDRAM Controller at 133MHz
39823: 02/02/20: Re: Pseudorandom Bitstream
39824: 02/02/20: Re: Xilinx ISE 3.3 upgrade to 4.1
39838: 02/02/21: Re: Do I need to install software in order to use Multilinx?
39840: 02/02/21: Re: Xilinx IP Core multiplier performance
39843: 02/02/21: Re: Do I need to install software in order to use Multilinx?
39856: 02/02/21: Re: Do I need to install software in order to use Multilinx?
39857: 02/02/21: Re: Virtex-E BRAM timing
39858: 02/02/21: Re: CLKDLL x4 problem
39859: 02/02/21: Re: SRL16E Initialization
39879: 02/02/21: Re: Whether an FPGA & CPLD device has been spoiled.
39880: 02/02/21: Re: FPGA: JTAG CABLE
39881: 02/02/21: Re: Using a CoreGen component
39882: 02/02/21: Re: Do I need to install software in order to use Multilinx?
39917: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39921: 02/02/22: Re: Coolrunner and ISP
39953: 02/02/22: Re: QPRO questions
40158: 02/03/01: Re: Comparison between two FPGAs- what is decisive factor?
40159: 02/03/01: Re: Creation of FPGA tips and tricks forum - help required
40161: 02/03/01: Re: Altera FPGAs
40164: 02/03/01: Re: IIR. convolution
40181: 02/03/01: Re: Clock multiplier/ADPLL in PLD
40198: 02/03/01: Re: Clock multiplier/ADPLL in PLD
40199: 02/03/01: Re: Rising and falling edge of a clk
40228: 02/03/02: Re: What FPGA to use?
40247: 02/03/03: Re: Rising and falling edge of a clk
40273: 02/03/04: Re: Altera FPGAs
40296: 02/03/05: Re: Altera FPGAs
40300: 02/03/05: Re: Minimum Size and Logic Sharing
40330: 02/03/05: Re: What FPGA to use?
40339: 02/03/05: Re: exceeding 2GB limits in xilinx
40341: 02/03/05: Re: Altera FPGAs
40353: 02/03/05: Re: Altera FPGAs
40389: 02/03/06: Re: FPGA or DSP
40390: 02/03/06: Re: FPGA or DSP in a power supply?
40391: 02/03/06: Re: exceeding 2GB limits in xilinx
40393: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
40424: 02/03/07: Re: Rising and falling edge of a clk
40446: 02/03/07: Re: FPGA or DSP in a power supply?
40457: 02/03/07: Re: Rising and falling edge of a clk
40483: 02/03/07: Re: Quartus II 2.0 fast fit option
40512: 02/03/08: Re: FPGA or DSP in a power supply?
40515: 02/03/08: Re: FPGA or DSP in a power supply?
40529: 02/03/08: Re: exceeding 2GB limits in xilinx
40540: 02/03/09: Re: BlockRam
40545: 02/03/09: Re: BlockRam
40546: 02/03/09: Re: exceeding 2GB limits in xilinx
40622: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
40652: 02/03/12: Re: exceeding 2GB limits in xilinx
40653: 02/03/12: Re: floating pins
40654: 02/03/12: Re: RTL/Gate-Level Simulation
40677: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
40683: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
40688: 02/03/13: Re: How do I infer a carry-chain parity generator in XST?
40689: 02/03/13: Re: Mystery two wire interface, or am I being dense?
40744: 02/03/14: Re: where to start with constraining..
40853: 02/03/16: Re: To Falk Brunner
40856: 02/03/17: Re: Difference between Virtex-II(E) und Virtex-E
40976: 02/03/19: Re: DDS in an FPGA
40980: 02/03/19: Re: Xilinx : Altera pin compatibility
41010: 02/03/19: Re: DDS in an FPGA
41037: 02/03/20: Re: STARTUP_VIRTEX primitive
41038: 02/03/20: Re: Any Stratix impressions based on results?
41054: 02/03/20: Re: which is the fastest FPGA ?
41094: 02/03/20: Re: questions from a newby
41127: 02/03/21: Re: simulation issues
41167: 02/03/22: Re: Maximum device usage for successful PAR
41188: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
41189: 02/03/22: Re: which is the fastest FPGA ?
41234: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
41238: 02/03/23: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
41244: 02/03/23: Re: Altera Stratix compared to Xilinx Virtex
41293: 02/03/25: Re: Maximum device usage for successful PAR
41294: 02/03/25: Re: which is the fastest FPGA ?
41295: 02/03/25: Re: Too many clocks
41320: 02/03/26: Re: question on LFSR
41324: 02/03/26: Re: question on LFSR
41364: 02/03/26: Re: question on LFSR
41382: 02/03/27: Re: question on LFSR
41400: 02/03/27: Re: clock source
41401: 02/03/27: Re: I2C Slave sampling edge
41402: 02/03/27: Re: XPower & Power Estimator Spreadsheet
41404: 02/03/27: Re: How can I add constrains?
41413: 02/03/27: Re: XPower & Power Estimator Spreadsheet
41431: 02/03/28: Re: I2C Slave sampling edge
41451: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41452: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41458: 02/03/29: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41530: 02/04/01: Re: Laying out the design
41543: 02/04/02: Re: Laying out the design
41544: 02/04/02: Re: powerpc in virtex2pro
41556: 02/04/02: Re: Laying out the design
41578: 02/04/02: Re: Marquis of Queensbury Rules
41587: 02/04/03: Re: Simulator for xilinx Cores?
41629: 02/04/03: Re: ACEX maximal clock...
41646: 02/04/04: Re: hand placement
41647: 02/04/04: Re: Schematic Stuff
41674: 02/04/05: Re: hand placement
41678: 02/04/05: Re: powerpc in virtex2pro
41680: 02/04/05: Re: Monostable multivibrator
41682: 02/04/05: Re: hand placement
41690: 02/04/05: Re: hand placement
41691: 02/04/05: Re: hand placement
41692: 02/04/05: Re: hand placement
41693: 02/04/05: Re: Schematic Stuff
41731: 02/04/06: Re: again this hand placement thing
41732: 02/04/06: Re: Simulator for xilinx Cores?
41733: 02/04/06: Re: hand placement
41734: 02/04/06: Re: hand placement
41843: 02/04/09: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41970: 02/04/12: Re: Built in multipliers in Virtex 2000E?
41971: 02/04/12: Re: Attributes *and* generics!?
41972: 02/04/12: Re: iMPACT FPGA detection error
41976: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41998: 02/04/12: Re: Attributes *and* generics!?
42004: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42024: 02/04/13: Re: Built in multipliers in Virtex 2000E?
42025: 02/04/13: Re: Laying out the design
42026: 02/04/13: Re: Marquis of Queensbury Rules
42027: 02/04/13: Re: PCI Bridge Question
42028: 02/04/13: Re: FPGA eval/dev boards with *serial* interface?
42141: 02/04/16: Re: creating my own RPMs(?) or similar
42181: 02/04/18: Re: FPGA Timing Problem
42548: 02/04/27: Re: Floorplanning
42549: 02/04/27: Re: SpartanII design considerations...
42553: 02/04/27: Re: Using 74HCT245N between Spartan-II and ISA
42554: 02/04/27: Re: Using 74HCT245N between Spartan-II and ISA
42566: 02/04/27: Re: Xilinx Programmable World 2002 - Review
42593: 02/04/28: Re: SpartanII design considerations...
42596: 02/04/28: Re: Xilinx Easypath- Selling parts with known defects
42907: 02/05/06: Re: 1000 I/O Pins -- What is cheapest FPGA?
42909: 02/05/06: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42973: 02/05/08: Re: VHDL: FIFO
43027: 02/05/09: Re: A special Thanks to :
43028: 02/05/09: Re: "easter egg" in FPGA design?
43037: 02/05/10: Re: "easter egg" in FPGA design?
43102: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
43203: 02/05/16: Re: Virtex-E interconnection
43267: 02/05/17: Re: RPMs
43268: 02/05/17: Re: Need Help on FPGA and Spiking Neurons
43270: 02/05/17: Re: What properties has FPGA?
43271: 02/05/17: Re: virtex 2 block rams
43296: 02/05/18: Re: Need Help on FPGA and Spiking Neurons
43297: 02/05/18: Re: RPMs
43316: 02/05/18: Re: button & 3 LED's
43319: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43336: 02/05/19: Re: RPMs
43337: 02/05/19: Re: Reading GSR signal of Spartan-II
43396: 02/05/21: Re: Rounding Accumulator
43397: 02/05/21: Re: Difference between Altera and Xilinx.
43398: 02/05/21: Re: button & 3 LED's
43399: 02/05/21: Re: Reading GSR signal of Spartan-II
43448: 02/05/21: Re: button & 3 LED's
43494: 02/05/22: Time for a new computer. Suggestions?
43495: 02/05/22: Re: 50Mhz driven - Overheat by Program?
43507: 02/05/22: Re: Time for a new computer. Suggestions?
43508: 02/05/22: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43509: 02/05/22: Re: inverse engeneering on XC3020.
43511: 02/05/22: Re: i need help getting started with fpgas
43549: 02/05/23: Re: FPGA, VHDL : RAM initialization
43550: 02/05/23: Re: Time for a new computer. Suggestions?
43557: 02/05/24: Re: Time for a new computer. Suggestions?
43573: 02/05/24: Re: Frequency synthesiser
43574: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
43587: 02/05/24: Re: Time for a new computer. Suggestions?
43634: 02/05/28: Re: Frequency synthesiser
43635: 02/05/28: Re: P&R times
43636: 02/05/28: Re: XACT - Xilinx design editor for a 2018 design desperately needed ...
43637: 02/05/28: Re: avoiding resynthesis
43639: 02/05/28: Re: SOPC for machine vision
43745: 02/05/31: Re: Time for a new computer. Suggestions?
43783: 02/06/03: Re: place and route simulation time
43845: 02/06/04: Re: divide by 5
43846: 02/06/04: Re: FPGA destruction possible?
43847: 02/06/04: Re: FPGA destruction possible?
43849: 02/06/04: Re: VirtexE DLL Output clock phase
43867: 02/06/04: Re: Hard macro in FPGA, or how to cut a big project in smaller ones
43868: 02/06/04: Re: VirtexE DLL Output clock phase
43869: 02/06/04: Re: FPGA destruction possible?
43870: 02/06/04: Re: FPGA destruction vs power management
43871: 02/06/04: Re: Small FIFOs in Spartan
43872: 02/06/04: Re: place and route simulation time
43886: 02/06/05: Re: Interpreting coregen footprint output in terms of slices
43903: 02/06/05: Re: Interpreting coregen footprint output in terms of slices
43917: 02/06/06: Re: xc3042
43918: 02/06/06: Re: Do I have metastability issues?
43928: 02/06/06: Re: FPGA destruction vs power management
43948: 02/06/07: Re: xc3042
43970: 02/06/07: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
43974: 02/06/07: Re: Doing Trig Functions in FPGA, EPLD
43990: 02/06/08: Re: Doing Trig Functions in FPGA, EPLD
43991: 02/06/08: Re: Xilinx ise software?
43992: 02/06/08: Re: Do I have metastability issues?
44010: 02/06/09: Re: Do I have metastability issues?
44027: 02/06/10: Re: where did my MHz go!
44040: 02/06/10: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44045: 02/06/10: Re: BUFGDLL again
44058: 02/06/11: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44108: 02/06/12: Re: MAP problem with RLOC'ed macros
44109: 02/06/12: Re: 20,000 gates?
44110: 02/06/12: Re: synthesis query: Xilinx + Synplify
44155: 02/06/12: Re: synthesis query: Xilinx + Synplify
44159: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44160: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44161: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44163: 02/06/13: Re: 20,000 gates?
44169: 02/06/13: Re: MAP problem with RLOC'ed macros
44179: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44180: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44181: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44182: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44183: 02/06/13: Re: Xilinx primitives & ModelSim
44202: 02/06/13: Re: MAP problem with RLOC'ed macros
44217: 02/06/14: Re: MAP problem with RLOC'ed macros
44218: 02/06/14: Re: MAP problem with RLOC'ed macros
44231: 02/06/14: Re: Xilinx primitives & ModelSim
44240: 02/06/14: Re: MAP problem with RLOC'ed macros
44255: 02/06/14: Re: TTL library in Xilinx?
44256: 02/06/14: Re: TTL library in Xilinx?
44257: 02/06/14: Re: Xilinx newest version?
44303: 02/06/17: Re: Xilinx System Generator FIR vs Core Generator FIR
44314: 02/06/17: Re: Which Synthesis tool for XILINX
44336: 02/06/18: Re: Which Synthesis tool for XILINX
44362: 02/06/18: Re: Which Synthesis tool for XILINX
44384: 02/06/19: Re: 5V tolerance
44402: 02/06/19: Re: 5V tolerance
44446: 02/06/20: Re: barrel shifter
44458: 02/06/20: Re: 5V tolerance
44459: 02/06/20: Re: How to get Unisims netlist?
44471: 02/06/21: Re: 5V tolerance
44472: 02/06/21: Re: hierarchy in Altera FPGAs
44473: 02/06/21: Re: what's the use of BlockRAM
44594: 02/06/24: Re: CIC filter
44596: 02/06/24: Re: Clock enable & Synplify 7.1
44604: 02/06/24: Re: CLK/2
44622: 02/06/25: Re: Multiply by 8 with DLL in Spaertan-II.
44650: 02/06/26: Re: Clock enable & Synplify 7.1
44651: 02/06/26: Re: too hot fpga device
44652: 02/06/26: Re: skew control between different signals ?
44658: 02/06/26: Re: Multiply by 8 with DLL in Spaertan-II.
44671: 02/06/26: Re: why not pipeline by default?
44677: 02/06/26: Re: 5V tolerance
44703: 02/06/27: Re: fast adders using HDL in Xilinx fpga
44714: 02/06/27: Re: Generate loop and RLOC
44718: 02/06/28: Re: Generate loop and RLOC
44729: 02/06/28: Re: variable decimation filter with rational sampling factors
44801: 02/07/01: Re: Can Coolrunner's be daisy chained?
44811: 02/07/02: Re: Converting Altera Block Ram to Xilinx Block Ram
44826: 02/07/02: Re: Power consumtion simulation for FPGA?
44834: 02/07/02: Re: Virtex II - Assigning Pins before routing?
44842: 02/07/02: Re: Power consumtion simulation for FPGA?
44867: 02/07/03: Re: Converting to Altera Quartus
44879: 02/07/03: Re: Power consumtion simulation for FPGA?
44893: 02/07/04: Re: Maximum frequency in Virtex and Virtex-E Devices
44902: 02/07/05: Re: Type conversion - adding integer to logic_vector
44914: 02/07/05: Re: Type conversion - adding integer to logic_vector
44917: 02/07/05: Re: Maximum frequency in Virtex and Virtex-E Devices
44929: 02/07/06: Re: Converting to Altera Quartus
44932: 02/07/06: Re: Converting to Altera Quartus
44938: 02/07/07: Re: Converting to Altera Quartus
44941: 02/07/07: Re: Newbie FPGA recommedation
44984: 02/07/09: Re: Virtex reset signal internaly hold?
44994: 02/07/09: Re: How can I preserve FFs in LeonardoSpectrum?
45026: 02/07/10: Re: 32 bit multiplier (1 cycle)
45039: 02/07/10: Re: DPLL
45067: 02/07/11: Re: Dynamic Addition Subtraction
45079: 02/07/11: Re: Need a non-pipelined signed integer divider
45095: 02/07/12: Re: Deterministic Output?
45118: 02/07/12: Re: Accurate Oscillator
45131: 02/07/13: Re: Accurate Oscillator
45140: 02/07/13: Re: Foundation 2.1i --- does it support vertexII?
45150: 02/07/13: Re: Accurate Oscillator
45173: 02/07/15: Re: Foundation 2.1i --- does it support vertexII?
45174: 02/07/15: Re: What proportion of an FPGA's configuration data is used for routing?
45188: 02/07/15: Re: How to add BUFG to an internal signal?
45189: 02/07/15: Re: Foundation 2.1i --- does it support vertexII?
45231: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45242: 02/07/17: Re: 6 parallel inputs to Mux? How?
45243: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45244: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
45284: 02/07/18: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45293: 02/07/18: Re: Xilinx XC9500/XC9500XL versus XC5200 Questions
45307: 02/07/18: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45341: 02/07/19: Re: black box components with parameters in Synplify
45342: 02/07/19: Re: Theft protection of FPGA configuration data
45349: 02/07/19: Re: Theft protection of FPGA configuration data
45351: 02/07/19: Re: dsp v fpga
45381: 02/07/21: Re: Spartan II JTAG connection with other devices
45411: 02/07/22: Re: Cheap licenses..
45413: 02/07/23: Re: black box components with parameters in Synplify
45427: 02/07/23: Re: xilinx v ti
45429: 02/07/23: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45430: 02/07/23: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45431: 02/07/23: Re: 16 X 16 multplier
45432: 02/07/23: Re: Translate the design from FPGA to Custom IC
45439: 02/07/23: Re: spiral / waterfall /watersluice : Which are your methods?
45440: 02/07/23: RLOC Origin problems in ISE4.2sp3?
45464: 02/07/24: Re: How's the FPGA design job market near you??
45465: 02/07/24: Re: RLOC Origin problems in ISE4.2sp3?
45472: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45520: 02/07/25: Re: How to implement efficient wide word comparator?
45521: 02/07/25: Re: delay pipes in verilog for spartan IIe?
45530: 02/07/25: Re: hold time
45543: 02/07/26: Re: RLOC Origin problems in ISE4.2sp3?
45544: 02/07/26: Re: logic elements v/s logic cells
45565: 02/07/26: Re: ALU in VHDL and a bunch of questions
45567: 02/07/27: Re: FPGA expert needed
45583: 02/07/27: Re: ALU in VHDL and a bunch of questions
45593: 02/07/28: Re: ALU in VHDL and a bunch of questions
45607: 02/07/29: Re: Complex FIR low pass filters
45608: 02/07/29: Re: Bit serial arithmetic Vs Digit serial Arithmetic
45609: 02/07/29: Re: ALU in VHDL and a bunch of questions
45619: 02/07/29: Re: secure FPGA
45626: 02/07/30: Re: ALU in VHDL and a bunch of questions
45627: 02/07/30: Re: logic elements v/s logic cells
45628: 02/07/30: Re: secure FPGA
45639: 02/07/30: Re: physical attacks (& secure FPGA) - some more questions
45650: 02/07/30: Re: Maximum FIR coefficient widths on FPGA
45653: 02/07/30: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45675: 02/07/31: Re: FPGA performance matrix..
45686: 02/08/01: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45758: 02/08/05: Re: Safe design speed
45778: 02/08/05: Re: Soundchip?
45786: 02/08/05: Re: Soundchip?
45788: 02/08/06: Re: clock timing
45800: 02/08/06: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45803: 02/08/06: Re: lots of shift registers
45806: 02/08/06: Re: Xilinx hiring practises
45902: 02/08/09: Re: ... milk for free, Opencores?
45904: 02/08/09: Re: Division
45917: 02/08/10: Re: unloading a fast ADC
45927: 02/08/11: Re: unloading a fast ADC
45932: 02/08/12: Re: articles about FPGA based DSP design
45956: 02/08/12: Re: Symplify Hacking/munging question...
45966: 02/08/13: Re: Division
45967: 02/08/13: Re: Symplify Hacking/munging question...
45968: 02/08/13: Re: Xilinx IBUFGDS with both inputs grounded ?
46000: 02/08/13: Re: Symplify Hacking/munging question...
46002: 02/08/13: Re: Divider in Xilinx System Generator
46003: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
46004: 02/08/13: Re: unloading a fast ADC
46019: 02/08/14: Re: routing long line ressources
46027: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46046: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46082: 02/08/16: Re: Divider in Xilinx System Generator
46090: 02/08/17: Re: V2PRO PowerPC floating point
46106: 02/08/19: Re: V2PRO PowerPC floating point
46122: 02/08/20: Re: BRAM simulation model error?
46123: 02/08/20: Re: Xilinx tools: which one? Esp. schematic
46124: 02/08/20: Re: Polyphase filtering...
46145: 02/08/20: Re: Xilinx FPGA start-up
46158: 02/08/20: Re: BRAM simulation model error?
46164: 02/08/20: Re: How to include Xilinx library for both ModelSim and Synplify?
46173: 02/08/21: Re: BRAM simulation model error?
46182: 02/08/21: Re: BRAM simulation model error?
46206: 02/08/21: Re: Xilinx tools: which one? Esp. schematic
46207: 02/08/21: Re: Logic Analyzers with an Altera Board
46208: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
46209: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
46212: 02/08/21: Re: Is this asynchronous design safe ?
46220: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
46221: 02/08/22: Re: Xilinx tools: which one? Esp. schematic
46235: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
46274: 02/08/23: Re: How to include Xilinx library for both ModelSim and Synplify?
46297: 02/08/25: Re: upgrade S/W -> timing worse
46306: 02/08/25: Re: upgrade S/W -> timing worse
46307: 02/08/25: Re: I2C BUS
46308: 02/08/25: Re: Floorplanning 101
46314: 02/08/26: Re: Virtex2 and Virtex-E speed performance
46330: 02/08/26: Re: writeing a synthesized vhdl code for "shifter "
46331: 02/08/26: Re: Can I directly connect XTAL to SpartanXL ?
46350: 02/08/27: Re: need cheap and dirty time delay for spartan2e
46371: 02/08/27: Re: FPGA speed level
46389: 02/08/28: Re: Any FSM optimizer?
46390: 02/08/28: Re: Stratix Experience
46400: 02/08/28: Re: My SpartanII thinks it's a Virtex??
46578: 02/09/04: Re: V2 Pipelined Embedded Mulitplier PAR issues
46624: 02/09/04: Re: Virtex-2 BRAM
46626: 02/09/04: Re: why the need for HIGH speed design?
46630: 02/09/04: Re: xilinx contact with regard to qpro
46641: 02/09/05: Re: Webpack 4.2 Schematic
46744: 02/09/06: Re: why the need for HIGH speed design?
46762: 02/09/07: Re: Fault tolerant FPGA design
46778: 02/09/09: Re: Fault tolerant FPGA design
46779: 02/09/09: Re: Fault tolerant FPGA design
47031: 02/09/15: Re: scan insertion is easily feasible
47041: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
47042: 02/09/16: Re: why the need for HIGH speed design?
47044: 02/09/16: Re: Measuring FPGA performance eg max clock speed
47045: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
47073: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
47074: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
47086: 02/09/17: Re: 1.8V regulator needed for Spartan IIE
47143: 02/09/18: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47144: 02/09/18: Re: linear-log converter required
47145: 02/09/18: Re: Multiple divide by 10
47149: 02/09/19: Re: C\C++ to VHDL Converter
47186: 02/09/20: Re: Multiple divide by 10
47187: 02/09/20: Re: Overheat with XCV-600E
47202: 02/09/20: Re: XCV600 Version and Firmware
47207: 02/09/20: Re: Multiple divide by 10
47208: 02/09/20: Re: Multiple divide by 10
47209: 02/09/20: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47211: 02/09/20: Re: GCLK pin used like an standard input
47212: 02/09/20: Re: ieee.math_real for presynthesis table calculation in vhdl
47245: 02/09/21: RPM zippering redux
47250: 02/09/21: Re: Can a fpga replace external inverters in a crystal osc ?
47261: 02/09/21: Re: RPM zippering redux
47280: 02/09/22: Re: VHDL : Lookup Table
47281: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
47282: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
47303: 02/09/23: Re: Xilinx RAM16x1D, Write fails in functional Simulation
47328: 02/09/23: Re: writing across a column in an SDRAM
47398: 02/09/25: Re: Multiple divide by 10
47419: 02/09/25: Re: Multiple divide by 10
47426: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
47444: 02/09/25: Re: ESD Undressing Story
47445: 02/09/25: Re: writing across a column in an SDRAM
47446: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
47447: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
47467: 02/09/26: Re: Dual Port RAM
47468: 02/09/26: Re: Can a fpga replace external inverters in a crystal osc ?
47504: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47518: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47539: 02/09/28: Re: Block Ram maximum speed
47548: 02/09/28: Re: Block Ram maximum speed
47605: 02/09/30: Re: FFT in FPGA?
47606: 02/09/30: Re: design multiplier
47611: 02/10/01: Re: design multiplier
47640: 02/10/01: Re: FFT in FPGA?
47641: 02/10/01: Re: Configuration:Startup
47665: 02/10/01: Re: question on ISE 5.1 and SMP machines...
47666: 02/10/01: Re: DFT , Design For Test HELPPPPP
47671: 02/10/02: Re: Rounting of non-global IO pad to a GCLKIOB site.
47679: 02/10/02: Re: C\C++ to VHDL Converter
47722: 02/10/02: Re: Moving average filter
47723: 02/10/02: Re: C\C++ to VHDL Converter
47726: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
47728: 02/10/02: Re: Help for Altera's FPGAs' pinout
47745: 02/10/03: Re: C\C++ to VHDL Converter
47746: 02/10/03: Re: Large Multiplexer
47750: 02/10/03: Re: Large Multiplexer
47775: 02/10/03: Re: A MAC design question
47807: 02/10/04: Re: Low power design
47808: 02/10/04: Re: Configuration:Startup
47809: 02/10/04: Re: C\C++ to VHDL Converter
47833: 02/10/04: Re: TCP/IP in FPGA
47843: 02/10/05: Re: Low power design
47878: 02/10/07: Re: Low power design
47879: 02/10/07: Re: C\C++ to VHDL Converter
47924: 02/10/07: Re: implementation of adaptive FIR with many input channels?
47928: 02/10/07: Re: USB2 in FPGA?
48006: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
48012: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
48019: 02/10/09: Re: USB2 in FPGA?
48032: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48036: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48037: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48053: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48055: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48069: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48070: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48071: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
48092: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48093: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48118: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48130: 02/10/11: Re: how do initialised signals really get set in Xilinx slices?
48135: 02/10/11: Re: Active HDL
48153: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
48159: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
48160: 02/10/12: Re: Sync Reset without clocks
48169: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
48173: 02/10/12: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
48174: 02/10/12: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
48198: 02/10/14: Re: hardmacro problem
48214: 02/10/14: Re: hardmacro problem
48215: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48240: 02/10/14: Re: Upgrading...
48242: 02/10/14: Re: comp.arch.fpga : Power consumption Benchmark
48244: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
48261: 02/10/15: Re: how to generate LUT for DA?
48263: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
48264: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
48307: 02/10/15: Re: Xilinx microblaze vs. picoblaze
48314: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48315: 02/10/16: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
48326: 02/10/16: Re: Upgrading...
48349: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48350: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48372: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48373: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48374: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48375: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48376: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48377: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
48381: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48386: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48400: 02/10/17: Re: Hobbyist FPGA
48406: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48425: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48447: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48448: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48473: 02/10/18: Re: Xilinx microblaze vs. picoblaze
48490: 02/10/18: Re: log calculation
48512: 02/10/18: Re: Floorplanner RPM. How to use it?
48516: 02/10/18: Re: Floorplanner RPM. How to use it?
48525: 02/10/19: Re: Number of Fpga posts vs dsp..
48527: 02/10/19: Re: Floorplanner RPM. How to use it?
48577: 02/10/21: Re: Floorplanner RPM. How to use it?
48578: 02/10/21: Re: Floorplanner RPM. How to use it?
48579: 02/10/21: Re: Floorplanner RPM. How to use it?
48608: 02/10/21: Re: Newbie Questions - Jan Gray XSOC
48613: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
48645: 02/10/22: Re: Floorplanner RPM. How to use it?
48646: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
48648: 02/10/22: Re: High Performance FPGA's - Xilinx and ??????
48661: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
48697: 02/10/23: Re: Newbie Questions - Jan Gray XSOC
48703: 02/10/23: Re: LCD driver implement with FPGA
48762: 02/10/24: Re: clock divider
48770: 02/10/24: Re: FPGA XC4005E
48791: 02/10/24: Re: Silly Virtex 2 Pro question...
48808: 02/10/24: Re: Silly Virtex 2 Pro question...
48813: 02/10/24: Re: Silly Virtex 2 Pro question...
48816: 02/10/24: Re: Pin locking Virtex 2 FPGA
48817: 02/10/24: Re: Pin locking Virtex 2 FPGA
48853: 02/10/25: Re: Pin locking Virtex 2 FPGA
48854: 02/10/25: Re: Please recommend a FPGA chip!
48872: 02/10/25: Re: Just some newbie ISE questions...
48962: 02/10/28: Re: for what do you use fpga's
48963: 02/10/28: Re: Phased clocks...
48980: 02/10/28: Re: filters on fpgas
48981: 02/10/28: Re: Phased clocks...
49020: 02/10/30: Re: Information--conference paper
49052: 02/10/30: Re: GlobalReset hogging routing resources
49092: 02/10/31: Re: BLOCK RAM : FIFO implementation
49133: 02/11/01: Re: FDRE inference in Synplify
49203: 02/11/05: Re: C\C++ to VHDL Converter
49222: 02/11/05: Re: C\C++ to VHDL Converter
49398: 02/11/11: Re: new to fpga, what language is better to start with
49415: 02/11/12: Re: HDL vs RTL
49477: 02/11/13: Re: Feedback from a 200 MHz Virtex2 design
49478: 02/11/13: Re: HDL vs RTL
49479: 02/11/13: Re: multi-channel filters - how many channels?
49487: 02/11/13: Re: Registering inputs or outputs of modules
49512: 02/11/14: Re: How much to build this? xvga to ntsc uhf broadcaster
49513: 02/11/14: Re: Anyone has VHDL code for decimator and interpolater?
49515: 02/11/14: Re: C\C++ to VHDL Converter
49516: 02/11/14: Re: multi-channel filters - how many channels?
49517: 02/11/14: Re: LUT Consumption in Virtex-2
49518: 02/11/14: Re: Registering inputs or outputs of modules
49523: 02/11/14: Re: LU-decomposition
49524: 02/11/14: Re: Feedback from a 200 MHz Virtex2 design
49525: 02/11/14: Re: Question about algorithm implementing in FPGA
49553: 02/11/14: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49593: 02/11/16: Re: Global clock routing
49628: 02/11/18: Re: Metastability in FPGAs
49629: 02/11/18: Re: Anyone has VHDL code for decimator and interpolater?
49672: 02/11/19: Re: Metastability in FPGAs
49674: 02/11/19: Re: clock difference between DLL input and output?
49695: 02/11/19: Re: Metastability in FPGAs
49709: 02/11/19: Re: Metastability in FPGAs
49710: 02/11/19: Re: FPGA to implement Bluetooth baseband
49711: 02/11/19: Re: how to use carry chain in Virtexe
49715: 02/11/19: Re: C\C++ to VHDL Converter
49716: 02/11/19: Re: C\C++ to VHDL Converter
49727: 02/11/20: Re: how to use carry chain in Virtexe
49762: 02/11/20: Re: Webpack and Virtex Pro?
49773: 02/11/21: Re: Global clock routing
49781: 02/11/21: Re: C\C++ to VHDL Converter
49782: 02/11/21: Re: programmable oscillator for Virtex-E (XCV2000E)
49783: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49784: 02/11/21: Re: how to use carry chain in Virtexe
49796: 02/11/21: Re: Global clock routing
49814: 02/11/21: Re: Global clock routing
49816: 02/11/21: Re: C\C++ to VHDL Converter
49835: 02/11/22: Re: Metastability in FPGAs
49843: 02/11/22: Re: Global clock routing
49850: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49851: 02/11/22: Re: LUT Consumption in Virtex-2
49852: 02/11/22: Re: how to use carry chain in Virtexe
49856: 02/11/22: Re: hardware image processing - log computation
49864: 02/11/22: Re: Conversion functions
49877: 02/11/23: Re: C\C++ to VHDL Converter
49921: 02/11/25: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49958: 02/11/26: Re: Fast Digital Synthesis Generator
49998: 02/11/27: Re: count based Frequency generator
49999: 02/11/27: Re: question about PCB traces for FPGA board... ?
50000: 02/11/27: Re: question about PCB traces for FPGA board... ?
50069: 02/11/30: Re: Spartan-II 2S200 PCI Board
50074: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
50086: 02/12/01: Re: ModelSim XE vcom 5.6a #ERROR: cannot read output
50087: 02/12/01: Re: question about programmable oscillator ?
50188: 02/12/04: Re: clock difference between DLL input and output?
50209: 02/12/05: Re: clock difference between DLL input and output?
50224: 02/12/05: Re: clock difference between DLL input and output?
50235: 02/12/06: Re: meaning of system gates vs. logic gates?
50269: 02/12/07: Re: Clocking in a Spartan IIE
50271: 02/12/07: Re: Clocking in a Spartan IIE
50295: 02/12/08: Re: memory in VHDL
50308: 02/12/08: Re: Virtex archtecture question
50323: 02/12/09: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
50349: 02/12/09: Re: clock recovery suggestions
50367: 02/12/10: Re: How to assign pins in VHDL?
50374: 02/12/10: Re: How to assign pins in VHDL?
50375: 02/12/10: Re: How to assign pins in VHDL?
50377: 02/12/10: Re: FPGA/PCI on low budget
50406: 02/12/10: Re: Clocking in a Spartan IIE
50408: 02/12/10: Re: How to assign pins in VHDL?
50409: 02/12/10: Re: FPGA/PCI on low budget
50410: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
50433: 02/12/10: Re: Clocking in a Spartan IIE
50438: 02/12/10: Re: ISA bus VGA
50439: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
50440: 02/12/10: Re: FPGA/PCI on low budget
50456: 02/12/11: Re: hardware image processing - log computation
50473: 02/12/11: Re: hardware image processing - log computation
50491: 02/12/11: Re: hardware image processing - log computation
50504: 02/12/11: Re: FPGA/PCI on low budget
50527: 02/12/12: Re: FPGA startup events
50556: 02/12/12: Re: what makes an implementation a patent?
50625: 02/12/14: Re: SpartanII Internal Clock ?
50703: 02/12/18: Re: How to asynchronously reset a flip-flop?
50704: 02/12/18: Re: Video timing generator on a Flex 20K / Acex 1K.
50726: 02/12/18: Re: FPGA instead of HDMP-1022/24
50745: 02/12/18: Re: Display "real" waves in simulation?
50754: 02/12/18: Re: How to asynchronously reset a flip-flop?
50756: 02/12/18: Re: Matrics Memory controller
50764: 02/12/19: Re: Display "real" waves in simulation?
50765: 02/12/19: Re: hardware image processing - log computation
50781: 02/12/19: Re: Is there any generic BIST architectures for Xilinx FPGAs for
50782: 02/12/19: Re: 16-bit LFSR
50794: 02/12/19: Re: Multi cycle Paths..
50808: 02/12/20: Re: Hi xilinx
50832: 02/12/20: Re: stupid rookie timing question
50847: 02/12/20: Re: FPGA Supercomputing opportunity
50848: 02/12/20: Re: How to handle Fautly Interconnection in Virtex ?
50849: 02/12/20: Re: Hi xilinx
50850: 02/12/20: Re: Async RAM on an FPGA board
50855: 02/12/20: Re: FPGA Supercomputing opportunity
50876: 02/12/21: Re: FPGA Supercomputing opportunity
50885: 02/12/21: Re: stupid rookie timing question
50886: 02/12/21: Re: Async RAM on an FPGA board
50888: 02/12/21: Re: stupid rookie timing question
50920: 02/12/23: Re: serdes
51218: 03/01/07: Re: Constraining a purely combinatorial logic path
51290: 03/01/10: Re: Xilinx 5.1i Map question
51391: 03/01/12: Re: SChematic design approach compared to VHDL entry approach
51433: 03/01/13: Re: Simulate Virtex Primitive using ModelSim
51453: 03/01/14: Re: Simulate Virtex Primitive using ModelSim
51474: 03/01/14: Re: Virtex, Virtex II and Virtex II Pro
51503: 03/01/15: Re: Open FPGA please!
51524: 03/01/15: Re: Open FPGA please!
51525: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51532: 03/01/15: Re: Open FPGA please!
51533: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51553: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
51562: 03/01/16: Re: 200K gates FPGA for GPU
51593: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51598: 03/01/17: Re: Xilinx Constraint Problem
51610: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51634: 03/01/17: Re: quality of software tools in general
51656: 03/01/18: Re: quality of software tools in general
51658: 03/01/18: Re: Schematic design approach compared to VHDL entry approach
51679: 03/01/19: Re: quality of software tools in general
51680: 03/01/19: Re: quality of software tools in general
51699: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51735: 03/01/20: Re: frequency matching of ring oscillators
51741: 03/01/21: Re: XST vs Synplify observations
51743: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51764: 03/01/21: Re: Virtex II embedded multipliers
51765: 03/01/21: Re: Tristate vs. MUX
51782: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51804: 03/01/22: Re: VHDL or Verilog?
51805: 03/01/22: Re: quality of software tools in general
51820: 03/01/22: Re: Virtex II: noise on Vcco causing loss of DCM lock
51898: 03/01/24: Re: What's the difference between LUT and RAM?
51911: 03/01/25: Re: Why so many pins?
51912: 03/01/25: Re: What's the difference between LUT and RAM?
51952: 03/01/27: Re: Extending a Virtex-II block RAM?
51960: 03/01/27: Re: Carry Logic propagation delay
51961: 03/01/27: Re: What's the difference between LUT and RAM?
51972: 03/01/28: Re: Carry Logic propagation delay
51973: 03/01/28: Re: VHDL or Verilog?
51986: 03/01/28: Re: 1024bit Adder
51990: 03/01/28: Re: Installing 2 versions of Xilinx software in the same machine
52001: 03/01/28: Re: What's the difference between LUT and RAM?
52013: 03/01/28: Re: Random number generator
52044: 03/01/29: Re: Xilinx memory size
52110: 03/01/31: Re: Random number generator (OT)
52111: 03/01/31: Re: STATE PROBLEM!
52140: 03/02/03: Re: SChematic design approach compared to VHDL entry approach
52153: 03/02/03: Re: Xilinx SwitchBox Structure
52154: 03/02/03: Re: one hot encoding
52163: 03/02/03: Re: Modules in a large design
52164: 03/02/03: Re: which microprocessor core?
52209: 03/02/04: Re: Modules in a large design
52219: 03/02/04: Re: xilinx virtex II floorplanning
52220: 03/02/04: Re: component instantiation in Xilinx
52227: 03/02/04: Re: Clock Enables
52229: 03/02/05: Re: low pass FIR filter in FPGA
52230: 03/02/05: Re: xilinx virtex II floorplanning
52258: 03/02/05: Re: DSP design in fpga - general guidelines please.
52277: 03/02/05: Re: Switching synthesis tools
52302: 03/02/06: Re: Help needed
52309: 03/02/06: Re: Help needed
52317: 03/02/06: Re: Help needed
52319: 03/02/06: Re: Clock Enables
52367: 03/02/07: Re: Partial Reconfiguration - Virtex-E
52368: 03/02/07: Re: Carry Save Adder
52397: 03/02/08: Re: FFT Size and speed
52398: 03/02/08: Re: FFT Size and speed
52399: 03/02/08: Re: Xilinx ISE 4.2i killing Windows 2000?
52400: 03/02/08: Re: Annapolis Microsystems Wildcard
52437: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
52469: 03/02/11: Re: Fast BlockRAM updates
52494: 03/02/11: Re: JBits
52515: 03/02/12: Re: Fast BlockRAM updates
52516: 03/02/12: Re: Fast BlockRAM updates
52517: 03/02/12: Re: Newbie Starting Places + Books?
52525: 03/02/12: Re: Distributed RAM/ROM
52528: 03/02/12: Re: difficulty in designing butterfly processor
52545: 03/02/13: Re: Newbie Starting Places + Books?
52551: 03/02/13: Re: Causing Modelsim to break using VHDL code
52747: 03/02/20: Re: Generating a sin wave with vhdl
52748: 03/02/20: Re: Xilinx Filter
52786: 03/02/21: Re: Generating a sin wave with vhdl
53049: 03/03/01: Atmel and Hotworks boards for sale
53051: 03/03/01: Re: Atmel and Hotworks boards for sale
53081: 03/03/03: Re: FPGA demo board schematic
53100: 03/03/04: Re: VHDL & FPGA Design tools
53102: 03/03/04: Re: Connect USB device to Spartan 2e FPGA
53166: 03/03/05: Re: VHDL & FPGA Design tools
53204: 03/03/06: Re: filter coefficients from sig. proc. toolbox to xilinx
53205: 03/03/06: Re: Partial reconfiguration
53218: 03/03/06: Re: Annapolis Microsystems Wildcard
53220: 03/03/07: VCC XC6216 Hotworks board for sale
53292: 03/03/10: Re: Multipliers Architectures use on FPGA COREGEN
53293: 03/03/10: Re: Motion Control IP Cores , anyone do them ?
53304: 03/03/10: Re: Minimum Real-state K-multiplier/divider
53313: 03/03/10: Re: Altera Clock
53315: 03/03/10: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
53325: 03/03/11: Re: Are there any FPGA magazines/journals?
53359: 03/03/11: Re: Can you recommend a text on...?
53434: 03/03/13: Re: The structure of the multiplier
53435: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53459: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53477: 03/03/14: Re: Path delay and timer question
53479: 03/03/14: Re: Using divided clock
53482: 03/03/14: Re: Adding delay to a signal?
53500: 03/03/14: Re: ROM containing complex numbers
53501: 03/03/14: Re: Adding delay to a signal?
53502: 03/03/14: Re: Adding delay to a signal?
53548: 03/03/16: Re: Adding delay to a signal?
53584: 03/03/17: Re: Help understanding 7408 and gate chip
53616: 03/03/18: Re: more footprints...
53633: 03/03/18: Re: Modelsim - FPGA - Simulink integration
53659: 03/03/19: Re: IFDs in Xilinx Foundation 4.1i
53678: 03/03/19: Re: Using FPGAs as coprocessors in a PC
53679: 03/03/19: Re: Bit patching of Xilinx VIRTEX-II devicex?
53754: 03/03/21: Re: FPGA FFT Questions
53762: 03/03/21: Re: source code for crc
53769: 03/03/22: Re: FPGA FFT Questions
53779: 03/03/22: Re: how do implement the algorithm in verilog?
53780: 03/03/22: Re: FPGA FFT Questions
53840: 03/03/25: Re: Permanent Local Damage to FPGA
53868: 03/03/26: Re: Permanent Local Damage to FPGA
53869: 03/03/26: Re: xst removes useful signals
53954: 03/03/28: Re: CLKDLL synthesized with synplify pro
53976: 03/03/29: Re: Spartan vs. Cyclone for arithmetic functions
54057: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54091: 03/04/02: Re: Matrix multiply in FPGA
54092: 03/04/02: Re: FFT 256pt on Spartan
54115: 03/04/02: Re: Matrix multiply in FPGA
54166: 03/04/03: Re: What is DA and SLR16?
54167: 03/04/03: Re: What is DA and SLR16?
54204: 03/04/04: Re: FFT 256pt on Spartan
54213: 03/04/04: Re: What is DA and SLR16?
54269: 03/04/06: Re: Should I bother with Xilinx Foundation 1.5 vs 2.1?
54535: 03/04/13: Re: An Improvement for the Booth multiplier
54595: 03/04/14: Re: An Improvement for the Booth multiplier
54604: 03/04/14: Re: Xilinx has released SpartanIII
54619: 03/04/15: Re: request for simple UART
54620: 03/04/15: Re: fpga fault tolerence.
54621: 03/04/15: Re: Clock Doubled domain
54647: 03/04/15: Re: Xilinx core generator: core speed?
54648: 03/04/15: Re: request for simple UART
54676: 03/04/15: Re: request for simple UART
54677: 03/04/15: Re: Xilinx core generator: core speed?
54678: 03/04/15: Re: fpga fault tolerence.
54709: 03/04/16: Re: Xilinx has released SpartanIII
54710: 03/04/16: Re: Basic components with Core generator?
54711: 03/04/16: Re: Hardware acceleration for raytracing purposes
54892: 03/04/21: Re: Clock Doubled domain
54903: 03/04/22: Re: spartan2e vs cyclone
54909: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE
54910: 03/04/22: Re: Complex FIR in FPGA
54940: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE software
54969: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6e
54985: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6estarter
54986: 03/04/23: Re: Challenge: (n mod 3) in hardware???
55036: 03/04/25: Re: Large adder placement / synthesis
55073: 03/04/25: Re: Large adder placement / synthesis
55074: 03/04/25: Re: Large adder placement / synthesis
55076: 03/04/25: Re: Dynamic Reconfigurable FPGAs
55090: 03/04/26: Re: Advice on FPGA IIR Filter
55091: 03/04/26: Re: Dynamic Reconfigurable FPGAs
55176: 03/04/29: Re: Xilinx XAct
55177: 03/04/29: Re: DSP/FPGA board
55180: 03/04/29: Re: RF transmitters/receivers with Xilinx Xtreme DSP Kit
55243: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE software
55246: 03/05/01: Re: DSP/FPGA board
55247: 03/05/01: Re: Schmitt Trigger an a Virtex
55277: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
55278: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software
55290: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software
55298: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
55299: 03/05/02: Re: Thermal Data for Logic Devices
55353: 03/05/05: Re: Thermal Data for Logic Devices
55395: 03/05/06: Re: xilinx area measure?
55400: 03/05/06: Re: Thermal Data for Logic Devices
55403: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
55404: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
55420: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
55421: 03/05/07: Re: OT: looking for I/Q mixers/modulators for TX and RX
55433: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
55456: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
55458: 03/05/09: Re: accurate power measurements
55541: 03/05/12: Re: Register in FPGA
55543: 03/05/12: Re: where to buy 1 virtex-e fg680
55560: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55566: 03/05/12: Re: How do I know of Xilinx connectivity restrictions?
55617: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
55618: 03/05/14: Re: how to calculate the gate count required for a FPGA design
55624: 03/05/14: Re: "Primitives" in XST?
55641: 03/05/14: Re: how to calculate the gate count required for a FPGA design
55663: 03/05/15: Re: how to calculate the gate count required for a FPGA design
55665: 03/05/15: Re: how to calculate the gate count required for a FPGA design
55702: 03/05/16: Re: VitalGlitch
55789: 03/05/20: Re: a (PC) workstation for FPGA development
55803: 03/05/20: Re: a (PC) workstation for FPGA development
55804: 03/05/20: Re: what are DCMs in FPGA
55820: 03/05/20: Re: a (PC) workstation for FPGA development
55830: 03/05/21: Re: a (PC) workstation for FPGA development
55845: 03/05/21: Re: a (PC) workstation for FPGA development
55853: 03/05/21: Re: FPGA design: firmware or hardware?
55871: 03/05/22: Re: FPGA design: firmware or hardware?
55885: 03/05/22: Re: a (PC) workstation for FPGA development
55897: 03/05/23: Re: a (PC) workstation for FPGA development
55898: 03/05/23: Re: FPGA design: firmware or hardware?
55916: 03/05/23: Re: FPGA design: firmware or hardware?
55920: 03/05/23: Re: FPGA design: firmware or hardware?
55992: 03/05/26: Re: fir distributed arithmetic
56081: 03/05/28: Re: FIFO Controller
56217: 03/05/31: Re: FIFO Controller
56218: 03/05/31: Re: FIFO Controller
56255: 03/06/01: Re: power consumption in CMOS..
56258: 03/06/01: Re: Need help with Xilinx ISE
56276: 03/06/02: Re: Need help with Xilinx ISE
56300: 03/06/02: Re: Xilinx : BEL constraint vs. ModelSim
56450: 03/06/05: Re: Multipliers - Ram ratio
56462: 03/06/05: Re: Multipliers - Ram ratio
56832: 03/06/16: Re: spartan 2e dll locking
56920: 03/06/18: Re: Controlling FPGA speed with VCCINT
57222: 03/06/25: Re: Interfacing IDE
57223: 03/06/25: Re: Multirate system in fpga
57864: 03/07/08: Re: scaling fixed point fft
57961: 03/07/10: Re: cascaded DLL's in VirtexE, routing problems
58008: 03/07/11: Re: DDS theory of operation
58009: 03/07/11: Re: Seminar: Digital Signal Processing, Programmable Device
58010: 03/07/11: Re: Fixed point signed multiplication algorithm
58085: 03/07/14: Re: Combinational logic and gate delays - Help
58086: 03/07/14: Re: An All Digital Phase Lock Loop
58096: 03/07/14: Re: An All Digital Phase Lock Loop
58173: 03/07/16: Re: An All Digital Phase Lock Loop
58187: 03/07/16: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
58189: 03/07/16: Re: Xilinx --> WARNING:DesignRules:372
58190: 03/07/16: Re: Cyclone vs Spartan-3
58191: 03/07/16: Re: device selection for game system
58248: 03/07/17: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
58249: 03/07/17: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
58282: 03/07/18: Re: How fast coregen FIR?
58285: 03/07/18: Re: An All Digital Phase Lock Loop
58369: 03/07/21: Re: device selection for game system
58409: 03/07/22: Re: FPGA Editor
58410: 03/07/22: Re: FPGA Editor
58411: 03/07/22: Re: asynchronous FIFO
58446: 03/07/23: Re: FPGA Editor
58453: 03/07/23: Re: Use ICAp iwth a soft IP core to decompress!!!!
58504: 03/07/24: Re: FPGA Editor
58505: 03/07/24: Re: FPGA Editor
58506: 03/07/24: Re: FPGA Editor
58633: 03/07/29: Re: how to design hardware for 2's complement parallel multiplier(at
58750: 03/07/31: Re: Question: String matching with CAM?
59413: 03/08/18: Re: custom memory array implementaion
59416: 03/08/18: Re: Old Xilinx FPGAs
59517: 03/08/20: Re: Xilinx FPGA pin locking/assignment
59588: 03/08/22: Re: DA FIR filter vs. MAC FIR filter
59589: 03/08/22: Re: ise 5.2 timing summary
59590: 03/08/22: Re: Async logic in FPGAs
59662: 03/08/25: Re: Thinking out loud about metastability
59665: 03/08/25: Re: Which Adder?
59675: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
59676: 03/08/25: Re: Thinking out loud about metastability
59677: 03/08/25: Re: TIG Constraint
59678: 03/08/25: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
59679: 03/08/25: Re: two questions
59770: 03/08/28: Re: How to listen to music through an FPGA pin?
59781: 03/08/28: Re: Thinking out loud about metastability
59797: 03/08/28: Re: Moving Sum
59801: 03/08/28: Re: How to listen to music through an FPGA pin?
59963: 03/09/02: Re: Compact FIR filters with multiplier blocks?
59969: 03/09/02: Re: HDL Designer from Mentor
59972: 03/09/02: Re: FPGA/DSP Expert - business partner for innovative FFT
59976: 03/09/03: Re: Thinking out loud about metastability
59997: 03/09/03: Re: Compact FIR filters with multiplier blocks?
60028: 03/09/03: Re: Thinking out loud about metastability
60069: 03/09/04: Re: Moving Sum
60075: 03/09/04: Re: New to FPGA, seeking advice
60128: 03/09/05: Re: New to FPGA, seeking advice
60129: 03/09/05: Re: Moving Sum
60175: 03/09/06: Re: Schematic simulation and then FPGA programming?
60513: 03/09/15: Re: FPGA start?
60514: 03/09/15: Re: fft size in fpga
60517: 03/09/15: Re: DDC design
60518: 03/09/15: Re: Original (5V) Xilinx Spartan ?
60625: 03/09/17: Re: Xilinx
60631: 03/09/17: Re: Xilinx
60654: 03/09/18: Re: Using LUTs for array of coefficients
60655: 03/09/18: Re: divide by on spartan3?
60702: 03/09/19: Re: Xilinx
60704: 03/09/19: Re: Xilinx
60706: 03/09/19: Re: Crystal Input to FPGA
60708: 03/09/19: Re: AWGN in VHDL
60718: 03/09/19: Re: Some question about using FPGA
60719: 03/09/19: Re: hardware image processing - log computation
60720: 03/09/19: Re: pipelined divider
60721: 03/09/19: Re: Transistor count
60722: 03/09/19: Re: fft size in fpga
60733: 03/09/20: Re: divide by on spartan3?
61158: 03/09/29: Re: OT: spam poll
61159: 03/09/29: Re: OT: spam poll
61164: 03/09/29: Re: Embedded/Microcontroller FPGA and Software Defined Radio
61165: 03/09/29: Re: pipelined divider
61323: 03/10/01: Re: Xilinx
61324: 03/10/01: Re: Xilinx
61325: 03/10/01: Re: Xilinx
61326: 03/10/01: Re: Using LUTs for array of coefficients
61335: 03/10/01: Re: Good VHDL/Verilog editor?
61336: 03/10/01: Re: Counting ones
61564: 03/10/06: Re: RLOC specification
61581: 03/10/07: Re: Interesting article about FPGAs
61595: 03/10/07: Re: More RPM / RLOC fun
61596: 03/10/07: Re: ise 5.2 sp 3 for spartan 3
61597: 03/10/07: Re: BF957C Application
61598: 03/10/07: Re: Xilinx courses
61599: 03/10/07: Re: Xilinx courses
61605: 03/10/07: Re: More RPM / RLOC fun
61606: 03/10/07: Re: Should I worry about metastability
61607: 03/10/07: Re: Should I worry about metastability
61608: 03/10/07: Re: Should I worry about metastability
61609: 03/10/07: Re: Timing from 1x to 2x and back
61621: 03/10/07: Re: More RPM / RLOC fun
61623: 03/10/07: Re: Xilinx DCMs, DDR, CLK0, and CLK180
61628: 03/10/08: Re: Digesting runs of ones or zeros "well"
61629: 03/10/08: Re: Digesting runs of ones or zeros "well"
61630: 03/10/08: Re: Digesting runs of ones or zeros "well"
61657: 03/10/08: Re: Instantiating LUTs and INIT strings [was Re: Digesting runs of ones
61682: 03/10/08: Re: Digesting runs of ones or zeros "well"
61683: 03/10/08: Re: Should I worry about metastability
61684: 03/10/08: Re: More RPM / RLOC fun
61691: 03/10/09: Re: Visualizing VHDL
61692: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61706: 03/10/09: Re: More RPM / RLOC fun
61733: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61734: 03/10/09: Re: Xilinx dedicated multiers vs multipliers in slice fabric
61735: 03/10/09: Re: Where is the logic?
61741: 03/10/09: Re: Where is the logic?
61742: 03/10/09: Re: Where is the logic?
61754: 03/10/10: Re: Digesting runs of ones or zeros "well"
61756: 03/10/10: Re: Inferring an accumulator using Verilog on Xilinx Spartan 2e
61768: 03/10/10: Re: Floorplanning, Routing, FPGA Editor
61791: 03/10/10: Re: Digesting runs of ones or zeros "well"
61913: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61915: 03/10/15: Re: How to program an XC5210
61929: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61954: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61955: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61982: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61983: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62005: 03/10/16: Re: Ph.inisheD.
62027: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
62112: 03/10/19: Re: ISE5.2 to ISE6.1
62135: 03/10/20: Re: Xilinx Slice and Altera ...?
62137: 03/10/20: Re: Should I worry about metastability
63525: 03/11/24: Re: any FPGA design for video frame memory control?
63957: 03/12/10: Re: Skew between the output of a DCM ?
63958: 03/12/10: Re: 400 Mb/s ADC
63960: 03/12/10: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
64006: 03/12/11: Re: Skew between the output of a DCM ?
64170: 03/12/18: Re: FIR Filter cores for Virtex-][
64194: 03/12/19: Re: FIR Filter cores for Virtex-][
64250: 03/12/22: Re: FIR Filter cores for Virtex-][
64253: 03/12/22: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64254: 03/12/22: Re: Spartan3 availability
64279: 03/12/23: Re: Spartan3 availability
64286: 03/12/24: Re: Spartan3 availability
64307: 03/12/26: Re: Spartan3 availability
64349: 03/12/29: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64482: 04/01/05: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64536: 04/01/07: Re: Is the P&R processing time proportional to the FPGA gate count or
64537: 04/01/07: Re: Questions about guard bits in CORDIC algorithm
64573: 04/01/07: Re: Virtex and Spartan
64806: 04/01/14: Re: Synthesis in VHDL vs. Verilog
64967: 04/01/16: Re: Why won't Xilinx document their code??
64968: 04/01/16: Re: Port mapping a Verilog component in a VHDL design
64990: 04/01/18: Re: How to generate a CSA tree?
64991: 04/01/18: Re: How to generate a CSA tree?
65061: 04/01/19: Re: par problems with modular design for partial reconfiguration
65077: 04/01/19: Re: par problems with modular design for partial reconfiguration
65121: 04/01/20: Re: SDRAM Controller timing problem
65176: 04/01/21: Re: OT: liability insurance
65178: 04/01/21: Re: Hardware to test (FPGA-based) prototype?
65189: 04/01/21: Re: OT: liability insurance
65190: 04/01/21: Re: WTD: info on AMD palce22v10
65232: 04/01/22: Re: OT: liability insurance
65233: 04/01/22: Re: WTD: info on AMD palce22v10
65254: 04/01/22: Re: OT: liability insurance
65299: 04/01/23: Re: Synthesizing pipelined multipliers in Synplify Pro
65300: 04/01/23: Re: is this a good idea
65305: 04/01/23: Re: Xilinx LVDS_25_DT termination issues????
65306: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65310: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65329: 04/01/24: Re: xilinx 70% tracking rule
65362: 04/01/26: Re: How to do with guard bits practically?
65371: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65372: 04/01/26: Re: Tristate buffer
65373: 04/01/26: Re: How to do with guard bits practically?
65375: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65379: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65448: 04/01/29: Re: building macros for Virtex-II with FPGA editor...
65466: 04/01/29: Re: Is FPGA fully static?
65468: 04/01/29: Re: Where to get FPGA devices for testing?
65496: 04/01/30: Re: Good/Affordable Stater kits
65576: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
65577: 04/02/02: Re: Where to get FPGA devices for testing?
65601: 04/02/03: Re: using IIR in DDC
65624: 04/02/03: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
65634: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
65638: 04/02/03: Re: Stratix II NIOS sizes ?
65721: 04/02/05: Re: The fastest interface between FPGA's
65723: 04/02/05: Re: Fast Fourier Transform
65745: 04/02/05: Re: A small clock synchronization challenge with Virtex E
66038: 04/02/11: Re: Pricing, 101
66040: 04/02/11: Re: attribute +generate statement
66059: 04/02/12: Re: Sine Wave Generation
66088: 04/02/12: Re: Sine Wave Generation
66113: 04/02/12: Re: is this enable structure ok for synthesis/high speed?
66185: 04/02/13: Re: Pricing, 101
66188: 04/02/13: Re: Sensible starter FPGA board
66220: 04/02/15: Re: DCM Jitter?
66365: 04/02/18: Re: GSR in Spartan3 ?
66400: 04/02/18: Re: Can FPGA bootstrap itself?
66401: 04/02/18: Re: regarding synchronization
66402: 04/02/18: Re: GSR in Spartan3 ?
66473: 04/02/19: Re: Dual-stack (Forth) processors
66505: 04/02/20: Re: GZIP algorithm in FPGA
66506: 04/02/20: Re: altera, xilinx susceptible to power transients?
66507: 04/02/20: Re: Array Divider
66513: 04/02/20: Re: multiple clocking in FPGA
66580: 04/02/23: Re: altera, xilinx susceptible to power transients?
66589: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66601: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66699: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66794: 04/02/26: Re: altera, xilinx susceptible to power transients?
66814: 04/02/26: Re: Suggestions: Eval/Demo Board.
66817: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66818: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66891: 04/02/28: Re: Polyphase filter
66910: 04/02/29: Re: difference btw H/W & S/W implementations !!
67002: 04/03/03: Re: Design never finish routing?
67033: 04/03/03: Re: XST ff merging - how do I "preserve" flip flops
67073: 04/03/04: Re: Global reset question?
67079: 04/03/04: Re: Global reset question?
67106: 04/03/05: Re: Global reset question?
67199: 04/03/08: Re: Can anyone advise me on how to reduce the compilation time for our
67215: 04/03/08: Re: Release asynchrounous resets synchronously
67262: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
67263: 04/03/09: Re: sorting need help as soon as possible
67266: 04/03/09: Re: Release asynchrounous resets synchronously
67278: 04/03/09: Re: sorting need help as soon as possible
67281: 04/03/09: Re: Release asynchrounous resets synchronously
67302: 04/03/09: Re: Release asynchrounous resets synchronously
67434: 04/03/11: Re: what exactly means fanout ?
67437: 04/03/11: Re: CORDIC vs. LUT
67438: 04/03/11: Re: Release asynchrounous resets synchronously
67447: 04/03/11: Re: Answering Machine RAM
67660: 04/03/16: Re: Answering Machine RAM
67695: 04/03/17: Re: newbie question about fpga internals
67696: 04/03/17: Re: Schematic Edition Tool : Suggestions
67707: 04/03/17: Re: newbie question about fpga internals
67708: 04/03/17: Re: Answering Machine RAM
67803: 04/03/19: Re: Xilinx ISE 6.2 and Virtex-II
67948: 04/03/23: Re: How many times can I burn an FPGA?
67962: 04/03/23: Re: How many times can I burn an FPGA?
67974: 04/03/23: Re: Bus width between registers in IIR
68000: 04/03/24: Re: Bus width between registers in IIR
68051: 04/03/25: Re: Bus width between registers in IIR
68111: 04/03/26: Re: Generating Xilinx cores.
68118: 04/03/26: Re: Spartan RAMB4 Timing
68126: 04/03/26: Re: Spartan RAMB4 Timing
68227: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68233: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68248: 04/03/31: Re: Real-time Image Process on FPGA
68276: 04/03/31: Re: Is there any Sync separator IP(Intellectual property) exists?
68278: 04/03/31: Re: Real-time Image Process on FPGA
68280: 04/03/31: Re: rs232 interface on nios
68281: 04/03/31: Re: speed vs. temperature
68304: 04/04/01: Re: Replace PPC in V2P with FPGA fabric!
68323: 04/04/01: Re: Replace PPC in V2P with FPGA fabric!
68462: 04/04/05: Re: Designing MUX with tri sate bus in xilinx virtex II FPGA
68467: 04/04/05: Re: Real-time Image Process on FPGA
68468: 04/04/05: Re: Logic required for multiplication
68485: 04/04/06: Re: Designing MUX with tri sate bus in xilinx virtex II FPGA
68497: 04/04/06: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
68554: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
68571: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68595: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68596: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68722: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
68724: 04/04/15: Re: Apples to Apples? Stratix II <> Virtex-II Pro
68807: 04/04/19: Re: vhdl example for use of external SRAM as a dual ported RAM?
68827: 04/04/19: Re: Image-reject IF downmixing
69046: 04/04/26: Re: Inferring Dynamic shift registers in XST
69069: 04/04/26: Re: Stretch Inc
69084: 04/04/26: Re: Inferring Dynamic shift registers in XST
69085: 04/04/26: Re: Inferring Dynamic shift registers in XST
69164: 04/04/28: Re: Image-reject IF downmixing
69165: 04/04/28: Re: Inferring Dynamic shift registers in XST
69302: 04/05/05: Re: XST, Virtex2-Pro, odd PAR counter timing failure
69332: 04/05/06: Re: Wire crossing in a large partially reconfigurable design.
69372: 04/05/08: Re: Muxes : 64X1
69436: 04/05/11: Re: FPGA wanted
69472: 04/05/11: Re: FPGA wanted
69473: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") -
69553: 04/05/13: Re: V2p block ram clock -> Q delay help
69561: 04/05/13: Re: V2p block ram clock -> Q delay help
69576: 04/05/14: Re: Quartus II Web Edition
69593: 04/05/14: Re: Simple way to generate random netlists of ALU cells
69672: 04/05/17: Re: Simple way to generate random netlists of ALU cells
69715: 04/05/18: Re: How to select an FPGA size (beginner)
69726: 04/05/18: Re: Webpack 6.1, ISEexamples, and CoreGen
69727: 04/05/18: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69743: 04/05/19: Re: How to select an FPGA size (beginner)
69744: 04/05/19: Re: Webpack 6.1, ISEexamples, and CoreGen
69787: 04/05/19: Re: How to select an FPGA size (beginner)
69788: 04/05/19: Re: Nios II Going Live...
69790: 04/05/20: Re: How to select an FPGA size (beginner)
69872: 04/05/22: Re: OT: Electronics learner kit?
70072: 04/06/01: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70091: 04/06/02: Re: FPGA + A/D converter
70099: 04/06/02: Re: 5 V inputs to 3.3 V CPLD
70120: 04/06/03: Re: tri-state in altera
70135: 04/06/04: Re: tri-state in altera and xilinx
70136: 04/06/04: Re: tri-state in altera and xilinx
70141: 04/06/04: Re: tri-state in altera and xilinx
70142: 04/06/04: Re: tri-state in altera and xilinx
70193: 04/06/08: Re: slice # change from .syr to map report
70287: 04/06/11: Re: Xilinx: infering dual port ROM in VHDL
70355: 04/06/14: Re: SDRAM
70602: 04/06/21: Re: Is there a verilog version of PicoBlaze?
70638: 04/06/22: Re: VIRTEX v Spartan 3
70648: 04/06/22: Re: Family Photo Album
70701: 04/06/23: Re: Exponential Function
70724: 04/06/24: Re: RAM in Altera EABs and Xilinx Block Rams
71289: 04/07/13: Re: FIR filter running out of FPGA memory in stratix ep1s60
71329: 04/07/14: Re: new Lattice FPGAs vs Cyclone and SpartanIII
71330: 04/07/14: Re: FPGAs starting with incorrect bitstream !?
71372: 04/07/15: Re: FPGA with fully asynchronous RAM
71392: 04/07/16: Would Tom buy from Nu Horizons?
71393: 04/07/16: Re: Multi-phase Motor Controller?
71597: 04/07/23: Re: Xilinx registers resetr value
73962: 04/10/01: Re: Removing set/reset logic for shift register (HDL ADVISOR )
73964: 04/10/01: Re: Xilinx SRL16 test
72997: 04/09/09: Re: Completed my first Virtex4 design
73494: 04/09/22: Re: Ring Oscillator Redux
74941: 04/10/21: Re: Async reset
74942: 04/10/21: Re: ModelSim is ungraceful with my stupidity...
74973: 04/10/22: Re: Altera Cubic Cyclonium
75019: 04/10/24: Re: Altera Cubic Cyclonium
75097: 04/10/26: Re: Low-power FPGAs?
75305: 04/11/01: Re: "frying" FPGAs
74089: 04/10/03: Re: Hardware Log and EXP
74090: 04/10/03: Re: Hardware Log and EXP
74092: 04/10/03: Re: How to generate a signal on Xilinx Spartan II
74093: 04/10/03: Re: Removing set/reset logic for shift register (HDL ADVISOR )
74118: 04/10/04: Re: XC2V1000 Block RAM size
74188: 04/10/05: Re: Sine function implementation in FPGA??
74189: 04/10/05: Re: Xilinx Multiple Clock Domains
74237: 04/10/06: Re: I need help for Xilinx Demo Board (XC40xx-PC84
74268: 04/10/06: Re: Removing set/reset logic for shift register (HDL ADVISOR )
74272: 04/10/06: Re: Interfacing an 1GS ADC
74276: 04/10/06: Re: Removing set/reset logic for shift register (HDL ADVISOR )
74407: 04/10/10: Re: Interfacing an 1GS ADC
74408: 04/10/10: Re: Sine function implementation in FPGA
74409: 04/10/10: Re: Xilinx Multiple Clock Domains
74421: 04/10/11: Re: CORDIC NCO Frequency resolution?
74506: 04/10/12: Re: CORDIC NCO Frequency resolution?
74755: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
74756: 04/10/18: Re: Virtex 4 released today
74758: 04/10/18: Re: Virtex 4 released today
74761: 04/10/18: Re: Unwanted shift in multiplier
74768: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
75640: 04/11/11: Re: Xilinx Tshirts in football package.....
75785: 04/11/15: Re: Digital LP filter in multiplier free FPGA
75786: 04/11/15: Re: digital analog conversion
76076: 04/11/23: Re: Favourite Design Entry Optomisation Method?
76131: 04/11/25: Re: how to evaluate the needed number of gate?
76348: 04/11/30: Re: 99% Utilisation !
76359: 04/11/30: Re: CIC - Hogenauer glitch
76360: 04/11/30: Re: Adder Tree Placement
76423: 04/12/01: Re: CIC - Hogenauer glitch
76424: 04/12/01: Re: 99% Utilisation !
76426: 04/12/01: Re: EDIF -> Map & Place -> EDIF ?
76590: 04/12/06: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA
76680: 04/12/08: Re: making an fpga hot
76737: 04/12/09: Re: Adder Tree Placement
76741: 04/12/09: Re: how to speed up my accumulator ??
76742: 04/12/09: Re: how to speed up my accumulator ??
76884: 04/12/15: Re: XILINX slice structure detaild description
76885: 04/12/15: Re: algorithm: square operation
76926: 04/12/15: Re: Inferring SRLs with INIT value
76960: 04/12/17: Re: Inferring SRLs with INIT value
76961: 04/12/17: Re: Digital clock synthesis
76963: 04/12/17: Re: Digital clock synthesis
77180: 04/12/28: Re: MAP failes after inserting ILA and ICON cores to the design
77181: 04/12/28: Re: CIC filter implementation using FPGA
77182: 04/12/28: Re: recommendations for a FIFO..
77219: 04/12/30: Re: Multipliers implementation (xilinx)
77439: 05/01/06: Re: xilinx as video processor?
77553: 05/01/10: Re: a general question
78172: 05/01/25: Re: dsp, arithmetic scaling questions, advice
78173: 05/01/25: Re: Creating a pyramid of shift registers
78989: 05/02/10: Variable phase shift on Spartan3 DCMs. Does it work?
78997: 05/02/10: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79215: 05/02/15: Re: Fast counting in Spartan 3
79334: 05/02/17: Re: clock split approach for 270MHz design in Spartan2E
79365: 05/02/17: Re: FPGA Hardware/Cell Diagnostics
80286: 05/03/03: Re: Need suggestion abt FFs without RST for pipelined datapath.
80788: 05/03/11: Re: FIR Filter On FPGA
80790: 05/03/11: Re: low speed FIR filter in FPGA
80