Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Authors (M)
M:
12855: 98/11/02: Q: fifo flags
13164: 98/11/18: Re: Q: fifo flags
35292: 01/09/27: Fastest way to become a Verilog samurai?
m:
31725: 01/06/04: Re: EPC2: no output signals
123028: 07/08/14: Delaying a pulse train
123030: 07/08/14: Re: Delaying a pulse train
123037: 07/08/14: Re: Delaying a pulse train
123044: 07/08/15: Re: Delaying a pulse train
123119: 07/08/16: Re: Delaying a pulse train
123132: 07/08/16: Re: Delaying a pulse train
125995: 07/11/11: Programming connection
125996: 07/11/11: Re: Programming connection
126008: 07/11/12: Re: Programming connection
126025: 07/11/12: Re: Programming connection
128969: 08/02/11: Re: Virtex5 DCM lower limit
129672: 08/03/02: Re: Software for FPGA-based PC scope
134502: 08/08/14: Re: EBAY: XC2V1000-5FG456C
134503: 08/08/14: Re: EBAY: XC2V1000-5FG456C
135086: 08/09/15: Moving to Altera from Xilinx
135211: 08/09/20: Altera and DDR3
135256: 08/09/23: Re: Altera and DDR3
135829: 08/10/16: Linux on Microblaze
137530: 09/01/21: DVI, HDMI, DisplayPort
137744: 09/01/28: Microblaze and NAND flash
M E:
110565: 06/10/17: 8B/10B vs. Start/Stop for SERDES
117456: 07/03/31: ISE on Fedora?
117758: 07/04/09: Re: ISE on Fedora?
M & J:
17926: 99/09/17: Re: PCI core for Orca 3T
m burgess:
6325: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
6326: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
M Burgess:
864: 95/03/16: Specialist Vacancies
M H:
11685: 98/08/31: Re: CPLD/FPGA software
M Ihsan Baig:
114943: 07/01/27: Higher studies
117934: 07/04/13: SoC
119383: 07/05/17: video soltion provider
119430: 07/05/18: Re: video soltion provider
122841: 07/08/08: Ph.D in France
M Kartheepan:
12231: 98/10/06: Re: FIR Filter Design
12253: 98/10/07: Re: FIR Filter Design
m m:
134648: 08/08/23: Digital-to-Analog Converter LTC 2624, Spartan-3A
134699: 08/08/26: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
134845: 08/09/03: LED lights flashing while LCD shows chars, Spartan-3A
134966: 08/09/08: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
135135: 08/09/17: Two-complement value from ADC, Spartan-3A, 3E
135314: 08/09/25: Re: LED lights flashing while LCD shows chars, Spartan-3A
135720: 08/10/13: Testing Analog-to-Digital Converter, Spartan-3A, LTC1407-A
M Murphy:
17657: 99/08/19: Digital Design Engineer needed - Please read
17905: 99/09/16: Chip Level Ciruit Designers needed, please read
M Pedley:
34247: 01/08/17: Atmel CPLD - JEDEC to ABEL
34279: 01/08/18: Re: Atmel CPLD - JEDEC to ABEL
34872: 01/09/12: Programming Delays in ABEL
34878: 01/09/12: Re: Programming Delays in ABEL
34879: 01/09/12: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
48647: 02/10/22: High Performance FPGA's - Xilinx and ??????
48713: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
49427: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
M R Wheeler:
10504: 98/05/25: Altera MaxPlus using third party programmer
21721: 00/03/30: MaxPlus9.5 License and Fitter problems
21765: 00/03/31: Re: MaxPlus9.5 License and Fitter problems
22330: 00/05/05: MaxPlus9.5/6 License problems
M Schreiber:
40318: 02/03/05: exceeding 2GB limits in xilinx
42393: 02/04/22: Using LogiBlox in Virtex2
45008: 02/07/09: Bi-Directional Bus problem in Xilinx FPGA
45048: 02/07/10: Re: Bi-Directional Bus problem in Xilinx FPGA
48796: 02/10/24: Pin locking Virtex 2 FPGA
49563: 02/11/15: Re: Registering inputs or outputs of modules
51581: 03/01/16: FPGA Express FSM state ordering
52074: 03/01/30: Re: Floor Planning DCM
M Shehzad Hanif:
71311: 04/07/14: Xilinx Virtex-II Configuration in Slave Serial
M Smith:
34337: 01/08/21: Help the clueless guy....
M Sweger:
6927: 97/07/09: Re: Generating Sine/Cosine digitally
15437: 99/03/24: Re: Reconfigurable computing thesis on the web
M Wirtzfeld:
30505: 01/04/11: Introductory Question - LSB to MSB Conversion.
<m-gupta@nwu.edu>:
14687: 99/02/11: Mentor-Alliance Interface
m.:
57055: 03/06/22: vga controller
M. Aberbour:
9054: 98/02/17: System Gates and Logic Cells...
M. Bodnar:
71471: 04/07/19: Boards Comparable to Alpha-Data's ADM-XRC-II
M. Boin:
10733: 98/06/14: Metrology Software- Survey
M. Hamed:
117503: 07/04/02: X_OBUF and other error messages with ModelSim
117549: 07/04/03: Re: X_OBUF and other error messages with ModelSim
117744: 07/04/09: Modelsim Low and High violations
117861: 07/04/11: Timing violations though constraints have been met
117887: 07/04/12: Re: Timing violations though constraints have been met
117891: 07/04/12: SETUP & HOLD time confusion
117944: 07/04/13: Re: SETUP & HOLD time confusion
118117: 07/04/17: Block RAM strange behavior, address off by one
118145: 07/04/18: Re: Block RAM strange behavior, address off by one
118151: 07/04/18: Re: Block RAM strange behavior, address off by one
118163: 07/04/18: Re: Block RAM strange behavior, address off by one
118169: 07/04/18: Re: Block RAM strange behavior, address off by one
118192: 07/04/19: Re: Compiling a library
118393: 07/04/25: Modelsim simulation progress in batch/command line mode?
118400: 07/04/25: Timing constraints with asynchronous clocks
118438: 07/04/26: Re: Modelsim simulation progress in batch/command line mode?
118442: 07/04/26: Re: Timing constraints with asynchronous clocks
118493: 07/04/27: Placement error for adjacent pins
118512: 07/04/28: Re: Placement error for adjacent pins
128650: 08/02/01: Keeping Xilinx tool from Optimizing out Debugging signals
128655: 08/02/01: Re: Keeping Xilinx tool from Optimizing out Debugging signals
129012: 08/02/12: Re: Timing Constraint not met
130098: 08/03/14: Detecting a pulse with minimum width
130105: 08/03/14: Re: Detecting a pulse with minimum width
138513: 09/02/25: Converting state machine encoding to std_logic_vector
M. Movahedin:
712: 95/02/14: Synopsys FPGA Compiler
717: 95/02/16: Re: Synopsys FPGA Compiler
2265: 95/11/15: Re: Looking for large circuit
3769: 96/07/29: A Survey on Design Errors
3806: 96/08/05: A Survey on Design Errors, Now by E-mail
4144: 96/09/18: A Survey on Design Errors
M. Praekelt:
35636: 01/10/12: Lattice discontinues all smaller MACH circuits and other devices
M. Randelzhofer:
44731: 02/06/28: Re: blank CPLD
44750: 02/06/29: Re: blank CPLD
44795: 02/07/01: Re: blank CPLD
45624: 02/07/29: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45699: 02/08/01: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45999: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
50177: 02/12/04: Re: Low Speed Serial Bus Suggestions
M. Sachemo:
37985: 01/12/28: instruction processor
M. Sherman:
6391: 97/05/21: Engineering Opportunity - http://www.digjobs.com
M. Simon:
26413: 00/10/15: Re: palasm
26414: 00/10/15: Re: FPGA PCB design examples
28123: 00/12/21: Re: FPGA and Board for Microprocessor Design?
28251: 01/01/03: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
29809: 01/03/12: Re: Configuration devices
M. Spicker:
6918: 97/07/09: Re: Generating Sine/Cosine digitally
M.+M. Monhart:
25094: 00/08/25: experiences with USB core vendors
<m.adithya@gmail.com>:
98177: 06/03/06: Asynchronous FIFO design question
98182: 06/03/06: Re: Asynchronous FIFO design question
<m.afgani@gmail.com>:
115770: 07/02/20: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
M.B.:
26495: 00/10/18: Re: Announce: Free HC11 CPU Core
30846: 01/05/01: ccd imaging with fpga
30918: 01/05/03: Re: ccd imaging with fpga
32665: 01/07/04: FPGA projects
38309: 02/01/11: Re: FPGA and CCD : any experience?
<m.beard@vertex-solutions.co.uk>:
20359: 00/02/07: ASIC Opportunities
<m.bodenbach@ifen.com>:
86939: 05/07/10: Re: Running prog from PROM
M.Kmann:
95240: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95243: 06/01/21: Re: OT:Shooting Ourselves in the Foot
M.Randelzhofer:
54611: 03/04/15: Re: Xilinx has released SpartanIII
55717: 03/05/17: Re: smallest embedded cpu.
56595: 03/06/10: Re: XC95288 programming problem
56729: 03/06/12: Analog signals connected to xilinx spartan2
56734: 03/06/13: Re: Analog signals connected to xilinx spartan2
57282: 03/06/26: Re: Low-power FPGA
57503: 03/07/01: Re: Cyclone vs Spartan-3
58791: 03/08/01: Re: 5 volt tolerant Xilinx parts
71358: 04/07/15: Re: MUXCY-based multiplexers
71826: 04/08/01: SPARTANII pinout table mysteries ???
71871: 04/08/03: SPARTAN-3 VCCAUX supply current
71897: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
71898: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
72223: 04/08/11: new XILINX 9500XL datasheets
74667: 04/10/16: Re: which xilinx CPLD to select?
77514: 05/01/08: WebPack download problem
79552: 05/02/21: WYSIWYG option in xilinx webpack 6.3
79587: 05/02/21: Re: WYSIWYG option in xilinx webpack 6.3
80495: 05/03/07: Re: Cheap alternatives to Mach 210s
84848: 05/05/30: Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1
90384: 05/10/11: Re: Question regarding FPGA startup ROMs
90874: 05/10/24: Re: Implementing five stage pipeline
91554: 05/11/08: Re: Need some help with interfacing spartan III to a computer...
91555: 05/11/08: Re: Suggestions/Recommendations with CPLD's and Software
92260: 05/11/25: Re: XC2000
93306: 05/12/19: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93309: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
98355: 06/03/08: Re: 5v Xilinx development board
98630: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
104569: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
108789: 06/09/16: Re: XPLA3 going obsolete?
109334: 06/09/24: Re: Spartan 3 or 3E ?
129715: 08/03/03: Re: my Spartan-4 wishlist
132392: 08/05/25: New Xilinx device package options for S3E & S3A
132819: 08/06/07: Re: 1 Pin MTE Cable
133905: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133909: 08/07/19: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133998: 08/07/21: Re: audio serial port i2s
135034: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135041: 08/09/12: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135826: 08/10/17: Re: A couple of CPLD design challenges for the group
137407: 09/01/14: Re: ttl compatible
138624: 09/03/02: Re: Antti-Brain issue 6 released
M.S.Gaur:
30643: 01/04/20: XSV boards memory addressing
30613: 01/04/19: Looking for digital video to VGA RGB conversion
M.Simon:
14060: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
15211: 99/03/13: Re: Infidels Invited, Heathens Highly Welcome !
15550: 99/03/30: Re: IP cores and software industry
15646: 99/04/06: Re: newbie: FPGA suggestion
15725: 99/04/10: Re: FPGA testing board
15742: 99/04/11: Re: FPGA vs CPLD? Any Experts out there?
15888: 99/04/19: Re: Forth Processor
16110: 99/05/04: Re: Anyone use 27256 for config?
17680: 99/08/23: Re: microcontroller vs FPGA
M.Sivanandan:
28770: 01/01/23: fpga: regarding startup virtex
M.Stekelenburg:
11140: 98/07/21: Re: How to write a VHDL counter of up & down
<M.Vasilko@computer.org>:
11136: 98/07/21: ANNOUNCE: Dynamically Reconfigurable Hardware WWW Library
16250: 99/05/12: Re: High speed reconfigurability
17509: 99/08/03: Re: Partial Reconfiguration?
M.Z.:
140261: 09/05/06: Re: Setting top level VHDL generics in XST
m0:
41479: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
42969: 02/05/08: Re: "free" tools ... ?
43011: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43012: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43355: 02/05/20: Re: Anyody else get spam about "FPGA Video Seminar"?
43373: 02/05/20: Re: Architecture for high-level reconfigurable computing
43579: 02/05/24: Re: FPGA, VHDL : RAM initialization
43890: 02/06/05: Re: VIRTEX-E XCV405E Orcad schematic required
M6:
89603: 05/09/20: picoblaze IDE for Linux
89696: 05/09/22: Re: picoblaze IDE for Linux
89706: 05/09/22: Re: picoblaze IDE for Linux
<m>:
53341: 03/03/11: Re: Are there any FPGA magazines/journals?
53345: 03/03/11: Can you recommend a text on...?
m_l_g3:
137060: 08/12/21: Re: Bit width in CPU cores
137088: 08/12/22: Re: Bit width in CPU cores
137089: 08/12/22: Re: Bit width in CPU cores
<m_oylulan@hotmail.com>:
84386: 05/05/18: CORDIC bit-serial vs. bit-parallel
85201: 05/06/06: Xilinx ISE 7.1i
85292: 05/06/07: Re: CORDIC bit-serial vs. bit-parallel
86340: 05/06/25: interfacing to multiple converters
86349: 05/06/26: Re: interfacing to multiple converters
103273: 06/05/30: Mains pick-up on I/O pins
103396: 06/06/01: Re: Mains pick-up on I/O pins
103728: 06/06/09: Current from FPGA pins to ADC
103887: 06/06/14: Re: Current from FPGA pins to ADC
<m_rajanikant@my-deja.com>:
22640: 00/05/16: c -> FPGA netlist compiler
ma:
83782: 05/05/06: newbie question
83823: 05/05/07: Re: newbie question
83841: 05/05/07: Re: newbie question
94173: 06/01/06: Programming Xilinx PowerPC
94176: 06/01/06: Re: Programming Xilinx PowerPC
94179: 06/01/06: Re: Programming Xilinx PowerPC
94181: 06/01/07: Re: Programming Xilinx PowerPC
108654: 06/09/14: Developing new blocks for sysgen
112415: 06/11/21: CORDIC FM Demodulation
112437: 06/11/22: Re: CORDIC FM Demodulation
112441: 06/11/22: Re: CORDIC FM Demodulation
112730: 06/11/28: Digital PLL and FM demodulation
112756: 06/11/28: Re: Digital PLL and FM demodulation
113413: 06/12/13: IQ multiplier
113437: 06/12/13: Re: IQ multiplier
113440: 06/12/13: Complex mixer
Ma. Jose Avedillo de Juan:
12653: 98/10/22: state assignment & fpgas
Maaf:
87850: 05/08/02: 5V non-volatile reprogrammable FPGA/CPLD
87892: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
Mac:
64384: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
65698: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
77754: 05/01/16: Re: What is the difference between ASIC and FPGA?.
80858: 05/03/12: Re: ISE build dependencies
80882: 05/03/14: Re: ISE build dependencies
81001: 05/03/16: Re: LVDS as general differential input ?
81264: 05/03/20: Re: RS 232 receiver using spartan 3 board
81270: 05/03/21: Re: RS 232 receiver using spartan 3 board
82680: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
82681: 05/04/16: Re: salary ballpark please guys
82704: 05/04/16: Re: salary ballpark please guys
82746: 05/04/17: Re: salary ballpark please guys
82748: 05/04/17: Re: salary ballpark please guys
83345: 05/04/28: Re: XC9500 - creating RS485 Mux
83350: 05/04/28: Re: Virtex slow clock multiply options?
83396: 05/04/29: Re: Virtex slow clock multiply options?
83397: 05/04/29: Re: Virtex slow clock multiply options?
83678: 05/05/05: Re: Does this group allow JobPostings?
84780: 05/05/27: Re: Ethernet / digital logic questions
84887: 05/05/31: Re: What is a typical job scope when FPGAs are involved?
85023: 05/06/03: Re: PCI master clock trace
85024: 05/06/03: Re: need a book: Hilbert transform
85229: 05/06/07: Re: Sch & Layout Free Program
95163: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95166: 06/01/21: Re: OT:Shooting Ourselves in the Foot
mac teh knife:
44294: 02/06/16: new computer
44327: 02/06/17: Re: Which Synthesis tool for XILINX
MACEI'S:
56888: 03/06/18: BCH or Hamming Code
56986: 03/06/20: Is this is possible???
57855: 03/07/08: Multiple Files to Synthesis in Make File ?
57858: 03/07/08: Books
57910: 03/07/09: Make file ...........Help Please
57991: 03/07/11: how to compile .vhd files one by one using makefile
58112: 03/07/15: how to remove this error
58114: 03/07/15: Make file ...........Help Please
58265: 03/07/18: bit to rbt conversion
60262: 03/09/09: AWGN in VHDL
Maciej (@):
55567: 03/05/12: GSR
Maciej Bartkowiak:
18781: 99/11/15: Need advice on interfacing SDRAM modules
18844: 99/11/18: Re: Need advice on interfacing SDRAM modules
Maciej Witaszek:
68777: 04/04/17: NIOS: Run program from SDRAM
68779: 04/04/18: Re: Nios - cyclone toolchain questions
68910: 04/04/21: Re: NIOS: Run program from SDRAM
Maciejos:
75888: 04/11/18: Spartan-3 configuring problem
75892: 04/11/18: Re: Spartan-3 configuring problem
75896: 04/11/18: Re: Spartan-3 configuring problem
Maciek:
42589: 02/04/28: Xilinx
43059: 02/05/11: dual port fifo
43063: 02/05/11: Re: dual port fifo
45725: 02/08/02: spartan i/o
45755: 02/08/05: Re: spartan i/o
58527: 03/07/25: Re: Should I use ABEL?
58531: 03/07/25: Quartus and memory initialization
58532: 03/07/25: Re: Quartus and memory initialization
59932: 03/09/02: Altera Devices
59945: 03/09/02: Re: Altera Devices
Maciek Kudla:
26166: 00/10/06: Problem Foundation 3.1 sp 3
Mack:
109567: 06/09/29: Interfacing second bram port to user logic?
109579: 06/09/29: Re: Interfacing second bram port to user logic?
110838: 06/10/24: DDR SDRAM access with MPMC2, Databus Width
110887: 06/10/25: Re: DDR SDRAM access with MPMC2, Databus Width
110976: 06/10/26: Re: DDR SDRAM access with MPMC2, Databus Width
mack:
72957: 04/09/08: AMBA AHB
73001: 04/09/09: Re: AMBA AHB
73094: 04/09/14: AHB-Slave
73108: 04/09/14: EDK
73358: 04/09/20: AHB_SLAVE
75477: 04/11/07: Mixed RTL ,XILINX EDK
75505: 04/11/08: Re: Mixed RTL ,XILINX EDK
Mad I.D.:
118530: 07/04/29: DS18B20 connection on FPGA?
138138: 09/02/07: [VHDL] Simple syntax error, but why ?
138139: 09/02/07: Re: Simple syntax error, but why ?
138141: 09/02/07: Re: Simple syntax error, but why ?
138751: 09/03/08: Dual port RAM on Spartan
138752: 09/03/08: Re: Dual port RAM on Spartan
138897: 09/03/13: XST: Unconnected output pins
<madaan@my-dejanews.com>:
12436: 98/10/12: I2C Core
15808: 99/04/15: JPEG Codec
madair:
114434: 07/01/15: Constraining Multiple clock design
maddy:
84895: 05/05/31: Re: FPGA Boards
Madeleine Delaat:
<MadHatter7@myself.com>:
139806: 09/04/14: Re: Low-cost Altera FPGA roadmap
140711: 09/05/22: Re: SPAM?
<madhav1111@gmail.com>:
83458: 05/04/30: using cadence tool
madhu:
39215: 02/02/04: Glitch detect
Madhu:
39385: 02/02/07: Re: conv_integer problem ???
39861: 02/02/21: Here is an argument and can anyone help me out
64515: 04/01/06: How do you initialize signals in VHDL?
79614: 05/02/22: Re: BACK to FPGA
madhukar:
71698: 04/07/28: Dcm clock for fpga
<MadhuPankaj11@gmail.com>:
129498: 08/02/26: Re: Interrupt Handler page missing in from software platform settings
Madhura:
36609: 01/11/13: FPGA synthesis
36749: 01/11/19: Re: FPGA synthesis
36759: 01/11/19: Re: FPGA synthesis
73744: 04/09/28: Microblaze : ilmb_Cntrl
73814: 04/09/29: Re: Microblaze : ilmb_Cntrl
73611: 04/09/25: Re: Microblaze:ISE-EDK
73420: 04/09/21: Microblaze:ISE-EDK
Madhura Bokil:
38454: 02/01/15: FPGA : VHDL netlist for simulation
Madhura P:
56918: 03/06/18: Design Validation
<madhurk@my-deja.com>:
17611: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
Madison:
20159: 00/01/28: Testbenches
<madisonfff@usa.net>:
27164: 00/11/13: Clear AND Preset Pins
<madmarsu@mygale.org>:
11394: 98/08/10: Re: Food poison
madQ:
18290: 99/10/12: Download Ia.n.i.!!! It's free!
18293: 99/10/12: Download Ia.n.i.!!! It's free!
18336: 99/10/16: Download Ia.n.i.!!! It's free!
18354: 99/10/18: Download Ia.n.i.!!! It's free!
18402: 99/10/22: Download Ia.n.i.!!! It's free!
Mads Ulrik Kristoffersen:
55175: 03/04/29: Xilinx XAct
MaEs:
64148: 03/12/18: Re: www.fpga-faq.com
66647: 04/02/24: Re: FPGA vendors and their patents
maespin:
22702: 00/05/18: verilog modules into viewlogic designs
Maf:
36672: 01/11/15: Re: Prototyping Board
Magali Oudard:
29718: 01/03/06: School project
Magne Munkejord:
115460: 07/02/12: Problem with floating inputs on LVDS ports
115490: 07/02/12: Re: Problem with floating inputs on LVDS ports
115551: 07/02/13: Re: Problem with floating inputs on LVDS ports
<magne.munkejord@gmail.com>:
132139: 08/05/15: question about high speed serial links with clock forwarding in
Magnus Danielson:
67186: 04/03/08: 66B mode of VirtexII-ProX Rocket I/O
67258: 04/03/09: Re: 66B mode of VirtexII-ProX Rocket I/O
68745: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
68746: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
Magnus Homann:
8470: 97/12/18: md5 in a FPGA?
8480: 97/12/20: Re: md5 in a FPGA?
8572: 98/01/09: Re: Xilinx Configuration Problem
8771: 98/01/25: Re: UART Spec
8844: 98/02/01: FPGA/ASIC - same difference?
9011: 98/02/13: PLD programming and board testing (JTAG)
9574: 98/03/24: Re: "CORE Competency" ???
10356: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
12387: 98/10/10: Schematic entry?
13488: 98/12/05: Re: XILINX FPGA reaches GHz speeds
13665: 98/12/17: Re: Fast *Industrial* 22V10?
13726: 98/12/21: Re: Fast *Industrial* 22V10?
13728: 98/12/21: Re: Fast *Industrial* 22V10?
13753: 98/12/22: Re: Fast *Industrial* 22V10?
13799: 98/12/28: Re: 22V10 Metastability - help please
13805: 98/12/28: Re: 22V10 Metastability - help please
13836: 98/12/29: Re: 22V10 Metastability - help please
13843: 98/12/29: Re: 22V10 Metastability - help please
13852: 98/12/29: Re: 22V10 Metastability - help please
13883: 98/12/31: Re: 22V10 Metastability - help please
13884: 98/12/31: Re: 22V10 Metastability - help please
13885: 98/12/31: Re: 22V10 Metastability - help please
13920: 99/01/02: Re: IS: 2001, A Logic Odyssey (WAS: 22V10 Metastability - help please)
14048: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14051: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13999: 99/01/06: Re: Gömmer grisöron...
14042: 99/01/08: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
15184: 99/03/11: Re: Infidels Invited, Heathens Highly Welcome !
16080: 99/04/30: Re: Double Port ram for Altera EPF10K20
16545: 99/05/27: Re: Virtex based PCI cards
16323: 99/05/16: Re: Synchronizer design?
16427: 99/05/21: Re: How synthesize tools concern with size of the design?
16476: 99/05/25: Re: How synthesize tools concern with size of the design?
16700: 99/06/03: Re: virtex vs apex20k family comparison for DSP ?
17564: 99/08/10: Re: Designing a Virtex board
17999: 99/09/22: Dual-port RAM in Apex
18335: 99/10/16: Re: VITERBI
18345: 99/10/16: Re: Xilinx 4k and DPRAM for leonardo question
18951: 99/11/22: Re: Virtex: Getting flip-flops into the pads
19084: 99/11/28: Re: Virtex: Getting flip-flops into the pads
19139: 99/12/02: Re: data serializer/decoder FPGA solution
19303: 99/12/11: Re: Altera APEX lpm modules in Synplify
19534: 99/12/29: Re: USB2 core call for Volunteers
19546: 99/12/30: Re: IRDY/TRDY Dedicated or Special Pin Name
19548: 99/12/30: Re: PCI slot 3.3V pins.
19553: 99/12/30: Re: USB2 core call for Volunteers
19562: 99/12/31: Re: PCI slot 3.3V pins.
19678: 00/01/07: Re: Design security
20101: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20115: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20496: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20498: 00/02/11: A FPGA hickup
20506: 00/02/12: Re: A FPGA hickup
20526: 00/02/13: Re: A FPGA hickup
20578: 00/02/15: Re: A FPGA hickup
20585: 00/02/15: Re: Xilinx Virtex Reset
20586: 00/02/15: Using SRL16 for synching asynch inputs?
20642: 00/02/16: Re: Xilinx hold time problems...
20649: 00/02/16: Re: Xilinx hold time problems...
21160: 00/03/08: Re: antifuse fpga's replacing xilinx
21174: 00/03/09: Re: antifuse fpga's replacing xilinx
21175: 00/03/09: Re: antifuse fpga's replacing xilinx
21182: 00/03/09: Re: antifuse fpga's replacing xilinx
21211: 00/03/10: Re: antifuse fpga's replacing xilinx
21673: 00/03/28: Re: FPGA & single point failure
21905: 00/04/06: Re: JTAG programming
22796: 00/05/24: Re: Xilinx Virtex E
23045: 00/06/10: Re: XILINX RAM Useless
23047: 00/06/10: Re: math help needed
24539: 00/08/12: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24540: 00/08/12: Re: Who needs all those printed ac parameters?
25078: 00/08/25: Re: largest fpga in the industry
26567: 00/10/20: Re: Very Lucrative FPGA Jobs
26587: 00/10/21: Re: UCF Question
26612: 00/10/22: Re: UCF Question
26616: 00/10/22: Re: UCF Question
26625: 00/10/23: Re: UCF Question
26757: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
26804: 00/10/30: Re: Very Lucrative FPGA Jobs
27336: 00/11/18: Re: In the news
27383: 00/11/20: Re: In the news
27413: 00/11/21: Re: In the news
27449: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27464: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27472: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27485: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27489: 00/11/24: Re: How to reduce the Tco
27493: 00/11/24: Re: How to reduce the Tco
27623: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
27634: 00/11/30: Re: Synplify Benchmarks
27646: 00/12/01: Re: Synplify Benchmarks
27647: 00/12/01: Re: Synplify Benchmarks
27671: 00/12/01: Re: Synplify Benchmarks
27672: 00/12/01: Re: Synplify Benchmarks
27842: 00/12/12: Re: dual port ram for altera
27846: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
28141: 00/12/22: Re: really fast counter in SpartanXL?
28146: 00/12/22: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28164: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
29579: 01/02/27: Re: Spartan II power
30191: 01/03/27: Re: What's new in Synplify 6.20 than 6.13
29654: 01/03/04: Re: Metastability
29792: 01/03/10: Re: Metastability
29875: 01/03/14: Re: Again Spartan II power
29876: 01/03/15: Re: Metastability
29877: 01/03/15: Re: Metastability
29878: 01/03/15: Re: Metastability
30033: 01/03/21: Re: Looking for Skew information
30150: 01/03/26: Re: No inputs on XC9536XL
30298: 01/04/02: Re: xapp258 question
30335: 01/04/03: Re: xapp258 question
30735: 01/04/26: Re: Something about the counter
30779: 01/04/28: Re: C++ To Gates
30793: 01/04/29: Re: C++ To Gates
30794: 01/04/29: Re: C++ To Gates
30820: 01/04/30: Re: C++ To Gates
30821: 01/04/30: Re: C++ To Gates
30822: 01/04/30: Re: C++ To Gates
30836: 01/05/01: Re: C++ To Gates
30839: 01/05/01: Re: Multiple state machines in altera AHDL
30957: 01/05/04: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
31675: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31678: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31966: 01/06/10: Re: Help in FIFO design
31967: 01/06/10: Re: problem: bahavior simulation of xilinx's coregen cores
31968: 01/06/10: Re: Flash programming via FPGA's JTAG ????
32410: 01/06/26: Re: Register balancing in FPGA Express
32479: 01/06/27: Re: clock speed in XC95288XL
32502: 01/06/28: Clock muxes
32551: 01/06/29: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32657: 01/07/04: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32788: 01/07/09: Re: SpartanII: non clock pad drives clock net ?
32892: 01/07/11: Re: Handel-C
32954: 01/07/12: Re: PCI arbiter core
32976: 01/07/13: Re: Xilinx BRAM failures
32978: 01/07/13: Re: Design entry
34203: 01/08/16: Re: Replication of FFs in Xilinx XC4000
35405: 01/10/03: Re: Which Cable for the Xilinx 3064XL ?
35422: 01/10/04: Re: Which Cable for the Xilinx 3064XL ?
35917: 01/10/23: Re: Verilog vs. VHDL
36423: 01/11/08: Re: Xilinx dedicated IO pins
36461: 01/11/09: Re: Xilinx dedicated IO pins
36837: 01/11/21: Re: slew rate of virtex output buffers figures
36929: 01/11/26: Re: ALTERA's Mercury CDR
37114: 01/11/30: Re: SpartanIIE
38369: 02/01/12: Re: Repost: Should clock skew be included for setup time analysis?
38440: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38441: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38490: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
39132: 02/02/01: Re: APEX-II vs VIRTEX-II
39133: 02/02/01: Re: Spartan II power-up current - again
39351: 02/02/07: Re: CLKDLL x4 problem
40147: 02/02/28: Re: Altera's new family Stratix
40315: 02/03/05: Re: Constraining help required for clk_enable
40789: 02/03/15: Re: where to start with constraining..
40790: 02/03/15: Re: High speed clock routing
40802: 02/03/15: Re: High speed clock routing
40834: 02/03/16: Re: High speed clock routing
40835: 02/03/16: Re: High speed clock routing
40872: 02/03/17: Re: just bought...
40873: 02/03/17: Re: To Falk Brunner
40919: 02/03/18: Re: just bought...
41930: 02/04/11: Re: regarding gate count of the design
41931: 02/04/11: Re: Built in multipliers in Virtex 2000E?
42494: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42717: 02/05/01: Re: Availability of XC2S150E-6FG456I
44538: 02/06/22: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
51768: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51769: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
55355: 03/05/05: Re: Virtex2 BUFGMUX problem ?
56091: 03/05/28: Re: JTAG madness
56128: 03/05/29: Re: JTAG madness
56232: 03/05/31: Re: FPGA's an Flash
60217: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
60497: 03/09/15: Re: Xilinx S3 I/O robustness question
60994: 03/09/26: Re: Regulator for Spartan 2
61507: 03/10/06: Re: Digesting runs of ones or zeros "well"
61658: 03/10/08: Re: BF957C Application
65344: 04/01/25: Re: changing values in a fifo
66241: 04/02/15: Re: Pricing, 101
66713: 04/02/25: How would you...
66750: 04/02/26: Re: How would you...
67558: 04/03/14: Re: Issues in Rocket I/O
Magnus Jacobsson:
50243: 02/12/06: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
50253: 02/12/06: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
mahalingamv@gmail.com:
117292: 07/03/27: is edk 8.1 availabe for download
119298: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
120197: 07/06/02: ngdbuild error : multiple drivers and driving non buffer primitives
120248: 07/06/04: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120249: 07/06/04: Re: any experiences concerning xup and digilent inc.?
120318: 07/06/05: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120732: 07/06/15: edk clock problem
120834: 07/06/18: Re: edk clock problem
<mahalingamv@gmail.com>:
99914: 06/03/30: design compiler optimization
Mahboob Ahmed:
17989: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
17988: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
18319: 99/10/14: Virtex FPGA PCI select I/O Characteristics.
19072: 99/11/27: Siemens HSCX development tools.
19467: 99/12/23: PCI slot 3.3V pins.
mahdavi:
37053: 01/11/29: Test Bench for MaxPlus ?
mahdi:
115443: 07/02/11: CLOCK GENERATOR
115753: 07/02/19: ROC PORT
115867: 07/02/22: Re: ROC PORT
115868: 07/02/22: 2x technique
115869: 07/02/22: internal DCM
115883: 07/02/22: Re: internal DCM
115884: 07/02/22: Re: 2x technique
Mahei:
109488: 06/09/27: Re: Looking for ispMACH4000 eval boards
<mahenreddy@gmail.com>:
115921: 07/02/25: Edge vs Level triggering
maher:
137841: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
137847: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
137850: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
mahesh:
106979: 06/08/23: Re: PCIe latency
133222: 08/06/20: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
133446: 08/06/29: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133461: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133475: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
Mahesh M. Bandi:
52336: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52343: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52344: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52345: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52363: 03/02/07: Re: NIOS and ACEX1K
Mahim Mishra:
66563: 04/02/22: Help with Xilinx EDK 6.1
66672: 04/02/24: Re: Help with Xilinx EDK 6.1
66858: 04/02/27: Xilinx ISE Impact crashes during configuration
66892: 04/02/28: Re: Xilinx ISE Impact crashes during configuration
66893: 04/02/28: Xilinx iMPACT error: "Done did not go high"
66908: 04/02/29: Re: Xilinx iMPACT error: "Done did not go high"
67685: 04/03/17: Xilinx bit-file format?
73043: 04/09/11: JBits 3.0 and Virtex-II Pro
73238: 04/09/16: xdl tool, or Xilinx Design Language
Mahmoud:
94939: 06/01/19: Re: newbie question about Xillinx JTAG cable
94831: 06/01/18: Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??
95457: 06/01/23: Re: Xilinx ISE & StateCad
95601: 06/01/24: Re: Verilog tutorial by John Sanguinetti
96050: 06/01/28: Re: Digilent FPGA & Handel-C
96349: 06/02/02: Re: How will synthesizers handle these statements?
Mahmut C. Genceli:
18180: 99/10/05: Re: Free Hardware "CPLD board"
mahshid:
123354: 07/08/24: Dynamic power estimation using Xpower
123368: 07/08/25: Re: Dynamic power estimation using Xpower
<mahurshi@gmail.com>:
98193: 06/03/06: A few questions about FPGAs
<mai99drh@studserv.uni-leipzig.de>:
76847: 04/12/14: Re: pausing execution on ppc405
Maik H.:
132762: 08/06/06: Re: Your favourite DSP textbooks/websites?
Maik Ritter:
117907: 07/04/13: Are there Quartus II Web Edition limitations?
117913: 07/04/13: Re: Are there Quartus II Web Edition limitations?
117977: 07/04/15: Re: Are there Quartus II Web Edition limitations?
<Maik>:
135209: 08/09/20: Re: Peter says Good Bye
Mail Delivery Service:
85190: 05/06/06: Delivery Status Notification
<mail83870@pop.net>:
11431: 98/08/13: Newbie seeks cheap fun w/FPGAs
<mail@deeptrace.com>:
93551: 05/12/24: Xilinx ISE Simulator
93719: 05/12/28: Re: Xilinx ISE Simulator
93933: 06/01/03: Re: Xilinx ISE Simulator
94932: 06/01/19: Disabling cross domain checking for Xilinx ISE
94938: 06/01/19: Re: Disabling cross domain checking for Xilinx ISE
94964: 06/01/19: Bogus Hold Violations with 2X clock on Xilinx ISE 7.1
mailmekaran:
103472: 06/06/03: VHDL code For Floating point adder and Multiplier
<mailsatishv@gmail.com>:
121714: 07/07/11: New board JTAG error
121735: 07/07/12: Re: New board JTAG error
<mailservice@bulkmail.net>:
7232: 97/08/17: Do you like to receive $2 million ?
maimuna:
45939: 02/08/12: changing width of array
46096: 02/08/19: to reduce the circuit design
46222: 02/08/21: Re: to reduce the circuit design
46262: 02/08/23: Re: to reduce the circuit design
Mainak Sen:
66128: 04/02/12: xsa-50 board
76065: 04/11/23: Xilinx Multimedia Board
Maire:
36861: 01/11/22: Synplicity & BlockRAMs
maisk:
54858: 03/04/20: Re: test
majordomo@att.net:
7125: 97/08/03: HELP!!NEED A CACHE SIMULATOR A.S.A.P
Mak:
83291: 05/04/27: Re: PCI plug n play and Graphics card implementation
89042: 05/09/03: High baud rate chips for RS232 protocol
107773: 06/09/01: Interface of 8051 microcontroller with FPGA Block RAM
107789: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
107791: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108681: 06/09/14: Critcal path in XILINX ISE (XST)
110585: 06/10/18: EDIF netlist timing simulation
110587: 06/10/18: Re: EDIF netlist timing simulation
<mak@cromp.ernet.in>:
4677: 96/11/28: Reconfigurable FPGAs in Networking
makarand:
133571: 08/07/03: Free Webinars on PMP Certification Awareness and Roadmap
Makarand Joshi:
13588: 98/12/10: Re: Array Range Legal?
13594: 98/12/10: Re: Array Range Legal?
Make Money Fast:
Makesh Soundarajan:
71020: 04/07/05: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71056: 04/07/06: Re: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71070: 04/07/07: Re: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
makhan:
112529: 06/11/23: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
113910: 06/12/28: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
122746: 07/08/06: Re: how to test the FPGA on the board
122748: 07/08/06: Re: Download the contents of the FPGA's RAM block
122835: 07/08/08: Re: Download the contents of the FPGA's RAM block
131105: 08/04/10: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131115: 08/04/11: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Maki:
33285: 01/07/22: Re: Maxplus II download sites
34135: 01/08/15: Re: Building a clock out of a PLD
75779: 04/11/15: Re: Gap between layers in PCB
88185: 05/08/11: LatticeXP availability
89949: 05/09/30: Lattice XP availability
89951: 05/09/30: Re: Lattice XP availability
99534: 06/03/26: Re: BlockROM inference in XST - This is just plain silly
100159: 06/04/04: Lattice ispLever Starter Download
100235: 06/04/05: Re: Lattice ispLever Starter Download
124299: 07/09/18: Re: Tristate bus on spartan FPGA
125885: 07/11/08: Re: Non-volatile FPGA in a small package
125907: 07/11/08: Re: Non-volatile FPGA in a small package
127813: 08/01/08: Re: True Dual Port RAM
127901: 08/01/10: Re: How to program and initialize Lattice XP devices
127931: 08/01/10: Re: True Dual Port RAM
128489: 08/01/28: Re: My first Flash FPGA
128503: 08/01/29: Re: My first Flash FPGA
makmorbi:
52713: 03/02/19: FPGA's at High Temperatures
67654: 04/03/16: Re: Quartus II 4.0 Web Edition Software & Documentation - Available for download
70314: 04/06/11: Low Power FPGA Design Seminar
73368: 04/09/20: Altera Max II
Makoto Honda:
54461: 03/04/11: Re: Dynamic Reconfigurable FPGAs
Malachy Devlin:
16372: 99/05/19: Re: Virtex based PCI cards
16424: 99/05/21: Re: Virtex based PCI cards
19062: 99/11/26: Programming Virtex device via JTAG
20919: 00/02/28: PCI 64 bit / 66 MHz
22673: 00/05/17: appropriate ASIC Prototyping Board
22674: 00/05/17: Reccomend an ASIC emulation board
malavica:
137644: 09/01/26: How to make a ram shared?
Malcolm Bugler:
6994: 97/07/20: AM186 to P/C104 PLD design
Malcolm Reeves:
28457: 01/01/13: ANN: Test Bench tool V2.01 - powerful and cheap
malgi:
47876: 02/10/06: Re: Low power design
<malino@primenet.com>:
18763: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
19008: 99/11/23: Re: VHDL vs. schematic entry
Malki:
14703: 99/02/12: Re: Board for XC4085XL
mammo:
101836: 06/05/07: Funky experiment on a Spartan II FPGA
101839: 06/05/07: Re: Funky experiment on a Spartan II FPGA
101857: 06/05/07: Re: Funky experiment on a Spartan II FPGA
Mamoon Hamid:
16276: 99/05/12: Re: Can use pullup in XC9500XL?
mamtachalana:
70610: 04/06/21: system verilog
mamu:
132140: 08/05/15: Re: Camera link interface
134999: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
139467: 09/03/31: Dedicated clock routes in Xilinx FPGA
man cheng:
5207: 97/01/31: What is the different between FPGA and CPLD?
Man`y:
6974: 97/07/18: looking for a contract opening
Manan:
20476: 00/02/11: HELP ! Problems in mapping
<manan.kathuria@gmail.com>:
79941: 05/02/26: setup-hold time problems
<Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>>:
48581: 02/10/21: Nios and quartus linux version
48655: 02/10/22: Re: Nios and quartus linux version
48979: 02/10/28: Leonardo and lpm (Altera)
49791: 02/11/21: Altera Logick lock newbie
49912: 02/11/25: Re: Altera Logick lock newbie
54918: 03/04/22: Re: quartus_cmd under Linux
57892: 03/07/09: Xilinx price question
Mancini Stephane:
60991: 03/09/26: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61421: 03/10/03: Re: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61815: 03/10/13: Quartus 2.2, SOPC builder and leonardo
61850: 03/10/14: Re: Quartus 2.2, SOPC builder and leonardo
62212: 03/10/22: NIOS simulation with modelsim -> strange behaviour
64263: 03/12/23: Avnet Virtex II Pro Dvpt board : linux drivers ??
65219: 04/01/22: Virtex II Pro, powerpc 405 and ucOSII
67588: 04/03/15: Virtex II Pro default I/O mode
68603: 04/04/09: I2C bus and tristate interface for V2pro
72890: 04/09/07: EDK 3.2 and modelsim ppc simulation
73060: 04/09/13: Re: EDK 3.2 and modelsim ppc simulation
73067: 04/09/13: Xilinx EDK and plb master
73113: 04/09/14: Re: Xilinx EDK and plb master
73272: 04/09/17: Xilinx EDK & IPIF performance
75395: 04/11/04: Xilinx EDK PLB/OPB bridge (and IPIF)
87162: 05/07/18: EDK and powerpc-eabi compiler
89448: 05/09/15: Xilinx V2Pro & SATA hard disk
89454: 05/09/15: Re: Xilinx V2Pro & SATA hard disk
<mandana@physics.ubc.ca>:
85462: 05/06/09: JTAG programming: JAM files versus ISC (IEEE1532) files
85719: 05/06/14: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
85816: 05/06/16: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
Mandeep Singh:
15583: 99/03/31: Reconfigurable Computing
Mandilas Antony:
56714: 03/06/12: error compiling
57385: 03/06/29: clock signals
57386: 03/06/29: memory
57387: 03/06/29: Re: memory
MANDY & DOUGLAS:
39204: 02/02/04: Re: RAM question
40010: 02/02/25: Re: IIR. convolution
<maneri@my-dejanews.com>:
15539: 99/03/29: PAMette for Rapid Prototyping
15644: 99/04/05: Re: How to implement Matched Filter in FPGA?
Manfred Aigner:
3381: 96/05/23: XACT Memgen + Mentor
3438: 96/05/30: Re: how to use memgen
3498: 96/06/11: Double Port Ram - Xact Libs
3559: 96/06/21: Routing
Manfred Balik:
62331: 03/10/27: Altera ACEX1K configuration and initialisation
63212: 03/11/18: Re: Acek 1K - Quartus II - timing issues
67699: 04/03/17: PC104 Evaluation Board
71261: 04/07/13: Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif
71745: 04/07/29: Re: Implementing control registers (VHDL)
72577: 04/08/25: Altera Quartus II 4.1 double-click on QPF-File doesn't work
72928: 04/09/08: i2c-core from opencores.org
75680: 04/11/12: DualPortRAM serial IN - parallel OUT
80182: 05/03/02: Altera APEX20KE clock problem
80289: 05/03/03: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
80334: 05/03/04: Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
86961: 05/07/11: output-value isn't stored
89340: 05/09/13: Migration Altera APEX20KE to ???
91449: 05/11/07: which Altera CPLD?
92082: 05/11/22: Quartus Problem
96248: 06/02/01: Re: Quartus Fitter Warning
104150: 06/06/20: Quartus 6.0 Fitter Critical Warning
104188: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
104203: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
107782: 06/09/01: bidirectional connection between two bidirectional ports
107801: 06/09/01: Re: bidirectional connection between two bidirectional ports
108078: 06/09/05: Re: bidirectional connection between two bidirectional ports
108082: 06/09/05: Re: bidirectional connection between two bidirectional ports
112536: 06/11/24: Altera MAX3000A OE and GCLR-Pins
112647: 06/11/27: Re: Altera MAX3000A OE and GCLR-Pins
113725: 06/12/20: CPLD speed/temperature equivalent
114127: 07/01/05: Altera Cyclone II die revision?
116722: 07/03/16: old Quartus project files
118176: 07/04/19: Altera M4K memory usage
118181: 07/04/19: Re: Altera M4K memory usage
Manfred Kraus:
10909: 98/06/30: Re: Xilinx file compression
10994: 98/07/09: Re: question on combinational logic synthesis for FPGA
12014: 98/09/24: Re: How to reduce ringing/ground bounce from FPGA output pin?
12881: 98/11/03: Re: New free FPGA CPU
12883: 98/11/03: Re: Digital Sine Generator
13067: 98/11/14: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
14419: 99/01/29: Re: PLL in FPGA
14658: 99/02/09: Re: dual port RAM on XC4000
19131: 99/12/01: data serializer/decoder FPGA solution
19148: 99/12/02: Re: data serializer/decoder FPGA solution
25993: 00/09/29: Xilinx Logicore Generator
28575: 01/01/17: Re: Looking for prototyping board
28640: 01/01/19: Re: Best design for asyn. interface DSP <-> FPGA?
29835: 01/03/13: 64 simultan A/D Converters in an SPARTAN-II
29846: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
32534: 01/06/29: Re: FPGA Boards
32673: 01/07/04: clock frequency synthesizer for FPGA
32726: 01/07/06: Re: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
32734: 01/07/06: Re: Xilinx PCI development board
35428: 01/10/04: CoreGenerator and WebPack ISE
35550: 01/10/10: Re: CoreGenerator and WebPack ISE
35647: 01/10/12: Re: PWM Signal in VHDL ?
36096: 01/10/29: Re: University project: DSO
36567: 01/11/12: Re: Quadrature Encoder Sampling Time
39950: 02/02/22: Replacing expensive configuration SPROM
40460: 02/03/07: Re: DDR-Interface
40755: 02/03/14: Re: use virtex2 DCM as delay line
40756: 02/03/14: Re: Xilinix FPGA width 5V IO
40757: 02/03/14: Re: Proto boards for labs
40991: 02/03/19: Re: 1,5V power supply?
40992: 02/03/19: Re: virtex 2 orcad symbols?
40993: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
40995: 02/03/19: Re: Xilinx JTAG Cables
42230: 02/04/18: Re: fpga limitation
42421: 02/04/23: Re: Prototyping Boards for Hobbyist CPU/System Designs
42652: 02/04/30: Re: Frequency synthesiser
42823: 02/05/03: Re: Frequency synthesiser
42824: 02/05/03: DDR SDRAM controller for VIRTEX-II
43968: 02/06/07: Re: Problem with spartan2 vhdl code
44014: 02/06/10: Re: Looking for FPGA board with USB interface
44302: 02/06/17: Which Synthesis tool for XILINX
44338: 02/06/18: Re: Which Synthesis tool for XILINX
44339: 02/06/18: Re: Which Synthesis tool for XILINX
44347: 02/06/18: Re: Pls Recommend a Development Board - Have you checked out the CESYS boards ?
44401: 02/06/19: Re: Pls Recommend a Xilinx development Board
44700: 02/06/27: Re: Applying voltage to FPGA I/O while FPGA is not powered
44916: 02/07/05: Re: Routing Virtex-II 256 pin BGA on 4 layers
44962: 02/07/08: Re: Newbie FPGA recommedation
45302: 02/07/18: Re: Advice on tools and question on Virtex2
45611: 02/07/29: Re: Programming FLASH with Xilinx Parallel Cable III
45612: 02/07/29: Re: secure FPGA
45728: 02/08/02: Re: lots of shift registers
46073: 02/08/16: Re: Fun FPGA system
46074: 02/08/16: Re: Testing the X2S_USB Spartan 2 board
54341: 03/04/08: Re: Power Supply for Spartan II FPGA
56481: 03/06/06: Re: Virtex 2 evaluation board
56482: 03/06/06: Re: Level Converters
56665: 03/06/11: A way to copy Modelsim waveforms into word documents
56674: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
56675: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
57642: 03/07/03: Spartan-3 availability
57648: 03/07/03: Re: Spartan-3 availability
57713: 03/07/04: Re: Spartan-3 availability
59103: 03/08/08: Re: clock management on SPARTAN2
60418: 03/09/12: Re: CMOS camera w/ USB2 -- crazy?
64163: 03/12/18: Re: Spartan3 availability
64780: 04/01/13: Re: SDRAM Controller timing problem
65801: 04/02/06: Virtex-3 PRO
66535: 04/02/21: Re: Can FPGA bootstrap itself?
66782: 04/02/26: Re: Suggestions: Eval/Demo Board.
88405: 05/08/17: Re: Easy USB2.0 hi-speed device solutions ?
120619: 07/06/12: Re: Affordable pcie card ?
Manfred Kuhland:
21013: 00/03/02: Re: Error in Xilinx application note XAPP131?
Manfred Muecke:
43570: 02/05/24: SOPC for machine vision
43572: 02/05/24: Re: SOPC for machine vision
43608: 02/05/27: Re: SOPC for machine vision
72409: 04/08/18: Re: What schematic tool (VHDL) is the best?
72422: 04/08/18: Re: What schematic tool (VHDL) is the best?
80776: 05/03/11: Re: New in C to RTL
<manfredk@internode.on.net>:
130245: 08/03/18: Re: vhdl type conversions
Manfredo:
26864: 00/11/01: Re: I need some VHDL/Synthesis Design BOOK recommendations!!
mani:
129724: 08/03/03: reconfiguration of virtex 2 pro
Manish:
75541: 04/11/08: FPGA as "Differential SSTL_2" clock driver
75577: 04/11/10: Re: FPGA as "Differential SSTL_2" clock driver
98272: 06/03/07: Crosstalk Analysis on a FPGA
Manish_Shrivastava:
14062: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14179: 99/01/18: Re: Reed-Muller99 CFP
<manishr@softjin.com>:
81960: 05/04/05: DCM LOCKED as reset
Manjunath:
35331: 01/09/29: Re: Meta-stability
manjunath.rg@gmail.com:
98300: 06/03/08: FPGA imple. of aes
98376: 06/03/08: Re: FPGA imple. of aes
98504: 06/03/11: Re: FPGA imple. of aes
98563: 06/03/12: Re: FPGA imple. of aes
MANJUNATHAN:
29944: 01/03/19: about placement and routing
Manjunathan:
29922: 01/03/16: about core generator
30104: 01/03/22: PLACE and ROUTE
30108: 01/03/23: Timing analysis after implementation
30272: 01/03/30: VIRTEX BLOCK RAM
30332: 01/04/03: to add macro in the design
33775: 01/08/04: how to replicate the Logic through VHDL attribut ?
33823: 01/08/06: how to give timing constraint in an hierarchy des
34008: 01/08/10: how to acheive high frquency in Xinlinx Virtex E
35303: 01/09/27: Meta-stability
<mankin18@gmail.com>:
113905: 06/12/28: SPI slave problem
113909: 06/12/28: Re: SPI slave problem
113916: 06/12/29: Re: SPI slave problem
113917: 06/12/29: Re: SPI slave problem
114020: 07/01/02: Re: SPI slave problem
114025: 07/01/02: Re: SPI slave problem
Mankit Wong:
7421: 97/09/09: Re: Which FPGA ?
11403: 98/08/11: Re: Gray code counter in ABEL HDL?
11616: 98/08/27: Re: CPLD/FPGA software
12770: 98/10/29: 8051 VHDL Model
17550: 99/08/10: Re: Lattice cable for 2032?
manmohan singh:
67155: 04/03/07: licence for Xilinx 2.1i
67306: 04/03/09: Re: licence for Xilinx 2.1i
mann!:
79950: 05/02/26: Re: setup-hold time problems
79969: 05/02/27: maximum frequency of operation
79970: 05/02/27: maximum freq of operation of a circuit
Mann`y:
3634: 96/07/05: Looking for a PCI bus model
4938: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4943: 97/01/03: Usb Cores ( synthesisable ) and ( simulation models )
Manny:
110240: 06/10/12: Glitches in post-layout (PAR) simulation
110249: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110255: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110259: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110262: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110263: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110265: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110307: 06/10/13: Xilinx FPGAs in battery-powered scenarios
110317: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110344: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
111894: 06/11/12: Xilinx platform cable USB
111994: 06/11/14: Re: Xilinx platform cable USB
113822: 06/12/23: IEEE fixed-point package FATAL_ERROR
115118: 07/01/31: Synthesis of DSP algorithms
115274: 07/02/05: Re: moving data from slower to faster clock domain
116340: 07/03/07: Re: Query regarding Project.Plz help very urgent
116372: 07/03/07: Re: Introducing picosecond delay between two output signals
118326: 07/04/23: Slave PLB core interrupt
118364: 07/04/24: Re: Slave PLB core interrupt
118645: 07/05/01: Read 64-bit value over PLB
118956: 07/05/08: Re: Read 64-bit value over PLB
119000: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119140: 07/05/12: downto usage in EDK
119310: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119312: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119314: 07/05/16: Re: seeking insights for potential reconfigurable computing application platforms
120279: 07/06/04: System Generator installation
120775: 07/06/15: Simulating analogue signal using ISE simulator
120795: 07/06/16: Re: Simulating analogue signal using ISE simulator
123245: 07/08/21: Re: Synthesizing fixed_pkg in ISE 9.2
123246: 07/08/21: Spartan-3A DSP vs. Cyclone III Power-wise
123285: 07/08/22: Re: Spartan-3A DSP vs. Cyclone III Power-wise
124229: 07/09/14: Virtex II pro design question
124236: 07/09/15: Re: Virtex II pro design question
124422: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124424: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
125035: 07/10/15: Re: FPGA quiz: what can be wrong
125054: 07/10/15: Re: FPGA quiz: what can be wrong
125066: 07/10/16: Re: FPGA quiz: what can be wrong
125078: 07/10/16: Re: FPGA quiz: what can be wrong
125156: 07/10/16: gold code - seed value
134496: 08/08/13: XMD & Ultracontroller
134549: 08/08/17: Ultracontroller-2 on ML403
138012: 09/02/03: Core interface protocol
138106: 09/02/06: Re: Core interface protocol
139673: 09/04/08: Re: Modulo-10 counter
139674: 09/04/08: Re: Modulo-10 counter
139676: 09/04/08: Re: ANN: Antti-Brain March issue released
140400: 09/05/12: Lockable shared memory co-simulation
140522: 09/05/15: Re: Lockable shared memory co-simulation
Manoj Chaubal:
2170: 95/10/25: Re: PLD in small package ?? anyone
2418: 95/12/02: New ALDEC tools for XACT 6.0
Manoj K Krishnan:
33667: 01/08/01: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
manoj.rajpoot@gmail.com:
105084: 06/07/13: Routing Information of Xilinx's Virtex-II FPGA
<manolete@discontrol.net>:
123393: 07/08/27: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
Manolis Stratakis:
4498: 96/11/06: PCB Handling of chip packages greater than 100 pins?
Manpreet:
99754: 06/03/28: Re: need help,test on Spartan3 starter kit
99755: 06/03/28: how to immitate clock behavior----Please guide
mans (myname_here):
118024: 07/04/16: Matlab Simulink HDL coder generated code interface.
118112: 07/04/17: creating library in ISE 9
118130: 07/04/18: ISE Smart Ident
118133: 07/04/18: Compiling a library
118167: 07/04/18: VHDL source code for polyphase filter
118184: 07/04/19: Re: VHDL source code for polyphase filter
118281: 07/04/21: simulating with OSe 9.1.3
118294: 07/04/23: VHDL editing with UltraEdit
118382: 07/04/25: Re: VHDL editing with UltraEdit
mans (use_my_name_here):
117438: 07/03/30: Sysgen compilation target
117753: 07/04/09: record type port in vhdl and simulation in ISE
Mansih Mahajan:
15982: 99/04/24: Looking for FPGA/ASIC design/verification position
Mansoor Naseer:
54518: 03/04/12: Some suggestions on system design on PCB
mansoor.naseer@gmail.com:
83218: 05/04/26: PCI plug n play and Graphics card implementation
<mansoor.naseer@gmail.com>:
138546: 09/02/26: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
139580: 09/04/05: Re: clock multipliers, dividers, and more clocks...
139766: 09/04/13: Re: buy XSA-50
manu:
99235: 06/03/21: Re: BRAM for virtex-4
99634: 06/03/27: Re: C-based FPGA programming/mixed languages
99976: 06/03/31: Re: ISE 8.1, EDK 8.1 installation
100332: 06/04/07: Re: xilinx xc2vp30
100337: 06/04/07: Re: OPB master
105431: 06/07/22: version control of ISE+EDK projects with CVS and/or SVN
Manuel:
55823: 03/05/20: modulators and demodulators help
Manuel Alejandro Jimenez-Cede:
718: 95/02/16: Looking for Tech Info
Manuel Bessler:
95247: 06/01/21: Re: Raggedstone specifications ...
95813: 06/01/26: Re: Spartan-3 Starter Board
Manuel Gericota:
46190: 02/08/21: ERA60100 Data Sheet
Manuel Zaera Sanz:
47305: 02/09/23: MTBF
<manuel-lozano@mixmail.com>:
115254: 07/02/05: problem with microblaze gcc toolchain
117473: 07/04/01: broken mb-gcc -O2 ?
117482: 07/04/02: Re: broken mb-gcc -O2 ?
122722: 07/08/04: mb-gdb: problem simulating memory mapped i/o devices
129743: 08/03/04: FPGA for a DVB common interface implementation
129744: 08/03/04: FPGA for a DVB common interface implementation
133524: 08/07/02: minipci breadboard with fpga
133541: 08/07/03: Re: minipci breadboard with fpga
<manuel.bessler@gmail.com>:
94874: 06/01/18: Re: Raggedstone specifications ...
<manygates>:
72483: 04/08/20: GAL,PAL,PLD, CPLD,FPGA
72487: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72501: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72502: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
2mao:
115215: 07/02/02: Re: Xilinx Interconnects/Routing
<mar@tcelectronic.com>:
18791: 99/11/16: Re: Need advice on interfacing SDRAM modules
marada:
110987: 06/10/26: Re: Microblaze : FSL bus
112649: 06/11/27: Re: Microblaze : FSL bus
Marc:
26922: 00/11/03: Re: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
28929: 01/01/30: Clocking system with CPLD? - timing.JPG (0/1)
29096: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29097: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (1/1)
29119: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29121: 01/02/06: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29124: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
37877: 01/12/22: Beginners question: several circuits in one chip
38166: 02/01/08: Re: Suitability of Atmel for project?
61996: 03/10/16: Re: Running Quartus II on ReadHat Linux 9.0
62626: 03/11/03: Re: Altera "my support" :-(
64219: 03/12/21: Re: advantages of ethernet MAC ip core
64320: 03/12/28: Re: advantages of ethernet MAC ip core
67776: 04/03/18: Re: Problems with Memory Initialization Files in Modelsim
68969: 04/04/23: 64-bit SODIMM module on 32-bit SDRAM-controller?
71427: 04/07/18: Re: FPGA Development board with onboard Ethernet PHY
71820: 04/08/01: Re: FPGA prototype board with ethernet interfaces
73541: 04/09/23: Cyclone FPGA as Cardbus controller
82972: 05/04/20: Re: Differential timing specification in Xilinx FPGA
83811: 05/05/07: Re: Parallel Cable IV opened in "Compatibility Mode"
87052: 05/07/13: Re: Virtex 300: what could cause pin to short?
marc:
33351: 01/07/24: Register Chain
Marc 'Nepomuk' Heuler:
6903: 97/07/07: Re: Generating Sine/Cosine digitally
7836: 97/10/20: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
7837: 97/10/20: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
7838: 97/10/20: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
Marc A. Baker:
103536: 06/06/05: Re: Documentation miss? (sp3/xilinx)
125877: 07/11/07: Re: Non-volatile FPGA in a small package
Marc Baker:
3871: 96/08/12: Re: Using Carry logic in XC4000...
4042: 96/09/05: Re: Address of ALTERA & XILINX
4221: 96/10/01: Re: XilinX XC5200 address pointer based FIFO
4319: 96/10/14: Re: Xilinx XACT Performance Appl. Note?
4335: 96/10/17: Re: Xilinx xchecker.exe and Windows NT
4383: 96/10/22: Re: What are I/O's doing prior to configuration?
4713: 96/12/05: Re: XACT under WinNT is very slow
13949: 99/01/04: Re: 1.5i changes
23814: 00/07/10: Re: Xilinx Data memory
24891: 00/08/21: Re: power consumption for spartan xcs05(XL)
25172: 00/08/29: Re: Spartan II vs. Virtex
25213: 00/08/30: Re: Xilinx and CD databooks (rant)
29029: 01/02/02: Re: JTAG Programming with SpartanII demo card
29090: 01/02/05: Re: JTAG Programming with SpartanII demo card
37125: 01/11/30: Re: SpartanIIE
37127: 01/11/30: Re: SpartanIIE
37532: 01/12/13: Re: FPGA introduction
39664: 02/02/15: Re: Spartan-II becomes Vertex.
46982: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
46984: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
48679: 02/10/22: Re: FPGA XC4005E
50419: 02/12/10: Re: [Spartan-IIE] Additional DLL input pins
50760: 02/12/18: Re: Errors in Xilinx pinout spreadsheet
51280: 03/01/09: Re: External RAM...
52675: 03/02/18: Re: What's the difference between LUT and RAM?
52676: 03/02/18: Re: Easy links to Xilinx documentation
55606: 03/05/13: Re: Missing App Notes
60622: 03/09/17: Re: How to contact the writer of Xilinx FPGA application notes?
60623: 03/09/17: Re: Original (5V) Xilinx Spartan ?
62232: 03/10/22: Re: Spartan 3 pinout typo?
62234: 03/10/22: Re: SpartanXL
63932: 03/12/09: Re: SPARTAN-II, busy signal
64031: 03/12/12: Re: Spartan IIE daisy chain problems
64032: 03/12/12: Re: Xilinx Spartan II pull-up, simple questions
66981: 04/03/02: Re: Xilinx : RLOC ORIGIN
67502: 04/03/12: Re: ISE 6.2 issues
71473: 04/07/19: Re: Understanding Xilinx Spartan 3 datasheet IOB timing information
Marc Battyani:
19319: 99/12/14: State machine ok with binary encoding but unstable with one hot encoding
19330: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19463: 99/12/22: Re: State machine ok with binary encoding but unstable with one hot encoding
19645: 00/01/06: BGA sockets and Virtex
22087: 00/04/20: Fast (> 100Mb) serial link to PC
22966: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
25895: 00/09/25: Using the xilinx "pull-up to 5V" in VHDL
25913: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25914: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25918: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25920: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25966: 00/09/28: FPGA Express pb
25974: 00/09/28: Re: FPGA Express pb
25977: 00/09/28: Re: FPGA Express pb
25995: 00/09/29: Xilinx 2.1 to 3.1 pb
25998: 00/09/29: Re: Xilinx 2.1 to 3.1 pb
29715: 01/03/06: Re: Parallel Port EPP
30162: 01/03/26: Logic trimmed (XCS40 F3.1)
30170: 01/03/27: Re: Logic trimmed (XCS40 F3.1)
30421: 01/04/07: Synchronous demodulation in FPGA
34199: 01/08/16: Virtex-II and 5V devices
34219: 01/08/16: Re: Virtex-II and 5V devices
34228: 01/08/16: Re: Virtex-II and 5V devices
34241: 01/08/17: Re: Virtex-II and 5V devices
34266: 01/08/17: Re: Virtex-II and 5V devices
34945: 01/09/14: Re: A vs. X
34955: 01/09/15: Re: A vs. X
35850: 01/10/20: what is carry mode INC-F-CI ?
48362: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
53030: 03/02/28: Re: PCB board design software vs outsourcing?
54727: 03/04/16: Re: Xilinx has released SpartanIII
57840: 03/07/08: phase noise in NCO
57867: 03/07/09: Re: phase noise in NCO
57868: 03/07/09: Re: phase noise in NCO
57869: 03/07/09: Re: phase noise in NCO
58052: 03/07/13: Re: phase noise in NCO
58053: 03/07/13: Re: phase noise in NCO
58055: 03/07/14: Re: phase noise in NCO
87421: 05/07/23: Fastest way to compute floating point log and exp
87452: 05/07/24: Re: Fastest way to compute floating point log and exp
87453: 05/07/24: Re: Fastest way to compute floating point log and exp
88486: 05/08/19: Best FPGA for floating point performance
88493: 05/08/19: Re: Best FPGA for floating point performance
88495: 05/08/19: Re: Best FPGA for floating point performance
88496: 05/08/19: Re: Best FPGA for floating point performance
88500: 05/08/20: Re: Best FPGA for floating point performance
88711: 05/08/25: Re: Best FPGA for floating point performance
89018: 05/09/02: SI considerations for single chip memory configurations
105246: 06/07/18: Re: NAND flash hangs
111543: 06/11/05: Re: Scientific Computing on FPGA
111575: 06/11/06: Re: Scientific Computing on FPGA
116191: 07/03/04: Large power planes vs. power islands vs. slits for decoupling
116225: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116227: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116259: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116279: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116280: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
116284: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116290: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
118162: 07/04/18: Any recommendation for proto PCB
121008: 07/06/21: Re: Nios II problem
121010: 07/06/21: Re: Interesting problems about high performance computing
121820: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
121858: 07/07/13: What is the resistance of a big FPGA for VCCINT (unpowered)
121873: 07/07/14: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121940: 07/07/15: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122198: 07/07/23: Re: FPGA for HPC
128349: 08/01/22: Re: FPGA decoupling calculation
128367: 08/01/23: Re: FPGA decoupling calculation
Marc Boulais:
4458: 96/10/31: Re: Weird pre-config VCC-GND short in Altera or Xilinx
5198: 97/01/30: Re: Altera support better than Xilinx
10967: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
Marc D Bumble:
30548: 01/04/13: Re: pseudo random numbers
Marc Daumas:
9398: 98/03/09: Re: Floating point representation on FPGA
9566: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
Marc David Bumble:
2997: 96/03/11: Reconfigurable Computing Languages
6141: 97/04/16: Re: Exponential function architecture
Marc Delvaux:
13200: 98/11/19: Re: Content Addressable Memorys
17491: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
17498: 99/08/02: Re: Semi-deterministic behaviour in FPGA's
Marc Elpel:
21819: 00/04/02: Re: 82C54
Marc Faure:
30914: 01/05/03: Re: FPGA based PCI cards
Marc Guardiani:
50001: 02/11/27: Re: Frequency multiplier with digital h/w
56709: 03/06/11: Re: Xilinx Spartan 2 and global reset/clock buffer
56831: 03/06/16: Re: XILINX Error Message
57926: 03/07/09: Re: okay what am I missing??? Please
58608: 03/07/28: Re: help neede-----Error Pack 1107 -Unable to combine the following
58688: 03/07/30: Re: ALTERA Byte BlasterII
58689: 03/07/30: Re: tri-State buffer troubles ...
58865: 03/08/03: Re: Unused Pins on big Virtex-II
59235: 03/08/12: Re: Xilinx ISE error
60444: 03/09/13: Re: Webpack Vs. ISE
60445: 03/09/13: Re: What are Pull ups?
60459: 03/09/13: Re: Webpack Vs. ISE
60660: 03/09/19: Re: HDL Bencher for ISE5.1 Version
61247: 03/10/01: Re: ISE WebPack 6.1 Impact problem
61316: 03/10/01: Re: ISE WebPack 6.1 Impact problem
61392: 03/10/02: Re: ISE 6.1 Dies Out of the Gate
62083: 03/10/18: Re: ISE5.2 to ISE6.1
62359: 03/10/28: Re: Altera ACEX1K configuration and initialisation
62580: 03/11/02: Re: Xilinx Weback 6.1i - Java Exception
62908: 03/11/11: Re: ISE 5.2 to 6.1
63078: 03/11/14: Re: Archiving Projects
63349: 03/11/20: Re: Apex power calculator
64786: 04/01/14: Re: Xilinx ECS - connecting a single net to multiple bus lines?
64891: 04/01/15: Re: Please help with Xilinx ISE Schematic question
65835: 04/02/07: Re: Xilinx webpack
66407: 04/02/19: Re: regarding synchronization
66731: 04/02/26: Re: Xilinx webpack 6.1.03i error
66880: 04/02/28: Re: Xilinx ISE Impact crashes during configuration
67932: 04/03/23: Re: XC95288 easy to crack?
68298: 04/04/01: Re: XAPP134's VHDL code
69236: 04/05/01: Re: Connecting a crystal to a Cyclone or Max PLD
69723: 04/05/19: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69889: 04/05/23: Re: strange behaviour of the design
71808: 04/07/31: Re: Xilinx is still in YEAR 2003 ?
94166: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
94313: 06/01/09: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94749: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
98772: 06/03/16: Re: Why Xilinx does not specify clock to output MINIMUM time???
99500: 06/03/25: Re: Installing ISE 8.1i - don't use a space in the install path
103459: 06/06/02: Re: clockless arbiters on fpgas?
107549: 06/08/29: Re: Quartus software and dual-purpose pins
108398: 06/09/10: Re: bidirectional connection between two bidirectional ports
111820: 06/11/10: Re: Non deterministic behaviour in quartus II ?
113267: 06/12/09: Re: JTAG programming of Altera Cyclone and CONF_DONE
113552: 06/12/16: Re: JTAG programming of Altera Cyclone and CONF_DONE
Marc Heuler:
7997: 97/11/05: ABEL HDL state machine question
8201: 97/11/26: Re: what is metastability time of a flip_flop
11393: 98/08/09: Gray code counter in ABEL HDL?
Marc K.:
22638: 00/05/15: Re: ? economical SPROM programmer for Xilinx
22453: 00/05/09: Re: virtex e lvds clock recovery
22637: 00/05/15: Re: CLKing external RAM from FPGA (Virtex E)
22639: 00/05/15: Re: Virtex clock buffers
22649: 00/05/16: Re: CLKing external RAM from FPGA (Virtex E)
22662: 00/05/16: Re: Propogation Delay
22707: 00/05/18: Re: Propogation Delay
22709: 00/05/19: Re: CLKing external RAM from FPGA (Virtex E)
22765: 00/05/23: Re: CLKing external RAM from FPGA (Virtex E)
22818: 00/05/25: Re: PCI core
22820: 00/05/25: Re: CRC
Marc Kelly:
53326: 03/03/10: Xilinx Post Place & Route VHDL output.
70484: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
75199: 04/10/28: Xilinx V-II BUFGMUX oddities..
75232: 04/10/30: Re: Xilinx V-II BUFGMUX oddities..
104125: 06/06/19: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104131: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104132: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104135: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104178: 06/06/20: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
106365: 06/08/12: Xilinx V4FX Embedded MAC.
115901: 07/02/24: Interfacing to 10Gig ethernet with Xilinx FPGAs
115905: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115907: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
Marc Klingelhofer:
23331: 00/06/22: Re: Problem copying text from the Spartan II data sheet
24358: 00/08/04: Packaging info overwhelms timing (was Who needs ... printed ac parameters?)
24999: 00/08/23: Re: Mealy vs Moore FSM model
28122: 00/12/21: Parallel clock termination (Was: 3V -> 5V clock signal level conversion)
38207: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
39389: 02/02/07: Re: Xilinx ISE 3.3 upgrade to 4.1
Marc Le Roy:
67526: 04/03/13: Re: about edif
67848: 04/03/21: Re: Added example VC++ program to download XIlinx FPGAs
82687: 05/04/16: Differential timing specification in Xilinx FPGA
Marc Levy:
13878: 98/12/30: Re: Xilinx XC4000 cinfigured from EPC2?
Marc Matthey:
25196: 00/08/30: Re: Synthesis
marc Nance:
40925: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
Marc Palmarini:
3631: 96/07/05: FPGA vs CPLD
Marc Patrick Kelly:
53348: 03/03/11: Re: Xilinx Post Place & Route VHDL output.
Marc Peter:
14368: 99/01/27: Cheap P&R tool for Xilinx 3K series?
Marc R:
72972: 04/09/09: JTAG Connection For PPC Using VisonProbe V2PRO V2P30
Marc Randolph:
41411: 02/03/27: Re: Maximum device usage for successful PAR
42630: 02/04/29: Re: DCM off chip deskew
42675: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
43420: 02/05/21: Re: How to generate fractional-N clock ?
43624: 02/05/27: Re: footprint competabilty in virtex-II devices
43698: 02/05/29: Re: virtex 2 : DCM divided clock
44021: 02/06/10: Re: Cascaded PROMS
44536: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
44581: 02/06/24: Re: Clock enable & Synplify 7.1
44646: 02/06/25: Re: Clock enable & Synplify 7.1
44695: 02/06/27: Re: Clock enable & Synplify 7.1
44896: 02/07/04: Re: Virtex II - IO TILE, IOB PAD #4
45562: 02/07/26: Re: Xilinx DCMs, RST, and phase coherence
45754: 02/08/04: Re: a chip which can trans ethenet data through E1 interface
47352: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47385: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47421: 02/09/25: Re: Unpredictable Place and Route
47455: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47492: 02/09/26: Re: Altera Cyclone low-cost FPGA chips?
48062: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48384: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48424: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48716: 02/10/23: Re: Silly Virtex 2 Pro question...
49546: 02/11/14: Re: Has anyone tried Lattice's chips?
50353: 02/12/09: Re: virtex output pin voltage
50551: 02/12/12: Re: VirtexII pin assignments/signal flow
50565: 02/12/12: Re: VirtexII pin assignments/signal flow
51269: 03/01/09: Re: External RAM...
51415: 03/01/13: Re: DLL/PLL with global clock net
51638: 03/01/17: Re: How can I use DCM to 1/24 freq-division?
51714: 03/01/20: Re: How can I use DCM to 1/24 freq-division?
52537: 03/02/12: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52677: 03/02/18: Re: Flop count..
52745: 03/02/20: Re: PCB Design for a Xilinx Spartan-II FPGA
52800: 03/02/22: Re: spartan III what is it?
52990: 03/02/27: Re: several fpga high bandwidth questions
53077: 03/03/03: Re: Virtex II - Driving more than one global clock net from one incoming clock pin
53219: 03/03/06: Re: Issues in Outsourcing?
53262: 03/03/08: Re: Clocking a spartanIIE with a 5V signal?
53455: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53887: 03/03/26: Re: Virtex II pro board design question
53914: 03/03/27: Re: Virtex II pro board design question
53978: 03/03/28: Re: Spartan vs. Cyclone for arithmetic functions
54071: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54329: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54716: 03/04/16: Re: spartan 3 pin compatible with 2E?
54980: 03/04/23: Re: Xilinx has released SpartanIII
55007: 03/04/24: Re: Xilinx has released SpartanIII
55183: 03/04/29: Re: Virtex-II DCM frequency synthesizer
55191: 03/04/29: Re: Virtex-II DCM frequency synthesizer
55548: 03/05/12: Re: CRC Generator for 6Byte serial Transmission
55573: 03/05/12: Re: Exploting the DDR input registers in Virtex2
55926: 03/05/23: Re: Virtex2 DCM CLKIN_PERIOD
56142: 03/05/29: Re: 20 to 5 encoder optimization?
56147: 03/05/29: Re: FIFO Controller
56171: 03/05/29: Re: FIFO Controller
56275: 03/06/02: Re: SONET/SDH chipset on FPGA
56500: 03/06/06: Re: Quartus II time delay
56580: 03/06/09: Re: Shift registers
56604: 03/06/10: Re: Shift registers
56855: 03/06/17: Re: Implementaion of Mux-DFF with Virtex ..
57142: 03/06/24: Re: Transfer between clock domains at 350 MHz
57241: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57319: 03/06/27: Re: multiple asychronous resets
57672: 03/07/03: Re: Cyclone vs Spartan-3
57715: 03/07/04: Re: DCM usage question
58597: 03/07/28: Re: CRC questions
58776: 03/08/01: Re: 5 volt tolerant Xilinx parts
59272: 03/08/13: Re: Xilinx DLL driving multiple off chip clocks
60396: 03/09/11: Re: Paging Peter Alfke (3S1000 pricing)
60890: 03/09/24: Re: Configuration Options:
61212: 03/09/30: Re: Bit error rate
61511: 03/10/06: Re: Timing from 1x to 2x and back
61523: 03/10/06: Re: Should I worry about metastability
61557: 03/10/06: Re: Should I worry about metastability
61627: 03/10/08: Re: Xilinx DCMs, DDR, CLK0, and CLK180
62572: 03/11/02: Re: Some FPGA questions
62765: 03/11/07: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62814: 03/11/08: Re: Virtex II DCM & ZBT SRAM
62832: 03/11/09: Re: FPGAs and DRAM bandwidth
62882: 03/11/10: Re: Unconstrained net to DLL's
63065: 03/11/13: Re: How to bring PLL's output to Pin_F1
63118: 03/11/15: Re: Do I need to connect all Vref in a bank together?
63367: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63375: 03/11/20: Re: State Machines....
63376: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63435: 03/11/21: Re: verification vs validation
63495: 03/11/24: Re: Aurora_401 reference allows 8B/10B bypass?
63662: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from
63715: 03/12/01: Re: programmable fir and simulation
63761: 03/12/03: Re: Xilinx Virtex-II: DCM int & ext feedback
63806: 03/12/04: Re: Xilinx Virtex-II: DCM int & ext feedback
63965: 03/12/10: Re: Easypath question (was "Hard-tocopy" rant)
64041: 03/12/13: Re: advantages of ethernet MAC ip core
64436: 04/01/04: Re: please help! state machine
65003: 04/01/18: Re: 802.3 mii
65151: 04/01/21: Re: changing values in a fifo
66907: 04/02/29: Re: difference btw H/W & S/W implementations !!
67336: 04/03/10: Re: A hardware question?
67345: 04/03/10: Re: LVDS
67468: 04/03/12: Re: Issues in Rocket I/O
67528: 04/03/13: Re: XAPP607: Is this just paperwork or based on a real design
67571: 04/03/14: Re: Issues in Rocket I/O
67662: 04/03/16: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000
67665: 04/03/16: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67667: 04/03/16: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67841: 04/03/20: Re: Xilinx timing analyzer
67855: 04/03/21: Re: Xilinx map -timing through ise gui
68100: 04/03/26: Re: Xilinx map -timing through ise gui
68112: 04/03/26: Re: Switching clocks in FPAG internal clock trees
68800: 04/04/19: Re: Xilinx Rocket IO CRC+Clock Corrections results in CRC error
68984: 04/04/23: Re: Xilinx XST problems packing signals into IOB registers...
69027: 04/04/25: Re: Inferring Dynamic shift registers in XST
69101: 04/04/27: Re: Design PAR in Stratix
69296: 04/05/05: Re: Max7000s: how to use the enable of the dffe flip-flop?
69320: 04/05/06: Re: Max7000s: how to use the enable of the dffe flip-flop?
69391: 04/05/10: Re: Serial Data Capture
69434: 04/05/11: Re: FPGA vs Microprocessor: newbie question
69653: 04/05/17: Re: load on a clock signal in FPGA
70130: 04/06/03: Re: tri-state in altera
70211: 04/06/09: Re: V4 teaser, correction
70212: 04/06/09: Re: xilinx gigabit MAC core full vs half duplex
70986: 04/07/04: Re: crc32 vhdl implementation (4 bit data)
71008: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71037: 04/07/06: Re: crc32 vhdl implementation (4 bit data)
71065: 04/07/07: Re: crc32 vhdl implementation (4 bit data)
71298: 04/07/13: Re: synchronus reset on bufg? (xilinx)
71985: 04/08/05: Re: xilinx: non LOC pins causing havoc
72026: 04/08/05: Re: xilinx: non LOC pins causing havoc
72188: 04/08/10: Re: Example of network router and # of LUTs utilized - Searching
72458: 04/08/19: Re: A timer with Celoxica RC100
72676: 04/08/28: Re: 16-depth FIFO and 64-depth FIFO use the same Ram
73757: 04/09/29: Re: luts are optimized away
73038: 04/09/11: Re: Need some help with some technical claims...
75142: 04/10/26: Re: Best Place and Route
75282: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
74109: 04/10/04: Re: does ISE 6.3 improve timing vs. ISE 6.2 ?
74420: 04/10/11: Re: Interfacing an 1GS ADC
75321: 04/11/02: Re: XST: suppressing incorrect optimizations in VHDL code
74338: 04/10/08: Re: Interfacing an 1GS ADC
74570: 04/10/14: Re: GLKP and GLKS
75425: 04/11/05: Re: Xilinx Maximum output required time after clock
75457: 04/11/06: Re: IO Timing constraints with internal clocks
75581: 04/11/10: Re: Overshoot/undershoot towards 2V4000
75610: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
75726: 04/11/13: Re: Spartan3 Block RAM from WebPACK
76223: 04/11/29: Re: XST question
76476: 04/12/03: Re: making an fpga hot
76497: 04/12/04: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76609: 04/12/07: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76704: 04/12/09: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76756: 04/12/10: Re: Floorplanning with only usage estimates. Is it possible?
76832: 04/12/13: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76844: 04/12/14: Re: Newbie question: fitting in cpld
76879: 04/12/15: Re: Linking FPGAs with RocketIOs
76962: 04/12/17: Re: Inferring SRLs with INIT value
77016: 04/12/20: Re: Using low-core-voltage devices in industrial applications
77096: 04/12/22: Re: MAP failes after inserting ILA and ICON cores to the design
77114: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design
77213: 04/12/30: Re: Rocket I/O Fail modes/problems help
77235: 04/12/31: Re: Newbie looking for multiported-RAM to interface to a Spartan-III
77243: 05/01/01: Re: Altera NIOS II/Stratix II vs Xilinx Products
77304: 05/01/04: Re: code fragment causes error during bitstream generation... ISE 6.2 & Spartan3
77408: 05/01/06: Re: Utilisation of Xilinx FPGAs
77459: 05/01/07: Re: Utilisation of Xilinx FPGAs
77512: 05/01/08: Re: a general question
77897: 05/01/19: Re: LVDS through connectors
77909: 05/01/20: Re: LVDS through connectors
78053: 05/01/23: Re: question regarding the physical dimensions of FPGAs
78068: 05/01/24: Re: question regarding the physical dimensions of FPGAs
78126: 05/01/25: Re: Impact errors programing V4LX25
78490: 05/02/01: Re: Pericom PI6C2404 equivalent
79000: 05/02/10: Re: Local clocking in spartan 3
79001: 05/02/10: Re: theta(jb) for V2-PRO in FG676
79020: 05/02/11: Re: RocketIO in 32-bit Mode
79063: 05/02/12: Re: xilinx MGT compatibility?
79252: 05/02/15: What do future FPGA's need? (was: Updated S2 Power specs)
79266: 05/02/16: Re: Virtex4: On using a LC clock pin for global clock.
79296: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
79297: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
79298: 05/02/16: Re: clock split approach for 270MHz design in Spartan2E
79530: 05/02/20: Re: hdl:lament
79581: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79671: 05/02/22: Re: FPGA board with best cost/CLB ratio?
79957: 05/02/26: Re: Fast 28x28 multiplier + adder in Virtex4
80057: 05/02/28: Re: virtex4 virtex-4 FX eval board
80137: 05/03/01: Re: RocketIO, where to start?
80176: 05/03/02: Re: Missing Virtex4 Speedfile
80177: 05/03/02: Re: Xilinx ISE7.1
80264: 05/03/02: Re: Virtex4 : speed improvement
80265: 05/03/02: Re: bad synchronous description error
80487: 05/03/07: Re: VoIP & FPGA
80627: 05/03/09: Re: Xilinx vs Altera high-end solutions
80674: 05/03/09: Re: Global Reset paths
80675: 05/03/09: Re: Xilinx vs Altera high-end solutions
80741: 05/03/10: Re: Xilinx vs Altera high-end solutions
80743: 05/03/10: Re: RocketIO and Gigabit Ethernet
80744: 05/03/10: Re: ethernet core on a xc3s200
80745: 05/03/10: Re: 1,5Mhz Clock
80746: 05/03/10: Re: Global Reset paths
80778: 05/03/11: Re: Global Reset paths
80779: 05/03/11: Re: Xilinx vs Altera high-end solutions
80830: 05/03/11: Re: RocketIO and Gigabit Ethernet
80998: 05/03/15: Re: Xilinx ISE and IP cores
81000: 05/03/15: Re: Memory gate count in ASIC and in FPGA
81052: 05/03/16: Re: Memory gate count in ASIC and in FPGA
81148: 05/03/18: Re: Xilinx ISE and IP cores
81209: 05/03/19: Re: Is an XC3S1500 enough to implement a MP@ML MPEG-2 decoder?
81210: 05/03/19: Re: (Stupid/Newbie) Question on UART
81212: 05/03/19: Re: One-hot statemachine design problems
81213: 05/03/19: Re: Stratix II vs Virtex 4
81228: 05/03/19: Re: Spartan 3E vs. Cyclone2
81232: 05/03/19: Re: (Stupid/Newbie) Question on UART
81334: 05/03/21: Re: rocketio
81422: 05/03/23: Re: clock division using DCM, how?
81423: 05/03/23: Re: changing DDR2 pin LOC on UCF generated by MIG for virtex4
81471: 05/03/24: Re: (Stupid/Newbie) Question on UART
81492: 05/03/24: Re: LVPECL, Virtex II and the EP445
81504: 05/03/25: Re: LVPECL, Virtex II and the EP445
81517: 05/03/25: Re: LVPECL, Virtex II and the EP445
81543: 05/03/26: Re: Multi-FPGA PCB data aggregation?
81555: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81557: 05/03/27: Re: some +. for Altera
81584: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81613: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81746: 05/03/30: Re: Achieving required speed in Virtex-II Pro FPGA
81748: 05/03/30: Re: Driving two DCM with same clock input pad.
81768: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
81794: 05/03/31: Re: One or two DLLs for a SDRAM controller?
81809: 05/04/01: Re: Virtex DCM phase alignment and CLK2X registering
81900: 05/04/04: Re: IBUFG and BUFG +xilinx
81901: 05/04/04: Re: Xilinx XPower - Accuracy Information
81964: 05/04/05: Re: One or two DLLs for a SDRAM controller?
82035: 05/04/05: Re: Xilinx V2-Pro + Select Map programming
82131: 05/04/07: Re: Stupid question
82189: 05/04/08: Re: Clock Jitter on Xilinx FPGA
82379: 05/04/11: Re: Timing
82380: 05/04/11: Re: ISE 7.1 for 64 bit Linux ???
82411: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
82453: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
82480: 05/04/13: Re: Simulation and actual FPGA implementation, how different it is?
82540: 05/04/13: Re: virtex4 reconfiguration time
82617: 05/04/14: Re: virtex4 reconfiguration time
82618: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
82622: 05/04/14: Re: clock input over an I/O pin
82673: 05/04/15: Re: clock input over an I/O pin
82738: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82742: 05/04/17: Re: Xilinx tools from the commandline
82801: 05/04/18: Re: Xilinx tools from the commandline
83344: 05/04/27: Re: Sync + FIFO
83493: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
83504: 05/05/01: Re: Virtex4 and ISE reality check?
83565: 05/05/03: Re: Max freq. of operation in FPGA?
83567: 05/05/03: Re: Xilinx tools from the commandline
83617: 05/05/03: Re: Max freq. of operation in FPGA?
83737: 05/05/05: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
83814: 05/05/06: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83990: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
84062: 05/05/11: Re: Slice Virtex II = Equivalent gates ??
84369: 05/05/17: Re: Registers replication on Xilinx IOBs
84387: 05/05/18: Re: VHDL array question
84428: 05/05/18: Re: VHDL array question
84435: 05/05/18: Re: How many logic cells are there in one slice
84451: 05/05/19: Re: How many logic cells are there in one slice
84603: 05/05/22: Re: Virtex4 Block Ram : ISE6.3 Problem
84661: 05/05/24: Re: re:FSM stops working
84663: 05/05/24: Re: Nondeterministic ISE Placement
84664: 05/05/24: Re: Xilinx Answer Record 21127
84866: 05/05/31: Re: Timing summary
85148: 05/06/06: Re: Magical Mystery Tour of ISE environment variables
85549: 05/06/10: Re: floorplanning
85555: 05/06/10: Re: computer upgrade time.
85572: 05/06/10: Re: computer upgrade time.
85608: 05/06/11: Re: OrCAD Symbol For Xilinx V2PRO
85909: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85993: 05/06/19: Re: FPGAs: Where will they go?
86000: 05/06/20: Re: ISE 7.1 Service Pack 2 - Ready yet?
86335: 05/06/25: Re: ISE 7.1 Service Pack 2 - Ready yet?
86346: 05/06/25: Re: ISE 7.1 Service Pack 2 - Ready yet?
86506: 05/06/29: Re: V4 and NBTI question, again..
86507: 05/06/29: Re: Good FPGA for an encryptor
86572: 05/06/30: Re: V4 and NBTI question, again..
87236: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87246: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87342: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87344: 05/07/21: Re: Xilinx software update?
87365: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87671: 05/07/27: Re: Delay Generators in FPGAs
87709: 05/07/28: Re: Delay Generators in FPGAs
87710: 05/07/28: Re: Virtex4 local clock timing
87883: 05/08/03: Re: RocketIO connexion to an optical transceiver
87938: 05/08/03: Re: RocketIO connexion to an optical transceiver
87951: 05/08/04: Re: RocketIO connexion to an optical transceiver
88286: 05/08/14: Re: Clock for serializer with a Spartan3
88516: 05/08/21: Re: Using very large number in VHDL
88574: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88575: 05/08/23: Re: Using very large number in VHDL
88638: 05/08/24: Re: Send IP packets at the Ethernet level with VIRTEX4
88750: 05/08/27: Re: infering a BRAM block for a dual ported ROM
88752: 05/08/27: Re: ISE 7.1 and DCM clkfx
88753: 05/08/27: Re: SERDES
88850: 05/08/30: Re: infering a BRAM block for a dual ported ROM
88948: 05/08/31: Re: Spartan 3 Serdes
88999: 05/09/02: Re: Spartan 3 Serdes
89490: 05/09/16: Re: DCM question
89743: 05/09/23: Re: 10G serial port with no FEC?
90838: 05/10/22: Re: clock frequency after RTL synthesis vs PAR
90844: 05/10/22: Re: clock frequency after RTL synthesis vs PAR
91777: 05/11/12: Re: Add files to Xilinx ISE Project w/script
93494: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93720: 05/12/28: Re: Xilinx LVDS termination resistor
95666: 06/01/25: Re: encryption
96413: 06/02/03: Re: Back to max thermal and power for XC4VLX200's
96471: 06/02/03: Re: Back to max thermal and power for XC4VLX200's
97689: 06/02/26: Re: ERROR:MapLib:482
98143: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98295: 06/03/08: "toys" = John
100288: 06/04/06: Re: Inferring SRL in Xilinx FPGA
100289: 06/04/06: Re: LVDS in Cyclone-II
100365: 06/04/07: Re: Inferring SRL in Xilinx FPGA
100930: 06/04/21: Re: Bluetooth with FPGA?????
102632: 06/05/18: Re: Reality of V5 as ES
102919: 06/05/23: Re: xilinx pricing discrepancy
103176: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
106274: 06/08/10: Re: ISE software bug???
106584: 06/08/15: Re: Large Spartan3 vs. Small V5
107049: 06/08/23: Re: Global signal conservation
109766: 06/10/05: Re: Generate 16MHz from 75MHz using DCM
110757: 06/10/21: Re: Inferring block ram in Spartan II with non standard bus sizes
116924: 07/03/20: Re: IOSTANDARD default value in Xilinx UCF-Files?
116926: 07/03/20: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
121059: 07/06/24: Re: What wrong with the DCM of Virtex4 in my project?
121299: 07/07/01: Re: intermitent boot in V4
122174: 07/07/22: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122181: 07/07/23: Re: Running Virtex5 GTP at lower data rate
122743: 07/08/06: Re: Single Ended signal in sync with V5 GTP
124536: 07/09/26: Re: Logic minimization software with LUT6 support?
124832: 07/10/06: Re: Virtex 13?
125230: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
126284: 07/11/19: Re: New Laptop for work
126955: 07/12/06: Re: clock lines
127003: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127004: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127031: 07/12/09: Re: Which FPGA and memory to use? The eternal X vs. A question.
127165: 07/12/12: Re: Xilinx RocketIO problems
127289: 07/12/17: Re: global clock (gclk) input at xilinx virtex4 fpga
129990: 08/03/12: Re: its regarding to the Max Frequency in xilinx FPGA
134409: 08/08/09: Re: Coolrunner programming - best way?
134539: 08/08/16: Re: A timing question
Marc Reinert:
20412: 00/02/09: Viterbi Dec. in VHDL (on Xilinx XC4000)
20475: 00/02/11: Re: Viterbi Dec. in VHDL (on Xilinx XC4000)
25606: 00/09/15: PCI-Tip? (for Xilinx Virtex/-E)
26107: 00/10/04: Re: Xilinx Licensing.
26171: 00/10/06: programm Xilinx FPGAs via JTAG
26220: 00/10/09: Re: programm Xilinx FPGAs via JTAG // so far, so good
26222: 00/10/09: Re: programm Xilinx FPGAs via JTAG // so far, so good
26486: 00/10/18: Virtex-E and ADC
26496: 00/10/18: Re: F3.1i, Win2k, LMACs
26502: 00/10/18: Re: Virtex-E and ADC
27582: 00/11/29: Selfmade Cores or something similar (Xilinx)
27825: 00/12/11: Cannot get chip's information from Synopsys
29685: 01/03/05: Parallel Port EPP
29745: 01/03/07: Re: Parallel Port EPP
35720: 01/10/15: JTAG-Programmer Linux
Marc Reinig:
83192: 05/04/25: Help creating a System Ace file
85474: 05/06/09: Re: ISE tools to use SMP?
86419: 05/06/27: Re: USB 2.0 core with 1.1 tranceiver problem
88946: 05/09/01: Re: usb and xc95
89360: 05/09/13: Re: Reading a PAL fusemap with a microscope
100381: 06/04/07: Re: USB Interface to Virtex-4
102462: 06/05/16: Re: Virtex 5 announced and sampling
104876: 06/07/07: Re: Chaos in FF metastability
105204: 06/07/17: Virtex 4, LVDS I/O: Sanity check please
105241: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105249: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105845: 06/08/01: Re: Implementing Haar Decomposition on 256 sample input using only sysgen blocks
111483: 06/11/03: Re: Scientific Computing on FPGA
111621: 06/11/07: Re: Scientific Computing on FPGA
125449: 07/10/25: Re: Paper about selecting fixed point bit widths?
128077: 08/01/14: Re: FPGA's as DSP's
129625: 08/02/29: Need info on systolic arrays in actual use
129631: 08/02/29: Re: Need info on systolic arrays in actual use
129647: 08/03/01: Re: Need info on systolic arrays in actual use
Marc Roche:
27645: 00/12/01: Re: jtag for fpga
Marc Van Riet:
50907: 02/12/22: Re: State of the PCB world
52016: 03/01/29: GNU C for custom processor
52075: 03/01/30: Re: GNU C for custom processor
54847: 03/04/20: Re: Is there any information about Xilinx bitstream file format?
56552: 03/06/09: Re: FPGA Development Board
57061: 03/06/23: Re: "Ethernet only" network
58867: 03/08/03: Re: Size does matter
58877: 03/08/04: Re: Size does matter
58992: 03/08/06: Re: Size does matter
63073: 03/11/13: Re: Building the 'uber processor'
Marc Verhoeven:
11783: 98/09/09: Re: DataIO + EPC1 problem
11794: 98/09/10: Re: DataIO + EPC1 problem
Marc Warden:
24759: 00/08/17: Re: Non-disclosures in job interviews
25598: 00/09/14: Re: hardware compatibility and patent infringement
27675: 00/12/02: Re: ANNOUNCE: Checksum and CRC Code/Article
27676: 00/12/02: Re: ANNOUNCE: Checksum and CRC Code/Article
Marc Weber:
121144: 07/06/26: Can FPGAs inputs detect low currents?
121161: 07/06/27: my project / FPGA as USB client ? (Re: Can FPGAs inputs detect low currents?)(
Marc-Eric Uldry:
31401: 01/05/22: inout signals between Viewdraw schematics and VHDL components
marc_ely:
110660: 06/10/19: Re: Using Opencores I2S master
110661: 06/10/19: Fastest ISE Compile PC?
110664: 06/10/19: Fixing Down Parts of Logic in ISE (8.2)
110704: 06/10/20: Re: FAQ: Re: Fastest ISE Compile PC?
111131: 06/10/30: Re: Fastest ISE Compile PC?
113531: 06/12/15: Xilinx ISE 8.2.3 - Re-Creating Projects
113532: 06/12/15: Xilins ISE Re-Creating Projects
113582: 06/12/17: Re: Xilins ISE Re-Creating Projects
Marcel:
43359: 02/05/20: How to generate fractional-N clock ?
43361: 02/05/20: Re: How to generate fractional-N clock ?
44410: 02/06/19: Xilinx .bit file via jtag ?
44421: 02/06/19: Re: Xilinx .bit file via jtag ?
44548: 02/06/23: Xilinx webpack if - else if statement ??
44587: 02/06/24: Re: Xilinx webpack if - else if statement ??
45197: 02/07/15: Which is best method for register with settable and clearable bits
46435: 02/08/29: Re: sensing an oscillator
47271: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
47272: 02/09/22: Re: Cheap development package for beginner?
Marcel Melters:
27873: 00/12/13: Dual-ported RAM instantiation in Virtex-E ?
27879: 00/12/13: Re: Dual-ported RAM instantiation in Virtex-E ?
27910: 00/12/14: Re: Dual-ported RAM instantiation in Virtex-E ?
Marcel van de Burgwal:
123143: 07/08/17: iMPACT command for selecting remote host running CableServer?
Marcel Wattinger:
31205: 01/05/15: Virtex Handbook
Marceli Firlej:
38999: 02/01/29: MapLab:30 Error in ISE 4.1i
Marcello Lajolo:
4959: 97/01/04: Re: Flex 8K boot-up problem
Marcelo Enrique Moisan Naulin:
18144: 99/10/03: A question
Marcelo Moisan:
18168: 99/10/04: I need a Link
18493: 99/10/27: XACT
Marcin Czeczko:
6992: 97/07/20: GAL Programmer
Marcin E. Hamerla:
32015: 01/06/11: Re: Pin locking in Maxplus2
38857: 02/01/26: Problem with Altera programmer
38878: 02/01/27: Re: Problem with Altera programmer
38929: 02/01/28: Re: Problem with Altera programmer
39222: 02/02/04: Re: Destroying a CPLD by JTAG
39229: 02/02/04: Re: Destroying a CPLD by JTAG
44498: 02/06/21: Re: Help!I can't use the programmer of Max-plus II on windows XP.
47155: 02/09/19: Re: using CPLD's inverter in oscillator circuit
48832: 02/10/25: Re: maxplus2 on WinXP
48958: 02/10/28: Re: Porting from Xilinx to Altera?
49028: 02/10/30: Re: Altera 1k100 serial EEPROM
49863: 02/11/22: Re: BGA footprints
49868: 02/11/22: Re: BGA footprints
49893: 02/11/24: Re: BGA footprints
51709: 03/01/20: FLEXlm
51752: 03/01/21: Re: FLEXlm
51785: 03/01/21: Re: FLEXlm
51800: 03/01/22: Re: FLEXlm
52132: 03/02/02: Re: How to program Altera EPC1213
52477: 03/02/11: Re: What is wrong with Altera Website?
54408: 03/04/10: Re: Cheap(er) FPGA configuration?
Marcin Michalak:
30154: 01/03/26: Asynchronus Mashine States
30180: 01/03/27: Re: Asynchronus Mashine States
Marcin Olak:
75459: 04/11/06: Problem with Nios Development Board (Cyclone)
75460: 04/11/06: Re: Problem with Nios Development Board (Cyclone)
76133: 04/11/25: 386 IP Core
76142: 04/11/25: Re: 386 IP Core
Marcin Piaskowski:
2898: 96/02/26: FPGA and testing
Marcio A. A. Fialho:
76144: 04/11/25: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
76400: 04/12/01: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
<marcj@zwallet.com>:
marco:
32572: 01/06/30: free 8 bit cpu core and spartan2
93357: 05/12/20: Place and Route Algorithms
93407: 05/12/21: Re: Place and Route Algorithms
103537: 06/06/05: ProjectMgmt WARNING from ISE 8.1i XST
114167: 07/01/05: data transfer from fast APB clock domain.
114178: 07/01/06: Re: data transfer from fast APB clock domain.
Marco:
8458: 97/12/16: Adaptec SCSI AVA 1505 and DOS
32220: 01/06/20: AHDL & IDE
32692: 01/07/05: Altera ACEX
32825: 01/07/10: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
55864: 03/05/21: Re: Asynchronous State Machines and HDLs
75373: 04/11/03: Re: FPGA for Game and Amusement
78919: 05/02/10: HELP: Graphic LCD + Keypad + printer
78971: 05/02/10: Re: Graphic LCD + Keypad + printer
78982: 05/02/10: Sending text from fpga to printer
79044: 05/02/11: Re: Sending text from fpga to printer
79060: 05/02/12: Re: Sending text from fpga to printer
79203: 05/02/15: OPB IPIF HELP!!!
79450: 05/02/19: Graphic LCD
79477: 05/02/19: Re: Graphic LCD
79493: 05/02/20: Re: Graphic LCD
79526: 05/02/20: Re: Graphic LCD
80342: 05/03/04: VHDL Instantiation
80345: 05/03/04: 1,5Mhz Clock
80349: 05/03/04: RAM Address Calculating
80350: 05/03/04: Re: 1,5Mhz Clock
80382: 05/03/04: Re: 1,5Mhz Clock
80383: 05/03/04: Re: VHDL Instantiation
80417: 05/03/05: Synthesis with EDK 6.3
80431: 05/03/05: reading data from register and writing to ram
80436: 05/03/05: Re: reading data from register and writing to ram
80452: 05/03/06: State Machine Trouble
80458: 05/03/06: Re: State Machine Trouble
80466: 05/03/06: EST Guide
80484: 05/03/07: Re: EST Guide
80773: 05/03/11: How to make a stdout peripheral?
80780: 05/03/11: BFM Simulation Trouble
80782: 05/03/11: Core Generator Troubles
81150: 05/03/18: C Manual for Microblaze Software
82611: 05/04/15: Help OPB <> Wishbone wrapper
82817: 05/04/18: OPB to Wishbone Wrapper
83072: 05/04/22: A PC for make synthesis
83232: 05/04/26: Re: A PC for make synthesis
83240: 05/04/26: Re: A PC for make synthesis
83661: 05/05/04: Help
84154: 05/05/13: Handling Interrupt
84501: 05/05/20: ISE and Linux
84564: 05/05/21: Re: ISE and Linux
84570: 05/05/21: Re: ISE and Linux
84572: 05/05/21: Re: ISE and Linux
84575: 05/05/21: How to make a 1.44MHz clock?
84586: 05/05/22: Re: How to make a 1.44MHz clock?
84587: 05/05/22: Re: How to make a 1.44MHz clock?
84631: 05/05/23: Re: How to make a 1.44MHz clock?
84801: 05/05/27: Accessing BRAM as a SRAM
84804: 05/05/27: Re: Design flow of Spartan3 for my own embedded processor and HW logic?
84806: 05/05/27: Re: Accessing BRAM as a SRAM
84816: 05/05/28: Re: Accessing BRAM as a SRAM
84817: 05/05/28: Re: Accessing BRAM as a SRAM
84825: 05/05/28: Re: Accessing BRAM as a SRAM
84867: 05/05/31: opb bram controller
84868: 05/05/31: Accessing Bram
84932: 05/06/01: Re: Accessing Bram
84951: 05/06/01: Re: Accessing Bram
85366: 05/06/08: Available under the terms of the SignOnce IP License
85415: 05/06/09: Re: Available under the terms of the SignOnce IP License
85433: 05/06/09: Mapping Dual Port Ram into Microblaze address space
85547: 05/06/10: Re: Mapping Dual Port Ram into Microblaze address space
85585: 05/06/11: Re: computer upgrade time.
85647: 05/06/13: RAM State Machine Examples
85974: 05/06/19: Microblaze address space and variables
86001: 05/06/20: Re: Microblaze address space and variables
86051: 05/06/21: Re: Microblaze address space and variables
86061: 05/06/21: Re: Microblaze address space and variables
86141: 05/06/22: Re: Microblaze address space and variables
86165: 05/06/22: Re: Microblaze address space and variables
86317: 05/06/24: Memory Controller and State Machine
86717: 05/07/05: Connecting ADC to Opb_Spi core
86722: 05/07/05: Re: Connecting ADC to Opb_Spi core
86731: 05/07/05: Re: Connecting ADC to Opb_Spi core
86733: 05/07/05: Re: Connecting ADC to Opb_Spi core
87110: 05/07/15: Linux Fedora and Xilinx ISE
87123: 05/07/15: Re: Linux Fedora and Xilinx ISE
87169: 05/07/18: Red Hat Enterprise 64 bit and ISE WebPack
88259: 05/08/13: Troubles when mapping registers into microblaze address space
88261: 05/08/13: Re: Troubles when mapping registers into microblaze address space
88307: 05/08/15: How to disconnect a signal?
88355: 05/08/16: Re: How to disconnect a signal?
88390: 05/08/17: Changing data into mapped register
88414: 05/08/17: Modelsim on a remote display
88431: 05/08/18: Re: Modelsim on a remote display
88441: 05/08/18: Re: Modelsim on a remote display
88443: 05/08/18: State Machine and BUFG
88445: 05/08/18: Re: State Machine and BUFG
88448: 05/08/18: Re: Modelsim on a remote display
88453: 05/08/18: Re: State Machine and BUFG
88470: 05/08/18: Re: State Machine and BUFG
88511: 05/08/20: Verilog translation
88534: 05/08/22: Re: Verilog translation
88569: 05/08/23: Stdin / stdout through RS232
88576: 05/08/23: Re: Stdin / stdout through RS232
88577: 05/08/23: Using bootloader
88582: 05/08/23: Re: Stdin / stdout through RS232
88585: 05/08/23: Re: Using bootloader
88587: 05/08/23: Re: Stdin / stdout through RS232
88603: 05/08/23: Xilinx Xapp482: syncword?
88679: 05/08/25: Microblaze Simple Bootloader
88690: 05/08/25: Re: Stdin / stdout through RS232
88693: 05/08/25: Re: Stdin / stdout through RS232
88724: 05/08/26: Bootloader Linker Script Help
88758: 05/08/27: Mark to initialize BRAM
88774: 05/08/28: How to reduce software size?
88783: 05/08/28: Re: mails from Aman Mediratta
88785: 05/08/28: Question about program and memory location
88908: 05/08/31: Hi-Z input
88916: 05/08/31: Re: Hi-Z input
88917: 05/08/31: Re: LCD Interface
88929: 05/08/31: Re: Hi-Z input
88954: 05/09/01: Re: Hi-Z input
88957: 05/09/01: A strange behavior
88989: 05/09/02: Re: A strange behavior
89000: 05/09/02: Modelsim simulation question
89036: 05/09/03: The best way to sum 8 datas?
89056: 05/09/04: Re: The best way to sum 8 datas?
89175: 05/09/07: Re: spartan 3 starter kit auto configuration at power up
89450: 05/09/15: Re: ISE 7.1 service packs
89491: 05/09/16: Interrupt Handling
89529: 05/09/18: Xilinx Wizard does not create vhdl DMA template?
89749: 05/09/24: "Free" core and license
89774: 05/09/26: Re: "Free" core and license
89814: 05/09/27: Re: How to run ngcbuild in windows xp environment?
89880: 05/09/29: Turion 64 performance
90066: 05/10/04: High Load
90070: 05/10/04: Re: High Load
90072: 05/10/04: Re: High Load
90137: 05/10/05: Re: High Load
90176: 05/10/06: Re: High Load
90178: 05/10/06: Re: High Load
90179: 05/10/06: FSM with High load on clock signal
90241: 05/10/07: Re: FSM with High load on clock signal
90246: 05/10/07: Re: FSM with High load on clock signal
90252: 05/10/07: Re: FSM with High load on clock signal
90259: 05/10/07: Re: FSM with High load on clock signal
90987: 05/10/26: Re: C source for Spartan-3 with microblaze soft core for RS-232 comm
91068: 05/10/28: Sigma-Delta A/D
91119: 05/10/30: Re: Sigma-Delta A/D
91121: 05/10/30: Re: Sigma-Delta A/D
91126: 05/10/30: Re: Sigma-Delta A/D
91127: 05/10/30: Re: Sigma-Delta A/D
91128: 05/10/30: Re: Sigma-Delta A/D
91145: 05/10/31: Re: Sigma-Delta A/D
91148: 05/10/31: Integrator
91192: 05/11/01: Re: Sigma-Delta A/D
91317: 05/11/03: I have received a job offer
91321: 05/11/03: Re: I have received a job offer
91360: 05/11/04: Re: I have received a job offer
91452: 05/11/07: Spartan3 bus for DSP
91531: 05/11/08: Bus for Spartan3
91641: 05/11/10: Re: Looking for tutorials for bootloader writing on xilinx SOC ??
91720: 05/11/11: Clock signal for an external peripheral
91724: 05/11/11: Re: Clock signal for an external peripheral
91726: 05/11/11: Re: Bus for Spartan3
91782: 05/11/13: Re: Clock signal for an external peripheral
92228: 05/11/24: case statement fault
92239: 05/11/24: Re: case statement fault
92537: 05/12/01: Which Phy transceiver for 10/100 ethernet?
92756: 05/12/06: VHDL SPI core
92794: 05/12/07: How to connect 2 FPGA?
92802: 05/12/07: Re: How to connect 2 FPGA?
92867: 05/12/08: Re: How to connect 2 FPGA?
92969: 05/12/10: Re: How to connect 2 FPGA?
93445: 05/12/22: Opencores Can Controller
94260: 06/01/09: spartan3 differential I/O
94282: 06/01/09: Re: spartan3 differential I/O
94757: 06/01/17: Spartan3 initialization with DSP
94841: 06/01/18: Re: Spartan3 initialization with DSP
94910: 06/01/19: Re: Spartan3 initialization with DSP
94917: 06/01/19: Re: Spartan3 initialization with DSP
95412: 06/01/23: SSOs and Vcco on Spartan3
95427: 06/01/23: Re: SSOs and Vcco on Spartan3
95458: 06/01/23: Re: SSOs and Vcco on Spartan3
95648: 06/01/24: Re: Newbie: xilinx vs arm
95692: 06/01/25: Spartan3 DC datasheet
95926: 06/01/27: Xilinx OBUF attributes on Spartan3
95937: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95941: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95954: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95957: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95960: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95958: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
96601: 06/02/07: input signals in ISE simulator
96642: 06/02/07: Re: ISE Simulator
97517: 06/02/23: Spartan3 decoupling
98147: 06/03/06: Pullup questions on Spartan3
98150: 06/03/06: Re: Pullup questions on Spartan3
98155: 06/03/06: Vccaux regulator
98170: 06/03/06: Re: Pullup questions on Spartan3
98201: 06/03/06: Re: Vccaux regulator
98202: 06/03/06: Re: Pullup questions on Spartan3
98204: 06/03/07: Re: Power estimates in XC3S1500
98205: 06/03/07: Re: Power estimates in XC3S1500
98211: 06/03/07: Re: Xilinx LVDS
98212: 06/03/07: Re: Xilinx LVDS
98275: 06/03/07: Re: Power estimates in XC3S1500
98276: 06/03/08: DCM question
98285: 06/03/08: Re: DCM question
98334: 06/03/08: Re: DCM question
98375: 06/03/08: Re: DCM question
98572: 06/03/13: Re: using EDK with the gcc -g option...
99861: 06/03/30: need your comments
100082: 06/04/03: Re: need your comments
100203: 06/04/05: Re: need your comments
100637: 06/04/14: PROG_B and JTAG
102327: 06/05/15: pull-ups and jtag questions
102334: 06/05/15: Re: pull-ups and jtag questions
102503: 06/05/16: Re: SPI master
102990: 06/05/24: fpga debug
102993: 06/05/24: Re: fpga debug
102996: 06/05/24: Re: fpga debug
103083: 06/05/25: ISE .ant file
103212: 06/05/28: ISE 8.1 with 7.1
103216: 06/05/29: Re: ISE 8.1 with 7.1
103220: 06/05/29: Re: ISE 8.1 with 7.1
103230: 06/05/29: Re: ISE 8.1 with 7.1
103402: 06/06/01: timings
103509: 06/06/04: Re: timings
103895: 06/06/14: boot mode pins on Spartan3
103899: 06/06/14: Re: boot mode pins on Spartan3
103900: 06/06/14: Re: boot mode pins on Spartan3
103977: 06/06/16: bga routing
104039: 06/06/16: Re: bga routing
104097: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104105: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104300: 06/06/23: is picoblaze worth in my project?
107190: 06/08/25: Error message in ISE7.1
107659: 06/08/30: pull-ups for Spartan3
137751: 09/01/28: Re: Complete optical processors and digital photonics to replace electronics in all form factors for commodity high performance computing at the speed of light for all.
Marco Albero:
121511: 07/07/06: I need relocate my program outside bram...
121595: 07/07/09: Problem usign xilfatfs...
121627: 07/07/10: Re: Here you have the 'system.hms'
121628: 07/07/10: Re: And here the 'system.mss'
122003: 07/07/17: Sending large amount of data with lwIP...
Marco Castellon:
34479: 01/08/27: DUART core synthesizable in Xilinx FPGA.
Marco Cavadini:
7528: 97/09/19: FPGA/CPLD Overview
Marco Kluge:
58111: 03/07/15: Bus macros and partial reconfiguration
Marco Landert:
29883: 01/03/15: Re: NIOS 16-Bit
29862: 01/03/14: NIOS 16-Bit
29871: 01/03/14: Re: NIOS 16-Bit
marco p.:
70668: 04/06/23: 5V board in a 3.3V PCI slot
70713: 04/06/24: Re: 5V board in a 3.3V PCI slot
Marco Rivero:
583: 95/01/11: Backannotating Xilinx pinouts to ViewLogic symbols... BUT Not by hand!
8803: 98/01/28: Comments about Xilinx Alliance m1.4 w/Novell and other problems
Marco Sanvido:
17925: 99/09/17: Re: Xilinx development board > XVC400
19066: 99/11/26: Re: HDL Editor
Marco Schmidt:
1571: 95/07/19: routing
1620: 95/08/03: Re: 16 bit computer on fpga's
Marco Serafini:
39078: 02/01/31: Setting PCI command register in WinNT OS
39135: 02/02/01: Re: Setting PCI command register in WinNT OS
39139: 02/02/01: Re: Pin assignment on ACEX1K
39309: 02/02/06: Re: Adding internal JTAG chains on FPGA
42268: 02/04/19: Re: fpga limitation
42274: 02/04/19: RAM function in Altera device
49431: 02/11/12: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
Marco T.:
93513: 05/12/23: Virtex-4FX and ethernet mac
93548: 05/12/24: Re: Virtex-4FX and ethernet mac
93678: 05/12/28: CP2101 <-> Printer?
93723: 05/12/29: USB Printer Interface
93743: 05/12/29: Re: USB Printer Interface
94075: 06/01/05: EDK 8.1i
94444: 06/01/11: Re: best evm for virtex-4 and linux
94827: 06/01/18: Selling Microblaze based Machines
94993: 06/01/20: Loading Data from Prom
95823: 06/01/26: Microblaze data cache question
95922: 06/01/27: Re: Microblaze data cache question
95932: 06/01/27: Multichannel Opb Memory Controller question
95935: 06/01/27: Re: Multichannel Opb Memory Controller question
95938: 06/01/27: Re: Multichannel Opb Memory Controller question
95944: 06/01/27: Re: Multichannel Opb Memory Controller question
95975: 06/01/27: Re: Multichannel Opb Memory Controller question
96022: 06/01/28: Connection between FSL and XCL
96230: 06/02/01: Parallel Cable IV does not work with parallel to usb cable
97350: 06/02/21: SMSC 91c111 and LwIP
97365: 06/02/21: Re: SMSC 91c111 and LwIP
97504: 06/02/23: System with multiple buses
97827: 06/02/28: conv_integer
97831: 06/02/28: Re: conv_integer
97888: 06/03/01: Virtex-4FX Mini Module TEMAC examples
97891: 06/03/01: Re: Virtex-4FX Mini Module TEMAC examples
97944: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
97966: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
98020: 06/03/03: Virtex-4FX MiniModule Atmel Flash
98078: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98083: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98087: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98111: 06/03/05: Re: Virtex-4FX MiniModule Atmel Flash
98380: 06/03/09: Troubles when upgrading Embedded Virtex-4Fx PowerPc
98435: 06/03/10: Someone need to port LwIP to ll_temac core/wrapper?
98454: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
98502: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
99331: 06/03/23: Re: Problem with LwIP and MicroBlaze
99351: 06/03/23: Re: Problem with LwIP and MicroBlaze
99624: 06/03/27: Opb Spi Controller Trouble
99772: 06/03/29: Storing variables into data ocm memory
99784: 06/03/29: Re: problem with IO in EDK 8.1
99791: 06/03/29: Re: Storing variables into data ocm memory
100346: 06/04/07: Re: Virtex-4 Gigabit Ethernet design
100359: 06/04/07: Re: Someone need to port LwIP to ll_temac core/wrapper?
100730: 06/04/17: Which is the best way to measure low frequencies?
100772: 06/04/18: Re: Which is the best way to measure low frequencies?
100852: 06/04/19: Storing Variables into LMB Memory
101434: 06/05/01: Question about the ip I developed
101436: 06/05/01: Re: Question about the ip I developed
101590: 06/05/03: Re: Someone need to port LwIP to ll_temac core/wrapper?
102716: 06/05/19: Re: Ethernet & ML401
102717: 06/05/19: Re: Use USB ports on ML401
102731: 06/05/19: Re: Ethernet & ML401
102773: 06/05/20: Re: Ethernet & ML401
103179: 06/05/27: DVI connected to Virtex-4
103511: 06/06/05: MIL Qualified RTOS for PowerPc 405
103525: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
105448: 06/07/23: Delta sigma Modulator Interface
105833: 06/08/01: Re: FPGA LABVIEW programming
105887: 06/08/02: Re: FPGA LABVIEW programming
111112: 06/10/29: Safe Routing
113454: 06/12/14: Re: what are your current SoC design for ?
113775: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113776: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113785: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
115613: 07/02/15: ML403 FPGA and CPLD
119049: 07/05/10: Gain and Offset Correction
119056: 07/05/10: Re: Gain and Offset Correction
119150: 07/05/13: Digital gain and offset correction
119161: 07/05/14: Re: Digital gain and offset correction
119196: 07/05/14: Re: Digital gain and offset correction
119216: 07/05/15: Re: Digital gain and offset correction
128365: 08/01/23: Pwm Sine Generation
128375: 08/01/23: Re: Pwm Sine Generation
128386: 08/01/23: Re: Pwm Sine Generation
128714: 08/02/05: Minimum Oscillator Frequency
128765: 08/02/05: Re: Minimum Oscillator Frequency
129100: 08/02/14: Rom Implementation in a CPLD
<marcobuffa@gmail.com>:
98763: 06/03/16: ISE 8.1 linux 64bit license key
98980: 06/03/18: Re: ISE 8.1 linux 64bit license key
100834: 06/04/19: incremental synthesis xst ise 8.1
Marcos:
54669: 03/04/15: Altera PCI Development
Marcos G.:
66950: 04/03/01: Wanted: Insight "Virtual Workbench" for Xilinx XCV300 information
Marcum N. Nance III:
6919: 97/07/09: Re: VHDL to EDIF translater
marcus aurelius:
Marcus Bednara:
43122: 02/05/14: Virtex2 placement problem
Marcus Harnisch:
72560: 04/08/24: Re: DDR SDRAM
72621: 04/08/26: Re: DDR SDRAM
72661: 04/08/27: Re: DDR SDRAM
103719: 06/06/09: Re: Good free or paid merge software that edits two similar files?
115065: 07/01/30: Re: video buffering scheme, nonsequential access (no spatial locality)
123434: 07/08/28: Re: New keyword 'orif' and its implications
Marcus Lankenau:
10604: 98/06/05: Atmel AT40K
10603: 98/06/05: Re: Example of 8051 codes to configure Xilinx fpga
10640: 98/06/08: Q: FPGA Place and Route Software
10912: 98/06/30: Spartan test-board
10938: 98/07/05: Re: Spartan test-board
10988: 98/07/08: Re: Configure with BIT file
11153: 98/07/21: problems with xilinx foundation
11433: 98/08/13: How to do FFT
Marcus Schaemann:
65394: 04/01/27: Which Environment for Xilinx Design?
Marcus Svensson:
63742: 03/12/02: Modelsim 5.8 corrupt call stack when adding signals to wave window.
63762: 03/12/03: Re: Modelsim 5.8 corrupt call stack when adding signals to wave window.
<marcus.erlandsson@gmail.com>:
138879: 09/03/13: Re: What happens at opencores.org?
138887: 09/03/13: Re: What happens at opencores.org?
<marcus.harnisch@gmx.net>:
83416: 05/04/29: Re: *RANT* Ridiculous EDA software "user license agreements"?
Mardin:
37601: 01/12/17: division 64
37966: 01/12/27: CRC-32 verilog source code
37970: 01/12/27: Re: CRC-32 verilog source code
37993: 01/12/28: Re: CRC-32 verilog source code
Marek Jaskula:
46704: 02/09/06: new in fpga
48423: 02/10/17: Digilab DIO1 rev.B
Marek Kraft:
114954: 07/01/27: Rank order filtering - XAPP953 - what am I doing wrong?
119353: 07/05/17: Re: Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
120914: 07/06/20: Suggestions for Xilinx based evaluation board for image processing
Marek Ponca:
18370: 99/10/20: Seeking for FPGA/CPLD (Starter) kit
31054: 01/05/10: Waveforms painting
31060: 01/05/10: Re: Waveforms painting
31082: 01/05/11: Re: Waveforms painting
63437: 03/11/21: FC II & Generic
77453: 05/01/07: Synthesis of more FSMs in one file using DC
Marek Skotnica:
1281: 95/05/26: ? FPGA library for ORCAD
4411: 96/10/25: Re: win95 env variables
<marek.kraft@gmail.com>:
126729: 07/11/30: Using DDR RAM on XUP V2Pro board
126759: 07/12/01: Re: Using DDR RAM on XUP V2Pro board
<mares.vit@gmail.com>:
125815: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125818: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125822: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
Margaret Dailey:
15728: 99/04/10: Consulting Engineers Wanted
17219: 99/07/09: Designers wanted
17396: 99/07/23: Re: "Contract Outsourcing?!"
17397: 99/07/23: Mixed Signal Design Engineers Wanted
17540: 99/08/08: Designers wanted
18176: 99/10/05: Designers wanted
Margaret Martonosi:
5996: 97/04/03: Configurable Computing Post-Doc at Princeton
6201: 97/04/25: Postdoc Position Available: Configurable Computing, Performance and Synthesis Tools
<margaretatwork@my-deja.com>:
20906: 00/02/26: IC Validation Engineers/Managers Wanted
Margie Way:
13890: 98/12/31: JOB FPGA/CA Startup
14353: 99/01/26: FPGA/Lead job opportunity at Cisco
<mariab52@my-deja.com>:
22872: 00/05/29: Problem with databus for external ROM using 'Z'
22873: 00/05/29: Problem with databus for external RAM using 'Z'
mariani:
35725: 01/10/15: help request about lattice isp 1032
37059: 01/11/29: palette LUT design(searching ROM)
Marie:
77823: 05/01/18: decrease slew rate - Actel Libero
85487: 05/06/10: programmation with IMPACT with one PROM and two FPGAs
90173: 05/10/06: Actel Libero upgrade - problem with clk pin - Synplify
90197: 05/10/06: Re: Actel Libero upgrade - problem with clk pin - Synplify
90257: 05/10/07: Re: Actel Libero upgrade - problem with clk pin - Synplify
Marija:
68177: 04/03/29: maybe a stupid question
68272: 04/03/31: Re: maybe a stupid question
68482: 04/04/06: number of BRAMs
68512: 04/04/07: timing constraints... again
68519: 04/04/07: Re: Accesing a procedure
68520: 04/04/07: how to use a .ucf file?
68521: 04/04/07: Re: timing constraints... again
Marilyn:
Marinos J. Yannikos:
6718: 97/06/19: APS-X84 - recommended?
19805: 00/01/12: Re: HW resources increased
19824: 00/01/13: Re: HW resources increased
Mario:
32166: 01/06/17: PCI Config Address Space
Mario Ivancic:
65368: 04/01/26: isp Cable for Lattice CPLD
Mario Niebaum:
9637: 98/03/27: Re: VHDL shareware editor?
Mario Prato:
68908: 04/04/21: cpld in plcc84 package
Mario Trams:
54631: 03/04/15: Re: synthesis of a VHDL module in Xilinx
54931: 03/04/22: Re: Initial values for internal RAM
55198: 03/04/30: Re: general: vhdl
55231: 03/05/01: Re: [little OT] SystemC
55441: 03/05/08: Re: Software and hardware monopoly is bad
55468: 03/05/09: Re: [Altera or Xilinx] Questions
55472: 03/05/09: Re: variable clock source for CPLD, PIC
55539: 03/05/12: Re: Register in FPGA
55706: 03/05/16: Re: smallest embedded cpu.
55716: 03/05/16: Re: smallest embedded cpu.
55808: 03/05/20: Re: Xilinx : Tools
55833: 03/05/21: Re: Thermal problems with large FPGA BGA's
55840: 03/05/21: Re: Register in FPGA
55869: 03/05/22: Re: Xilinx : Tools
55873: 03/05/22: Re: Asynchronous State Machines and HDLs
56976: 03/06/20: Re: FPGA device + CPU
56977: 03/06/20: Re: Investment in FPGA
56978: 03/06/20: Re: Port Mode
56979: 03/06/20: Re: Port Mode
57405: 03/06/30: Re: Parallel processing
57771: 03/07/07: Re: division
57913: 03/07/09: Re: how can I use a signal defined in one Architecture to another Architecture
58113: 03/07/15: Re: programming a PLD/CPLD with a PIC?
58217: 03/07/17: Re: Digital Design with just one clock at one edge
58229: 03/07/17: Re: PCI - disabling
58232: 03/07/17: Re: PCI - disabling
58654: 03/07/30: Re: Simulation
59388: 03/08/18: Re: serial communication between pc and altera fpga
59693: 03/08/26: Re: FPGA minimum operating frequencies
59694: 03/08/26: Re: Two near-identicial clocks?
59699: 03/08/26: Re: Two near-identicial clocks?
60044: 03/09/04: Re: New to FPGA, seeking advice
60107: 03/09/05: Re: Suitable FPGA architecture for Robots..
60190: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
60361: 03/09/11: Xilinx-gdb Sources publicly available?
60408: 03/09/12: Re: Xilinx-gdb Sources publicly available?
60927: 03/09/25: Re: Reading from FPGA Issue
61344: 03/10/02: Re: Good VHDL/Verilog editor?
61345: 03/10/02: Re: Host-PCI Bridge
61506: 03/10/06: Re: Host-PCI Bridge
62655: 03/11/04: Re: Building the 'uber processor'
62785: 03/11/07: Re: Building the 'uber processor'
62986: 03/11/12: Re: Logic implementation in SRAM/OTP FPGAs
63725: 03/12/02: Re: problem with RS485 or RS232
64544: 04/01/07: Re: Virtex and Spartan
64545: 04/01/07: Re: Simulating multi-chip design
64850: 04/01/15: Re: Generating clock delays
65777: 04/02/06: Re: Artificial Intelligence/FPGA
65778: 04/02/06: Re: need desperate help!
69531: 04/05/13: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69539: 04/05/13: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
70018: 04/05/27: Re: Propogation delays and setup times
70781: 04/06/28: Re: Newbie question -fanout of iopins in fpga
71306: 04/07/14: Re: mcu vs fpga help me to choose !!
71737: 04/07/29: Re: FPGA vs CPLD
71738: 04/07/29: Re: wishbone protocol documentation
71782: 04/07/30: Re: FPGA vs CPLD
mariosevr:
135684: 08/10/12: Microblaze Network On Chip
Mariotto:
19043: 99/11/25: CIC Filters in FPGA
19561: 99/12/31: code error in active vhdl
marise:
66830: 04/02/26: Re: Question: size of Stratix??
marius:
19092: 99/11/28: Re: implementing TCP/IP on PLD
Marius Vollmer:
14235: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
33950: 01/08/09: Re: Alliance tools going away?
35035: 01/09/18: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35076: 01/09/20: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35078: 01/09/20: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35129: 01/09/22: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
55045: 03/04/25: Re: ise4.2i and wine
55742: 03/05/18: Re: Xilinx announces 90nm sampling today!
56520: 03/06/07: Re: Logical analyzer via USB or printer port
57684: 03/07/03: Re: Xilinx ISE drops support for more parts
66169: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66213: 04/02/14: Re: Peter's 1Hz-640MHz Synth project
66349: 04/02/18: Can FPGA bootstrap itself?
66538: 04/02/21: Re: Can FPGA bootstrap itself?
66583: 04/02/23: Re: Can FPGA bootstrap itself?
66663: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
67094: 04/03/05: Re: Need to speed up Stratix compiles.
67411: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
68448: 04/04/05: Re: FPGA input
69023: 04/04/26: Re: Quartus for linux
69104: 04/04/27: Re: Design PAR in Stratix
76705: 04/12/09: Re: Open source FPGA EDA Tools
76964: 04/12/17: Re: Open source FPGA EDA Tools
77292: 05/01/03: Re: Large open source FPGAs?
77391: 05/01/06: Re: Open source FPGA EDA Tools
77461: 05/01/07: Re: Open source FPGA EDA Tools
79630: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
80791: 05/03/11: Xilinx XST 6.3i: Typo in generics, silent failure?
80850: 05/03/12: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
80963: 05/03/15: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
81772: 05/03/31: One or two DLLs for a SDRAM controller?
81904: 05/04/04: Re: One or two DLLs for a SDRAM controller?
81906: 05/04/04: Re: One or two DLLs for a SDRAM controller?
81963: 05/04/05: Re: WebPack_7.1 on Linux ?
MariuszK:
109676: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
Mark:
11261: 98/07/31: Symbols, design changes, pin changes
11300: 98/08/03: Re: Symbols, design changes, pin changes
15826: 99/04/16: High speed reconfigurability
20964: 00/03/01: Re: Materials on PCI
20966: 00/03/01: Re: Materials on PCI
23503: 00/06/27: Re: JTAG emulation of TI DSPs
29463: 01/02/22: Virtex II availability
29854: 01/03/13: FPGA : Simple FD latch glitchs
34084: 01/08/13: Re: Use of lpm in Xilinx Foundation 2.1i
34085: 01/08/14: Re: Use of lpm in Xilinx Foundation 2.1i
34328: 01/08/21: FPGA MP3 decoder
34331: 01/08/21: Re: FPGA MP3 decoder
36657: 01/11/14: Re: Synopsys+Xilinx vs Synplicity
36667: 01/11/14: Re: Xilinx s/w upgrade 4.1 problems
37017: 01/11/28: Re: reducing PAR time
37018: 01/11/28: Re: Is there a full open-source synthesis path for any FPGA?
37078: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
37079: 01/11/29: Re: reducing PAR time
37081: 01/11/29: Re: reducing PAR time
37123: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37128: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37129: 01/11/30: What do you like/dislike about place and route tools?
40562: 02/03/11: How to Align 7x DDR Data Input to a XC2V6000-5?
40608: 02/03/11: Re: FPGA download fails
40637: 02/03/12: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40698: 02/03/13: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40727: 02/03/14: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
44390: 02/06/19: Re: new computer
44442: 02/06/20: Re: new computer
44982: 02/07/08: Re: Getting started with FPGAs
61001: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61261: 03/10/01: Interface Between National Semi Channel Link TX AND Virtex-II
71865: 04/08/02: Best tool(s) for filter float->fixed->VHDL flow?
72499: 04/08/20: Virtex II LVDS plus DDR?
88938: 05/08/31: New PCI Express Group
88939: 05/08/31: Re: Spartan 3 Serdes
88945: 05/08/31: Re: Spartan 3 Serdes
92098: 05/11/22: Re: Quartus Problem
92099: 05/11/22: Patient Monitors: Reading RS232 output w/ an FPGA
92226: 05/11/24: Re: Patient Monitors: Reading RS232 output w/ an FPGA
108723: 06/09/15: Re: Problems with NIOS II PIO interrupt
108724: 06/09/15: Re: microblaze lwip
109789: 06/10/05: Re: Nios II interrupt
111240: 06/10/31: Re: Nios 2 application running from external ram
111705: 06/11/08: Re: Nios2 access to EPCS device without using HAL drivers
129600: 08/02/28: Re: Picoblaze enhencement and assembler
131251: 08/04/17: Help, router can't rout all connections (XILINX)
131255: 08/04/17: Re: Help, router can't rout all connections (XILINX)
131257: 08/04/17: Re: Help, router can't rout all connections (XILINX)
131258: 08/04/17: Re: Help, router can't rout all connections (XILINX)
140372: 09/05/11: Re: Dual Port RAM Inference
140377: 09/05/11: Re: Dual Port RAM Inference
140379: 09/05/11: Re: Dual Port RAM Inference
140629: 09/05/20: Re: Online tool that generates parallel CRC and Scrambler
mark:
14898: 99/02/24: Re: Xilinx Virtex
15069: 99/03/04: Re: Virtex & Xchecker
15148: 99/03/09: Virtex Programming Weirdness
29357: 01/02/15: Design of a divide by 6.5 counter ?
46901: 02/09/11: XC2V Embedded Multipliers and Chipscope Usage
47098: 02/09/17: Re: XC2V Embedded Multipliers and Chipscope Usage
Mark Linn:
80257: 05/03/02: newbie ABEL questions
80331: 05/03/03: Re: newbie ABEL questions
Mark (UK):
70666: 04/06/23: Re: Asteroids Deluxe in an FPGA
70717: 04/06/24: Re: Asteroids Deluxe in an FPGA
Mark A. Odell:
21929: 00/04/07: Re: Any free design of 8051 in the net?
40681: 02/03/12: Re: Mystery two wire interface, or am I being dense?
72484: 04/08/20: Re: GAL,PAL,PLD, CPLD,FPGA
Mark Aaldering:
61: 94/08/06: Re: Intel iFX questions
4811: 96/12/17: Re: Fpga, Epld, cpld....
4924: 96/12/31: Re: I2C Bus Interface in FPGAs
4960: 97/01/04: Re: EPX880 & 8160 to Become Obsolete
5496: 97/02/20: Re: Xilinx or Altera?
6206: 97/04/26: Re: prep benchmarks for FPGAs
6219: 97/04/29: Re: Low power PLD?
7219: 97/08/15: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
9020: 98/02/14: Re: Philips P5Z22V10 wanted
9021: 98/02/14: Re: Altera Classic Devices 1810, 910, 5128 Problems
10831: 98/06/24: Re: Q: I squared C on an FPGA
13785: 98/12/28: Re: 22V10 Metastability - help please
17130: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
23233: 00/06/18: Re: Reed Solomon in Xilinx FPGA?
23583: 00/07/01: Re: Free PCI core
32180: 01/06/18: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
35818: 01/10/18: Re: Xilinx PCI core and XST
42293: 02/04/19: Re: Source code for a NIOS instruction set simulator?
42314: 02/04/19: was: NIOS ISS, MicroBlaze Cycle Accurate ISS
42390: 02/04/22: Re: NIOS ISS, MicroBlaze Cycle Accurate ISS
Mark Adams:
5077: 97/01/21: Re: Meta Assembler wanted
5526: 97/02/22: Re: Xilinx or Altera?
6893: 97/07/07: Re: Altera archiving
7916: 97/10/29: Re: Modeling using Altera devices
14190: 99/01/18: Re: Ratings for Synplicity Synplify
mark andrew:
81004: 05/03/15: Re: Which HDL?
92283: 05/11/25: How to tell which synthesis tool I am using
Mark Anstice:
29865: 01/03/14: Xilinx webpack supported pachages
Mark Aren:
75590: 04/11/10: Advice on Contemporary Low cost, Medium Density CPLDs
Mark Baert:
32181: 01/06/18: data compression IP for FPGA's
Mark Barr:
38788: 02/01/25: Get error that part is invalid or not supported when Run from synthesis
45119: 02/07/12: Foundation 2.1i --- does it support vertexII?
Mark Borgerson:
33771: 01/08/03: Newbie Question: LPT245 in CoolRunner?
34029: 01/08/12: Xilinx WebPack .UCF file
34222: 01/08/16: Re: Xilinx WebPack .UCF file
Mark Bowlby:
23516: 00/06/28: Re: Virtex Demo Board
Mark Byers:
2456: 95/12/07: Re: (no subject)
Mark Cartlidge:
2470: 95/12/11: Re: Help on boards using FPGA devices for hareware realisation
Mark Champion:
6313: 97/05/14: Re: VHDL or Verilog?
6342: 97/05/16: Re: VHDL or Verilog?
Mark Christensen:
3725: 96/07/22: Re: FPGA vs CPLD
3794: 96/08/02: Re: US-NH FPGA Design Engineer, Avionics
3817: 96/08/06: "Xilinx nixes its antifuse arrays"
Mark Christiaens:
89707: 05/09/23: Announcement Free Symposium on the Future of Configurable Hardware
Mark Coles:
25550: 00/09/13: emma/dy ssn
Mark Condit:
17315: 99/07/20: Re: Xilinx/Synopsys License Problem
Mark Curry:
28920: 01/01/29: Re: looping and ranges
31393: 01/05/21: Re: LFSR Taps for 64 bit registers?
Mark D'Sylva:
39183: 02/02/03: Re: JTAG Boundary Scan with the XDS510
39203: 02/02/04: Re: JTAG Boundary Scan with the XDS510
Mark de Wit:
8069: 97/11/13: Looking for dynamically reprogrammable FPGA's
Mark Dixon:
55266: 03/05/02: SPI-4.2 dynamic alignment - how'd they do that?
Mark Enwright:
20368: 00/02/07: Cool website... Engineering Salary Survey
Mark Fanara:
3459: 96/06/03: Re: RS422 Connections and Pin-outs
3481: 96/06/06: Re: RS422 Connections and Pin-outs
Mark Ferguson:
33793: 01/08/05: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
Mark Fleming:
85955: 05/06/19: Re: Upgrading the EDK from 6.3
Mark Freeman:
67478: 04/03/12: Re: PWM, PLD programming ,(up/down ramp frequency)
Mark Garaway:
3821: 96/08/06: Problem With Xilinx/Viewlogic PROwave
3908: 96/08/18: Re: XACT6.0:prosim and routed design
5523: 97/02/21: Re: Q: Anyone bought APS-X84 FPGA board?
Mark Goldberg:
3552: 96/06/20: Agencies Avaliable
Mark Gonzales:
2716: 96/01/29: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Mark Goodson:
8599: 98/01/12: Re: SDRAM model
9672: 98/03/30: Re: VHDL shareware editor?
Mark Grindell:
17178: 99/07/07: Re: ALTERA GDF to VHDL QUESTION
17179: 99/07/07: Re: 100 Billion operations per sec.!
17180: 99/07/07: Re: 100 Billion operations per sec.!
17286: 99/07/17: Re: fpga 10k50 and up prototype with a/d d/a
17347: 99/07/22: Re: fpga 10k50 and up prototype with a/d d/a
17348: 99/07/22: Re: Chemical FPGAs
17470: 99/07/30: Semi-deterministic behaviour in FPGA's
Mark Haase:
92645: 05/12/02: Re: Quick question, how do I supply +-5V?
Mark Harrison:
30479: 01/04/10: CONTRACTORS
Mark Harvey:
10829: 98/06/24: vhdl model for duart
17877: 99/09/15: R: PROBLEMS WITH ORCA
18000: 99/09/22: No Subject
18351: 99/10/18: R: Reading a Lattice ispLSI 1016
18695: 99/11/08: R: StateCAD versus Viewdraw
19042: 99/11/25: R: How to use multiple resets?
19309: 99/12/13: R: Command line for FPGA Express
20178: 00/01/30: Re: ARM core?
20179: 00/01/30: Re: Testbenches
20433: 00/02/10: Re: Xilinx vs Altera
20434: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20471: 00/02/11: Re: MP3 & Wavelet on FPGA
20750: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20783: 00/02/22: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
21664: 00/03/28: Xilinx DLL properties
22201: 00/05/01: Re: Xilinx CPLD Make file
22389: 00/05/07: Re: edif
22508: 00/05/10: SpartanXL driving 5V CMOS input
22741: 00/05/22: Re: Spartan 2 Industrial temp range versions
23053: 00/06/11: Re: using DDL in virtex FPGA
25390: 00/09/09: Re: VirtexE availability?
25506: 00/09/13: Re: VirtexE availability?
25507: 00/09/13: Re: VirtexE availability?
25508: 00/09/13: Re: VirtexE availability?
25689: 00/09/17: Re: VirtexE availability?
26350: 00/10/12: Re: Xilinx FDN Express vs. Base Express ??
26418: 00/10/15: Re: DLL's Spread Spectrum Compatible ??
26605: 00/10/22: Re: Cheapy FPGA sw
27131: 00/11/12: Re: ChipScope
27318: 00/11/17: Re: 5v parallel cable with 2.5/3.3v spartan II?
27333: 00/11/18: Re: Altera MAX+PlusII v.s. Xilinx Foundation
30660: 01/04/22: Re: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
Mark Hillers:
19386: 99/12/17: Simulation of Virtex-XDW
20595: 00/02/15: coregen-bug produces bad blockram > 16 bit
20613: 00/02/16: Re: coregen-bug produces bad blockram > 16 bit
20682: 00/02/17: Re: coregen-bug produces bad blockram > 16 bit
20709: 00/02/18: Re: coregen-bug produces bad blockram > 16 bit
23897: 00/07/14: synopsys 2000.05 loses control of virtexBlockRam
26805: 00/10/30: ChipScope, MultiLINX and NT
Mark Holland:
70079: 04/06/01: Problems with PLAmap (part of RASP package) from UCLA
Mark Indovina:
2307: 95/11/18: Re: [q][Reverse Engineering Protection]
MARK INDOVINA Xxxxx Ppppp:
32: 94/08/01: Re: How pricey is FPGA development?
91: 94/08/12: John Cooley is looking for FPGA/Synth Benchmarks
483: 94/12/01: Re: Bit Serial ?
885: 95/03/21: Re: Free Viewlogic design kits?
932: 95/03/31: Re: Opinions on IBM PowerPC for Electronics CAD lab
973: 95/04/05: Re: Neocad merges with Xilinx
1027: 95/04/18: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
Mark Johnson:
562: 95/01/04: Re: What's Up At ViewLogic?
6583: 97/06/04: Re: Memory workshop, San Jose
7887: 97/10/27: Re: All Digital DLL or PLL with less than 20ps resolution
8130: 97/11/20: Study guide for metastability
8268: 97/12/04: Fun real-world problem re: metastability, can YOU work it?
8441: 97/12/15: Re: MTBF Calculation. Looking for articles on the subject
8453: 97/12/16: metastability: full citation of Hohl, extracting TAU and T0
10666: 98/06/09: Re: papers wanted on DRAM
Mark Jones:
77753: 05/01/16: Re: What is the difference between ASIC and FPGA?.
82489: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82544: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
Mark Kahrs:
1020: 95/04/17: Re: Need "fusemap" information from vendor, likely?
Mark Kinsley:
17314: 99/07/20: Solaris vs. NT
17319: 99/07/21: Re: Solaris vs. NT
38753: 02/01/24: Intel vs. AMD
38807: 02/01/25: Re: Intel vs. AMD
38997: 02/01/29: Re: Synthsis Tools for Xilinx
Mark Korsloot:
14536: 99/02/03: Re: Q:EEPROM for Xilinx XC4k
24273: 00/08/02: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
25594: 00/09/14: Re: CPLD: Basic informations
29528: 01/02/25: Re: Second Source For ALTERA EPC1 ?
30248: 01/03/29: Re: PCI-X core
30251: 01/03/29: Re: VHDL question
47106: 02/09/17: Re: Question on Fast CPLDs
Mark L. Hampton:
2558: 96/01/02: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
Mark Lancaster:
13539: 98/12/08: Re: Verilog/FPGA Express Synth Problem
17694: 99/08/24: Re: Parallel in Serial out
17709: 99/08/25: Re: Parallel in Serial out
Mark Levis:
15607: 99/04/02: Re: New Book: Programming Embedded Systems in C and C++
Mark Levitski:
75283: 04/11/01: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
75318: 04/11/02: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
75319: 04/11/02: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
74622: 04/10/15: Question on Xilinx VirtexPro II FPGA chip... please
74717: 04/10/17: Re: Xilinx VirtexE internal oscillator
74718: 04/10/17: Re: Xilinx VirtexE internal oscillator
74832: 04/10/20: Re: Question on Xilinx VirtexPro II FPGA chip... please
Mark Lew:
Mark Luscombe:
15704: 99/04/09: Re: ZBT to Virtex Interface at +100M
20452: 00/02/10: Xilinx Virtex Reset
20551: 00/02/14: Re: Xilinx Virtex Reset
20636: 00/02/16: Re: Xilinx Virtex Reset
20681: 00/02/17: Re: Xilinx Virtex Reset
Mark Mahoney:
27188: 00/11/14: Job posting info
Mark Markham:
9479: 98/03/16: Re: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
Mark McDougall:
72963: 04/09/09: Re: Need assistance with an FPGA based project.
73052: 04/09/13: Re: Need some help with some technical claims...
73629: 04/09/27: Re: embedded linux on FPGA?
72921: 04/09/08: Re: Need assistance with an FPGA based project.
73098: 04/09/14: Re: Need some help with some technical claims...
73148: 04/09/15: Re: EDK OPB Uart 16550
75157: 04/10/28: Re: Programmable I/O Card for the PC - does it exist ?
75179: 04/10/28: Re: Viewing/Controling C-Build Outputs
76728: 04/12/10: Re: Getting Started With Simple Sound Synthesis
77938: 05/01/21: Re: C programmer, what does this syntax mean?
77940: 05/01/21: Re: Xilinx Sum in VHDL
80893: 05/03/14: Re: Which HDL?
81010: 05/03/17: Re: Need recommendation on an FPGA board with a USB socket.
81335: 05/03/22: OCIDEC3 testbench failure
81337: 05/03/22: Re: OCIDEC3 testbench failure
81342: 05/03/22: Re: OCIDEC3 testbench failure
81615: 05/03/29: newbie verilog question
81688: 05/03/30: Re: newbie verilog question
82323: 05/04/11: Re: Shared bus on FPGA
83207: 05/04/26: Re: Space Invaders!
88080: 05/08/09: Re: how to reduce vga memory????????
88081: 05/08/09: Re: how to reduce vga memory????????
88474: 05/08/19: Re: how to reduce vga memory????????
88557: 05/08/23: Re: how to reduce vga memory????????
88558: 05/08/23: Re: uDMA Hard drive interface - putting together multiple programs.
89244: 05/09/09: Re: Cyclone conf flash - 25p10 !
89245: 05/09/09: Re: Quartus II - Timing Analyzer
89252: 05/09/09: Re: Cyclone conf flash - 25p10 !
89292: 05/09/12: Re: Has anyone successfully used opencores PCI in FPGA desings?
89326: 05/09/13: Re: SDRAM quality
89378: 05/09/14: Re: SDRAM quality
89385: 05/09/14: Re: fan out capability of FPGA
89386: 05/09/14: Re: fan out capability of FPGA
89580: 05/09/20: Re: Reprogramming FPGA over PCI???
89902: 05/09/30: Re: There is a way to instantiate 'N' VHDL components using a repetitive
90305: 05/10/10: Re: 16550 VHDL code
90429: 05/10/13: Re: [OT]Re: converting 12v signal to 3.3v
91061: 05/10/28: Re: hex rep. in VHDL
91178: 05/11/01: Re: hex rep. in VHDL
91186: 05/11/01: Re: hex rep. in VHDL
91191: 05/11/01: Simulating Cyclone II PLL
91229: 05/11/02: Re: hex rep. in VHDL
91801: 05/11/14: Re: PCI test bench
91927: 05/11/17: Re: UART CORE FOR NIOS
92219: 05/11/24: Re: Unconnected Ports
92780: 05/12/07: Re: VHDL SPI core
93102: 05/12/14: Re: Frequency dependent SOPC builder components
93159: 05/12/15: Re: Frequency dependent SOPC builder components
95907: 06/01/27: Re: ATA controller in fpga
96217: 06/02/01: Re: ERROR message when programming FPGA with Altium Designer 2004
96219: 06/02/01: Re: scrambling
96934: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97868: 06/03/01: Re: FPGA communication, I2C and DAC
98002: 06/03/03: Re: DMA and PCI in SoPC Builder
98633: 06/03/14: Re: Why does Xilinx hate version control?
100771: 06/04/18: Re: Quartus SignalTap and bus turn around
100774: 06/04/18: Re: How to connect FPGA and =?ISO-8859-1?Q?=B5C?=
101953: 06/05/09: Re: PCI Express and DMA
102041: 06/05/10: Re: PCI Express and DMA
102042: 06/05/10: Re: PCI Express and DMA
102052: 06/05/10: Re: simulation works fine but the actual chip doesnt work
102130: 06/05/11: Re: PCI Express and DMA
102145: 06/05/11: XCFxxP Plaform Flash Device Questions
102147: 06/05/11: Re: XCFxxP Plaform Flash Device Questions
102202: 06/05/12: Re: simulation works fine but the actual chip doesnt work
103678: 06/06/08: Re: Incrmental Compilation in Quartus 5.1
104085: 06/06/19: Re: Floppy to FPGA?
104138: 06/06/20: Re: Floppy to FPGA?
104298: 06/06/23: Re: stimulus for FPGA
104406: 06/06/27: Re: Space invaders on Spartan3e starter board
104411: 06/06/27: Re: Space invaders on Spartan3e starter board
104570: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104575: 06/06/30: Re: Spartan3e starter kit vga mod
104781: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit
105251: 06/07/19: Re: Which PCI core for Cyclone II board?
105307: 06/07/20: Re: Which PCI core for Cyclone II board?
105505: 06/07/25: Re: Which PCI core for Cyclone II board?
105506: 06/07/25: Re: Which PCI core for Cyclone II board?
105556: 06/07/26: Re: Virtex4 Rocket I/O. Power filtering.
105600: 06/07/27: Re: Which PCI core for Cyclone II board?
105605: 06/07/27: Re: Which PCI core for Cyclone II board?
106302: 06/08/11: NgdBuild:604 error
106303: 06/08/11: Re: NgdBuild:604 error
106468: 06/08/14: Re: NgdBuild:604 error
106534: 06/08/15: Re: NgdBuild:604 error
106582: 06/08/16: Re: NgdBuild:604 error
106663: 06/08/17: Re: Quartus and source control (continued)
106664: 06/08/17: Re: xilinx or altera?
106665: 06/08/17: Re: xilinx or altera?
106676: 06/08/17: Re: Quartus and source control (continued)
106677: 06/08/17: Re: Quartus and source control (continued)
107756: 06/09/01: Re: Performance Appraisals
109377: 06/09/26: Re: Help required regarding PCI Master core
109448: 06/09/27: Re: Help required regarding PCI Master core
109527: 06/09/28: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109543: 06/09/28: Re: Help required regarding PCI Master core
109544: 06/09/28: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109745: 06/10/05: Re: Help required regarding PCI Master core
110038: 06/10/10: Re: Quartus II 6.0
110087: 06/10/11: Re: Nios software IDE
110088: 06/10/11: Re: Nios software IDE
110100: 06/10/11: Re: Nios software IDE
110172: 06/10/12: Re: a clueless bloke tells Xilinx to get a move on
110178: 06/10/12: Re: Cyclone PLL
110627: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110815: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
111191: 06/10/31: Re: FPGA's for Ethernet?
111270: 06/11/01: Re: FPGA's for Ethernet?
111435: 06/11/03: Re: regardign signal assinment statement............................
111438: 06/11/03: Re: Help required regarding PCI Master core
111548: 06/11/06: Re: Help required regarding PCI Master core
111623: 06/11/07: Modelsim problem - mixed VHDL,Verilog & VHO
111669: 06/11/08: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111670: 06/11/08: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111716: 06/11/09: Re: Graphics-2-FPGA
111718: 06/11/09: Re: floating point arithemetic on fpga
111719: 06/11/09: Re: Non deterministic behaviour in quartus II ?
111720: 06/11/09: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111779: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111780: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111899: 06/11/13: Re: SPI module in FPGA
111967: 06/11/14: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111972: 06/11/14: Re: Nested Generate Statement in VHDL
112099: 06/11/16: Re: Problems with Opencores' I2C "READ" function
113304: 06/12/11: Re: JTAG programming of Altera Cyclone and CONF_DONE
113370: 06/12/12: Re: JTAG programming of Altera Cyclone and CONF_DONE
113593: 06/12/18: Re: JTAG programming of Altera Cyclone and CONF_DONE
114264: 07/01/10: Re: Accessing SATA hard disk for read/write IO through FPGA in an
115179: 07/02/02: Re: Graphics demo using FPGA?
115244: 07/02/05: Re: query in P&R of FPGA
116667: 07/03/15: Re: .bit file to VHDL/verilog source code
117217: 07/03/27: Re: how to read a sequence of video
117812: 07/04/11: Re: Newbie with bus width mismatch problem. Quartus II
118217: 07/04/20: Re: Regarding drivers for FPGA based PCI cards
118398: 07/04/26: Re: I make a usb blaster for altera by myself!
119467: 07/05/21: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
119713: 07/05/25: Re: 6502 and CPU licences in general
119714: 07/05/25: Re: VGA signal through breadboard?
120087: 07/06/01: Re: After PAR simulation, should I assume that it will work on FPGA
120219: 07/06/04: Re: Regarding multiple write problem in opencores pci bridge
120220: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120221: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120227: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120486: 07/06/08: Re: A first FPGA project
120503: 07/06/08: Re: A first FPGA project
120560: 07/06/10: Re: A first FPGA project
120674: 07/06/14: Re: Frogger and Scramble released
120947: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120950: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121012: 07/06/22: Re: Can anyone identify the manufacturer of this Chip ?
121068: 07/06/25: Re: Can anyone identify the manufacturer of this Chip ?
121111: 07/06/26: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121112: 07/06/26: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121152: 07/06/27: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121238: 07/06/29: Re: d-link router?
121428: 07/07/04: Re: Hobbyist trying to decide which device to start with...
121621: 07/07/10: Re: LiveDesign, Altium [opinion]
121773: 07/07/13: Re: Xilinx PCIe endpoint core minimalistic design
122039: 07/07/18: Re: Generating video noise.
123383: 07/08/27: Re: Annoying
123488: 07/08/29: Re: VGA controller in the EDK ?
123718: 07/09/03: Re: [Nios II] How Can I define the pio inputs as a interrupt?
123849: 07/09/06: Re: =?ISO-8859-1?Q?=A1=BENios_II=A1=BFHow_Can_I_Find_O?=
123978: 07/09/10: Re: Anyway to stop Altera Stratix II SignalTap data acquisition
124014: 07/09/11: Re: How to simple convert a hex or mif file from Altera to Xilinx
124082: 07/09/12: Re: PCI byte enalbes in read cycles
124083: 07/09/12: Re: PCI byte enalbes in read cycles
124098: 07/09/12: Re: PCI byte enalbes in read cycles
124189: 07/09/14: Re: overloading ' operators in VHDL
124531: 07/09/26: Re: Never buy Altera!!!!
124603: 07/09/28: Re: Never buy Altera!!!!
124604: 07/09/28: Re: Never buy Altera!!!!
124933: 07/10/11: Xiinx ERROR:PhysDesignRules:10
125213: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125214: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125410: 07/10/25: Re: builing a SPI interface in vhdl
125463: 07/10/26: Re: is Quartus 7.1 really that S*** !?
125464: 07/10/26: Re: fgpa beginner
126630: 07/11/29: Quartus memory init file
126637: 07/11/29: Re: Quartus memory init file
126644: 07/11/29: ISE WARNING Xst:647
126645: 07/11/29: Re: Quartus memory init file
126706: 07/11/30: Re: ISE WARNING Xst:647
126713: 07/11/30: Re: ISE WARNING Xst:647
126799: 07/12/03: Re: ISE WARNING Xst:647
126803: 07/12/03: Re: ISE WARNING Xst:647
128522: 08/01/30: Re: regarding DMA memory to memory copy in NIOS II
128566: 08/01/31: Re: ROM/LUT
128706: 08/02/05: Re: 4-bit table look-up
128866: 08/02/08: Re: I/O mode to use for USB ..?
128924: 08/02/11: Re: Strange "Style guide" requirements...
129756: 08/03/05: Re: [Altera] How to infer some code into ROM-blocks (in automatic
130994: 08/04/08: Re: Avalon Bus <-> Wishbone Bus
133262: 08/06/23: Re: is lwIP absolutely necessary for tcp-ip?
133329: 08/06/25: Re: Configuration Management Best Practices
133504: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133536: 08/07/03: Re: Nintendo DS Screenshots / Video Capture
133786: 08/07/15: Re: Reading FPGA internal memory data
133789: 08/07/15: Re: Reading FPGA internal memory data
134628: 08/08/22: Re: Apple II on FPGA
134944: 08/09/08: Re: need sme help on data encryption based on fpga
135151: 08/09/18: Re: Moving to Altera from Xilinx
135167: 08/09/19: Re: Moving to Altera from Xilinx
135316: 08/09/26: Re: Please recommend good textbook or technical report about FPGA
136041: 08/10/29: ISE 9.2.03i problem
136042: 08/10/29: Re: ISE 9.2.03i problem - work-around
136069: 08/10/30: Re: ISE 9.2.03i problem
136070: 08/10/30: Re: ISE 9.2.03i problem
136087: 08/10/31: Re: ISE 9.2.03i problem
136088: 08/10/31: Re: ISE 9.2.03i problem
136089: 08/10/31: Re: ISE 9.2.03i problem
136142: 08/11/04: Re: ISE 9.2.03i problem
136143: 08/11/04: Re: Why does Nios cannot pass make?
136150: 08/11/04: Re: Why does Nios cannot pass make?
136362: 08/11/13: Re: ISE 9.2.03i problem
136365: 08/11/13: Re: ISE 9.2.03i problem
136460: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136481: 08/11/19: Re: vga interfacing for image display
136533: 08/11/21: Re: Altera DE3 - USB Bulk Transfer
136584: 08/11/24: Re: Altera DE3 - USB Bulk Transfer
136585: 08/11/24: Re: Altera DE3 - USB Bulk Transfer
137168: 08/12/30: Re: How do I xor two signals in VHDL?
137202: 09/01/02: Re: Altera - Create sof file with software inside.
137508: 09/01/21: Re: Image enhancement on FPGA
138277: 09/02/12: Re: Read a PS2 Keyboard input
138644: 09/03/03: Re: Character generator ROM and VGA controller for Spartan 3E
139196: 09/03/24: Globals in mixed-language projects
139552: 09/04/03: Re: clock multipliers, dividers, and more clocks...
139584: 09/04/06: Re: clock multipliers, dividers, and more clocks...
139598: 09/04/07: Re: Modulo-10 counter
139599: 09/04/07: Re: Modulo-10 counter
139605: 09/04/07: Re: pll
139634: 09/04/08: Re: Modulo-10 counter
139817: 09/04/15: Re: Ethernet on Altera FPGA: Help required
139838: 09/04/16: Re: Synchronous clocking between Cyclone III and SDRAM
Mark McMahon:
42754: 02/05/02: Xilinx Download Cable III
49951: 02/11/26: Re: Fast Digital Synthesis Generator
50175: 02/12/04: Re: PROM for XC2S300
Mark Momcilovich:
29350: 01/02/15: Re: Configuration of FPGA using SPROM
40528: 02/03/08: Re: Synopsys Design Compiler
46185: 02/08/21: Re: INOUT port
46405: 02/08/28: Re: My SpartanII thinks it's a Virtex??
Mark Moyer:
56962: 03/06/19: Re: Stapl Player vs. SVF Player
57014: 03/06/20: Re: PALs, GALs and ABEL
59811: 03/08/28: Re: Convert Jedec to logical equations
Mark Murray:
102808: 06/05/21: Quartus ByteBlaster in Active Serial Programming mode not working
102817: 06/05/21: Re: Quartus ByteBlaster in Active Serial Programming mode not working
Mark Nass:
981: 95/04/06: Re: Need 100 MHz, relatively low power FPGAs
Mark Nelson:
41553: 02/04/02: Re: Data Compression in FPGAs
Mark Ng:
31295: 01/05/17: Re: Xilinx Coolrunner 100% routable - but the tools aren't
32799: 01/07/09: Re: XC9500 drive capability
32802: 01/07/09: Re: Xilink WebPACK keeps removing a pin I want to keep.
42081: 02/04/15: Re: Xilinx FPGA load - XAPP 502
42640: 02/04/29: Re: Xilinx XC9500XL family - disabling the bus-hold circuits
44922: 02/07/05: Re: Setting individual slewrate on Xilinx Coolrunner II
46829: 02/09/09: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
48890: 02/10/25: Re: cpld I/O modes
55635: 03/05/14: Re: CollRunner-II EVB problems
66024: 04/02/11: Re: NAND flash interface?
70480: 04/06/17: Re: SPARTAN-IIE -> LVCMOS18
70956: 04/07/02: Re: Xilinx VS. Lattice ABEL code a standard?
72228: 04/08/11: Re: new XILINX 9500XL datasheets
72835: 04/09/03: Re: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
73561: 04/09/23: Re: High speed counters on Xilinx CoolRunner-II
75875: 04/11/17: Re: 5V inputs with series resistor on Spartan-3
Mark Norton:
4832: 96/12/18: Proper target for design
Mark Osterud:
5683: 97/03/07: FPGA Reliability
Mark Pettigrew:
34716: 01/09/05: Re: FPGA : USB in an FPGA, has anyone done it before?
Mark Proctor:
22365: 00/05/05: Re: [BitGen] - pb option UserClk
Mark Purcell:
11221: 98/07/27: Re: How to write a VHDL counter of up & down
11299: 98/08/03: Re: [****] VHDL Compile Error ( +, & Operator )
11302: 98/08/03: VHDL std_logic_vector to integer
11314: 98/08/04: Re: VHDL std_logic_vector to integer
11334: 98/08/05: Re: VHDL std_logic_vector to integer
11336: 98/08/05: Re: VHDL std_logic_vector to integer
11428: 98/08/12: Re: Gray code counter in ABEL HDL?
11477: 98/08/18: Re: Help on Xilinx !
11489: 98/08/19: Re: Where are the multiple drivers?
11535: 98/08/21: Re: half full flag in a xilinx async fifo?
11629: 98/08/27: Re: half full flag in a xilinx async fifo?
11650: 98/08/28: Re: half full flag in a xilinx async fifo?
11923: 98/09/18: Re: ASIC -> FPGA async issues
11971: 98/09/22: Re: ASIC -> FPGA async issues
Mark Raviola:
30229: 01/03/28: Recommended Oscillators for DLL's at 25 MHz
Mark Rawlings:
26270: 00/10/10: Computer Architecture emulator on a Xilinx chip
Mark Rogers:
15521: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
15527: 99/03/29: IP cores and software industry
15535: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
15558: 99/03/30: Re: Free Xilinx Vendor Tools ... NOT :-(
Mark Russell:
27870: 00/12/13: Hold time constraints in virtex?
28005: 00/12/19: Re: Hold time constraints in virtex?
Mark Sandford:
1033: 95/04/18: Re: Free Hardware
50432: 02/12/10: Re: Tiny Forth Processors
56359: 03/06/03: Re: size of SRAM, antifuses and EPROM elements
56381: 03/06/03: Re: Spartan-3 questions?
56818: 03/06/16: Re: Downloading bit-stream with a microprocessor.
57673: 03/07/03: Re: ARM+FPGA
58556: 03/07/25: Re: device selection for game system
67956: 04/03/23: Re: How many times can I burn an FPGA?
Mark Sandstrom:
4640: 96/11/25: How to utilize XC4000e IOB FFs in Synopsys?
6383: 97/05/20: Problem in Leonardo synthesis targetting Altera
6395: 97/05/21: Re: Problem in Leonardo synthesis targetting Altera
6871: 97/07/04: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6970: 97/07/17: Problem with unexpanded logic in xnf synhesized by Leonardo
6978: 97/07/18: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6997: 97/07/21: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
Mark Sasten:
14093: 99/01/12: Foundation v1.5i Spartin Problems
27020: 00/11/07: Re: Architecture/environment suggestions
71947: 04/08/04: Re: adding real UART to xilinx ultracontroller design.
83740: 05/05/05: Re: including components, i.e. SRL16
Mark Schellhorn:
55705: 03/05/16: Eng. samples -- differences from production?
56283: 03/06/02: Re: Parallel_case Synthesis directive
56331: 03/06/03: Re: Parallel_case Synthesis directive
64158: 03/12/18: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
64266: 03/12/23: Re: pcix core in XC2VP7
64360: 03/12/30: Re: virtex-II problems
64473: 04/01/05: Re: Xilinx Logicore PCI64 Problem
64716: 04/01/12: Re: pci-x core
64776: 04/01/13: logicore PCIX issue/question
64800: 04/01/14: Re: logicore PCIX issue/question
64879: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64884: 04/01/15: Re: logicore PCIX issue/question
64926: 04/01/16: Re: DMA w/ Xilinx PCIX core: speed results and question
67257: 04/03/09: Re: a way to use netlists from C
67802: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
69400: 04/05/10: Re: PCIX DMA Serverworks chipset
70851: 04/06/30: PCI-X DMA problem w/ Xeon?
72124: 04/08/09: Re: PCI express FPGA board
Mark Shand:
934: 95/03/31: Re: meta-systems, who are they ?
3517: 96/06/13: External SRAM, XC4000 and clock hackery
4154: 96/09/19: Re: 256K EEPROM
4429: 96/10/28: Re: Has anyone ever used a C -> Xilinx netlister?
5479: 97/02/19: Re: [Q] Xilinx FPGA Resources
5480: 97/02/19: Re: PCI Prototyping board with a XC4013E or XC4013EX
15228: 99/03/15: Re: Questions on Pamette.
Mark Sitkowski:
3650: 96/07/09: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3659: 96/07/10: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
Mark Smith:
48943: 02/10/28: Re: VHDL v. Verilog, Xilinx v. Altera.
76581: 04/12/06: Re: making an fpga hot
76582: 04/12/06: Re: How to subscribe to the newsgroup comp.arch.fpga
77908: 05/01/20: Re: LVDS through connectors
Mark Smotherman:
4008: 96/09/02: query: C to FPGA?
Mark Snook:
643: 95/01/26: Exemplar vs. NeoCAD
925: 95/03/30: FPGA synthesis
1050: 95/04/21: VHDL -> Xilinx synthesis
1138: 95/05/04: Re: IOLOC or Other Xilinx Tools
1215: 95/05/16: PLDShell Plus
1250: 95/05/22: global clocks in ASYL
1332: 95/06/02: Re: AT&T serial EEPROMS
1745: 95/08/24: Quicklogic/Cypress/Warp3
2239: 95/11/08: Wanted Xilinx XC3090LTQ176-8PC
7977: 97/11/05: Re: Vital files generated by maxplus2
13101: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
mark spencer:
59674: 03/08/25: Dini DN3000K10S board for sell
Mark Stephens:
2672: 96/01/22: Re: Virtual Computer Corp. still in business?
2714: 96/01/29: GAL programming for hobby use...Is there no hope?
2734: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
2746: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
2872: 96/02/21: Giga Operations ... Comments from customers?
Mark Sterk:
30384: 01/04/05: Re: DSP Volume-control in FPGA
Mark Summerfield:
14941: 99/02/26: Re: Xilinx ABEL?
16273: 99/05/13: Re: Synchronizer design?
16291: 99/05/14: Re: Synchronizer design?
17895: 99/09/16: Re: simple VHDL?
17917: 99/09/17: Re: simple VHDL?
17967: 99/09/20: Re: simple VHDL?
19026: 99/11/25: Re: implementing TCP/IP on PLD
19036: 99/11/25: Re: implementing TCP/IP on PLD
19057: 99/11/26: Re: Analog
19145: 99/12/02: Re: data serializer/decoder FPGA solution
19971: 00/01/21: Re: Indexing functions
19972: 00/01/21: Re: Patent licences for circuits in FPGA
19973: 00/01/21: Re: looping FIFO?
20757: 00/02/21: Re: multiplier
21269: 00/03/15: Re: Programming FPGAs via backplane (Xilinx)
Mark Taylor:
34301: 01/08/20: Some questions about Spartan2 (& a bug report for XST sp8)
34305: 01/08/20: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34334: 01/08/21: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34448: 01/08/25: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34449: 01/08/25: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34466: 01/08/26: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34467: 01/08/26: Some questions about Spartan2 (& a bug report for XST sp8)
34510: 01/08/28: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34608: 01/08/30: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34624: 01/08/31: Re: Xilinx FPGA Editor - how to route to an internal macro net?
Mark Thorson:
21198: 00/03/10: Re: Extremely fault tolerant strategies
Mark van de Belt:
19147: 99/12/02: Command line for FPGA Express
19172: 99/12/03: Re: Command line for FPGA Express
19405: 99/12/20: Re: How to include SpartanXL code in C souce code?
19470: 99/12/23: Re: Bi-directional 3-State Buffer
39062: 02/01/30: Re: MapLab:30 Error in ISE 4.1i
39894: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39896: 02/02/21: INIT on XC2S30
39928: 02/02/22: Re: INIT on XC2S30
39995: 02/02/23: Re: Replacing expensive configuration SPROM
63068: 03/11/13: Re: unknown devices in JTAG chain
63069: 03/11/13: Writing Blockrams in VHDL
63103: 03/11/14: Re: Writing Blockrams in VHDL
63104: 03/11/14: Re: Inferring Dual Port Block RAM
63397: 03/11/20: Re: avoiding GCLK
63665: 03/11/27: Re: Dual port RAM for Xilinx
63666: 03/11/27: Re: PCI LogiCORE with ISE 5.2
63815: 03/12/04: Re: Dual port RAM for Xilinx
Mark van Wyk:
110938: 06/10/25: Re: Xilinx documentation typos
Mark Vorenkamp:
1396: 95/06/14: Re: Any one working on Cypress PLD's ?
Mark W Brehob:
20989: 00/03/02: Re: Extremely fault tolerant strategies
24435: 00/08/08: Re: Memory specification
28279: 01/01/05: Re: Nondeterministic FSMs in hardware?
Mark W.:
21076: 00/03/06: Re: An optical allusion that will astound you, works on all spec pc's:) 9523
Mark Walter:
30354: 01/04/04: Xilinx Foundation 2.1i License
30868: 01/05/02: Serial UART
30910: 01/05/03: Re: Serial UART
31528: 01/05/29: Re: My80-- i8080A instruction compatible processor core
32193: 01/06/19: Xilinx Student 2.1i FPGA Supported Chips
34035: 01/08/12: Use of lpm in Xilinx Foundation 2.1i
Mark Webster:
1023: 95/04/18: Viewlogic 4.1 & Windows '95
2639: 96/01/17: ProSeries + Actel & Xilinx
3777: 96/07/30: Re: BIDIR Buses
Mark Willey:
8619: 98/01/14: VLSI Design of an FPGA
9291: 98/03/05: Re: The case for free operating systems and EDA
9289: 98/03/05: Re: The case for free operating systems and EDA
9308: 98/03/06: Re: The case for free operating systems and EDA
9309: 98/03/06: Re: The case for free operating systems and EDA
9373: 98/03/07: Re: The case for free operating systems and EDA
Mark Williams:
54550: 03/04/14: Re: Hardware acceleration for raytracing purposes
Mark Woods:
5948: 97/03/28: Re: viewoffice <--> viewoffice compatibility
8778: 98/01/26: Re: Looking for someone to help......
17115: 99/07/01: Re: How to build a NetBridge use FPGA
17116: 99/07/01: Re: FPGAs v/s DSPs in Cell phones
17837: 99/09/10: Re: FreeDES and Free6502 Comments
Mark Wyman:
21212: 00/03/10: Re: **NEW VERSION** MindBender v1.2 814
Mark Zenier:
60: 94/08/06: Re: This (new) froup
2659: 96/01/20: Re: PLD JDEC Files
2717: 96/01/29: Re: GAL programming for hobby use...Is there no hope?
5940: 97/03/27: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
8291: 97/12/05: Re: what is metastability time of a flip_flop
11674: 98/08/31: Re: New Evolutionary Electronics Book
11808: 98/09/10: Re: New Evolutionary Electronics Book
23210: 00/06/17: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
<mark.jarvin@gmail.com>:
112961: 06/12/02: Re: Firmware for Xilinx USB cable
112997: 06/12/04: Re: Firmware for Xilinx USB cable
113215: 06/12/08: Re: Firmware for Xilinx USB cable
<mark.snook@arm.com>:
8683: 98/01/20: Altera serial PROMs and Xilinx FPGAs
<mark4415@my-deja.com>:
27869: 00/12/13: Hold time constraint in Xilinx?
<mark_harvey@my-deja.com>:
18281: 99/10/12: Re: Lattice 1016 replacement
21256: 00/03/14: JTAG by parallel port
MarkAren:
134443: 08/08/11: Altera question - MAX3000 vs MAX7000
134446: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
134514: 08/08/15: Q: Demo Altera NIOS II SOPC limitations
134525: 08/08/16: Re: Q: Demo Altera NIOS II SOPC limitations
134553: 08/08/17: MJL Cyclone Development kit and Quartus II
137211: 09/01/02: MAX7000 power and slew rate control
137234: 09/01/05: Re: MAX7000 power and slew rate control
137235: 09/01/05: Re: MAX7000 power and slew rate control
137283: 09/01/07: Re: MAX7000 power and slew rate control
MarkCondit:
4005: 96/09/02: Re: Looking for s/w to generate test vectors
4006: 96/09/02: Re: FPGA vs. Custom design
Marketer:
17492: 99/07/31: Aesthetic software
Markku Vähätaini:
6368: 97/05/19: Re: suggestion about a pcmcia in a fpga
<markmcmahon@hotmail.com>:
122386: 07/07/26: Is my microblaze cache functioning?
122818: 07/08/07: Microblaze GPIO interrupt
128733: 08/02/05: GCLK overmapped
129970: 08/03/11: Re: Making changes to custom IP in EDK
130216: 08/03/18: FSL or DMA w/ FIFO?
130226: 08/03/18: Re: FSL or DMA w/ FIFO?
130232: 08/03/18: Re: FSL or DMA w/ FIFO?
136210: 08/11/05: Re: Reading files from CF (microblaze 7 and plb)
markn:
5943: 97/03/28: HELP! - peel programming?
Marko:
30238: 01/03/29: Re: Problems with NIC and FlexLM / W2K
30788: 01/04/29: Re: Virtex-II: Clock-to-PAD Issue
31355: 01/05/20: Re: Can anyone comment on the difference between modelsim PE and XE
35690: 01/10/13: Instantiating Virtex II library macros.
35691: 01/10/13: How to instantiate I/O port with both registered input and output?
70942: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
81149: 05/03/18: FIFO i Handel-C
85687: 05/06/13: Re: Searching FPGA board for private use
86882: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
86883: 05/07/07: Re: about fast adder
86897: 05/07/08: Re: Possible bug in Vertex-4 Rocket-IO?
86919: 05/07/08: Re: Possible bug in Vertex-4 Rocket-IO?
86920: 05/07/08: Re: Rocket IO failure after power cycle.
86929: 05/07/09: Re: Possible bug in Vertex-4 Rocket-IO?
86943: 05/07/10: Re: Possible bug in Vertex-4 Rocket-IO?
88561: 05/08/22: Re: ISE7.1i SP3, Dual port block ram, coregen issue
89107: 05/09/05: Re: Modelsim XE and multi-file Verilog projects
89265: 05/09/09: Re: Signed addition
97291: 06/02/20: Is FPGA code called firmware?
97298: 06/02/20: Re: Is FPGA code called firmware?
97340: 06/02/20: Re: arctangent again
97883: 06/03/01: Re: Serious problem with XST
Marko S:
102148: 06/05/11: sqrt(a^2 + b^2) in synthesizable VHDL?
102166: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102167: 06/05/11: ISE 8.1 error, help. Or where is the path?
102170: 06/05/11: Re: ISE 8.1 error, help. Or where is the path?
<marko.udvanc@trilus-spe.si>:
22024: 00/04/13: Re: jtag/jtagprog and fpga-demo-board
markp:
28090: 00/12/20: Re: 3V -> 5V clock signal level conversion
28098: 00/12/21: Re: 3V -> 5V clock signal level conversion
28107: 00/12/21: Re: Help with encoder/decoder
28118: 00/12/21: Re: Help with encoder/decoder
28168: 00/12/23: Re: really fast counter in SpartanXL?
28199: 00/12/28: Re: really fast counter in SpartanXL?
47762: 02/10/03: Re: Need advice wiring up a CPLD
47773: 02/10/03: Re: Need advice wiring up a CPLD
75738: 04/11/13: Digital LP filter in multiplier free FPGA
75741: 04/11/13: Re: Digital LP filter in multiplier free FPGA
75771: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75772: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75773: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75774: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75857: 04/11/17: Re: Digital LP filter in multiplier free FPGA
98337: 06/03/08: Parallel readback on Spartan IIE
98347: 06/03/08: Re: Parallel readback on Spartan IIE
Markus:
67100: 04/03/05: Re: How do I fix this type of errors?
86232: 05/06/23: Xilinx Impact-Tool: Error when downloading partial bitstream
101489: 06/05/02: Re: XDL router info needed
110584: 06/10/18: Re: from LUT contents to boolean equation
113202: 06/12/08: Re: Xilinx PAR crashing with 'make'
116854: 07/03/20: ModelSim PE exit code 211
116915: 07/03/21: Re: ModelSim PE exit code 211
116938: 07/03/21: Re: Using xilkernel with C++
122415: 07/07/27: Re: Xilinx, converting ncd back to edif
123243: 07/08/21: Re: Amount of wire and logic
125327: 07/10/22: Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
125348: 07/10/23: Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
128361: 08/01/23: Re: Problem with UART EDK 9.2.02i
128766: 08/02/06: Re: Problems with GDB in EDK 9.2
129127: 08/02/15: Re: Microblaze 7.0 on V2pro?
131942: 08/05/08: Re: EDK for spartan2?
132503: 08/05/29: Re: Virtex 2 with PLB_v34 and EDK 10.1
135440: 08/10/02: Re: reasonable timing analysis without mapping design to IO
135735: 08/10/14: Microblaze and PowerPC405/440
136287: 08/11/10: Re: Tilera multicore replaces FPGA?
136790: 08/12/05: Re: Preventing PAR from routing signals in closed area groups
136829: 08/12/08: Re: Preventing PAR from routing signals in closed area groups
136859: 08/12/09: Re: Inverting bus connection order in Verilog
136907: 08/12/12: Re: How to insert ChipScope
137230: 09/01/05: Re: Classifying different kinds of FPGA optimizations
138380: 09/02/18: Re: ERROR: overlaps section...
138405: 09/02/20: Re: VHDL long elsif state machine
138555: 09/02/27: Re: mb-gcc producing incorrect code ???
markus:
108861: 06/09/18: Xilinx XAPP775: 10GbE PCS
109070: 06/09/20: Re: i2c,ahb,apb
109262: 06/09/22: Re: i2c,ahb,apb
109362: 06/09/25: Re: i2c,ahb,apb
110559: 06/10/17: OpenCores.org's I2C: Clock Stretching Support
112079: 06/11/15: Problems with Opencores' I2C "READ" function
112125: 06/11/16: Re: Problems with Opencores' I2C "READ" function
112408: 06/11/21: I2C "READ" Setup/Hold Requirement
112468: 06/11/22: Re: I2C "READ" Setup/Hold Requirement
113070: 06/12/05: Re: Usage of BUFIO in Virtex 4?
113119: 06/12/06: Re: Usage of BUFIO in Virtex 4?
113124: 06/12/06: Re: Clock phase shift
Markus Blank:
81971: 05/04/05: Protection measurements
Markus Dobschall:
28353: 01/01/09: Error in Logic Simulator
31477: 01/05/27: dual channel NCO in Xilinx VirtexE
Markus Fras:
36551: 01/11/12: PLL in Altera's Apex20K
49274: 02/11/07: Programming Altera EPC16
114875: 07/01/25: Xilinx USB download cable
114877: 07/01/25: Re: Xilinx USB download cable
116410: 07/03/08: Xilinx CoreGen fifo - ngdbuild error
116446: 07/03/09: Re: Xilinx CoreGen fifo - ngdbuild error
121447: 07/07/04: Change PicoBlaze ROM Code on Spartan 3E Development Board
122391: 07/07/26: DCM with Xilinx Spartan 3E and Precision
122416: 07/07/27: Re: DCM with Xilinx Spartan 3E and Precision
139859: 09/04/17: EDIF generation with Synopsys Design Compiler version B-2008.09
Markus Fuchs:
74335: 04/10/08: Flex10K10A, I2C, MultiVolt IO, pull-ups
74487: 04/10/12: Re: Flex10K10A, I2C, MultiVolt IO, pull-ups
108562: 06/09/13: SoC Development Board
108907: 06/09/19: Re: SoC Development Board
108908: 06/09/19: Re: SoC Development Board
Markus Knauss:
83544: 05/05/02: JTAG communication Problems in Quartus using Signal Tap
83557: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83582: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83583: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83691: 05/05/05: Re: JTAG communication Problems in Quartus using Signal Tap
87029: 05/07/13: Re: QII simulation annoyance
93267: 05/12/17: Altera based Video development board
93277: 05/12/18: Re: Altera based Video development board
117455: 07/03/31: Config PROM for Spartan II
117675: 07/04/06: Re: Config PROM for Spartan II
Markus Koechy:
70825: 04/06/29: File format *.eqn in Altera IDE
74285: 04/10/07: Re: spartan 3 starter kit
Markus Kuhn:
97105: 06/02/16: Implementing a two-modulus PLL divider in Altera Stratix II
97147: 06/02/17: Re: Communication between FPGA and PC with ethernet
97762: 06/02/27: Re: VGA specification
99632: 06/03/27: Re: Altera web site inaccessible
99780: 06/03/29: Re: Please recomend textbook with AES encryption.
99886: 06/03/30: Re: USB phy in dev board
101265: 06/04/28: Re: ISE 8.1i for Linux ?
101906: 06/05/08: Re: Quartus and source control
118411: 07/04/26: Altera Quartus II v7.0 under openSUSE 10.2
119658: 07/05/24: Quartus 7.1 segv on recent Linux distributions
119659: 07/05/24: Re: Altera Cyclone II - used in 100USD Laptop
119701: 07/05/24: Re: Quartus 7.1 segv on recent Linux distributions
129865: 08/03/07: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
Markus Leberecht:
8074: 97/11/14: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8107: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8109: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
Markus Meng:
30872: 01/05/02: [Q] PC104 Slave Board Minimum Signal Requirements ...
31096: 01/05/11: Re: [Q]CardBus PC Card with PCI device
31953: 01/06/09: [Xilinx] Spartan II Devices ..internal tristate busses ...
33635: 01/08/01: [ALTERA] EPC1 devices in DIP8 package for sell
33969: 01/08/09: Spartan-II serial configuration problem from ATMEL device
34283: 01/08/18: [Spartan-II] JTAG configuration problem ...
35600: 01/10/11: [Spartan-XL] Driving a BUFGS from a std. IO ...
37359: 01/12/08: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37367: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37384: 01/12/09: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37453: 01/12/11: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ? Update ...
38073: 02/01/03: ACTEL SX-A serie and ROM implementation ...
38225: 02/01/09: Triscend ARM+FPGA chips Experience
38755: 02/01/24: UCF Parsing Error for Pin2Pin Constraints 3.1i
38795: 02/01/25: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38806: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
39759: 02/02/19: I/O Type of the Xilinx CCLK pin ??
40729: 02/03/13: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40827: 02/03/16: Why do I want to do this ??
40829: 02/03/16: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
41937: 02/04/11: HDLC Controller Design
47307: 02/09/23: Fast serial interconnect bus using spartan-II
50180: 02/12/04: HowTo 'freeze' a placement
50346: 02/12/09: [Spartan-IIE] Additional DLL input pins
51194: 03/01/06: SPI programming through the pc parallel port
52087: 03/01/31: More than four clocks within a spartan-ii device?
52150: 03/02/03: Spartan-II OBUF Driver Impedance
52831: 03/02/24: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
52842: 03/02/24: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
52896: 03/02/25: Unprogrammed XC9536XL is driving the databus high
52905: 03/02/25: Re: Unprogrammed XC9536XL is driving the databus high
52946: 03/02/26: Re: Unprogrammed XC9536XL is driving the databus high
52949: 03/02/26: Re: Unprogrammed XC9536XL ... the end ...
53057: 03/03/02: Re: Design Manager in ISE 5.x
53418: 03/03/13: [Xilinx] Looking for Parallel Cable III ...
53627: 03/03/18: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
55538: 03/05/12: CRC Generator for 6Byte serial Transmission
55661: 03/05/15: [Q] HowTo Speed Constraint Multiple Clock Constraints for Spartan-II
55912: 03/05/23: Using Desigin Constraints in VHDL for Xilinx Spartan-II
55947: 03/05/24: Re: CLKDLL: Dividing
56229: 03/05/31: Re: FPGA's an Flash
56245: 03/06/01: Re: FPGA's an Flash
56348: 03/06/03: Re: FPGA's an Flash
56444: 03/06/05: Re: FPGA's an Flash
57200: 03/06/25: Max Allowable Clock Skew on local Clocks - Spartan-II -5
57209: 03/06/25: Re: Max Allowable Clock Skew on local Clocks - Spartan-II -5
57625: 03/07/03: [DLL Virtex/Spartan-II] Which is the right feedback in x1 and x2 Appl
57628: 03/07/03: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
58027: 03/07/12: Re: CLKDLLE CLK2X180 Outpu doesn't work
61875: 03/10/14: DCM driving multiple OBUF's ... skew in between ...
63138: 03/11/16: Re: More basic questions about Spartan 2 IOB
64155: 03/12/18: www.micron.com VHDL models gone ??
64312: 03/12/27: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
67475: 04/03/12: Which Clock Source for TI's TLK1501, TLK2501 SERDES Chips
67522: 04/03/13: XAPP607: Is this just paperwork or based on a real design
67578: 04/03/15: Re: XAPP607: Is this just paperwork or based on a real design
67840: 04/03/20: Re: LVDS
72451: 04/08/19: [Synthesis][VHDL] HowTo prevent Removal of Registers ...
73784: 04/09/29: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
73957: 04/10/01: Re: Altera SDRAM controller - Only 2 words burst???
72828: 04/09/03: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
73498: 04/09/22: [ALTERA] NIOS-II + MMU + FPU
75528: 04/11/08: Re: SpartanII + ARM7 Question
75529: 04/11/08: Re: SRAM to be able to read/write Micron SDRAM
75596: 04/11/10: Re: SpartanII + ARM7 Question
77166: 04/12/27: [Xilinx ISE6.3 SP3] WebUpdate dies at 84% ...
83161: 05/04/25: [Sparan-II] Internal Power-On Reset Block?
83176: 05/04/25: Re: [Sparan-II] Internal Power-On Reset Block?
83685: 05/05/05: Re: [Sparan-II] Internal Power-On Reset Block?
83881: 05/05/09: Re: 8051 IP core
88194: 05/08/11: [Q] Virtex-IV with RLDRAM-II any experience with it?
88429: 05/08/18: [Q] Synthesis : HowTo Preserve FSM encodings
95881: 06/01/26: Re: DDR2 SDRAM controller
95831: 06/01/26: Re: DDR2 SDRAM controller
97009: 06/02/14: Re: Altera RoHS Irony
106512: 06/08/14: [Xilinx] MIG V1.6 Reduced max Speed for DDR2 controllers ??
109615: 06/10/01: Re: ddr2 sodimm controller
109616: 06/10/01: Re: Anyone had success with MIG, DDR2 and V2Pro?
111515: 06/11/04: Re: JTAG connection for chipscope
111516: 06/11/04: Re: PCI
111518: 06/11/04: Re: chipscope
Markus Michel:
14545: 99/02/04: Re: Need Help! clock multiplier!
14556: 99/02/04: Re: VHDL problem (Xilinx-problem)
15436: 99/03/24: Synplify -> MaxPlus II
15957: 99/04/23: Re: on using EAB of FLEX10k
16228: 99/05/11: Re: Synchronizer design?
16818: 99/06/11: Re: Configuring AlteraFlex10k with maxII
16865: 99/06/15: Re: Configuring AlteraFlex10k with maxII
20859: 00/02/24: PCI 64 bit / 66 MHz
25064: 00/08/25: DLL Properties on Xilinx Virtex/VirtexE
26671: 00/10/24: IOBUF's replaced by IBUF's
27438: 00/11/22: Re: Resetting Flip-Flops in Virtex
30948: 01/05/04: Re: Use of record type in a hierarchical architecture
Markus Pfaff:
989: 95/04/08: Xilinx XC3000a/4000 as LCD-driver
Markus Rettinger:
3248: 96/05/03: SILAGE
Markus Rossmann:
10375: 98/05/15: Re: Neural Network implementation
Markus Sponsel:
30986: 01/05/08: Re: Licensing PB in Synplify_pro 6.2
46900: 02/09/11: Re: Saving results with modelsim
50125: 02/12/03: Re: register OR latch ?
58378: 03/07/22: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
Markus Svilans:
103707: 06/06/08: Re: Good free or paid merge software that edits two similar files?
Markus Walter:
51134: 03/01/03: Alternative to theXilinx XC4005E
Markus Wannemacher:
1555: 95/07/14: Q: New XILINX XC6200-FPGA
1594: 95/07/24: Re: PREP data
1635: 95/08/09: Re: Looking for info on ACM FPGA'96 workshop
1727: 95/08/21: Re: List of FPGA Based Computing Machines
2126: 95/10/18: Re: Library of Parametrized Modules info
3176: 96/04/18: Re: Crosspoint Solutions
4584: 96/11/18: GEC Plessey, Toshiba, PlusLogic FPGAs?
6069: 97/04/09: comp.arch.fpga archiv dead?
6077: 97/04/10: Crosspoint Solutions FPGA???
9850: 98/04/09: German only: Neues FPGA-Kochbuch
10445: 98/05/19: German only: Neues FPGA-Kochbuch
10468: 98/05/20: Re: Archives for comp.arch.fpga?
12120: 98/09/30: Re: Free FPGA/HDL Newsletter Announcement
12486: 98/10/13: Re: books
12607: 98/10/20: Re: Where to find comp.arch.fpga newsgroup archive
14754: 99/02/15: Re: comp.arch.fpga Archives
15703: 99/04/09: Re: FPGA testing board
16922: 99/06/17: Re: FPGA board for ISA bus wanted
18771: 99/11/13: Re: looking for Xilinx/Actel Board
22036: 00/04/14: Re: Demo - board
38794: 02/01/25: XC2V10000 still on the Xilinx roadmap?
Markus Wolfgart:
44580: 02/06/24: Old Synario SW, how to adapt for MACH211 and MACH4-64/32 programming?
49030: 02/10/30: Data sheet for an Altera EPS464LC wanted!
49062: 02/10/31: Which PCI-IO-Chip manufacturer to prefer?
49365: 02/11/11: Re: Which PCI-IO-Chip manufacturer to prefer?
49780: 02/11/21: XCS-05-3PC84 and XCS10-3PC84 Question
49845: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49907: 02/11/25: Re: XCS-05-3PC84 and XCS10-3PC84 Question
Markus Zingg:
62413: 03/10/29: How to protect fpga based design against cloning?
62418: 03/10/29: Re: How to protect fpga based design against cloning?
62462: 03/10/30: Re: How to protect fpga based design against cloning?
63974: 03/12/10: Re: Soldering of FPGAs
64094: 03/12/16: Re: Soldering of FPGAs
98590: 06/03/13: Re: Soldering SMT/BGA
106018: 06/08/05: verilog versus vhdl
109424: 06/09/26: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109430: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109685: 06/10/03: JTAG cable @ 2.5 V - where?
109710: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
116460: 07/03/09: Virtex 4 FX12 - where are the EMACs and PPC core located?
116529: 07/03/12: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
116546: 07/03/12: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
<markus.jank@de.bosch.com>:
123500: 07/08/29: Strange behaviour of a design
123553: 07/08/29: Re: Strange behaviour of a design
<markus.jank@gmx.de>:
123598: 07/08/30: Re: Strange behaviour of a design
123802: 07/09/04: Re: Strange behaviour of a design
<markx.gregory@intel.com>:
15779: 99/04/14: Intel Opportunity
marlboro:
54069: 03/04/01: Re: parity checking trick for PCI core
57196: 03/06/25: Re: Interfacing IDE
58272: 03/07/18: Re: How fast coregen FIR?
58280: 03/07/18: 4.2i sp3 map error xc2v3000-ff1152
59078: 03/08/07: Re: Need help: getting 3.1i Coregen working on P4-system
60121: 03/09/05: Re: Schematic simulation and then FPGA programming?
61434: 03/10/03: Re: Graphics rendering revisited
61435: 03/10/03: Re: Graphics rendering revisited
Marlboro:
48013: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
50843: 02/12/20: Vitex DLL and external PLL
51279: 03/01/09: Re: External RAM...
51461: 03/01/14: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51519: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
53029: 03/02/28: SCSI SPI-4 interface
57443: 03/06/30: 48bit adder won't fit
57446: 03/06/30: Re: 48bit adder won't fit
58340: 03/07/21: virtex2 map error?
59539: 03/08/21: Re: DCM vs state machine
59552: 03/08/21: Re: DCM vs state machine
59581: 03/08/22: LVPECL I/O and Fndtn4.2
64483: 04/01/05: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
66312: 04/02/16: Re: FIR filter coefficient (with COE file)
70654: 04/06/22: Re: Is the Xilinix XC3020 atill supported?
72388: 04/08/17: Re: let me have logic design for traffic light
72754: 04/08/31: Re: The Effect of Pin Assginment
74314: 04/10/07: Xilinx lead free parts hidden fact
74648: 04/10/15: Re: direct calculation of the modulus ?
76047: 04/11/23: Re: Help! What is this card?
96798: 06/02/10: Re: Spartan3 embedded synchronous multipliers
101936: 06/05/08: Re: flashing a led
103091: 06/05/25: Re: Virtex 5 announced
106295: 06/08/10: Re: Who is your favourite FPGA guru?
107122: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107885: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108581: 06/09/13: Re: X4000 bad configuration
108591: 06/09/13: Re: X4000 bad configuration
108968: 06/09/19: Re: VHDL oddity
108971: 06/09/19: Re: Buffering the critical path.
109087: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109813: 06/10/05: Re: nicer code => slower code??
110079: 06/10/10: Re: FPGA to SRAM port interface
110121: 06/10/11: Re: FPGA to SRAM port interface
110219: 06/10/12: Re: VGA timing
110930: 06/10/25: Am I seeing meta-stable or what?
112853: 06/11/29: Re: DVI clock generation
113897: 06/12/28: Re: better ways for debugging?
113898: 06/12/28: Re: remove logic redundancy
113929: 06/12/29: Re: remove logic redundancy
114967: 07/01/28: Re: how do you code this?
114969: 07/01/28: Re: how do you code this?
114972: 07/01/28: Re: video buffering scheme, nonsequential access (no spatial locality)
115375: 07/02/08: Re: question abt DPRAM
115495: 07/02/12: Re: substracting a whole array of values at once
115496: 07/02/12: Re: substracting a whole array of values at once
115501: 07/02/12: Re: ModelSim - Do Files
116042: 07/02/28: Xilinx USB flatform cable length mistery ?
116048: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116348: 07/03/07: DFF with clock and async-preset tied together
119754: 07/05/25: IOSTANDARD user constrain
119771: 07/05/25: Re: IOSTANDARD user constrain
120156: 07/06/01: Weekend pop quiz
120167: 07/06/02: Re: Weekend pop quiz
120194: 07/06/02: Re: Weekend pop quiz
120204: 07/06/03: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120466: 07/06/07: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120470: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120474: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120563: 07/06/10: Re: adaptive filter FPGA
120647: 07/06/12: Re: adaptive filter FPGA
120690: 07/06/13: Re: adaptive filter FPGA
120719: 07/06/14: Re: adaptive filter FPGA
120760: 07/06/15: Re: Stolen Spartan 3E-1600 Development Board
124469: 07/09/23: Re: Gated Clock Problems
125034: 07/10/15: Re: FIFO depth
125147: 07/10/16: Re: Unrouted nets (Xilinx FPGA Editor)
125972: 07/11/10: Re: FIFO interface design
126791: 07/12/02: Re: Traffic Light with counter
128596: 08/01/31: Design security for pre-Virtex2 parts ?
128656: 08/02/01: Re: Design security for pre-Virtex2 parts ?
131121: 08/04/11: Re: Xilinx tech Xclusive
134666: 08/08/25: Re: Analog Imager interface to FPGA
134668: 08/08/25: Re: Analog Imager interface to FPGA
134692: 08/08/26: Re: Analog Imager interface to FPGA
135190: 08/09/19: Is it hard to detect an ucf sytax error?
136898: 08/12/11: How to insert ChipScope
138110: 09/02/06: ISE10.1 not support guide mode Map & PAR ?
138273: 09/02/11: Re: ISE10.1 not support guide mode Map & PAR ?
Marloboro:
58242: 03/07/17: How fast coregen FIR?
Maroc:
103923: 06/06/15: XPLA3 bidirectional bus
125167: 07/10/17: High level FPGA work flow: available tool?
125175: 07/10/17: Re: High level FPGA work flow: available tool?
maroni:
118231: 07/04/20: Clock signal FPGA XC95288xl144
Maroof H. Choudhury:
5567: 97/02/25: Re: Q: Search Engines for Electronic Parts?
Marra:
120565: 07/06/10: Re: Mobile DDR vs DDR2
marsala.miz@gmail.com:
137214: 09/01/03: DE2 Board DDR Controller Problem
marta:
103145: 06/05/26: ADV7321 interlaced mode
103234: 06/05/29: Re: ADV7321 interlaced mode
Marten:
59795: 03/08/28: Re: Selecting between two clock signals
Marten van Essen:
46926: 02/09/12: Re: Saving results with modelsim
Marteno Rodia:
140385: 09/05/12: [newbie asking] I don't like Xilinx
140411: 09/05/13: Re: I don't like Xilinx
140420: 09/05/13: Re: I don't like Xilinx
140506: 09/05/15: Re: I don't like Xilinx
Martijn:
106680: 06/08/17: Using XMD for memory dumps (speed)
106738: 06/08/18: Re: Using XMD for memory dumps (speed)
107187: 06/08/25: Xilinx IPIF DMA done interrupt ?
107407: 06/08/28: Re: Xilinx IPIF DMA done interrupt ?
Martin:
23962: 00/07/18: Re: Altera fitter woes
30564: 01/04/17: Re: XCV1000BG560: onchip ram
31403: 01/05/22: Counter problem
31414: 01/05/22: Re: Counter problem
31428: 01/05/23: Re: Counter problem
31647: 01/06/01: Re: Help requested in choosing a career
37111: 01/11/30: Ballynuey 2 Hostsoftware
41796: 02/04/08: Re: A learner of Modelsim
42929: 02/05/07: Re: Virtex 2: Partial Bitstream Generation
43275: 02/05/17: Re: Virtex2 placement problem
43610: 02/05/27: Re: FPGA, VHDL : RAM initialization
44823: 02/07/02: Re: Power consumtion simulation for FPGA?
45514: 02/07/25: Re: XST vs FPGA Express???
46864: 02/09/10: Re: Xilinx Parallell Cable IV and Wine
52829: 03/02/24: Looking for Virtex2Pro and Linux (PPC)
64036: 03/12/12: advantages of ethernet MAC ip core
67396: 04/03/11: Clock and data synchronization
69147: 04/04/28: Clock frequency converter from 1.544MHz to 2.048MHz (or multiples)
77172: 04/12/28: PicoBlaze implementation
77777: 05/01/17: USB Host
77811: 05/01/17: Re: USB Host
77815: 05/01/18: Re: USB Host
78158: 05/01/25: Linux on V2P
78193: 05/01/26: Re: Linux on V2P
78358: 05/01/31: OT: Design security
78409: 05/01/31: Re: Design security
78489: 05/02/02: Re: Design security
81460: 05/03/24: OT: EDA tools
81511: 05/03/26: Re: OT: EDA tools
81512: 05/03/26: Re: OT: EDA tools
87338: 05/07/21: Xilinx software update?
87350: 05/07/22: Re: Xilinx software update?
87463: 05/07/24: Re: Xilinx software update?
88960: 05/09/01: "Perform Timing-Driven Packing and Placement" error?
88994: 05/09/02: Re: "Perform Timing-Driven Packing and Placement" error?
88996: 05/09/02: Re: "Perform Timing-Driven Packing and Placement" error?
91776: 05/11/13: Bitstream compression
91798: 05/11/13: Re: Bitstream compression
91843: 05/11/15: Re: Bitstream compression
91844: 05/11/15: RoHS
91881: 05/11/15: Re: RoHS
91892: 05/11/16: Re: RoHS
91909: 05/11/16: Re: RoHS
93923: 06/01/03: Re: FPGA DVI output with CH7301
94505: 06/01/12: OT: RoHS and Lead?
94533: 06/01/13: Re: OT: RoHS and Lead?
97985: 06/03/02: DMA and PCI in SoPC Builder
98030: 06/03/03: Re: DMA and PCI in SoPC Builder
98168: 06/03/06: Re: DMA and PCI in SoPC Builder
98377: 06/03/09: Re: DMA and PCI in SoPC Builder
113438: 06/12/13: GUI Based vs. Manual Instantiation of Components
137337: 09/01/09: Software Debugging on Power PC
137338: 09/01/09: Re: Software Debugging on Power PC
138331: 09/02/16: PowerPC 405 Problem on Xilinx Virtex II FPGA
martin:
49602: 02/11/17: mcu and fpga interface question
Martin Bosma:
97583: 06/02/24: USB 2.0 OTG in FPGA
97591: 06/02/24: Re: USB 2.0 OTG in FPGA
Martin Anding:
6104: 97/04/12: Re: Cadence dfII Layout Plotter: which type are the best solution ?
Martin Brown:
50010: 02/11/28: Re: hardware image processing - log computation
85866: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
martin capitanio:
31102: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31119: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
Martin Charlwood:
127058: 07/12/10: GAL16V8
Martin Curran-Gray:
201: 94/09/20: Re: PLD for async state machine?
215: 94/09/26: Xilinx 4000
1681: 95/08/15: Re: Timespecs in XNF format
Martin Czamai:
41941: 02/04/11: Insight service and PCI demo board question
41984: 02/04/12: Re: Insight service and PCI demo board question
Martin d'Anjou:
4336: 96/10/17: Re: xc4000 and 2 clocks
4346: 96/10/18: Re: xc4000 and 2 clocks
4671: 96/11/27: Re: How to use Xilinx ?
4746: 96/12/10: Re: ASICs Vs. FPGA in Safety Critical Apps.
6042: 97/04/07: Chip Temperature (was:Re: Sole source)
6050: 97/04/08: Re: Chip Temperature (was:Re: Sole source)
Martin dAnjou:
5370: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
Martin DAnjou:
3854: 96/08/09: Re: ANNOUNCE : HDL Editor
Martin Darwin:
28635: 01/01/18: Re: revision control tools ??
38266: 02/01/10: Re: asic vs. fpga
38310: 02/01/11: Re: asic vs. fpga
131865: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
Martin Duffy:
13322: 98/11/25: DynaChip
13939: 99/01/04: Re: PLL in FPGAs?
15118: 99/03/08: Re: Current State of FPGA-based PCI Interfaces?
15501: 99/03/26: Re: IBM 600MHz FPGA
16015: 99/04/28: Re: High speed PLL inside FPGA
16040: 99/04/29: martin_duffy@compuserve.com
16041: 99/04/29: Re: martin_duffy@compuserve.com
16933: 99/06/17: Actel's proASIC
Martin E.:
42177: 02/04/17: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42840: 02/05/04: SelectRAM and DCM
42869: 02/05/05: Re: SelectRAM and DCM
42870: 02/05/05: Re: SelectRAM and DCM
42921: 02/05/07: Re: Frequency synthesiser
46340: 02/08/26: VirtexII: HSWAP_EN
46347: 02/08/26: Re: VirtexII: HSWAP_EN
46348: 02/08/27: Re: VirtexII: HSWAP_EN
46351: 02/08/27: Re: VirtexII: HSWAP_EN
46373: 02/08/27: Re: VirtexII: HSWAP_EN
47470: 02/09/26: Choosing Virtex II Speed grade
47484: 02/09/26: Re: Choosing Virtex II Speed grade
107239: 06/08/25: FPGA -> SATA?
107258: 06/08/25: Re: FPGA -> SATA?
108235: 06/09/07: Re: TI TFP410 DVI transmitter help?
Martin Eisenberg:
87899: 05/08/03: Re: System Engineering in the R/D World
Martin Ellis:
80902: 05/03/14: Re: editing waveforms under Linux
82753: 05/04/17: Re: Xilinx tools on Linux
82892: 05/04/19: Re: Xilinx tools on Linux
88925: 05/08/31: Re: Fine grain vs. Coarse Grain Architectures
91314: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91319: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91339: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91344: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
96625: 06/02/07: Re: FPGA ogg Vorbis/Theora player
96908: 06/02/13: Re: Async Processors
Martin Ericson:
62050: 03/10/17: How to get Synplify 7,0 Pro and Xilinx EDK 3,2 work together.
Martin Euredjian:
35328: 01/09/29: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35415: 01/10/03: [OT] Prototyping with BGA's
47761: 02/10/03: Re: USB2 in FPGA?
47934: 02/10/08: Re: USB2 in FPGA?
47957: 02/10/08: Re: USB2 in FPGA?
50427: 02/12/10: VirtexII pin assignments/signal flow
50509: 02/12/11: Re: VirtexII pin assignments/signal flow
50559: 02/12/12: Re: VirtexII pin assignments/signal flow
53804: 03/03/24: Re: synthesizability question
53812: 03/03/24: Re: synthesizability question
54024: 03/03/31: uP interface question
54081: 03/04/02: Re: uP interface question
54082: 03/04/02: Excel and FPGA's
54102: 03/04/02: Re: uP interface question
54104: 03/04/02: Re: Excel and FPGA's
54125: 03/04/03: Re: Excel and FPGA's
54126: 03/04/03: Re: Excel and FPGA's
54137: 03/04/03: Re: uP interface question
55925: 03/05/23: DCM Trouble
55935: 03/05/23: Re: DCM Trouble
55943: 03/05/24: Re: FPGA design: firmware or hardware?
56288: 03/06/02: Re: Virtex 2 evaluation board
56361: 03/06/04: Re: Online courses for FPGA
56566: 03/06/09: Shift registers
56589: 03/06/10: Re: Shift registers
56624: 03/06/10: Re: DVI with a Virtex-II
56626: 03/06/10: Re: Shift registers
56653: 03/06/11: Re: Shift registers
56683: 03/06/11: Re: DVI with a Virtex-II - summary
56692: 03/06/11: Re: DVI with a Virtex-II - summary
56693: 03/06/11: Re: DVI with a Virtex-II
56725: 03/06/12: Re: DVI with a Virtex-II
56858: 03/06/17: Logic removal
57067: 03/06/23: Re: vga controller
57077: 03/06/23: Re: vga controller
57099: 03/06/23: Re: vga controller
57101: 03/06/23: Re: vga controller
57215: 03/06/25: Re: Xilinx Webpack bugs bugs bugs
57293: 03/06/27: Re: why so many problems Xilinx ?
57339: 03/06/27: STARTUP_WAIT
57438: 03/06/30: Re: Asynchronous RESET?
57801: 03/07/07: Pulse stretching
57816: 03/07/07: Re: Pulse stretching
57888: 03/07/09: Re: Pulse stretching
57938: 03/07/10: Re: okay what am I missing??? Please
58031: 03/07/12: Parallel processing (synthesis and simulation)
58290: 03/07/19: Re: Initialize Block RAM
58322: 03/07/21: Re: Instantiating pins on Virtex-II Pro
58373: 03/07/22: Re: asynchronous FIFO
58404: 03/07/22: Re: FPGA Editor
58405: 03/07/22: Re: Instantiating pins on Virtex-II Pro
58406: 03/07/22: Re: FPGA Editor
58423: 03/07/23: Floorplanner "features"
58424: 03/07/23: Re: FPGA Editor
58426: 03/07/23: Re: Floorplanner "features"
58444: 03/07/23: Re: FPGA Editor
58461: 03/07/24: Re: FPGA Editor
58462: 03/07/24: Re: FPGA Editor
58463: 03/07/24: Re: Active Probe
58465: 03/07/24: Multi Pass Place & Route
58485: 03/07/24: Re: FPGA Editor
58491: 03/07/24: Re: FPGA Editor
58493: 03/07/24: Re: FPGA Editor
58517: 03/07/25: Re: FPGA Editor
58518: 03/07/25: Re: Reseting the whole thing
58520: 03/07/25: Re: Pricing question....
58521: 03/07/25: Re: Reseting the whole thing
58523: 03/07/25: Re: Multi Pass Place & Route
58555: 03/07/26: Re: Multi Pass Place & Route
58570: 03/07/27: Re: FPGA Editor
58578: 03/07/27: Re: FPGA Editor
59036: 03/08/06: Re: Patent granted for "system on a chip" framework?
59049: 03/08/07: OT: Offshore engineering
59065: 03/08/07: Re: Patent granted for "system on a chip" framework?
59067: 03/08/07: Re: Offshore engineering
59143: 03/08/10: Re: Xilinx virtex II DCM CLKFX output not working
59153: 03/08/10: Re: Offshore engineering
59173: 03/08/11: Re: FPGA for a Newcomer
59175: 03/08/11: Re: a quick searching problem
59200: 03/08/12: Re: Win2k service packs for running Xilinx tools
59271: 03/08/13: Re: Xilinx DLL driving multiple off chip clocks
59377: 03/08/18: Re: custom memory array implementaion
59415: 03/08/19: Re: "sniffing" signals
59472: 03/08/20: Re: Synchronous FSM
59498: 03/08/20: Re: performance tweaking FPGA designs
59615: 03/08/25: TIG Constraint
59626: 03/08/25: Re: TIG Constraint
59653: 03/08/25: Re: TIG Constraint
59666: 03/08/25: Re: TIG Constraint
59759: 03/08/27: Re: WebPack ISE and Norton Anti-virus
59823: 03/08/29: Re: Max finding
59877: 03/08/30: Re: Shift register
60033: 03/09/04: Re: ISE 5.2 constraint file problem
60212: 03/09/08: Impact error
60228: 03/09/08: Re: Impact error
60246: 03/09/09: Re: Impact error
60938: 03/09/25: Graphics rendering
60985: 03/09/26: Re: Graphics rendering
61016: 03/09/26: Re: Graphics rendering
61019: 03/09/26: Re: Graphics rendering
61041: 03/09/26: Re: Graphics rendering
61042: 03/09/26: Re: Graphics rendering
61049: 03/09/26: Re: Graphics rendering
61065: 03/09/27: Re: Graphics rendering
61066: 03/09/27: Re: Graphics rendering
61071: 03/09/27: Re: Graphics rendering
61072: 03/09/27: Re: Graphics rendering
61083: 03/09/27: Re: Graphics rendering
61107: 03/09/28: ISE: Parallel Processing
61334: 03/10/02: Re: Digesting runs of ones or zeros "well"
61374: 03/10/02: Re: Graphics rendering -- use a BRAM line buffer
61395: 03/10/03: Re: Apology to Martin Erudjian
61396: 03/10/03: Re: Graphics rendering revisited
61401: 03/10/03: Re: Safe state machine design problem
61406: 03/10/03: Re: Safe state machine design problem
61407: 03/10/03: Xilinx courses
61449: 03/10/04: Re: Xilinx courses
61455: 03/10/04: Re: Graphics rendering revisited
61457: 03/10/04: Re: Graphics rendering revisited
61460: 03/10/04: Re: Xilinx courses
61461: 03/10/04: Re: Xilinx courses
61462: 03/10/04: Re: Interesting article about FPGAs
61465: 03/10/04: Re: newbie to FPGA
61470: 03/10/05: Re: Interesting article about FPGAs
61472: 03/10/05: Re: Interesting article about FPGAs
61480: 03/10/05: Re: Interesting article about FPGAs
61487: 03/10/05: Re: Interesting article about FPGAs
61489: 03/10/06: Re: Interesting article about FPGAs
61548: 03/10/06: Re: Xilinx courses
61555: 03/10/06: Re: Xilinx courses
61560: 03/10/07: Re: Xilinx courses
61562: 03/10/07: RLOC specification
61570: 03/10/07: Re: RLOC specification
61573: 03/10/07: More RPM / RLOC fun
61577: 03/10/07: Re: Xilinx courses
61611: 03/10/07: Re: More RPM / RLOC fun
61613: 03/10/07: Re: More RPM / RLOC fun
61617: 03/10/07: Re: More RPM / RLOC fun
61619: 03/10/07: Re: Avnet Xilinx Virtex II Development Board - getting started
61631: 03/10/08: Re: Avnet Xilinx Virtex II Development Board - getting started
61634: 03/10/08: Re: Visualizing VHDL
61646: 03/10/08: Re: More RPM / RLOC fun
61675: 03/10/08: Re: Visualizing VHDL
61687: 03/10/09: Re: Visualizing VHDL
61689: 03/10/09: Floorplanning, Routing, FPGA Editor
61690: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61704: 03/10/09: Where is the logic?
61730: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61731: 03/10/09: Re: Where is the logic?
61732: 03/10/09: Re: Where is the logic?
61744: 03/10/09: Re: Where is the logic?
61746: 03/10/09: Re: Where is the logic?
61749: 03/10/10: Re: Where is the logic?
61764: 03/10/10: Re: Floorplanning, Routing, FPGA Editor
61789: 03/10/10: Re: Graphics rendering revisited
61798: 03/10/11: Re: FPGA Editor: Macro(Xilinx)
61812: 03/10/13: ISE6.1i Floorplanner
61813: 03/10/13: ISE6.1i RPM's, Multipliers and grids
61840: 03/10/14: Re: ISE6.1i RPM's, Multipliers and grids
61880: 03/10/14: Re: ISE6.1i RPM's, Multipliers and grids
62008: 03/10/16: Re: explain the vhdl code
62076: 03/10/17: Re: LUT and latch in the FPGA
62187: 03/10/21: Job postings
62188: 03/10/21: Re: please help, modelsim does not simulate
62236: 03/10/22: Re: Beginners advice for selecting an environment for FPGA design
62386: 03/10/28: Re: How can I lock design with ISE 5.2?
62440: 03/10/29: Re: How to protect fpga based design against cloning?
62441: 03/10/29: Re: Virtex-II DCM frequency synthesizer
62452: 03/10/30: Re: Questions that question????
62456: 03/10/30: Re: Xilinx Spartan3: Price
62457: 03/10/30: Re: Some FPGA questions
62565: 03/11/01: Re: Some FPGA questions
62589: 03/11/02: Re: Power-On-Reset from a xilinx
62594: 03/11/03: Re: Vendor supplied symbol/part models?
62684: 03/11/04: Re: DCM recover after interruption of input clock
62722: 03/11/05: Re: Virtex II DCM & ZBT SRAM
62770: 03/11/07: Re: Virtex II DCM & ZBT SRAM
62846: 03/11/10: Re: FPGAs and DRAM bandwidth
63028: 03/11/13: Re: Layout examples
63029: 03/11/13: Re: Transforming vector position to binary value
63036: 03/11/13: Re: Layout examples
63037: 03/11/13: Re: Transforming vector position to binary value
63061: 03/11/13: Re: Transforming vector position to binary value
63066: 03/11/13: Re: Transforming vector position to binary value
63092: 03/11/14: Re: Layout examples
63267: 03/11/19: Re: Transforming vector position to binary value
63346: 03/11/20: Re: Transforming vector position to binary value
63347: 03/11/20: Re: SDRAM-Controller XAPP134
63348: 03/11/20: Re: Xilinx UCF file conditional includes ?
63561: 03/11/25: Re: area constraints
63599: 03/11/26: Re: area constraints
63658: 03/11/27: Re: area constraints
63659: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63663: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63681: 03/11/28: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63687: 03/11/29: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63750: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
63854: 03/12/05: Block RAM simulation VII
63866: 03/12/06: Re: Block RAM simulation VII
63867: 03/12/06: Re: Floorplanning techniques
63874: 03/12/06: Re: Block RAM simulation VII
63876: 03/12/07: Re: Block RAM simulation VII
63887: 03/12/07: Re: Block RAM simulation VII
63890: 03/12/08: Re: Block RAM simulation VII
64030: 03/12/12: Re: Latches inferred ?
64042: 03/12/13: Re: Question about filters and verilog etc..
64218: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64231: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64240: 03/12/22: Re: FIR Filter cores for Virtex-][
64241: 03/12/22: Hyperthreading vs. Dual proc
64267: 03/12/23: Re: Hyperthreading vs. Dual proc
64268: 03/12/23: Re: Net name convention for Xilinx UCF files.
64276: 03/12/23: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
64296: 03/12/25: Re: How to get first bit '0' position in certain register?
64599: 04/01/08: Large/Fast static RAM
64604: 04/01/08: Re: Large/Fast static RAM
64638: 04/01/09: Re: Large/Fast static RAM
64650: 04/01/10: Re: Large/Fast static RAM
64687: 04/01/11: Re: PCB for FG456: layers
64746: 04/01/13: Re: Power plane assignments in a Xilinx PCI card
64824: 04/01/14: Faster than a speeding bullet...
64826: 04/01/14: XC2V1000-5FG456C
64827: 04/01/14: Re: XC2V1000-5FG456C
64835: 04/01/15: Re: Faster than a speeding bullet...
64883: 04/01/15: Re: yo, Mr. FPGA Engineer
64886: 04/01/15: Re: Faster than a speeding bullet...
65004: 04/01/18: Anisotropic filter
65112: 04/01/20: Re: SDRAM Controller timing problem
65206: 04/01/22: Re: OT: liability insurance
65427: 04/01/29: Re: Flip-Chip Package Substrate Solder Issue
65990: 04/02/11: Re: Do Xilinx Fix Their Prices?
66212: 04/02/14: Re: Pricing, 101
66236: 04/02/15: Re: DCM Jitter?
66268: 04/02/16: Polyphase filter
66290: 04/02/16: Re: Manual Partitioning to Multiple FPGAs
66304: 04/02/17: Re: DCM Jitter?
66431: 04/02/19: Re: Can FPGA bootstrap itself?
66436: 04/02/19: Re: Dual-stack (Forth) processors
66454: 04/02/20: Re: Dual-stack (Forth) processors
66456: 04/02/20: Re: Dual-stack (Forth) processors
66463: 04/02/20: Re: Dual-stack (Forth) processors
66464: 04/02/20: Re: Dual-stack (Forth) processors
66479: 04/02/20: Re: Dual-stack (Forth) processors
66523: 04/02/21: Re: Dual-stack (Forth) processors
66539: 04/02/21: Re: Dual-stack (Forth) processors
66545: 04/02/22: Re: Dual-stack (Forth) processors
66546: 04/02/22: Re: Can FPGA bootstrap itself?
66564: 04/02/23: Re: Dual-stack (Forth) processors
66676: 04/02/25: Re: Dual-stack (Forth) processors
66677: 04/02/25: Re: Why warnings: "Input <xyz> never used???"
66710: 04/02/25: Re: Dual-stack (Forth) processors
66831: 04/02/27: Re: Dual-stack (Forth) processors
66901: 04/02/29: Re: Xilinx iMPACT error: "Done did not go high"
66902: 04/02/29: Re: Polyphase filter
67163: 04/03/07: Re: Polyphase filter
67990: 04/03/24: Re: How many times can I burn an FPGA?
68041: 04/03/25: Re: How many times can I burn an FPGA?
72041: 04/08/06: Acceleration
72062: 04/08/06: Re: Acceleration
72121: 04/08/09: Carbon nanotubes
72151: 04/08/10: Re: Carbon nanotubes
72711: 04/08/30: Re: The Effect of Pin Assginment
72804: 04/09/02: Re: The Effect of Pin Assginment
Martin Filteau:
16536: 99/05/26: Re: floating points to fixed points on a FPGA
24560: 00/08/14: Re: CLKDLL for Virtex PCI?
27507: 00/11/25: Re: Virtex-PCI-Boards
Martin Fischer:
35383: 01/10/02: Which Cable for the Xilinx 3064XL ?
35420: 01/10/04: Re: Which Cable for the Xilinx 3064XL ?
35629: 01/10/12: PWM Signal in VHDL ?
37703: 01/12/19: How can I check my PLD program ?
37712: 01/12/19: Boundary Scn, Bist
38411: 02/01/14: Falling edge in PLD
38459: 02/01/15: Re: Falling edge in PLD
38838: 02/01/26: Peaks in smaller PLDs
38906: 02/01/28: Re: Peaks in smaller PLDs
Martin Forest:
32123: 01/06/14: Xilinx Virtex 2: Configurations problems
Martin Forsberg Lie:
52849: 03/02/24: Re: FPGA's at High Temperatures
52853: 03/02/24: Re: LVDS LCD
Martin Freeman:
25: 94/07/29: HOT CHIPS SYMPOSIUM VI, AUGUST 14-16, STANFORD UNIVERSITY
Martin Gagnon:
107205: 06/08/25: Re: Style of coding complex logic (particularly state machines)
Martin Geisse:
108691: 06/09/15: problems with IOSTANDARD
108808: 06/09/17: Re: problems with IOSTANDARD
108815: 06/09/17: Re: problems with IOSTANDARD
martin griffith:
18720: 99/11/09: Re: Sample Rate Conversion.
18798: 99/11/17: Re: Q: implementing TCP/IP on PLD
107537: 06/08/30: Re: September training?
107648: 06/08/30: Re: Performance Appraisals
107649: 06/08/30: Re: Performance Appraisals
107745: 06/09/01: Re: Performance Appraisals
107980: 06/09/03: Re: Please help me with (insert task here)
108056: 06/09/04: Re: Please help me with (insert task here)
108063: 06/09/05: Re: Please help me with (insert task here)
Martin Guibert:
17265: 99/07/15: Re: Dongle problems.
45322: 02/07/18: How's the FPGA design job market near you??
45331: 02/07/19: Re: How's the FPGA design job market near you??
45361: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
46627: 02/09/04: Re: Virtex-2 BRAM
49914: 02/11/25: Q about operating temperatures
Martin Hansel:
95963: 06/01/27: LogiBlox on Foundation 4.1 Error
Martin Heimlicher:
23167: 00/06/16: Re: PCI for a fpga board
27891: 00/12/13: How do I specify clock skew in the Altera Quartus tool ?
27892: 00/12/13: Multicycle timing requirements in Altera Quartus
27893: 00/12/13: Is it necessary to synchronize the reset signal in an FPGA ?
27970: 00/12/18: Re: async interface
Martin Hoffensetz:
7827: 97/10/20: Importing FLEX10k into Cadence
MARTIN jm:
63677: 03/11/28: Re: problem with RS485 or RS232
Martin Kellermann:
48059: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
54396: 03/04/10: Re: Modular Design: XAPP404
55378: 03/05/06: Re: Xilinx VirtexII Pro Rocket-IO
55437: 03/05/08: Re: Xilinx VirtexII Pro Rocket-IO--Power
58381: 03/07/22: Re: help needed..... ERROR:MapLib:30 - Bad format for LOC constraint AB12 on rx.
59432: 03/08/19: Re: Xilinx Parallel Cable III Schematic
63369: 03/11/20: Re: avoiding GCLK
64066: 03/12/15: Re: Extracting timing from a demo board (V2MB1000)
64753: 04/01/13: Re: V2Pro Rocket IO Primitive- Parameter and Port Settings
66682: 04/02/25: Re: Experience with Simulating RocketIO in Modelsim
66923: 04/03/01: Re: Xilinx iMPACT error: "Done did not go high"
67255: 04/03/09: Re: Reg..How to use BUFGMUX in Spartan 2 family
76033: 04/11/23: Re: Help! What is this card?
77689: 05/01/14: Re: Xilinx FPGA editor
martin lytz:
15910: 99/04/20: Re: What's the best way to learn about fpga's?
17263: 99/07/15: Re: Easy money !!! and it's REAL
Martin Maierhofer:
7188: 97/08/12: Job announcement?
Martin Mason:
1354: 95/06/06: AT17C128 and AT17C65 E2PROM PARTS
1394: 95/06/13: Re: 17C256 EEPROMs from Atmel.
1948: 95/09/22: Reprogrammable 17CXXX devices.
4108: 96/09/11: Re: 256K EEPROM
4473: 96/11/02: Re: Altera Configuration EPROM Equivalents
5263: 97/02/02: Re: Altera BitBlaster
6408: 97/05/22: logicores and parameterized macros
6584: 97/06/03: Re: In circuit programming of flash with Xilinx devices??
6585: 97/06/03: Re: New Reconfigurable Computing newsgroup?
6666: 97/06/10: Re: ATMEL 17Cxxx ISP function
7216: 97/08/15: Re: Price of Serial EEPROM is Outrageous
7524: 97/09/18: Re: Atmel 17256 serial config EEPROMs
7589: 97/09/24: Re: ISP Serial EEPROM for Altera FLEX10k
7767: 97/10/13: Atmel's NEW FPGA.
7765: 97/10/13: New AT40K FPGA Arch.
7945: 97/11/01: Re: Complex Multiplier
8429: 97/12/14: Re: combinational multipliers
8605: 98/01/12: Re: Xilinx Configuration Problem
8606: 98/01/12: Re: serial conf. PROMS
9022: 98/02/14: Re: altera max7000s and JTAG ISP
9135: 98/02/23: Re: Atmel SPROMs for Xilinx
9395: 98/03/09: Re: Problems with Atmel IDS 5.0 installation
9665: 98/03/29: Re: Dual port
10006: 98/04/21: Re: Could you help me save CLB's?
martin mason:
744: 95/02/22: Re: PLA? PAL? PLD? GAL?
839: 95/03/10: Re:FPGA bit serial multipliers
1204: 95/05/13: Re: Overheating (was Re: Compression algo's for FPGA's)
1676: 95/08/15: Fwd: Re: Xilinx PROMs
Martin Mason 408 436 4178:
214: 94/09/23: Reconfigurable FPGAs
447: 94/11/18: Encryption and reconfigurable FPGAs
Martin Maurer:
16864: 99/06/15: 3 Questions with XILINX CPLD
17127: 99/07/01: ABL-Problem (XILINX CPLD)
34710: 01/09/04: Searching a few pieces of Lattice ispLSI 1016E
67857: 04/03/21: XC95108: Problem with state machine reset in ABEL
67859: 04/03/21: XC95108: Problem with state machine reset in ABEL -> now full posting...
68782: 04/04/18: UART with FIFO -> CPLD / FPGA / ?
69031: 04/04/26: Xilinx CPLD - FSM - one hot - lost token...
69377: 04/05/09: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69623: 04/05/16: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
69854: 04/05/22: Re: FPGA Board with Flash Memory
70264: 04/06/11: Avoid action on very short peak on input signal (Xilinx Spartan 2)
72311: 04/08/14: Re: Free Spartan3 download program for GNU/Linux
Martin Melzer:
32786: 01/07/09: Metastability constants for Altera FPGAs?
Martin Meserve:
12205: 98/10/05: Re: Verilog Simulators
Martin Muggli:
48593: 02/10/21: Re: Using MXE II starter as a restricted user
Martin Neilan:
9692: 98/03/31: Digital PLL's or Manual Synching?
Martin Radetzki:
1556: 95/07/14: Re: Synopsys timing simulation of two XC3000 chips
1994: 95/09/29: Altera Sim. with Leapfrog
3354: 96/05/18: Re: is high input number mutliplxer inferrable?
3429: 96/05/29: Re: more about optimal synthesis of FSM
Martin Rice:
33084: 01/07/17: Coolrunner: availability
33893: 01/08/07: Re: Newbie Question: LPT245 in CoolRunner?
34165: 01/08/15: Re: Building a clock out of a PLD
34202: 01/08/16: Re: Xilinx WebPack .UCF file
35414: 01/10/03: What's a process?
37995: 01/12/29: Re: Look for FPGA Starterkit
38337: 02/01/11: Re: latch vs. register
Martin Riddle:
77817: 05/01/18: Re: Quartus II Command Line and Project Files
78109: 05/01/25: Re: Scripted Xilinx flow with free Webpack tools?
79548: 05/02/21: Re: does anyone have a c compiler for the picoblaze
81681: 05/03/30: Re: Custom compilation step in Quartus
83341: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
Martin Roenne:
34428: 01/08/24: Re: SmartMedia
Martin Rosner:
12344: 98/10/09: Re: FCCM 99?
Martin Ryba:
66208: 04/02/14: Re: Sine Wave Generation
Martin Sauer:
40726: 02/03/14: Difference between Virtex-II(E) und Virtex-E
40732: 02/03/14: Xilinix FPGA width 5V IO
40908: 02/03/18: Xilinx Virtex II in comparsion with Altera Apex 20KC
44743: 02/06/28: Programming a Xilinx CPDL with a Microcontroller
52610: 03/02/16: VITAL_primitives Library in Xilinx WebPack
56655: 03/06/11: Xilinx CPLD programming with microcontroller
56664: 03/06/11: Re: Xilinx CPLD programming with microcontroller
56882: 03/06/18: Fuse Map for Xilinx XPLA3
56886: 03/06/18: User Electronic Signature in Xilinx XPLA3
63450: 03/11/21: Xilinx WebPack and Linux/WINE
124259: 07/09/17: ECP2/M und Serdes
136647: 08/11/28: Dithering video signals
136662: 08/11/29: Re: Dithering video signals
Martin Schoeberl:
26082: 00/10/03: JVM processor
31452: 01/05/25: Re: FPGA
31453: 01/05/25: Re: Need A little prog?
31532: 01/05/29: Re: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
33039: 01/07/16: Re: Byteblasting an ACEX in running system?
33088: 01/07/17: Re: processor core
33144: 01/07/18: Xilinx WebPACK - ROM
33164: 01/07/18: Re: Xilinx WebPACK - ROM
33165: 01/07/18: Re: Xilinx WebPACK - ROM
33314: 01/07/23: Re: free VHDL and/or Verilog tools?
33411: 01/07/25: Re: FPGA Express or Spectrum?
33586: 01/07/31: RAM - VHDL - Altera,...
33591: 01/07/31: Re: RAM... got it
33628: 01/08/01: Re: RAM - VHDL - Altera,...
33674: 01/08/02: Re: RAM - VHDL - Altera,...
33746: 01/08/03: Re: Spartan II and asynchronous memory interface
38835: 02/01/26: Re: Pin assignment on ACEX1K
41180: 02/03/22: Re: Clock termination affecting JTAG interface
45574: 02/07/27: Re: can 555 be used as clock input to cplds
45575: 02/07/27: Re: Making my own software
48896: 02/10/26: Re: Crystal oscillator question
48897: 02/10/26: Re: slow slew rate signal...
49034: 02/10/30: Ann: Altera Prototyping Board
49382: 02/11/11: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49489: 02/11/13: Re: Tristate buffers + leonardo Spectrum
49491: 02/11/13: Re: EPP slave interface
50068: 02/11/30: Re: picoJava & the other of Eclipse Sun
50335: 02/12/09: Ann.: Ethernet, IO expansion for protoyping board
50384: 02/12/10: Re: Tiny Forth Processors
50403: 02/12/10: Re: Tiny Forth Processors
50404: 02/12/10: Re: Tiny Forth Processors
50405: 02/12/10: Re: State of the PCB world
50435: 02/12/10: Re: Tiny Forth Processors
50436: 02/12/10: Re: Tiny Forth Processors
50462: 02/12/11: Re: Tiny Forth Processors
50463: 02/12/11: Re: Tiny Forth Processors
50510: 02/12/11: Re: Tiny Forth Processors
50511: 02/12/11: Re: Tiny Forth Processors
50632: 02/12/14: Quartus does not start on Windows ME
50723: 02/12/18: Re: A/D converter in FPGA
50897: 02/12/22: Re: Programming ACEX1K from FlashEprom
50921: 02/12/23: Pin definition in Quartus
52694: 03/02/19: Cyclone EP1C6/EP1C12 pinout
52798: 03/02/22: Re: Should I choose Xilink or Altera for a small project
52928: 03/02/26: Re: configuring xilinx fpga with nand flash
52943: 03/02/26: Re: configuring xilinx fpga with nand flash
52955: 03/02/27: Re: configuring xilinx fpga with nand flash
53237: 03/03/07: Cyclone power up problem
53239: 03/03/07: Re: Cyclone power up problem
53336: 03/03/11: Re: Cyclone power up problem
53383: 03/03/12: Re: Cyclone power up problem
53398: 03/03/12: Re: Cyclone power up problem
53399: 03/03/12: Re: Cyclone power up problem
53403: 03/03/12: Re: Buying memory for FPGA...
53468: 03/03/13: Re: Cyclone power up problem
53469: 03/03/14: Re: Cyclone power up problem
53512: 03/03/14: Cyclone power up problem - Summery
53549: 03/03/16: Re: Cyclone power up problem - Summery
53550: 03/03/16: Re: Cyclone power up problem - Summery
53553: 03/03/16: Re: Cyclone power up problem - Summery
53567: 03/03/16: Re: FPGA dev boards
53574: 03/03/17: Re: FPGA dev boards
53703: 03/03/20: Re: Altera ACEX 1K
54149: 03/04/03: Re: Cyclone power up problem - Summery
54163: 03/04/03: Re: Altera Cyclone
54182: 03/04/04: Re: Cyclone power up problem - Summery
54186: 03/04/04: Re: Altera Cyclone
54234: 03/04/05: Re: Cyclone power up problem - 'Engineerus Emptor'
54400: 03/04/10: Re: Cheap(er) FPGA configuration?
54401: 03/04/10: Re: Cheap(er) FPGA configuration?
54460: 03/04/11: Re: Cheap(er) FPGA configuration?
54462: 03/04/11: Re: Ethernet MAC (was Re: Cheap(er) FPGA configuration?)
54465: 03/04/11: Re: Altera not supplying Leonardo any more
55018: 03/04/24: [ANN] Cyclone FPGA board
55142: 03/04/28: Re: Use of bidir ports on Flex 10k.
55326: 03/05/04: Output switching time
55350: 03/05/05: Re: Output switching time
55356: 03/05/05: Re: Output switching time
55370: 03/05/06: Re: Output switching time
55371: 03/05/06: Re: Output switching time
55374: 03/05/06: Re: Ibis for Cyclone?
55388: 03/05/06: Re: Ibis for Cyclone?
55477: 03/05/09: Re: Info about development kit
55728: 03/05/17: Re: Output switching time
55729: 03/05/17: Re: Output switching time
55770: 03/05/19: Re: Output switching time
56999: 03/06/20: Quartus bug or wrong VHDL?
57010: 03/06/20: Re: Quartus bug or wrong VHDL?
57035: 03/06/21: Re: Quartus bug or wrong VHDL?
57037: 03/06/21: Quartus / Leonardo frustration
58255: 03/07/18: Re: Altera ByteBlaster Standalone Programming Utility
58256: 03/07/18: Re: Graduation Day: My first 4-layer PCB
58775: 03/08/01: Re: Size does matter
58846: 03/08/02: Re: Size does matter
58897: 03/08/04: Re: opencores.org - Question on project licensing?
58908: 03/08/04: Re: opencores.org - Question on project licensing?
59253: 03/08/13: Re: Size does matter
59384: 03/08/18: Re: Never used FPGA board for sale
59396: 03/08/18: Re: Never used FPGA board for sale
59425: 03/08/19: Re: Never used FPGA board for sale
59447: 03/08/19: Re: serial communication between pc and altera fpga
59838: 03/08/29: Re: pricing, cyclone or spartan
59852: 03/08/29: Re: pricing, cyclone or spartan
59857: 03/08/29: Re: pricing, cyclone or spartan
60231: 03/09/08: Re: Sending and receiving Ethernet traffic
60245: 03/09/09: Re: Sending and receiving Ethernet traffic
62103: 03/10/19: Re: Picojava FPGA and Development board
62480: 03/10/30: Re: Some FPGA questions
63773: 03/12/03: Re: getting started in FPGA
66298: 04/02/16: Re: Dual-stack (Forth) processors
66391: 04/02/18: Re: Dual-stack (Forth) processors
66426: 04/02/19: Re: Dual-stack (Forth) processors
68228: 04/03/30: Re: Quartus removes Tristate Buffer
68546: 04/04/07: Re: Cyclone and ByteBlasterMV?
68594: 04/04/08: Re: Min. Reqmts For Altera Nios -- i.e Will it work on Parallax Cyclone FastPack?
68715: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
68720: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
68721: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
69248: 04/05/03: [ANN] Altera Cyclone EP1C12 FPGA Board
69370: 04/05/08: Re: Which board to buy? Status of open source tools?
71780: 04/07/30: Re: Suggestions for programming flash RAM for SoC via FPGA
72069: 04/08/07: LEGO mindstorms and FPGA
72086: 04/08/08: Re: LEGO mindstorms and FPGA
72092: 04/08/08: Re: LEGO mindstorms and FPGA
72162: 04/08/10: Re: LEGO mindstorms and FPGA
72166: 04/08/10: Re: LEGO mindstorms and FPGA
72334: 04/08/15: Re: LEGO mindstroms and FPGA
72410: 04/08/18: Re: nand flash memory chips
73946: 04/10/01: JOP on Spartan-3 Starter Kit
73976: 04/10/01: Re: JOP on Spartan-3 Starter Kit
73981: 04/10/01: Re: Capabilities of Spartan-3 Starter Kit (XC3S200).
74007: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74018: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74023: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74024: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74025: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74027: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74030: 04/10/02: Re: Capabilities of Spartan-3 Starter Kit (XC3S200).
74032: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74036: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74039: 04/10/02: Re: NV on-chip memory?
72987: 04/09/09: AD: ACEX 1K50 FPGA board clearance sale
72989: 04/09/09: Re: ACEX 1K50 FPGA board clearance sale
72990: 04/09/09: Re: AD: ACEX 1K50 FPGA board clearance sale
73569: 04/09/24: Re: spartan-3 sram
74956: 04/10/22: Re: interfacing a PC based program with a FPGA
74958: 04/10/22: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74965: 04/10/22: Re: Spartan 3 - Internal busses & tristate ?
74060: 04/10/03: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74061: 04/10/03: Re: NV on-chip memory?
74100: 04/10/04: Re: NV on-chip memory?
74102: 04/10/04: Re: Differences between Xilinx ISE Foundation and WebPACK.
74108: 04/10/04: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74164: 04/10/05: Re: Features of Xilinx ISE WebPACK & Altera's Quartus II.
74165: 04/10/05: Re: JOP on Spartan-3 Starter Kit
74217: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74264: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74311: 04/10/07: add/sub 2:1 mux and ena in a single LE (Cyclone)
74331: 04/10/08: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74332: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74370: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74373: 04/10/09: Re: PLL lock usage into Altera Stratix devices
74374: 04/10/09: Re: PLL lock usage into Altera Stratix devices
74378: 04/10/09: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74401: 04/10/10: Re: JOP on Spartan-3 Starter Kit
74403: 04/10/10: Re: JOP on Spartan-3 Starter Kit
74444: 04/10/11: Re: CAche memory
74529: 04/10/13: Re: EP1C12 or XC3S400?
74714: 04/10/17: Re: JOP on Spartan-3 Starter Kit
74719: 04/10/17: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
75829: 04/11/16: Re: Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
75953: 04/11/20: Re: FPGA development board
76007: 04/11/22: JOP on Trenz Retrocomputiong Board
78729: 05/02/07: Quartus project files
78734: 05/02/07: Cyclone configuration device
78743: 05/02/07: Re: Cyclone configuration device
78747: 05/02/07: Re: Cyclone configuration device
78750: 05/02/07: Re: Cyclone configuration device
78751: 05/02/07: Re: Cyclone configuration device
78794: 05/02/08: Re: Quartus project files
78795: 05/02/08: SimmStick FPGA module
78801: 05/02/08: Re: SimmStick FPGA module
78825: 05/02/08: Re: SimmStick FPGA module
78827: 05/02/08: Re: SimmStick FPGA module
78829: 05/02/08: Re: SimmStick FPGA module
78862: 05/02/09: Re: SimmStick FPGA module
78864: 05/02/09: Re: quartus "make clean" ?
78921: 05/02/10: Re: SimmStick FPGA module
78965: 05/02/10: Re: Writing IP-Cores while sleeping ;)
79128: 05/02/14: Re: SimmStick FPGA module
79149: 05/02/15: Re: SimmStick FPGA module
79151: 05/02/15: Re: SimmStick FPGA module
79533: 05/02/20: JOP VHDL simulation
79575: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79606: 05/02/21: Re: JOP VHDL simulation
79609: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79639: 05/02/22: SD Card and FPGA
79641: 05/02/22: Re: Tristate Discussion
79665: 05/02/22: Re: SD Card and FPGA
79667: 05/02/22: Re: FPGA board with best cost/CLB ratio?
79707: 05/02/23: Re: Tristate Discussion
80093: 05/03/01: Re: block adder for Altera!
83457: 05/04/30: Re: Flexray ip core
84796: 05/05/27: Re: ISE 7.1 small advice about project files (.ISE extension)
85426: 05/06/09: Re: Spartan 3 Starter kit group formed
85518: 05/06/10: Re: Microblaze 4.0 with uClinux is ok or not?
86494: 05/06/29: Re: Chess & FPGAs
86612: 05/06/30: Direct audio output from FPGA pins
86628: 05/07/01: Re: Direct audio output from FPGA pins
87525: 05/07/25: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
88816: 05/08/29: Re: digilent spartan 3 kit example project
88820: 05/08/29: JTAG conifguration via USB
91899: 05/11/16: Quartus crash
92066: 05/11/21: Re: Quartus crash
92202: 05/11/23: Wishbone comments
92204: 05/11/24: Re: Design Implementation in Xilinx XST
92230: 05/11/24: Memory in VHDL
92233: 05/11/24: Re: Memory in VHDL
92243: 05/11/24: Re: Memory in VHDL
92244: 05/11/24: Re: Memory in VHDL
92249: 05/11/24: Re: Memory in VHDL
92257: 05/11/24: Re: Wishbone comments
92326: 05/11/28: Re: Wishbone comments
92327: 05/11/28: Re: Memory in VHDL
92354: 05/11/28: Re: instruction counts and cache hits/misses on FPGA
92540: 05/12/01: Quartus db issue
92549: 05/12/01: Re: Quartus db issue
93018: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93022: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93639: 05/12/27: Re: Download to board with RS232
93644: 05/12/27: Re: Download to board with RS232
93738: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93744: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93747: 05/12/29: Actel Fusion
93756: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
96095: 06/01/30: Floating-Point Unit (for JOP)
96343: 06/02/02: Re: AC97 Controller
96426: 06/02/03: Quartus programmer problem
97727: 06/02/27: Re: miniuart
98529: 06/03/12: LEON processor core
98575: 06/03/13: Re: LEON processor core
105952: 06/08/03: Cyclone I & II memory fmax
105984: 06/08/04: Re: Cyclone I & II memory fmax
106007: 06/08/04: Re: Cyclone I & II memory fmax
106013: 06/08/05: Re: How to implement large ROM's from binary sources?
106033: 06/08/06: Re: Cyclone I & II memory fmax
106053: 06/08/07: Re: How do I treat "default" case which is useless?
106288: 06/08/10: Altera SOPC ModelSim question
106334: 06/08/12: JOP as SOPC component
106350: 06/08/12: Re: JOP as SOPC component
106355: 06/08/12: Re: JOP as SOPC component
106382: 06/08/12: Re: JOP as SOPC component
106389: 06/08/12: Re: JOP as SOPC component
106391: 06/08/12: Re: JOP as SOPC component
106397: 06/08/12: Re: JOP as SOPC component
106400: 06/08/12: Re: JOP as SOPC component
106452: 06/08/13: Re: JOP as SOPC component
106454: 06/08/13: Re: JOP as SOPC component
106458: 06/08/13: Re: JOP as SOPC component
106460: 06/08/13: Re: JOP as SOPC component
106462: 06/08/14: Re: JOP as SOPC component
106466: 06/08/14: Re: JOP as SOPC component
106467: 06/08/14: Re: JOP as SOPC component
106503: 06/08/14: Re: JOP as SOPC component
106506: 06/08/14: Re: JOP as SOPC component
106528: 06/08/15: Re: JOP as SOPC component
106619: 06/08/16: Re: Alternative for Mentor''s HDL Designer
106630: 06/08/16: Re: Alternative for Mentor''s HDL Designer
106672: 06/08/17: Re: Quartus and source control (continued)
106743: 06/08/18: Re: JOP as SOPC component
106891: 06/08/22: Re: JOP as SOPC component
106892: 06/08/22: Re: CPU design
106894: 06/08/22: Re: CPU design
106994: 06/08/23: Re: CPU design
106997: 06/08/23: Re: JOP as SOPC component
107002: 06/08/23: Re: JOP as SOPC component
107124: 06/08/24: Re: JOP as SOPC component
107128: 06/08/24: Re: JOP as SOPC component
107175: 06/08/25: Re: JOP as SOPC component
107366: 06/08/27: Re: JOP as SOPC component
107398: 06/08/28: Re: JOP as SOPC component
107550: 06/08/30: Re: JOP as SOPC component
119358: 07/05/17: FPGA and LEGO Mindstroms
129457: 08/02/25: The Java processor JOP is now GPL
138798: 09/03/11: What happens at opencores.org?
138895: 09/03/14: Re: What happens at opencores.org?
138896: 09/03/14: Re: What happens at opencores.org?
Martin Studach:
27285: 00/11/17: Re: FPGA Pin Nunber
Martin Thompson:
26918: 00/11/03: ACEX1K vs FLEX10K
34750: 01/09/06: Re: LPM_FIFO_DC
34751: 01/09/06: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34966: 01/09/17: Re: Altera 10K shortage
35214: 01/09/26: Re: Handle C
35216: 01/09/26: Re: WANTED source code of CPLD on TI 5402 DSK
35224: 01/09/26: Pentium 3 vs Pentium 4 benchmarks
35253: 01/09/27: Re: Pentium 3 vs Pentium 4 benchmarks
35511: 01/10/09: Re: ROM based FSMs
35536: 01/10/10: Re: anyone know of SDRDRAM controller for free?
35639: 01/10/12: Re: High level synthesis will never work well :)
35646: 01/10/12: Re: Use of Global in Altera FLEX 10KA
35740: 01/10/16: Re: open-drain bidirs in xilinx or altera
35805: 01/10/18: Re: open-drain bidirs in xilinx or altera
35806: 01/10/18: Re: SDRAM Controller for Xilinx Virtex
35900: 01/10/23: Re: Problems with writing into text file
36088: 01/10/29: Re: Digital image input for simulation on Altera FPGA
36548: 01/11/12: Re: Decoupling capacitors on Virtex II
36671: 01/11/15: Re: Incrementing counter from state-machine
36681: 01/11/15: Re: Decoupling capacitors on Virtex II
36864: 01/11/22: Re: Decoupling capacitors on Virtex II
36889: 01/11/23: Re: Decoupling capacitors on Virtex II
36921: 01/11/26: Re: Decoupling capacitors on Virtex II
38792: 02/01/25: Re: Intel vs. AMD
39025: 02/01/30: Re: Flex10KA vs MAX7000S
39318: 02/02/06: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39319: 02/02/06: Re: Making Altera development quicker
39353: 02/02/07: Re: Altera MAX7000 PLD's
39736: 02/02/18: Re: Making Altera development quicker
40019: 02/02/25: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
40062: 02/02/26: Re: RAM question
40129: 02/02/28: Re: Beginner Altera Questions
40130: 02/02/28: Re: Simulation Question
40169: 02/03/01: Re: Beginner Altera Questions
40382: 02/03/06: V-II DCM options
40401: 02/03/06: Re: V-II DCM options
41124: 02/03/21: Re: more questions
41284: 02/03/25: Re: High speed clock routing
41333: 02/03/26: Re: High speed clock routing
41797: 02/04/08: Variable phase-shift
41882: 02/04/10: Re: differences betw. EPF10K30E and EP1K30?
41940: 02/04/11: Attributes *and* generics!?
41983: 02/04/12: Re: Attributes *and* generics!?
42068: 02/04/15: Re: Attributes *and* generics!?
42069: 02/04/15: Re: Attributes *and* generics!?
42920: 02/05/07: Re: Availability of XC2S150E-6FG456I
43640: 02/05/28: Re: Strange error message from MaxPlus II !
44224: 02/06/14: Re: Power supply caps on PCB
44904: 02/07/05: Re: Type conversion - adding integer to logic_vector
44906: 02/07/05: Re: How to improve this VHDL code ?
44948: 02/07/08: Re: Type conversion - adding integer to logic_vector
46664: 02/09/05: Re: Hardware Code Morphing?
47625: 02/10/01: Re: design multiplier
47738: 02/10/03: Re: C\C++ to VHDL Converter
47791: 02/10/04: Re: C\C++ to VHDL Converter
47792: 02/10/04: Re: C\C++ to VHDL Converter
48116: 02/10/11: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48205: 02/10/14: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48330: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48414: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
49373: 02/11/11: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49428: 02/11/12: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
50330: 02/12/09: Re: Warnings in FPGA express
50386: 02/12/10: Re: Warnings in FPGA express
50387: 02/12/10: Re: How to assign pins in VHDL?
51833: 03/01/23: Re: Virtex II: noise on Vcco causing loss of DCM lock
51941: 03/01/27: Somewhat OT - TECO, was Re: VHDL or Verilog?
52289: 03/02/06: Re: JTAG from CAN
52879: 03/02/25: Re: LVDS LCD
53879: 03/03/26: Re: Problems with Altera Max Plus II software
53951: 03/03/28: Re: DSP-FPGA interface
54469: 03/04/11: Re: Really long vectors in VHDL
56132: 03/05/29: Re: JTAG madness
56611: 03/06/10: DVI with a Virtex-II
56662: 03/06/11: Re: DVI with a Virtex-II - summary
56716: 03/06/12: Re: DVI with a Virtex-II - summary
56717: 03/06/12: Re: DVI with a Virtex-II
56745: 03/06/13: Re: DVI with a Virtex-II
56793: 03/06/16: Re: DVI with a Virtex-II
56794: 03/06/16: Re: Problem with tristate-inout-pins of PS/2-Host
56844: 03/06/17: Re: Problem with tristate-inout-pins of PS/2-Host
57178: 03/06/25: Re: scaling fixed point fft
57233: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57301: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
57304: 03/06/27: Re: Eighty layers of metal!
57317: 03/06/27: Re: why so many problems Xilinx ?
58215: 03/07/17: Re: device selection for game system
58338: 03/07/21: Re: Graduation Day: My first 4-layer PCB
58699: 03/07/31: Re: VHDL Book Recommendations Please
59243: 03/08/13: News server for posting [was Re: Q: async flip-flop reset by a signal from a different clock domain]
59429: 03/08/19: Re: Async logic in FPGAs
59474: 03/08/20: Re: Parallel interface to an FPGA
59696: 03/08/26: Re: Altera ACEX 1K IOE
59937: 03/09/02: Re: Altera Devices
59983: 03/09/03: Re: Altera Devices
59984: 03/09/03: Re: altera latch synthesis
60104: 03/09/05: Re: Flex6K configuration PROM
60208: 03/09/08: Re: Flex6K configuration PROM
60209: 03/09/08: Re: Flex6K configuration PROM
60413: 03/09/12: Re: Reading and processing input from graphics cards (DVI)?
61574: 03/10/07: Re: beginner - exisit some free schematics programmer for fpga ?
61636: 03/10/08: Instantiating LUTs and INIT strings [was Re: Digesting runs of ones or zeros "well"]
61924: 03/10/15: Re: Xilinx Logic Handbook
62122: 03/10/20: Re: ISE5.2 to ISE6.1
62330: 03/10/27: Re: SDRAM Controller
62332: 03/10/27: Re: Altera ACEX1K configuration and initialisation
62371: 03/10/28: Re: Beginners advice for selecting an environment for FPGA design
62372: 03/10/28: Re: Memory for FPGA based LCD Driver/Controller
62472: 03/10/30: Re: PicoBlaze for Altera (ACEX1K)?
62618: 03/11/03: Re: Vendor supplied symbol/part models?
62649: 03/11/04: Re: Vendor supplied symbol/part models?
62929: 03/11/11: Re: Layout examples
62991: 03/11/12: Re: Layout examples
63030: 03/11/13: Re: Layout examples
63148: 03/11/17: Re: Layout examples
63922: 03/12/09: Re: Block RAM simulation VII
64100: 03/12/16: Re: VHDL-Testbench-Simulation in QuartusII
64451: 04/01/05: Re: Hyperthreading vs. Dual proc
64503: 04/01/06: Re: Hyperthreading vs. Dual proc
64711: 04/01/12: Re: image file reading in vhdl
65473: 04/01/30: Re: Where to get FPGA devices for testing?
66679: 04/02/25: Re: Altera ACEX chip wide reset
66748: 04/02/26: Re: Altera ACEX chip wide reset
68266: 04/03/31: Re: speed vs. temperature
68268: 04/03/31: Re: rs232 interface on nios
69428: 04/05/11: Re: Which board to buy? Status of open source tools?
69429: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69489: 04/05/12: Re: One issue about free hardware
69529: 04/05/13: Re: One issue about free hardware
69568: 04/05/14: Re: One issue about free hardware
69647: 04/05/17: Re: std_logic_vector vs unsigned
69685: 04/05/18: Re: std_logic_vector vs unsigned
69742: 04/05/19: Re: Malfunctioning dual port block ram.
69799: 04/05/20: Re: Malfunctioning dual port block ram.
69989: 04/05/26: Re: VHDL simple question: is 2-D array synthesizable
69990: 04/05/26: Re: Xilinx training
70349: 04/06/14: Re: SDRAM
70350: 04/06/14: Re: Costs of IPs
70623: 04/06/22: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70671: 04/06/23: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70708: 04/06/24: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70709: 04/06/24: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
71112: 04/07/08: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71207: 04/07/12: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71494: 04/07/20: Re: Using Verilog to embed the synthesis date and time
72740: 04/08/31: Re: Channel Link signals into Xilinx
73768: 04/09/29: Re: suggestions for Xilinx tool enhancements
73865: 04/09/30: Re: suggestions for Xilinx tool enhancements
75549: 04/11/09: Re: SDRAM sustained bursts
75828: 04/11/16: Re: Basic DVI example?
75885: 04/11/18: Re: video camera interface to FPGA
75886: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
77606: 05/01/12: Re: (d)ram interface
78950: 05/02/10: Re: Plea for help with MAX7000S
82045: 05/04/06: Re: Stupid question
82046: 05/04/06: Re: Structural vs Behavioral
82416: 05/04/12: Re: xapp134 on sdram controllers: @ bits reordering?
83882: 05/05/09: Re: DVI implementation
83936: 05/05/10: Re: DVI implementation
83998: 05/05/11: Re: DVI implementation
85143: 05/06/06: Re: Magical Mystery Tour of ISE environment variables
86682: 05/07/04: Re: vhdl source code cross reference tool
86759: 05/07/06: Re: Xilinx: XST synchronous FIFO using BRAMs
86814: 05/07/07: Re: fastest FPGA speed grade? Not the only measure, but ...
86894: 05/07/08: Re: aurora reliability
87106: 05/07/15: Re: ise 7.1 Input clk is never used.
87504: 05/07/25: Re: Problems installing windrvr.o in Red Hat EL3...
87646: 05/07/27: Re: how to measure number of cycles in ISE6.3
87718: 05/07/29: Re: Using unregistered inputs in FSM
87943: 05/08/04: Re: RocketIO connexion to an optical transceiver
88215: 05/08/12: Re: memory in verilog(its urgent plz help)
89480: 05/09/16: Re: IP Protection of code block in Xilinx FPGA?
89558: 05/09/19: Re: Xilinx ML403
89848: 05/09/28: Re: Image Processing Algorithm based on FPGA?
89849: 05/09/28: Re: Sythesis software for Virtex-4
89919: 05/09/30: Re: ... failed to route using a CLK template
90414: 05/10/12: [Going OT] Automotive Re: converting 12v signal to 3.3v
90443: 05/10/13: Re: [Going OT] Automotive Re: converting 12v signal to 3.3v
90706: 05/10/19: Re: Rosetta Results
90747: 05/10/20: Re: Rosetta Results
90864: 05/10/24: Re: Implementing five stage pipeline
90913: 05/10/25: Re: Implementing five stage pipeline
91630: 05/11/10: Re: Spartan 3e is slower than Virtex 2p
91727: 05/11/11: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91728: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91862: 05/11/15: Re: ISE, JTAG and ChipScopePro.
92284: 05/11/25: Re: Memory in VHDL
92285: 05/11/25: Re: Memory in VHDL
92811: 05/12/07: Re: I2C controller chipset to interface with FPGA
94928: 06/01/19: Re: FPGA Journal Article
94822: 06/01/18: Re: FPGA Journal Article
94930: 06/01/19: Re: FPGA Journal Article
94995: 06/01/20: Re: FPGA Journal Article
95807: 06/01/26: Re: So what happened to JHDLBits?
95806: 06/01/26: Re: open source fpga programmer programs
100074: 06/04/03: Re: deglitching a clock
100842: 06/04/19: Re: INFO: *.XDL file
100888: 06/04/20: Re: INFO: *.XDL file
100918: 06/04/21: Re: How to trsiate o/p pins?
101987: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102162: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102238: 06/05/12: Re: CoolRunner XPLA3 getting axed?
102511: 06/05/17: Re: Power for Spartan 3
102730: 06/05/19: Re: Processing DVI signals with an FPGA
103146: 06/05/26: Re: setting max fanout with xps flow
103564: 06/06/06: Re: Verilog vs VHDL
103568: 06/06/06: Re: Quartus and source control
104694: 06/07/04: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104718: 06/07/05: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
105178: 06/07/17: Re: Development Boards -Your chance to suggest features
105179: 06/07/17: Re: Need for reset in FPGAs
105213: 06/07/18: Re: Development Boards -Your chance to suggest features
105465: 06/07/24: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105568: 06/07/26: Re: Designing a matrix multpier block using existing xilinx toolbox
106057: 06/08/07: Re: verilog versus vhdl
107060: 06/08/24: Re: DCM vs. PLL
107181: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107182: 06/08/25: Re: ISERDES strange simulation behaviour
107481: 06/08/29: Re: high level languages for synthesis