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Authors (M)
M:
12855: 98/11/02: Q: fifo flags
13164: 98/11/18: Re: Q: fifo flags
35292: 01/09/27: Fastest way to become a Verilog samurai?
m:
31725: 01/06/04: Re: EPC2: no output signals
123028: 07/08/14: Delaying a pulse train
123030: 07/08/14: Re: Delaying a pulse train
123037: 07/08/14: Re: Delaying a pulse train
123044: 07/08/15: Re: Delaying a pulse train
123119: 07/08/16: Re: Delaying a pulse train
123132: 07/08/16: Re: Delaying a pulse train
125995: 07/11/11: Programming connection
125996: 07/11/11: Re: Programming connection
126008: 07/11/12: Re: Programming connection
126025: 07/11/12: Re: Programming connection
128969: 08/02/11: Re: Virtex5 DCM lower limit
129672: 08/03/02: Re: Software for FPGA-based PC scope
134502: 08/08/14: Re: EBAY: XC2V1000-5FG456C
134503: 08/08/14: Re: EBAY: XC2V1000-5FG456C
M E:
110565: 06/10/17: 8B/10B vs. Start/Stop for SERDES
117456: 07/03/31: ISE on Fedora?
117758: 07/04/09: Re: ISE on Fedora?
M & J:
17926: 99/09/17: Re: PCI core for Orca 3T
m burgess:
6325: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
6326: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
M Burgess:
864: 95/03/16: Specialist Vacancies
M H:
11685: 98/08/31: Re: CPLD/FPGA software
M Ihsan Baig:
114943: 07/01/27: Higher studies
117934: 07/04/13: SoC
119383: 07/05/17: video soltion provider
119430: 07/05/18: Re: video soltion provider
122841: 07/08/08: Ph.D in France
M Kartheepan:
12231: 98/10/06: Re: FIR Filter Design
12253: 98/10/07: Re: FIR Filter Design
M Murphy:
17657: 99/08/19: Digital Design Engineer needed - Please read
17905: 99/09/16: Chip Level Ciruit Designers needed, please read
M Pedley:
34247: 01/08/17: Atmel CPLD - JEDEC to ABEL
34279: 01/08/18: Re: Atmel CPLD - JEDEC to ABEL
34872: 01/09/12: Programming Delays in ABEL
34878: 01/09/12: Re: Programming Delays in ABEL
34879: 01/09/12: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
48647: 02/10/22: High Performance FPGA's - Xilinx and ??????
48713: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
49427: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
M R Wheeler:
10504: 98/05/25: Altera MaxPlus using third party programmer
21721: 00/03/30: MaxPlus9.5 License and Fitter problems
21765: 00/03/31: Re: MaxPlus9.5 License and Fitter problems
22330: 00/05/05: MaxPlus9.5/6 License problems
M Schreiber:
40318: 02/03/05: exceeding 2GB limits in xilinx
42393: 02/04/22: Using LogiBlox in Virtex2
45008: 02/07/09: Bi-Directional Bus problem in Xilinx FPGA
45048: 02/07/10: Re: Bi-Directional Bus problem in Xilinx FPGA
48796: 02/10/24: Pin locking Virtex 2 FPGA
49563: 02/11/15: Re: Registering inputs or outputs of modules
51581: 03/01/16: FPGA Express FSM state ordering
52074: 03/01/30: Re: Floor Planning DCM
M Shehzad Hanif:
71311: 04/07/14: Xilinx Virtex-II Configuration in Slave Serial
M Smith:
34337: 01/08/21: Help the clueless guy....
M Sweger:
6927: 97/07/09: Re: Generating Sine/Cosine digitally
15437: 99/03/24: Re: Reconfigurable computing thesis on the web
M Wirtzfeld:
30505: 01/04/11: Introductory Question - LSB to MSB Conversion.
<m-gupta@nwu.edu>:
14687: 99/02/11: Mentor-Alliance Interface
m.:
57055: 03/06/22: vga controller
M. Aberbour:
9054: 98/02/17: System Gates and Logic Cells...
M. Bodnar:
71471: 04/07/19: Boards Comparable to Alpha-Data's ADM-XRC-II
M. Boin:
10733: 98/06/14: Metrology Software- Survey
M. Hamed:
117503: 07/04/02: X_OBUF and other error messages with ModelSim
117549: 07/04/03: Re: X_OBUF and other error messages with ModelSim
117744: 07/04/09: Modelsim Low and High violations
117861: 07/04/11: Timing violations though constraints have been met
117887: 07/04/12: Re: Timing violations though constraints have been met
117891: 07/04/12: SETUP & HOLD time confusion
117944: 07/04/13: Re: SETUP & HOLD time confusion
118117: 07/04/17: Block RAM strange behavior, address off by one
118145: 07/04/18: Re: Block RAM strange behavior, address off by one
118151: 07/04/18: Re: Block RAM strange behavior, address off by one
118163: 07/04/18: Re: Block RAM strange behavior, address off by one
118169: 07/04/18: Re: Block RAM strange behavior, address off by one
118192: 07/04/19: Re: Compiling a library
118393: 07/04/25: Modelsim simulation progress in batch/command line mode?
118400: 07/04/25: Timing constraints with asynchronous clocks
118438: 07/04/26: Re: Modelsim simulation progress in batch/command line mode?
118442: 07/04/26: Re: Timing constraints with asynchronous clocks
118493: 07/04/27: Placement error for adjacent pins
118512: 07/04/28: Re: Placement error for adjacent pins
128650: 08/02/01: Keeping Xilinx tool from Optimizing out Debugging signals
128655: 08/02/01: Re: Keeping Xilinx tool from Optimizing out Debugging signals
129012: 08/02/12: Re: Timing Constraint not met
130098: 08/03/14: Detecting a pulse with minimum width
130105: 08/03/14: Re: Detecting a pulse with minimum width
M. Movahedin:
712: 95/02/14: Synopsys FPGA Compiler
717: 95/02/16: Re: Synopsys FPGA Compiler
2265: 95/11/15: Re: Looking for large circuit
3769: 96/07/29: A Survey on Design Errors
3806: 96/08/05: A Survey on Design Errors, Now by E-mail
4144: 96/09/18: A Survey on Design Errors
M. Praekelt:
35636: 01/10/12: Lattice discontinues all smaller MACH circuits and other devices
M. Randelzhofer:
44731: 02/06/28: Re: blank CPLD
44750: 02/06/29: Re: blank CPLD
44795: 02/07/01: Re: blank CPLD
45624: 02/07/29: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45699: 02/08/01: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45999: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
50177: 02/12/04: Re: Low Speed Serial Bus Suggestions
M. Sachemo:
37985: 01/12/28: instruction processor
M. Sherman:
6391: 97/05/21: Engineering Opportunity - http://www.digjobs.com
M. Simon:
26413: 00/10/15: Re: palasm
26414: 00/10/15: Re: FPGA PCB design examples
28123: 00/12/21: Re: FPGA and Board for Microprocessor Design?
28251: 01/01/03: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
29809: 01/03/12: Re: Configuration devices
M. Spicker:
6918: 97/07/09: Re: Generating Sine/Cosine digitally
M.+M. Monhart:
25094: 00/08/25: experiences with USB core vendors
<m.adithya@gmail.com>:
98177: 06/03/06: Asynchronous FIFO design question
98182: 06/03/06: Re: Asynchronous FIFO design question
<m.afgani@gmail.com>:
115770: 07/02/20: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
M.B.:
26495: 00/10/18: Re: Announce: Free HC11 CPU Core
30846: 01/05/01: ccd imaging with fpga
30918: 01/05/03: Re: ccd imaging with fpga
32665: 01/07/04: FPGA projects
38309: 02/01/11: Re: FPGA and CCD : any experience?
<m.beard@vertex-solutions.co.uk>:
20359: 00/02/07: ASIC Opportunities
<m.bodenbach@ifen.com>:
86939: 05/07/10: Re: Running prog from PROM
M.Kmann:
95240: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95243: 06/01/21: Re: OT:Shooting Ourselves in the Foot
M.Randelzhofer:
54611: 03/04/15: Re: Xilinx has released SpartanIII
55717: 03/05/17: Re: smallest embedded cpu.
56595: 03/06/10: Re: XC95288 programming problem
56729: 03/06/12: Analog signals connected to xilinx spartan2
56734: 03/06/13: Re: Analog signals connected to xilinx spartan2
57282: 03/06/26: Re: Low-power FPGA
57503: 03/07/01: Re: Cyclone vs Spartan-3
58791: 03/08/01: Re: 5 volt tolerant Xilinx parts
71358: 04/07/15: Re: MUXCY-based multiplexers
71826: 04/08/01: SPARTANII pinout table mysteries ???
71871: 04/08/03: SPARTAN-3 VCCAUX supply current
71897: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
71898: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
72223: 04/08/11: new XILINX 9500XL datasheets
74667: 04/10/16: Re: which xilinx CPLD to select?
77514: 05/01/08: WebPack download problem
79552: 05/02/21: WYSIWYG option in xilinx webpack 6.3
79587: 05/02/21: Re: WYSIWYG option in xilinx webpack 6.3
80495: 05/03/07: Re: Cheap alternatives to Mach 210s
84848: 05/05/30: Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1
90384: 05/10/11: Re: Question regarding FPGA startup ROMs
90874: 05/10/24: Re: Implementing five stage pipeline
91554: 05/11/08: Re: Need some help with interfacing spartan III to a computer...
91555: 05/11/08: Re: Suggestions/Recommendations with CPLD's and Software
92260: 05/11/25: Re: XC2000
93306: 05/12/19: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93309: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
98355: 06/03/08: Re: 5v Xilinx development board
98630: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
104569: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
108789: 06/09/16: Re: XPLA3 going obsolete?
109334: 06/09/24: Re: Spartan 3 or 3E ?
129715: 08/03/03: Re: my Spartan-4 wishlist
132392: 08/05/25: New Xilinx device package options for S3E & S3A
132819: 08/06/07: Re: 1 Pin MTE Cable
133905: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133909: 08/07/19: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133998: 08/07/21: Re: audio serial port i2s
M.S.Gaur:
30643: 01/04/20: XSV boards memory addressing
30613: 01/04/19: Looking for digital video to VGA RGB conversion
M.Simon:
14060: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
15211: 99/03/13: Re: Infidels Invited, Heathens Highly Welcome !
15550: 99/03/30: Re: IP cores and software industry
15646: 99/04/06: Re: newbie: FPGA suggestion
15725: 99/04/10: Re: FPGA testing board
15742: 99/04/11: Re: FPGA vs CPLD? Any Experts out there?
15888: 99/04/19: Re: Forth Processor
16110: 99/05/04: Re: Anyone use 27256 for config?
17680: 99/08/23: Re: microcontroller vs FPGA
M.Sivanandan:
28770: 01/01/23: fpga: regarding startup virtex
M.Stekelenburg:
11140: 98/07/21: Re: How to write a VHDL counter of up & down
<M.Vasilko@computer.org>:
11136: 98/07/21: ANNOUNCE: Dynamically Reconfigurable Hardware WWW Library
16250: 99/05/12: Re: High speed reconfigurability
17509: 99/08/03: Re: Partial Reconfiguration?
m0:
41479: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
42969: 02/05/08: Re: "free" tools ... ?
43011: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43012: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43355: 02/05/20: Re: Anyody else get spam about "FPGA Video Seminar"?
43373: 02/05/20: Re: Architecture for high-level reconfigurable computing
43579: 02/05/24: Re: FPGA, VHDL : RAM initialization
43890: 02/06/05: Re: VIRTEX-E XCV405E Orcad schematic required
M6:
89603: 05/09/20: picoblaze IDE for Linux
89696: 05/09/22: Re: picoblaze IDE for Linux
89706: 05/09/22: Re: picoblaze IDE for Linux
<m>:
53341: 03/03/11: Re: Are there any FPGA magazines/journals?
53345: 03/03/11: Can you recommend a text on...?
<m_oylulan@hotmail.com>:
84386: 05/05/18: CORDIC bit-serial vs. bit-parallel
85201: 05/06/06: Xilinx ISE 7.1i
85292: 05/06/07: Re: CORDIC bit-serial vs. bit-parallel
86340: 05/06/25: interfacing to multiple converters
86349: 05/06/26: Re: interfacing to multiple converters
103273: 06/05/30: Mains pick-up on I/O pins
103396: 06/06/01: Re: Mains pick-up on I/O pins
103728: 06/06/09: Current from FPGA pins to ADC
103887: 06/06/14: Re: Current from FPGA pins to ADC
<m_rajanikant@my-deja.com>:
22640: 00/05/16: c -> FPGA netlist compiler
ma:
83782: 05/05/06: newbie question
83823: 05/05/07: Re: newbie question
83841: 05/05/07: Re: newbie question
94173: 06/01/06: Programming Xilinx PowerPC
94176: 06/01/06: Re: Programming Xilinx PowerPC
94179: 06/01/06: Re: Programming Xilinx PowerPC
94181: 06/01/07: Re: Programming Xilinx PowerPC
108654: 06/09/14: Developing new blocks for sysgen
112415: 06/11/21: CORDIC FM Demodulation
112437: 06/11/22: Re: CORDIC FM Demodulation
112441: 06/11/22: Re: CORDIC FM Demodulation
112730: 06/11/28: Digital PLL and FM demodulation
112756: 06/11/28: Re: Digital PLL and FM demodulation
113413: 06/12/13: IQ multiplier
113437: 06/12/13: Re: IQ multiplier
113440: 06/12/13: Complex mixer
Ma. Jose Avedillo de Juan:
12653: 98/10/22: state assignment & fpgas
Maaf:
87850: 05/08/02: 5V non-volatile reprogrammable FPGA/CPLD
87892: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
Mac:
64384: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
65698: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
77754: 05/01/16: Re: What is the difference between ASIC and FPGA?.
80858: 05/03/12: Re: ISE build dependencies
80882: 05/03/14: Re: ISE build dependencies
81001: 05/03/16: Re: LVDS as general differential input ?
81264: 05/03/20: Re: RS 232 receiver using spartan 3 board
81270: 05/03/21: Re: RS 232 receiver using spartan 3 board
82680: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
82681: 05/04/16: Re: salary ballpark please guys
82704: 05/04/16: Re: salary ballpark please guys
82746: 05/04/17: Re: salary ballpark please guys
82748: 05/04/17: Re: salary ballpark please guys
83345: 05/04/28: Re: XC9500 - creating RS485 Mux
83350: 05/04/28: Re: Virtex slow clock multiply options?
83396: 05/04/29: Re: Virtex slow clock multiply options?
83397: 05/04/29: Re: Virtex slow clock multiply options?
83678: 05/05/05: Re: Does this group allow JobPostings?
84780: 05/05/27: Re: Ethernet / digital logic questions
84887: 05/05/31: Re: What is a typical job scope when FPGAs are involved?
85023: 05/06/03: Re: PCI master clock trace
85024: 05/06/03: Re: need a book: Hilbert transform
85229: 05/06/07: Re: Sch & Layout Free Program
95163: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95166: 06/01/21: Re: OT:Shooting Ourselves in the Foot
mac teh knife:
44294: 02/06/16: new computer
44327: 02/06/17: Re: Which Synthesis tool for XILINX
MACEI'S:
56888: 03/06/18: BCH or Hamming Code
56986: 03/06/20: Is this is possible???
57855: 03/07/08: Multiple Files to Synthesis in Make File ?
57858: 03/07/08: Books
57910: 03/07/09: Make file ...........Help Please
57991: 03/07/11: how to compile .vhd files one by one using makefile
58112: 03/07/15: how to remove this error
58114: 03/07/15: Make file ...........Help Please
58265: 03/07/18: bit to rbt conversion
60262: 03/09/09: AWGN in VHDL
Maciej (@):
55567: 03/05/12: GSR
Maciej Bartkowiak:
18781: 99/11/15: Need advice on interfacing SDRAM modules
18844: 99/11/18: Re: Need advice on interfacing SDRAM modules
Maciej Witaszek:
68777: 04/04/17: NIOS: Run program from SDRAM
68779: 04/04/18: Re: Nios - cyclone toolchain questions
68910: 04/04/21: Re: NIOS: Run program from SDRAM
Maciejos:
75888: 04/11/18: Spartan-3 configuring problem
75892: 04/11/18: Re: Spartan-3 configuring problem
75896: 04/11/18: Re: Spartan-3 configuring problem
Maciek:
42589: 02/04/28: Xilinx
43059: 02/05/11: dual port fifo
43063: 02/05/11: Re: dual port fifo
45725: 02/08/02: spartan i/o
45755: 02/08/05: Re: spartan i/o
58527: 03/07/25: Re: Should I use ABEL?
58531: 03/07/25: Quartus and memory initialization
58532: 03/07/25: Re: Quartus and memory initialization
59932: 03/09/02: Altera Devices
59945: 03/09/02: Re: Altera Devices
Maciek Kudla:
26166: 00/10/06: Problem Foundation 3.1 sp 3
Mack:
109567: 06/09/29: Interfacing second bram port to user logic?
109579: 06/09/29: Re: Interfacing second bram port to user logic?
110838: 06/10/24: DDR SDRAM access with MPMC2, Databus Width
110887: 06/10/25: Re: DDR SDRAM access with MPMC2, Databus Width
110976: 06/10/26: Re: DDR SDRAM access with MPMC2, Databus Width
mack:
72957: 04/09/08: AMBA AHB
73001: 04/09/09: Re: AMBA AHB
73094: 04/09/14: AHB-Slave
73108: 04/09/14: EDK
73358: 04/09/20: AHB_SLAVE
75477: 04/11/07: Mixed RTL ,XILINX EDK
75505: 04/11/08: Re: Mixed RTL ,XILINX EDK
Mad I.D.:
118530: 07/04/29: DS18B20 connection on FPGA?
<madaan@my-dejanews.com>:
12436: 98/10/12: I2C Core
15808: 99/04/15: JPEG Codec
madair:
114434: 07/01/15: Constraining Multiple clock design
maddy:
84895: 05/05/31: Re: FPGA Boards
Madeleine Delaat:
<madhav1111@gmail.com>:
83458: 05/04/30: using cadence tool
madhu:
39215: 02/02/04: Glitch detect
Madhu:
39385: 02/02/07: Re: conv_integer problem ???
39861: 02/02/21: Here is an argument and can anyone help me out
64515: 04/01/06: How do you initialize signals in VHDL?
79614: 05/02/22: Re: BACK to FPGA
madhukar:
71698: 04/07/28: Dcm clock for fpga
<MadhuPankaj11@gmail.com>:
129498: 08/02/26: Re: Interrupt Handler page missing in from software platform settings
Madhura:
36609: 01/11/13: FPGA synthesis
36749: 01/11/19: Re: FPGA synthesis
36759: 01/11/19: Re: FPGA synthesis
73744: 04/09/28: Microblaze : ilmb_Cntrl
73814: 04/09/29: Re: Microblaze : ilmb_Cntrl
73611: 04/09/25: Re: Microblaze:ISE-EDK
73420: 04/09/21: Microblaze:ISE-EDK
Madhura Bokil:
38454: 02/01/15: FPGA : VHDL netlist for simulation
Madhura P:
56918: 03/06/18: Design Validation
<madhurk@my-deja.com>:
17611: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
Madison:
20159: 00/01/28: Testbenches
<madisonfff@usa.net>:
27164: 00/11/13: Clear AND Preset Pins
<madmarsu@mygale.org>:
11394: 98/08/10: Re: Food poison
madQ:
18290: 99/10/12: Download Ia.n.i.!!! It's free!
18293: 99/10/12: Download Ia.n.i.!!! It's free!
18336: 99/10/16: Download Ia.n.i.!!! It's free!
18354: 99/10/18: Download Ia.n.i.!!! It's free!
18402: 99/10/22: Download Ia.n.i.!!! It's free!
Mads Ulrik Kristoffersen:
55175: 03/04/29: Xilinx XAct
MaEs:
64148: 03/12/18: Re: www.fpga-faq.com
66647: 04/02/24: Re: FPGA vendors and their patents
maespin:
22702: 00/05/18: verilog modules into viewlogic designs
Maf:
36672: 01/11/15: Re: Prototyping Board
Magali Oudard:
29718: 01/03/06: School project
Magne Munkejord:
115460: 07/02/12: Problem with floating inputs on LVDS ports
115490: 07/02/12: Re: Problem with floating inputs on LVDS ports
115551: 07/02/13: Re: Problem with floating inputs on LVDS ports
<magne.munkejord@gmail.com>:
132139: 08/05/15: question about high speed serial links with clock forwarding in
Magnus Danielson:
67186: 04/03/08: 66B mode of VirtexII-ProX Rocket I/O
67258: 04/03/09: Re: 66B mode of VirtexII-ProX Rocket I/O
68745: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
68746: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
Magnus Homann:
8470: 97/12/18: md5 in a FPGA?
8480: 97/12/20: Re: md5 in a FPGA?
8572: 98/01/09: Re: Xilinx Configuration Problem
8771: 98/01/25: Re: UART Spec
8844: 98/02/01: FPGA/ASIC - same difference?
9011: 98/02/13: PLD programming and board testing (JTAG)
9574: 98/03/24: Re: "CORE Competency" ???
10356: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
12387: 98/10/10: Schematic entry?
13488: 98/12/05: Re: XILINX FPGA reaches GHz speeds
13665: 98/12/17: Re: Fast *Industrial* 22V10?
13726: 98/12/21: Re: Fast *Industrial* 22V10?
13728: 98/12/21: Re: Fast *Industrial* 22V10?
13753: 98/12/22: Re: Fast *Industrial* 22V10?
13799: 98/12/28: Re: 22V10 Metastability - help please
13805: 98/12/28: Re: 22V10 Metastability - help please
13836: 98/12/29: Re: 22V10 Metastability - help please
13843: 98/12/29: Re: 22V10 Metastability - help please
13852: 98/12/29: Re: 22V10 Metastability - help please
13883: 98/12/31: Re: 22V10 Metastability - help please
13884: 98/12/31: Re: 22V10 Metastability - help please
13885: 98/12/31: Re: 22V10 Metastability - help please
13920: 99/01/02: Re: IS: 2001, A Logic Odyssey (WAS: 22V10 Metastability - help please)
14048: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14051: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13999: 99/01/06: Re: Gömmer grisöron...
14042: 99/01/08: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
15184: 99/03/11: Re: Infidels Invited, Heathens Highly Welcome !
16080: 99/04/30: Re: Double Port ram for Altera EPF10K20
16545: 99/05/27: Re: Virtex based PCI cards
16323: 99/05/16: Re: Synchronizer design?
16427: 99/05/21: Re: How synthesize tools concern with size of the design?
16476: 99/05/25: Re: How synthesize tools concern with size of the design?
16700: 99/06/03: Re: virtex vs apex20k family comparison for DSP ?
17564: 99/08/10: Re: Designing a Virtex board
17999: 99/09/22: Dual-port RAM in Apex
18335: 99/10/16: Re: VITERBI
18345: 99/10/16: Re: Xilinx 4k and DPRAM for leonardo question
18951: 99/11/22: Re: Virtex: Getting flip-flops into the pads
19084: 99/11/28: Re: Virtex: Getting flip-flops into the pads
19139: 99/12/02: Re: data serializer/decoder FPGA solution
19303: 99/12/11: Re: Altera APEX lpm modules in Synplify
19534: 99/12/29: Re: USB2 core call for Volunteers
19546: 99/12/30: Re: IRDY/TRDY Dedicated or Special Pin Name
19548: 99/12/30: Re: PCI slot 3.3V pins.
19553: 99/12/30: Re: USB2 core call for Volunteers
19562: 99/12/31: Re: PCI slot 3.3V pins.
19678: 00/01/07: Re: Design security
20101: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20115: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20496: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20498: 00/02/11: A FPGA hickup
20506: 00/02/12: Re: A FPGA hickup
20526: 00/02/13: Re: A FPGA hickup
20578: 00/02/15: Re: A FPGA hickup
20585: 00/02/15: Re: Xilinx Virtex Reset
20586: 00/02/15: Using SRL16 for synching asynch inputs?
20642: 00/02/16: Re: Xilinx hold time problems...
20649: 00/02/16: Re: Xilinx hold time problems...
21160: 00/03/08: Re: antifuse fpga's replacing xilinx
21174: 00/03/09: Re: antifuse fpga's replacing xilinx
21175: 00/03/09: Re: antifuse fpga's replacing xilinx
21182: 00/03/09: Re: antifuse fpga's replacing xilinx
21211: 00/03/10: Re: antifuse fpga's replacing xilinx
21673: 00/03/28: Re: FPGA & single point failure
21905: 00/04/06: Re: JTAG programming
22796: 00/05/24: Re: Xilinx Virtex E
23045: 00/06/10: Re: XILINX RAM Useless
23047: 00/06/10: Re: math help needed
24539: 00/08/12: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24540: 00/08/12: Re: Who needs all those printed ac parameters?
25078: 00/08/25: Re: largest fpga in the industry
26567: 00/10/20: Re: Very Lucrative FPGA Jobs
26587: 00/10/21: Re: UCF Question
26612: 00/10/22: Re: UCF Question
26616: 00/10/22: Re: UCF Question
26625: 00/10/23: Re: UCF Question
26757: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
26804: 00/10/30: Re: Very Lucrative FPGA Jobs
27336: 00/11/18: Re: In the news
27383: 00/11/20: Re: In the news
27413: 00/11/21: Re: In the news
27449: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27464: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27472: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27485: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27489: 00/11/24: Re: How to reduce the Tco
27493: 00/11/24: Re: How to reduce the Tco
27623: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
27634: 00/11/30: Re: Synplify Benchmarks
27646: 00/12/01: Re: Synplify Benchmarks
27647: 00/12/01: Re: Synplify Benchmarks
27671: 00/12/01: Re: Synplify Benchmarks
27672: 00/12/01: Re: Synplify Benchmarks
27842: 00/12/12: Re: dual port ram for altera
27846: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
28141: 00/12/22: Re: really fast counter in SpartanXL?
28146: 00/12/22: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28164: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
29579: 01/02/27: Re: Spartan II power
30191: 01/03/27: Re: What's new in Synplify 6.20 than 6.13
29654: 01/03/04: Re: Metastability
29792: 01/03/10: Re: Metastability
29875: 01/03/14: Re: Again Spartan II power
29876: 01/03/15: Re: Metastability
29877: 01/03/15: Re: Metastability
29878: 01/03/15: Re: Metastability
30033: 01/03/21: Re: Looking for Skew information
30150: 01/03/26: Re: No inputs on XC9536XL
30298: 01/04/02: Re: xapp258 question
30335: 01/04/03: Re: xapp258 question
30735: 01/04/26: Re: Something about the counter
30779: 01/04/28: Re: C++ To Gates
30793: 01/04/29: Re: C++ To Gates
30794: 01/04/29: Re: C++ To Gates
30820: 01/04/30: Re: C++ To Gates
30821: 01/04/30: Re: C++ To Gates
30822: 01/04/30: Re: C++ To Gates
30836: 01/05/01: Re: C++ To Gates
30839: 01/05/01: Re: Multiple state machines in altera AHDL
30957: 01/05/04: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
31675: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31678: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31966: 01/06/10: Re: Help in FIFO design
31967: 01/06/10: Re: problem: bahavior simulation of xilinx's coregen cores
31968: 01/06/10: Re: Flash programming via FPGA's JTAG ????
32410: 01/06/26: Re: Register balancing in FPGA Express
32479: 01/06/27: Re: clock speed in XC95288XL
32502: 01/06/28: Clock muxes
32551: 01/06/29: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32657: 01/07/04: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32788: 01/07/09: Re: SpartanII: non clock pad drives clock net ?
32892: 01/07/11: Re: Handel-C
32954: 01/07/12: Re: PCI arbiter core
32976: 01/07/13: Re: Xilinx BRAM failures
32978: 01/07/13: Re: Design entry
34203: 01/08/16: Re: Replication of FFs in Xilinx XC4000
35405: 01/10/03: Re: Which Cable for the Xilinx 3064XL ?
35422: 01/10/04: Re: Which Cable for the Xilinx 3064XL ?
35917: 01/10/23: Re: Verilog vs. VHDL
36423: 01/11/08: Re: Xilinx dedicated IO pins
36461: 01/11/09: Re: Xilinx dedicated IO pins
36837: 01/11/21: Re: slew rate of virtex output buffers figures
36929: 01/11/26: Re: ALTERA's Mercury CDR
37114: 01/11/30: Re: SpartanIIE
38369: 02/01/12: Re: Repost: Should clock skew be included for setup time analysis?
38440: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38441: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38490: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
39132: 02/02/01: Re: APEX-II vs VIRTEX-II
39133: 02/02/01: Re: Spartan II power-up current - again
39351: 02/02/07: Re: CLKDLL x4 problem
40147: 02/02/28: Re: Altera's new family Stratix
40315: 02/03/05: Re: Constraining help required for clk_enable
40789: 02/03/15: Re: where to start with constraining..
40790: 02/03/15: Re: High speed clock routing
40802: 02/03/15: Re: High speed clock routing
40834: 02/03/16: Re: High speed clock routing
40835: 02/03/16: Re: High speed clock routing
40872: 02/03/17: Re: just bought...
40873: 02/03/17: Re: To Falk Brunner
40919: 02/03/18: Re: just bought...
41930: 02/04/11: Re: regarding gate count of the design
41931: 02/04/11: Re: Built in multipliers in Virtex 2000E?
42494: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42717: 02/05/01: Re: Availability of XC2S150E-6FG456I
44538: 02/06/22: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
51768: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51769: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
55355: 03/05/05: Re: Virtex2 BUFGMUX problem ?
56091: 03/05/28: Re: JTAG madness
56128: 03/05/29: Re: JTAG madness
56232: 03/05/31: Re: FPGA's an Flash
60217: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
60497: 03/09/15: Re: Xilinx S3 I/O robustness question
60994: 03/09/26: Re: Regulator for Spartan 2
61507: 03/10/06: Re: Digesting runs of ones or zeros "well"
61658: 03/10/08: Re: BF957C Application
65344: 04/01/25: Re: changing values in a fifo
66241: 04/02/15: Re: Pricing, 101
66713: 04/02/25: How would you...
66750: 04/02/26: Re: How would you...
67558: 04/03/14: Re: Issues in Rocket I/O
Magnus Jacobsson:
50243: 02/12/06: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
50253: 02/12/06: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
mahalingamv@gmail.com:
117292: 07/03/27: is edk 8.1 availabe for download
119298: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
120197: 07/06/02: ngdbuild error : multiple drivers and driving non buffer primitives
120248: 07/06/04: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120249: 07/06/04: Re: any experiences concerning xup and digilent inc.?
120318: 07/06/05: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120732: 07/06/15: edk clock problem
120834: 07/06/18: Re: edk clock problem
<mahalingamv@gmail.com>:
99914: 06/03/30: design compiler optimization
Mahboob Ahmed:
17989: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
17988: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
18319: 99/10/14: Virtex FPGA PCI select I/O Characteristics.
19072: 99/11/27: Siemens HSCX development tools.
19467: 99/12/23: PCI slot 3.3V pins.
mahdavi:
37053: 01/11/29: Test Bench for MaxPlus ?
mahdi:
115443: 07/02/11: CLOCK GENERATOR
115753: 07/02/19: ROC PORT
115867: 07/02/22: Re: ROC PORT
115868: 07/02/22: 2x technique
115869: 07/02/22: internal DCM
115883: 07/02/22: Re: internal DCM
115884: 07/02/22: Re: 2x technique
Mahei:
109488: 06/09/27: Re: Looking for ispMACH4000 eval boards
<mahenreddy@gmail.com>:
115921: 07/02/25: Edge vs Level triggering
mahesh:
106979: 06/08/23: Re: PCIe latency
133222: 08/06/20: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
133446: 08/06/29: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133461: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133475: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
Mahesh M. Bandi:
52336: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52343: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52344: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52345: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52363: 03/02/07: Re: NIOS and ACEX1K
Mahim Mishra:
66563: 04/02/22: Help with Xilinx EDK 6.1
66672: 04/02/24: Re: Help with Xilinx EDK 6.1
66858: 04/02/27: Xilinx ISE Impact crashes during configuration
66892: 04/02/28: Re: Xilinx ISE Impact crashes during configuration
66893: 04/02/28: Xilinx iMPACT error: "Done did not go high"
66908: 04/02/29: Re: Xilinx iMPACT error: "Done did not go high"
67685: 04/03/17: Xilinx bit-file format?
73043: 04/09/11: JBits 3.0 and Virtex-II Pro
73238: 04/09/16: xdl tool, or Xilinx Design Language
Mahmoud:
94939: 06/01/19: Re: newbie question about Xillinx JTAG cable
94831: 06/01/18: Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??
95457: 06/01/23: Re: Xilinx ISE & StateCad
95601: 06/01/24: Re: Verilog tutorial by John Sanguinetti
96050: 06/01/28: Re: Digilent FPGA & Handel-C
96349: 06/02/02: Re: How will synthesizers handle these statements?
Mahmut C. Genceli:
18180: 99/10/05: Re: Free Hardware "CPLD board"
mahshid:
123354: 07/08/24: Dynamic power estimation using Xpower
123368: 07/08/25: Re: Dynamic power estimation using Xpower
<mahurshi@gmail.com>:
98193: 06/03/06: A few questions about FPGAs
<mai99drh@studserv.uni-leipzig.de>:
76847: 04/12/14: Re: pausing execution on ppc405
Maik H.:
132762: 08/06/06: Re: Your favourite DSP textbooks/websites?
Maik Ritter:
117907: 07/04/13: Are there Quartus II Web Edition limitations?
117913: 07/04/13: Re: Are there Quartus II Web Edition limitations?
117977: 07/04/15: Re: Are there Quartus II Web Edition limitations?
Mail Delivery Service:
85190: 05/06/06: Delivery Status Notification
<mail83870@pop.net>:
11431: 98/08/13: Newbie seeks cheap fun w/FPGAs
<mail@deeptrace.com>:
93551: 05/12/24: Xilinx ISE Simulator
93719: 05/12/28: Re: Xilinx ISE Simulator
93933: 06/01/03: Re: Xilinx ISE Simulator
94932: 06/01/19: Disabling cross domain checking for Xilinx ISE
94938: 06/01/19: Re: Disabling cross domain checking for Xilinx ISE
94964: 06/01/19: Bogus Hold Violations with 2X clock on Xilinx ISE 7.1
mailmekaran:
103472: 06/06/03: VHDL code For Floating point adder and Multiplier
<mailsatishv@gmail.com>:
121714: 07/07/11: New board JTAG error
121735: 07/07/12: Re: New board JTAG error
<mailservice@bulkmail.net>:
7232: 97/08/17: Do you like to receive $2 million ?
maimuna:
45939: 02/08/12: changing width of array
46096: 02/08/19: to reduce the circuit design
46222: 02/08/21: Re: to reduce the circuit design
46262: 02/08/23: Re: to reduce the circuit design
Mainak Sen:
66128: 04/02/12: xsa-50 board
76065: 04/11/23: Xilinx Multimedia Board
Maire:
36861: 01/11/22: Synplicity & BlockRAMs
maisk:
54858: 03/04/20: Re: test
majordomo@att.net:
7125: 97/08/03: HELP!!NEED A CACHE SIMULATOR A.S.A.P
Mak:
83291: 05/04/27: Re: PCI plug n play and Graphics card implementation
89042: 05/09/03: High baud rate chips for RS232 protocol
107773: 06/09/01: Interface of 8051 microcontroller with FPGA Block RAM
107789: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
107791: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108681: 06/09/14: Critcal path in XILINX ISE (XST)
110585: 06/10/18: EDIF netlist timing simulation
110587: 06/10/18: Re: EDIF netlist timing simulation
<mak@cromp.ernet.in>:
4677: 96/11/28: Reconfigurable FPGAs in Networking
makarand:
133571: 08/07/03: Free Webinars on PMP Certification Awareness and Roadmap
Makarand Joshi:
13588: 98/12/10: Re: Array Range Legal?
13594: 98/12/10: Re: Array Range Legal?
Make Money Fast:
Makesh Soundarajan:
71020: 04/07/05: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71056: 04/07/06: Re: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71070: 04/07/07: Re: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
makhan:
112529: 06/11/23: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
113910: 06/12/28: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
122746: 07/08/06: Re: how to test the FPGA on the board
122748: 07/08/06: Re: Download the contents of the FPGA's RAM block
122835: 07/08/08: Re: Download the contents of the FPGA's RAM block
131105: 08/04/10: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131115: 08/04/11: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Maki:
33285: 01/07/22: Re: Maxplus II download sites
34135: 01/08/15: Re: Building a clock out of a PLD
75779: 04/11/15: Re: Gap between layers in PCB
88185: 05/08/11: LatticeXP availability
89949: 05/09/30: Lattice XP availability
89951: 05/09/30: Re: Lattice XP availability
99534: 06/03/26: Re: BlockROM inference in XST - This is just plain silly
100159: 06/04/04: Lattice ispLever Starter Download
100235: 06/04/05: Re: Lattice ispLever Starter Download
124299: 07/09/18: Re: Tristate bus on spartan FPGA
125885: 07/11/08: Re: Non-volatile FPGA in a small package
125907: 07/11/08: Re: Non-volatile FPGA in a small package
127813: 08/01/08: Re: True Dual Port RAM
127901: 08/01/10: Re: How to program and initialize Lattice XP devices
127931: 08/01/10: Re: True Dual Port RAM
128489: 08/01/28: Re: My first Flash FPGA
128503: 08/01/29: Re: My first Flash FPGA
makmorbi:
52713: 03/02/19: FPGA's at High Temperatures
67654: 04/03/16: Re: Quartus II 4.0 Web Edition Software & Documentation - Available for download
70314: 04/06/11: Low Power FPGA Design Seminar
73368: 04/09/20: Altera Max II
Makoto Honda:
54461: 03/04/11: Re: Dynamic Reconfigurable FPGAs
Malachy Devlin:
16372: 99/05/19: Re: Virtex based PCI cards
16424: 99/05/21: Re: Virtex based PCI cards
19062: 99/11/26: Programming Virtex device via JTAG
20919: 00/02/28: PCI 64 bit / 66 MHz
22673: 00/05/17: appropriate ASIC Prototyping Board
22674: 00/05/17: Reccomend an ASIC emulation board
Malcolm Bugler:
6994: 97/07/20: AM186 to P/C104 PLD design
Malcolm Reeves:
28457: 01/01/13: ANN: Test Bench tool V2.01 - powerful and cheap
malgi:
47876: 02/10/06: Re: Low power design
<malino@primenet.com>:
18763: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
19008: 99/11/23: Re: VHDL vs. schematic entry
Malki:
14703: 99/02/12: Re: Board for XC4085XL
mammo:
101836: 06/05/07: Funky experiment on a Spartan II FPGA
101839: 06/05/07: Re: Funky experiment on a Spartan II FPGA
101857: 06/05/07: Re: Funky experiment on a Spartan II FPGA
Mamoon Hamid:
16276: 99/05/12: Re: Can use pullup in XC9500XL?
mamtachalana:
70610: 04/06/21: system verilog
mamu:
132140: 08/05/15: Re: Camera link interface
man cheng:
5207: 97/01/31: What is the different between FPGA and CPLD?
Man`y:
6974: 97/07/18: looking for a contract opening
Manan:
20476: 00/02/11: HELP ! Problems in mapping
<manan.kathuria@gmail.com>:
79941: 05/02/26: setup-hold time problems
<Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>>:
48581: 02/10/21: Nios and quartus linux version
48655: 02/10/22: Re: Nios and quartus linux version
48979: 02/10/28: Leonardo and lpm (Altera)
49791: 02/11/21: Altera Logick lock newbie
49912: 02/11/25: Re: Altera Logick lock newbie
54918: 03/04/22: Re: quartus_cmd under Linux
57892: 03/07/09: Xilinx price question
Mancini Stephane:
60991: 03/09/26: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61421: 03/10/03: Re: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61815: 03/10/13: Quartus 2.2, SOPC builder and leonardo
61850: 03/10/14: Re: Quartus 2.2, SOPC builder and leonardo
62212: 03/10/22: NIOS simulation with modelsim -> strange behaviour
64263: 03/12/23: Avnet Virtex II Pro Dvpt board : linux drivers ??
65219: 04/01/22: Virtex II Pro, powerpc 405 and ucOSII
67588: 04/03/15: Virtex II Pro default I/O mode
68603: 04/04/09: I2C bus and tristate interface for V2pro
72890: 04/09/07: EDK 3.2 and modelsim ppc simulation
73060: 04/09/13: Re: EDK 3.2 and modelsim ppc simulation
73067: 04/09/13: Xilinx EDK and plb master
73113: 04/09/14: Re: Xilinx EDK and plb master
73272: 04/09/17: Xilinx EDK & IPIF performance
75395: 04/11/04: Xilinx EDK PLB/OPB bridge (and IPIF)
87162: 05/07/18: EDK and powerpc-eabi compiler
89448: 05/09/15: Xilinx V2Pro & SATA hard disk
89454: 05/09/15: Re: Xilinx V2Pro & SATA hard disk
<mandana@physics.ubc.ca>:
85462: 05/06/09: JTAG programming: JAM files versus ISC (IEEE1532) files
85719: 05/06/14: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
85816: 05/06/16: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
Mandeep Singh:
15583: 99/03/31: Reconfigurable Computing
Mandilas Antony:
56714: 03/06/12: error compiling
57385: 03/06/29: clock signals
57386: 03/06/29: memory
57387: 03/06/29: Re: memory
MANDY & DOUGLAS:
39204: 02/02/04: Re: RAM question
40010: 02/02/25: Re: IIR. convolution
<maneri@my-dejanews.com>:
15539: 99/03/29: PAMette for Rapid Prototyping
15644: 99/04/05: Re: How to implement Matched Filter in FPGA?
Manfred Aigner:
3381: 96/05/23: XACT Memgen + Mentor
3438: 96/05/30: Re: how to use memgen
3498: 96/06/11: Double Port Ram - Xact Libs
3559: 96/06/21: Routing
Manfred Balik:
62331: 03/10/27: Altera ACEX1K configuration and initialisation
63212: 03/11/18: Re: Acek 1K - Quartus II - timing issues
67699: 04/03/17: PC104 Evaluation Board
71261: 04/07/13: Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif
71745: 04/07/29: Re: Implementing control registers (VHDL)
72577: 04/08/25: Altera Quartus II 4.1 double-click on QPF-File doesn't work
72928: 04/09/08: i2c-core from opencores.org
75680: 04/11/12: DualPortRAM serial IN - parallel OUT
80182: 05/03/02: Altera APEX20KE clock problem
80289: 05/03/03: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
80334: 05/03/04: Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
86961: 05/07/11: output-value isn't stored
89340: 05/09/13: Migration Altera APEX20KE to ???
91449: 05/11/07: which Altera CPLD?
92082: 05/11/22: Quartus Problem
96248: 06/02/01: Re: Quartus Fitter Warning
104150: 06/06/20: Quartus 6.0 Fitter Critical Warning
104188: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
104203: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
107782: 06/09/01: bidirectional connection between two bidirectional ports
107801: 06/09/01: Re: bidirectional connection between two bidirectional ports
108078: 06/09/05: Re: bidirectional connection between two bidirectional ports
108082: 06/09/05: Re: bidirectional connection between two bidirectional ports
112536: 06/11/24: Altera MAX3000A OE and GCLR-Pins
112647: 06/11/27: Re: Altera MAX3000A OE and GCLR-Pins
113725: 06/12/20: CPLD speed/temperature equivalent
114127: 07/01/05: Altera Cyclone II die revision?
116722: 07/03/16: old Quartus project files
118176: 07/04/19: Altera M4K memory usage
118181: 07/04/19: Re: Altera M4K memory usage
Manfred Kraus:
10909: 98/06/30: Re: Xilinx file compression
10994: 98/07/09: Re: question on combinational logic synthesis for FPGA
12014: 98/09/24: Re: How to reduce ringing/ground bounce from FPGA output pin?
12881: 98/11/03: Re: New free FPGA CPU
12883: 98/11/03: Re: Digital Sine Generator
13067: 98/11/14: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
14419: 99/01/29: Re: PLL in FPGA
14658: 99/02/09: Re: dual port RAM on XC4000
19131: 99/12/01: data serializer/decoder FPGA solution
19148: 99/12/02: Re: data serializer/decoder FPGA solution
25993: 00/09/29: Xilinx Logicore Generator
28575: 01/01/17: Re: Looking for prototyping board
28640: 01/01/19: Re: Best design for asyn. interface DSP <-> FPGA?
29835: 01/03/13: 64 simultan A/D Converters in an SPARTAN-II
29846: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
32534: 01/06/29: Re: FPGA Boards
32673: 01/07/04: clock frequency synthesizer for FPGA
32726: 01/07/06: Re: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
32734: 01/07/06: Re: Xilinx PCI development board
35428: 01/10/04: CoreGenerator and WebPack ISE
35550: 01/10/10: Re: CoreGenerator and WebPack ISE
35647: 01/10/12: Re: PWM Signal in VHDL ?
36096: 01/10/29: Re: University project: DSO
36567: 01/11/12: Re: Quadrature Encoder Sampling Time
39950: 02/02/22: Replacing expensive configuration SPROM
40460: 02/03/07: Re: DDR-Interface
40755: 02/03/14: Re: use virtex2 DCM as delay line
40756: 02/03/14: Re: Xilinix FPGA width 5V IO
40757: 02/03/14: Re: Proto boards for labs
40991: 02/03/19: Re: 1,5V power supply?
40992: 02/03/19: Re: virtex 2 orcad symbols?
40993: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
40995: 02/03/19: Re: Xilinx JTAG Cables
42230: 02/04/18: Re: fpga limitation
42421: 02/04/23: Re: Prototyping Boards for Hobbyist CPU/System Designs
42652: 02/04/30: Re: Frequency synthesiser
42823: 02/05/03: Re: Frequency synthesiser
42824: 02/05/03: DDR SDRAM controller for VIRTEX-II
43968: 02/06/07: Re: Problem with spartan2 vhdl code
44014: 02/06/10: Re: Looking for FPGA board with USB interface
44302: 02/06/17: Which Synthesis tool for XILINX
44338: 02/06/18: Re: Which Synthesis tool for XILINX
44339: 02/06/18: Re: Which Synthesis tool for XILINX
44347: 02/06/18: Re: Pls Recommend a Development Board - Have you checked out the CESYS boards ?
44401: 02/06/19: Re: Pls Recommend a Xilinx development Board
44700: 02/06/27: Re: Applying voltage to FPGA I/O while FPGA is not powered
44916: 02/07/05: Re: Routing Virtex-II 256 pin BGA on 4 layers
44962: 02/07/08: Re: Newbie FPGA recommedation
45302: 02/07/18: Re: Advice on tools and question on Virtex2
45611: 02/07/29: Re: Programming FLASH with Xilinx Parallel Cable III
45612: 02/07/29: Re: secure FPGA
45728: 02/08/02: Re: lots of shift registers
46073: 02/08/16: Re: Fun FPGA system
46074: 02/08/16: Re: Testing the X2S_USB Spartan 2 board
54341: 03/04/08: Re: Power Supply for Spartan II FPGA
56481: 03/06/06: Re: Virtex 2 evaluation board
56482: 03/06/06: Re: Level Converters
56665: 03/06/11: A way to copy Modelsim waveforms into word documents
56674: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
56675: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
57642: 03/07/03: Spartan-3 availability
57648: 03/07/03: Re: Spartan-3 availability
57713: 03/07/04: Re: Spartan-3 availability
59103: 03/08/08: Re: clock management on SPARTAN2
60418: 03/09/12: Re: CMOS camera w/ USB2 -- crazy?
64163: 03/12/18: Re: Spartan3 availability
64780: 04/01/13: Re: SDRAM Controller timing problem
65801: 04/02/06: Virtex-3 PRO
66535: 04/02/21: Re: Can FPGA bootstrap itself?
66782: 04/02/26: Re: Suggestions: Eval/Demo Board.
88405: 05/08/17: Re: Easy USB2.0 hi-speed device solutions ?
120619: 07/06/12: Re: Affordable pcie card ?
Manfred Kuhland:
21013: 00/03/02: Re: Error in Xilinx application note XAPP131?
Manfred Muecke:
43570: 02/05/24: SOPC for machine vision
43572: 02/05/24: Re: SOPC for machine vision
43608: 02/05/27: Re: SOPC for machine vision
72409: 04/08/18: Re: What schematic tool (VHDL) is the best?
72422: 04/08/18: Re: What schematic tool (VHDL) is the best?
80776: 05/03/11: Re: New in C to RTL
<manfredk@internode.on.net>:
130245: 08/03/18: Re: vhdl type conversions
Manfredo:
26864: 00/11/01: Re: I need some VHDL/Synthesis Design BOOK recommendations!!
mani:
129724: 08/03/03: reconfiguration of virtex 2 pro
Manish:
75541: 04/11/08: FPGA as "Differential SSTL_2" clock driver
75577: 04/11/10: Re: FPGA as "Differential SSTL_2" clock driver
98272: 06/03/07: Crosstalk Analysis on a FPGA
Manish_Shrivastava:
14062: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14179: 99/01/18: Re: Reed-Muller99 CFP
<manishr@softjin.com>:
81960: 05/04/05: DCM LOCKED as reset
Manjunath:
35331: 01/09/29: Re: Meta-stability
manjunath.rg@gmail.com:
98300: 06/03/08: FPGA imple. of aes
98376: 06/03/08: Re: FPGA imple. of aes
98504: 06/03/11: Re: FPGA imple. of aes
98563: 06/03/12: Re: FPGA imple. of aes
MANJUNATHAN:
29944: 01/03/19: about placement and routing
Manjunathan:
29922: 01/03/16: about core generator
30104: 01/03/22: PLACE and ROUTE
30108: 01/03/23: Timing analysis after implementation
30272: 01/03/30: VIRTEX BLOCK RAM
30332: 01/04/03: to add macro in the design
33775: 01/08/04: how to replicate the Logic through VHDL attribut ?
33823: 01/08/06: how to give timing constraint in an hierarchy des
34008: 01/08/10: how to acheive high frquency in Xinlinx Virtex E
35303: 01/09/27: Meta-stability
<mankin18@gmail.com>:
113905: 06/12/28: SPI slave problem
113909: 06/12/28: Re: SPI slave problem
113916: 06/12/29: Re: SPI slave problem
113917: 06/12/29: Re: SPI slave problem
114020: 07/01/02: Re: SPI slave problem
114025: 07/01/02: Re: SPI slave problem
Mankit Wong:
7421: 97/09/09: Re: Which FPGA ?
11403: 98/08/11: Re: Gray code counter in ABEL HDL?
11616: 98/08/27: Re: CPLD/FPGA software
12770: 98/10/29: 8051 VHDL Model
17550: 99/08/10: Re: Lattice cable for 2032?
manmohan singh:
67155: 04/03/07: licence for Xilinx 2.1i
67306: 04/03/09: Re: licence for Xilinx 2.1i
mann!:
79950: 05/02/26: Re: setup-hold time problems
79969: 05/02/27: maximum frequency of operation
79970: 05/02/27: maximum freq of operation of a circuit
Mann`y:
3634: 96/07/05: Looking for a PCI bus model
4938: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4943: 97/01/03: Usb Cores ( synthesisable ) and ( simulation models )
Manny:
110240: 06/10/12: Glitches in post-layout (PAR) simulation
110249: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110255: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110259: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110262: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110263: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110265: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110307: 06/10/13: Xilinx FPGAs in battery-powered scenarios
110317: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110344: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
111894: 06/11/12: Xilinx platform cable USB
111994: 06/11/14: Re: Xilinx platform cable USB
113822: 06/12/23: IEEE fixed-point package FATAL_ERROR
115118: 07/01/31: Synthesis of DSP algorithms
115274: 07/02/05: Re: moving data from slower to faster clock domain
116340: 07/03/07: Re: Query regarding Project.Plz help very urgent
116372: 07/03/07: Re: Introducing picosecond delay between two output signals
118326: 07/04/23: Slave PLB core interrupt
118364: 07/04/24: Re: Slave PLB core interrupt
118645: 07/05/01: Read 64-bit value over PLB
118956: 07/05/08: Re: Read 64-bit value over PLB
119000: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119140: 07/05/12: downto usage in EDK
119310: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119312: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119314: 07/05/16: Re: seeking insights for potential reconfigurable computing application platforms
120279: 07/06/04: System Generator installation
120775: 07/06/15: Simulating analogue signal using ISE simulator
120795: 07/06/16: Re: Simulating analogue signal using ISE simulator
123245: 07/08/21: Re: Synthesizing fixed_pkg in ISE 9.2
123246: 07/08/21: Spartan-3A DSP vs. Cyclone III Power-wise
123285: 07/08/22: Re: Spartan-3A DSP vs. Cyclone III Power-wise
124229: 07/09/14: Virtex II pro design question
124236: 07/09/15: Re: Virtex II pro design question
124422: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124424: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
125035: 07/10/15: Re: FPGA quiz: what can be wrong
125054: 07/10/15: Re: FPGA quiz: what can be wrong
125066: 07/10/16: Re: FPGA quiz: what can be wrong
125078: 07/10/16: Re: FPGA quiz: what can be wrong
125156: 07/10/16: gold code - seed value
134496: 08/08/13: XMD & Ultracontroller
Manoj Chaubal:
2170: 95/10/25: Re: PLD in small package ?? anyone
2418: 95/12/02: New ALDEC tools for XACT 6.0
Manoj K Krishnan:
33667: 01/08/01: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
manoj.rajpoot@gmail.com:
105084: 06/07/13: Routing Information of Xilinx's Virtex-II FPGA
<manolete@discontrol.net>:
123393: 07/08/27: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
Manolis Stratakis:
4498: 96/11/06: PCB Handling of chip packages greater than 100 pins?
Manpreet:
99754: 06/03/28: Re: need help,test on Spartan3 starter kit
99755: 06/03/28: how to immitate clock behavior----Please guide
mans (myname_here):
118024: 07/04/16: Matlab Simulink HDL coder generated code interface.
118112: 07/04/17: creating library in ISE 9
118130: 07/04/18: ISE Smart Ident
118133: 07/04/18: Compiling a library
118167: 07/04/18: VHDL source code for polyphase filter
118184: 07/04/19: Re: VHDL source code for polyphase filter
118281: 07/04/21: simulating with OSe 9.1.3
118294: 07/04/23: VHDL editing with UltraEdit
118382: 07/04/25: Re: VHDL editing with UltraEdit
mans (use_my_name_here):
117438: 07/03/30: Sysgen compilation target
117753: 07/04/09: record type port in vhdl and simulation in ISE
Mansih Mahajan:
15982: 99/04/24: Looking for FPGA/ASIC design/verification position
Mansoor Naseer:
54518: 03/04/12: Some suggestions on system design on PCB
mansoor.naseer@gmail.com:
83218: 05/04/26: PCI plug n play and Graphics card implementation
manu:
99235: 06/03/21: Re: BRAM for virtex-4
99634: 06/03/27: Re: C-based FPGA programming/mixed languages
99976: 06/03/31: Re: ISE 8.1, EDK 8.1 installation
100332: 06/04/07: Re: xilinx xc2vp30
100337: 06/04/07: Re: OPB master
105431: 06/07/22: version control of ISE+EDK projects with CVS and/or SVN
Manuel:
55823: 03/05/20: modulators and demodulators help
Manuel Alejandro Jimenez-Cede:
718: 95/02/16: Looking for Tech Info
Manuel Bessler:
95247: 06/01/21: Re: Raggedstone specifications ...
95813: 06/01/26: Re: Spartan-3 Starter Board
Manuel Gericota:
46190: 02/08/21: ERA60100 Data Sheet
Manuel Zaera Sanz:
47305: 02/09/23: MTBF
<manuel-lozano@mixmail.com>:
115254: 07/02/05: problem with microblaze gcc toolchain
117473: 07/04/01: broken mb-gcc -O2 ?
117482: 07/04/02: Re: broken mb-gcc -O2 ?
122722: 07/08/04: mb-gdb: problem simulating memory mapped i/o devices
129743: 08/03/04: FPGA for a DVB common interface implementation
129744: 08/03/04: FPGA for a DVB common interface implementation
133524: 08/07/02: minipci breadboard with fpga
133541: 08/07/03: Re: minipci breadboard with fpga
<manuel.bessler@gmail.com>:
94874: 06/01/18: Re: Raggedstone specifications ...
<manygates>:
72483: 04/08/20: GAL,PAL,PLD, CPLD,FPGA
72487: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72501: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72502: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
2mao:
115215: 07/02/02: Re: Xilinx Interconnects/Routing
<mar@tcelectronic.com>:
18791: 99/11/16: Re: Need advice on interfacing SDRAM modules
marada:
110987: 06/10/26: Re: Microblaze : FSL bus
112649: 06/11/27: Re: Microblaze : FSL bus
Marc:
26922: 00/11/03: Re: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
28929: 01/01/30: Clocking system with CPLD? - timing.JPG (0/1)
29096: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29097: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (1/1)
29119: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29121: 01/02/06: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29124: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
37877: 01/12/22: Beginners question: several circuits in one chip
38166: 02/01/08: Re: Suitability of Atmel for project?
61996: 03/10/16: Re: Running Quartus II on ReadHat Linux 9.0
62626: 03/11/03: Re: Altera "my support" :-(
64219: 03/12/21: Re: advantages of ethernet MAC ip core
64320: 03/12/28: Re: advantages of ethernet MAC ip core
67776: 04/03/18: Re: Problems with Memory Initialization Files in Modelsim
68969: 04/04/23: 64-bit SODIMM module on 32-bit SDRAM-controller?
71427: 04/07/18: Re: FPGA Development board with onboard Ethernet PHY
71820: 04/08/01: Re: FPGA prototype board with ethernet interfaces
73541: 04/09/23: Cyclone FPGA as Cardbus controller
82972: 05/04/20: Re: Differential timing specification in Xilinx FPGA
83811: 05/05/07: Re: Parallel Cable IV opened in "Compatibility Mode"
87052: 05/07/13: Re: Virtex 300: what could cause pin to short?
marc:
33351: 01/07/24: Register Chain
Marc 'Nepomuk' Heuler:
6903: 97/07/07: Re: Generating Sine/Cosine digitally
7836: 97/10/20: Re: Download Cable