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Messages from 102075

Article: 102075
Subject: CoolRunner XPLA3 getting axed?
From: Eli Hughes <emh203@psu.edu>
Date: Wed, 10 May 2006 08:58:43 -0400
Links: << >>  << T >>  << A >>
Is the coolrunner XPLA3 getting axed? I noticed that it is no longer a 
link on the xilinx font page.   The online store does not list them on 
the front page(only Cool runner II and the XC9500 Series).   Its also 
slim pickens' when you do find the part you need on Avnet or Nuhorizons. 
Digikey is horrible for Xilinx Now.

When I see this with other IC/MCU vendors I get scared.  I really like 
these chips.  The Cool Runner II series is great but I really dont like 
having the 1.8v Core Requirement (at least with lower speed logic).

I work at a University Research Lab where we typical build 10 or 20 of a 
design before passing it off to a sponsor.  It seems that lately I have 
to *really* pick through to see what is avaialble online before I do a 
design as the chips always seem to be out of stock.

Are all the other brands (Brand A, Brand L) like this as well?  Or 
should I just stop complaining.  I do love the technology but it seems 
that I spend more time finding parts than writing HDL.


Thanks
-Eli

Article: 102076
Subject: [Newbie] 64-point complex FFT with 32 bit floating-point representation
From: "Franco Tiratore" <trapule@googlemail.com>
Date: 10 May 2006 06:01:06 -0700
Links: << >>  << T >>  << A >>
Hi all.

I'm currently trying to understand whether or not it is possible to
implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
As far as I understand, the critical part of the project is the
64-point complex FFT with 32 bit floating-point representation (each
real or complex number is represented in 32-bit floating-point). The
FFT block should perform this calculation in no more than 2.5 us.
I'm not an expert in this field, can anyone help me to understand
whether or not this performance is achievable with the FPGAs currently
available on the market? If yes: can you address me to some specific
FPGA model? If not: what is the critical part of my specifications? (I
suppose the time delay and the floating point spec).

This is only one of my current doubts.
I hope we can start a profitable discussion. :-)

Ciao,
Franco


Article: 102077
Subject: Altera Equiv.
From: Eli Hughes <emh203@psu.edu>
Date: Wed, 10 May 2006 09:02:29 -0400
Links: << >>  << T >>  << A >>
I have a question for those experienced with Altera devices.  Could 
someone please identify (roughly) the Brand A equivilents of these brand 
X parts:

CoolRunner II
Spartan 3/3e
Virtex II

I am not trying to be a flame baiter, but I would really like to hear 
other people's thoughts of Altera's equivlents.  I used to use the 
Altera CPLD (MAX7000) a long time ago and had a good experience.  What 
are the FPGA devices like.


Thanks again.
-Eli

Article: 102078
Subject: Re: Quartus II 6.0 available
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 10 May 2006 13:03:40 GMT
Links: << >>  << T >>  << A >>
Leon <leon.heller@bulldoghome.com> wrote:
>Quartus II 6.0 is now available, I downloaded the Web Edition
>yesterday. I'm on the Altera mailing list but I don't remember seeing
>any notification of the new version. It worked OK when I tried it on a
>couple of small projects.

Only the linux version missing then ;)


Article: 102079
Subject: Re: Programming the JTAG flash in circuit
From: "dscolson@rcn.com" <dscolson@rcn.com>
Date: 10 May 2006 06:06:46 -0700
Links: << >>  << T >>  << A >>
Another software package is JDrive from Xilinx. I was able to modify it
to work with my system. JDrive uses the IEEE1532 standard. This allows
the programming algorithm, which is contained in a seperate file, to
change  while not effecting the program data.


Article: 102080
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Wed, 10 May 2006 15:10:55 +0200
Links: << >>  << T >>  << A >>
JJ wrote:
> Luke wrote:
> 
>>I must not have been very clear.  The 180MHz version had no bypassing
>>logic whatsoever.  It had three delay slots.  The 150MHz version did
>>have bypassing logic, it had one delay slot.
>>
>>I read up on carry lookahead for the spartan 3, and you're correct, it
>>wouldn't help for 16-bits.  In fact, it's slower than just using the
>>dedicated carry logic.
> 
> 
> I also used a 32b CSA design in the design prior to one described
> above. It worked but was pretty expensive, IIRC it gave me 32b adds in
> same cycle time as 16b ripple add but it used up 7 of 8b ripple add
> blocks and needed 2 extra pipe stages to put csa select results back
> together and combined that with the CC status logic. The 4 way MTA
> though just about took it without too much trouble but it also needed
> hazard and forwarding logic. Funny thing I saw was the doubling of
> adders added more C load to the pipeline FFs and those had to be
> duplicated as well and so the final cost of that 32 datapath was
> probably 2 or 3 x bigger than a plain ripple datapath and much harder
> to floorplan the P/R.
> 
> What really killed that design was an interlock mechanism designed to
> prevent the I Fetch and I Exec blocks from ever running code from same
> thread at same time, that 1 little path turned out to be 3 or 4 x
> longer than the 32b add time and no amount of redesign could make it go
> away, all that trouble for nout. The lesson learned was that complex
> architecture with any interlocks usually gets hammered on these paths
> that don't show up till the major blocks are done. The final state of
> that design was around 65MHz when I thought I would hit 300MHz on the
> datapath, and the total logic was about 3x the current design. Not much
> was wasted though, much of the conceptual design got rescued in simpler
> form. In an ASIC this is much less of a problem since transistor logic
> is relatively much faster per clock freq than FPGAs, it would have been
> more like 20 gates and ofcourse the major cpu designers can throw
> bodies at such problems.
> 
> I wonder how you will get the performance you want without finding an
> achilles heal till the later part is done. You have to finish the
> overall logic design before commiting to design specific blocks and it
> ends up taking multiple iterations. When I said 25MHz in the 1st post I
> meant that to reflect these sorts of critical paths that can't be
> forseen till your done rather than the datapaths. Thats why I went to
> the extreme MTA solution to abolish or severely limit almost all
> variables, make it look like a DSP engine and you can't fail.
> 
> Curiously how do you prototype the architecture, in cycle C, or go
> straight to HDL simulation?
> 
> Anyway have fun
> 
> John Jakson
> transputer guy
> 
> the details are at wotug.org if interested
> 

I personally use paper and pen.
I draw the datapath functionality and think about how they will map into 
Xilinx FPGA structures while drawing and designing.
I like to have large papers so I can draw timing diagrams on the same page.
Only when I have some design which I believe would be reasonable I start 
to code.

When I think more about it then I realize that my most used design tool 
is still the paper and pen.

Göran




Article: 102081
Subject: Re: CoolRunner XPLA3 getting axed?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 10 May 2006 15:22:45 +0200
Links: << >>  << T >>  << A >>
Eli Hughes schrieb:

> Are all the other brands (Brand A, Brand L) like this as well?  Or 
> should I just stop complaining.  I do love the technology but it seems 
> that I spend more time finding parts than writing HDL.

So it may be a good idea to "waste" a few cents and minutes to add a 
linear regulator for 1.8V instead of wasting hours to get not easy 
availabe parts. This hold especially true for a handfull of boards. For 
hundreds or thousands, this is another story.

Regards
Falk

Article: 102082
Subject: Re: CoolRunner XPLA3 getting axed?
From: Eli Hughes <emh203@psu.edu>
Date: Wed, 10 May 2006 09:39:03 -0400
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> Eli Hughes schrieb:
> 
>> Are all the other brands (Brand A, Brand L) like this as well?  Or 
>> should I just stop complaining.  I do love the technology but it seems 
>> that I spend more time finding parts than writing HDL.
> 
> 
> So it may be a good idea to "waste" a few cents and minutes to add a 
> linear regulator for 1.8V instead of wasting hours to get not easy 
> availabe parts. This hold especially true for a handfull of boards. For 
> hundreds or thousands, this is another story.
> 
> Regards
> Falk


I guess my frustration goes beyond the Cool Runnerm.  Take the Spartan 
3e.  Its been advertised on the website as the greast thing since sliced 
bread for *over* a year now.  I am sure its a nice chip.  I have been 
wanting to use it.   Click on the online store and select say the 
XC3S100E.   Its says special Qty.  Lead Time Call......   Its obvious 
that there is a diconnect between Marketing and Engineering/Development. 
  I dont mind delays, etc.  Just be up front about.


Article: 102083
Subject: Re: CoolRunner XPLA3 getting axed?
From: "dp" <dp@tgi-sci.com>
Date: 10 May 2006 06:42:00 -0700
Links: << >>  << T >>  << A >>
> So it may be a good idea to "waste" a few cents and minutes to add a
> linear regulator for 1.8V instead of wasting hours to get not easy
> availabe parts.

The thing is, how do you know which will be easily available tomorrow.
They discontinued the old coolrunner from Philips for purely political
reasons, how do you know what will suit them tomorrow. As long
as one firm - no matter which - has monopoly over a technology
things don't look good for us users...
(there is no competitive technology to the coolrunner on the market,
in case you did not know that) .
But then again, as long as there are reasonable people like Peter
and Austin at Xilinx - although I suspect they are a minority - there
is always hope one can eventually get a job done.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

Falk Brunner wrote:
> Eli Hughes schrieb:
>
> > Are all the other brands (Brand A, Brand L) like this as well?  Or
> > should I just stop complaining.  I do love the technology but it seems
> > that I spend more time finding parts than writing HDL.
>
> So it may be a good idea to "waste" a few cents and minutes to add a
> linear regulator for 1.8V instead of wasting hours to get not easy
> availabe parts. This hold especially true for a handfull of boards. For
> hundreds or thousands, this is another story.
> 
> Regards
> Falk


Article: 102084
Subject: Re: Xilinx 3s8000?
From: christopher.saunter@durham.ac.uk (c d saunter)
Date: Wed, 10 May 2006 13:57:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
=?ISO-8859-1?Q?Michael_Sch=F6berl?= (MSchoeberl@mailtonne.de) wrote:

: Do you say that this would still run at full speed?
: has anyone tried this?

: I suspect the emulation takes quite some ressources ...

Running an x86 virtual PC on an x86 host can use virtualization where most 
code (non priveledged stuff etc.) runs nativly, so there is a much less 
significant performance hit than with emulation.

You need a lot of memory though as both the host and guest OS' memory 
requirements must be fulfilled.

Also the old tools will have been used with older, slower PCs so will get 
a speed bost from the modern PC which probably offsets the virtualization 
overhead.

Where the VM aproach falls down is where you have software that is locked 
to some physical dongle...

cds

Article: 102085
Subject: Re: CoolRunner XPLA3 getting axed?
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 10 May 2006 13:59:03 GMT
Links: << >>  << T >>  << A >>
>I guess my frustration goes beyond the Cool Runnerm.  Take the Spartan 
>3e.  Its been advertised on the website as the greast thing since sliced 
>bread for *over* a year now.  I am sure its a nice chip.  I have been 
>wanting to use it.   Click on the online store and select say the 
>XC3S100E.   Its says special Qty.  Lead Time Call......   Its obvious 
>that there is a diconnect between Marketing and Engineering/Development. 
>  I dont mind delays, etc.  Just be up front about.

Check the store first, and then the specs?
Most engineers ought to know the substance of marketing by now =)


Article: 102086
Subject: Re: Unreactive Output Pins on Xilinx Virtex-II
From: "Robin Emery" <Robin.Emery@gmail.com>
Date: 10 May 2006 07:08:03 -0700
Links: << >>  << T >>  << A >>
Thank you all for your help.

I thought it might be helpful to post a quick conclusion...

With the use of ChipScope, we found that the problem was a timing error
of sorts: an asynchronous (from the POV of the FPGA) control input from
the parallel port was not synchronised in the design, resulting in a 1
in 10 failure rate (the rate was related to the CE input to some of the
flip-flops). Adding this to the VHDL fixed the problem ;-)

Many thanks,
Robin


Article: 102087
Subject: Re: Xilinx 3s8000?
From: Ron <News5@spamex.com>
Date: Wed, 10 May 2006 07:22:27 -0700
Links: << >>  << T >>  << A >>
Before abandoning this thread, I thought I would cobble together a 
72*72->144 multiplier using the 3s500's built-in 18*18->36 bit hardware 
multipliers. The result is shown below. As you can see, more slices and 
LUT's are required when using the built-in hardware multipliers than by 
the same width multiplier written in pure Verilog, *but* the frequency 
is also faster.

     Device utilization summary:
     ---------------------------
     Selected Device : 3s500epq208-4
      Number of Slices:                     817  out of   4656    17%
      Number of Slice Flip Flops:           669  out of   9312     7%
      Number of 4 input LUTs:              1094  out of   9312    11%
      Number of bonded IOBs:                 18  out of    158    11%
      Number of MULT18X18s:                  16  out of     20    80%
      Number of GCLKs:                        1  out of     24     4%

     Timing Summary:
     ---------------
     Speed Grade: -4
        Minimum period: 12.982ns (Maximum Frequency: 77.033MHz)
        Minimum input arrival time before clock: 10.583ns
        Maximum output required time after clock: 8.062ns
        Maximum combinational path delay: No path found

It's a little hard to believe that the circuit design using the builtin 
multipliers actually requires more FPGA space than doing the whole thing 
in Verilog, so I've pasted the Verilog source code that I wrote to test 
the hardware multipliers into this message below. As you can see, the 
synthesizer automatically chooses to use the builtin MULT18X18s simply 
because I specified an 18*18 bit multiply in the Verilog code (see 
m36.v) without requiring me to explicitely instantiate the MULT18X18 
multipliers by name.

There are three modules. They are:
1. m36.v
2. m72.v
3. main.v

"main.v" is a simple I/O interface for MX_72 which is the main 
multiplier. The only reason for having "main" is so that the synthesizer 
won't complain about running out of I/O pins. Let me know if you're able 
to cut down on the gate count significantly. I already know I could 
probably eliminate one or two temporary registers I used in MX_72, but 
doubt it would make much difference.

Regards,

Ron


//================= m72.v =================
// m72.v, (c) May 9, 2006, Ron Dotson

module MX_72 (reset,clock,a,b,  r,finished);
parameter N=72;  // Bus Width of input
parameter L=36;  // Half the Bus Width
parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7;
input       reset, clock;
input       [N-1:0] a,b;
output reg  [2*N-1:0] r;
output reg  finished;

reg         resetMX;
reg         [1:0] state;
reg         [L-1:0] a1,b1, a2,b2;
reg         [2*N-1:0] t1,t2,t3;
wire        [N-1:0] r1,r2,r3,r4;
wire        finished1,finished2,finished3,finished4;

MX_36 m1 (resetMX,clock,a1,b1,  r1,finished1);
MX_36 m2 (resetMX,clock,a1,b2,  r2,finished2);
MX_36 m3 (resetMX,clock,a2,b1,  r3,finished3);
MX_36 m4 (resetMX,clock,a2,b2,  r4,finished4);

always @(posedge clock)
if (reset==1)
     begin
     finished<= 0;
     resetMX<= 0;
     a2<= a[N-1:L];  // MSB a
     a1<= a[L-1:0];  // LSB a
     b2<= b[N-1:L];  // MSB b
     b1<= b[L-1:0];  // LSB b
     t1<= 0;
     t2<= 0;
     t3<= 0;
     state<= S0;
     end
else
     begin
     case (state)
         S0: begin
             resetMX<= 1;
             state<= S1;
             end
         S1: begin
             resetMX<= 0;
             state<= S2;
             end
         S2: begin
             if (finished1 & finished2 & finished3)
                 begin
                 t1[N-1:0]<= r1;
                 t1[2*N-1:N]<= r1[N-1]? -1: 0;  // extend sign
                 t2[2*N-1:L]<= r2 + r3;
                 t3[2*N-1:N]<= r4;
                 state<= S3;
                 end
             end
         S3: begin
             r<= t1 + t2 + t3;
             finished<= 1;
             end
     endcase
     end

endmodule

//================= m26.v =================
// m36.v, (c) May 9, 2006, Ron Dotson

module MX_36 (reset,clock,a,b,  result,finished);
parameter N=36; // Bus Width of input

input       reset, clock;
input       [N-1:0] a, b;
output reg  [2*N-1:0] result;
output reg  finished;

always @(posedge clock)
if (reset==1)
     begin
     finished<= 0;
     end
else
     begin
     result<= a*b;  // instantiates builtin h/w multiplier
     finished<= 1;
     end

endmodule

//================= main =================
// main.v, I/O interface
// (c) Jan 14, 2006, Ron Dotson

// Note: Need bus-width of 576 bits to solve "Most Wanted"
//       Cunningham numbers at:
//       http://homes.cerias.purdue.edu/~ssw/cun/want97
//
// SW2= A19(1) = resetMain    Expected  Was
// D1 = G1(7)= Led0  (~LD0)       X      X     D1
// D2 = G2(7)= Led1  (~LD1)       X      0     D2
// D3 = H1(7)= Led2               1      1     D3
// D4 = H2(7)= Led3  (Data bit 0) 1      1     D4
// D5 = J1(7)= Led4  (Data bit 1) 1      1     D5
// D6 = J2(7)= Led5  (Data bit 2) 0      0     D6
// D7 = K1(7)= Led[6]             1      1     D7
// D8 = K2(7)= Led[7]             1      1     D8

module main(resetMain,clock,Sw[7:0],  Led[7:0]);
parameter N=72;  // Bus Width of input
parameter L=36;  // Half the Bus Width
parameter S0=0,S1=1,S2=2,S3=3;
input      resetMain, clock;
input      [7:0] Sw;
output reg [7:0] Led;

reg        mReset;
reg        [1:0] state;
reg        [N-1:0] a,b;
wire       [2*N-1:0] r;             // 72*72->144
wire       finished, LD1,LD0;

MX_72 mx72 (mReset,clock,a,b,  r,finished);

always @(posedge clock)
if (~resetMain)             // SW2 = Low when pressed
     begin
     mReset<= 1;
     Led[7:0]<= -1;          // Leds OFF
     state<= S0;

//  a<= 17;  b<= 13;      // Test Case 1
//  a<= 137; b<= 223;     // Test Case 2
//  a<= 157; b<=223;      // Test Case 3
//  a<= 33013; b<= 35023; // Test Case 4

// Test Case 5
     a[ 71: 64]<= 8'hA9;
     a[ 63: 32]<= 32'h7B78BE29;
     a[ 31:  0]<= 32'h9C540469;

     b[ 71: 64]<= 8'h9B;
     b[ 63: 32]<= 32'hE4BB0E99;
     b[ 31:  0]<= 32'h19425200;
     end
else
     begin
     case (state)
     S0: begin
         mReset<= 1;
         Led[2]<=1;       // OFF
         state<= S1;
         end
     S1: begin
         if (mReset)
             mReset<= 0;
         else
             begin
             Led[2]<= ~Led[2];
             Led[0]<= ~LD0;
             Led[1]<= ~LD1;
             if (finished)
                 begin
                 state<= S2;           // Solved
                 end
             end
         end
     S2: begin
         if (Sw[7])                    // On=Up
             begin
             Led[0]<= ~LD0;            // D1
             Led[1]<= ~LD1;            // D2
             Led[2]<= 0;               // D3= ON
             Led[3]<= ~r[0]; // D4   (Data bit 0)
             Led[4]<= ~r[1]; // D5   (Data bit 1)
             Led[5]<= ~r[2]; // D6   (Data bit 2)
             Led[6]<= 0;
             Led[7]<= 0;    // finished. Turn on Led D8
             end
         else
             begin
             case (Sw[5:0])
                  0: begin
                     Led<= ~r[7:0];
                     end
                  1: begin
                     Led<= ~r[15:8];
                     end
                  2: begin
                     Led<= ~r[23:16];
                     end
                  3: begin
                     Led<= ~r[31:24];
                     end
                  4: begin
                     Led<= ~r[39:32];
                     end
                  5: begin
                     Led<= ~r[47:40];
                     end
                  6: begin
                     Led<= ~r[55:48];
                     end
                  7: begin
                     Led<= ~r[63:56];
                     end
                  8: begin
                     Led<= ~r[71:64];
                     end
                  9: begin
                     Led<= ~r[79:72];
                     end
                 10: begin
                     Led<= ~r[87:80];
                     end
                 11: begin
                     Led<= ~r[95:88];
                     end
                 12: begin
                     Led<= ~r[103:96];
                     end
                 13: begin
                     Led<= ~r[111:104];
                     end
                 14: begin
                     Led<= ~r[119:112];
                     end
                 15: begin
                     Led<= ~r[127:120];
                     end
                 16: begin
                     Led<= ~r[135:128];
                     end
                 17: begin
                     Led<= ~r[143:136];
                     end
                 default:
                    begin
                    Led<= -1;  // all OFF
                    end
             endcase
             end
         end
     endcase
     end
endmodule

Article: 102088
Subject: Re: CoolRunner XPLA3 getting axed?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 10 May 2006 16:43:59 +0200
Links: << >>  << T >>  << A >>
Eli Hughes schrieb:

> I guess my frustration goes beyond the Cool Runnerm.  Take the Spartan 
> 3e.  Its been advertised on the website as the greast thing since sliced 
> bread for *over* a year now.  I am sure its a nice chip.  I have been 
> wanting to use it.   Click on the online store and select say the 

What can a Spartan 3E do what a Spartan 3 can't? Not much I guess. So 
instead of wasting times with marketing battle, go for another 
(available) IC. Don't forget. We are engineers. We make valuable things 
out of AVAILABLE things. (At least, thats the myth ;-)

Regards
Falk

Article: 102089
Subject: Re: CoolRunner XPLA3 getting axed?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 10 May 2006 07:44:01 -0700
Links: << >>  << T >>  << A >>
looks like Xilinx is taking an exit from PLD(and non-volatile) -
market.

If there would be something new coming out we should have seen some
publicity on this by today.
( like mistake with the wrong posting about Virtex-5 )

Sure Both Altera and Lattice have their "new-PLD" families
(MAX2/machXO) out so Xilinx has the advantage todo the same even better
- machXO is better than MAX2 and CoolFPGA from xilinx could beat both
of them.

I would pretty much welcome Xilinx to have 'CoolFPGA' same as machXO,
but with 1 BRAM in smallest device and maybe more low power options.

Hm, lets see maybe there is something coming, sure one may wish Xilinx
to really get S3e and V4 production running first, guess it has higher
priority, possible to that extent that it doesnt any more make sense
for Xilinx even to attempt to compete with MAX2/machXO/XP

Antti


Article: 102090
Subject: Re: CoolRunner XPLA3 getting axed?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 10 May 2006 16:57:51 +0200
Links: << >>  << T >>  << A >>
dp schrieb:

> The thing is, how do you know which will be easily available tomorrow.
> They discontinued the old coolrunner from Philips for purely political
> reasons, how do you know what will suit them tomorrow. As long

Welcome to the real world. Besides, I don't think its thaaat bad. The 
old coolrunners are still in production, "just" a quick acquisition for 
new designs is not possible anymore. So what.

> as one firm - no matter which - has monopoly over a technology
> things don't look good for us users...

In general yes, but I would'nt overstate the problem. AFAIK Xilinx isn't 
ripping off its customers (even if some, eahhh newsgroupers, blame them 
for that.)

> (there is no competitive technology to the coolrunner on the market,
> in case you did not know that).

What about the MACH line from Lattice? The have also a zero power family 
(Z?). And in the case the is truely no competitive technology, we have 
to be glad to have the Xilinx parts at this low prices (uhhh, I could 
work in marketing, right? ;-)

> But then again, as long as there are reasonable people like Peter
> and Austin at Xilinx - although I suspect they are a minority - there
> is always hope one can eventually get a job done.

You can almost allways get the job done, if you don't glue yourself to 
ideal assumptions in a non-ideal world. If one IC is not available, try 
to use another. If this take longer, more troublesome whatever, tell 
your boss you are not McGyver.
And as someone else already stated, this lesson (about marketing blabla 
and utopia release dates) is well know nowadays. If you didn't attend 
this lesson before, you did now ;-)

Regards
Falk

Article: 102091
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 10 May 2006 16:59:07 +0200
Links: << >>  << T >>  << A >>
Göran Bilski schrieb:

> When I think more about it then I realize that my most used design tool 
> is still the paper and pen.

Dinosaur ;-)

Regards
Falk

Article: 102092
Subject: Re: CoolRunner XPLA3 getting axed?
From: "dp" <dp@tgi-sci.com>
Date: 10 May 2006 08:21:55 -0700
Links: << >>  << T >>  << A >>
> Welcome to the real world.

Oh, thanks for welcoming me. I was just wondering what this place was.

> Besides, I don't think its thaaat bad.

How many of your designed products have lived long enough
to see a discontinued component.

> You can almost allways get the job done ...

So far I have been able to avoid the "almost". Doing a job
means doing it within a time- and cost frame. When you have
a reasonable number of working designs in your library,
you will find out that unnecessary change of components
only extends the frame.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

Falk Brunner wrote:
> dp schrieb:
>
> > The thing is, how do you know which will be easily available tomorrow.
> > They discontinued the old coolrunner from Philips for purely political
> > reasons, how do you know what will suit them tomorrow. As long
>
> Welcome to the real world. Besides, I don't think its thaaat bad. The
> old coolrunners are still in production, "just" a quick acquisition for
> new designs is not possible anymore. So what.
>
> > as one firm - no matter which - has monopoly over a technology
> > things don't look good for us users...
>
> In general yes, but I would'nt overstate the problem. AFAIK Xilinx isn't
> ripping off its customers (even if some, eahhh newsgroupers, blame them
> for that.)
>
> > (there is no competitive technology to the coolrunner on the market,
> > in case you did not know that).
>
> What about the MACH line from Lattice? The have also a zero power family
> (Z?). And in the case the is truely no competitive technology, we have
> to be glad to have the Xilinx parts at this low prices (uhhh, I could
> work in marketing, right? ;-)
>
> > But then again, as long as there are reasonable people like Peter
> > and Austin at Xilinx - although I suspect they are a minority - there
> > is always hope one can eventually get a job done.
>
> You can almost allways get the job done, if you don't glue yourself to
> ideal assumptions in a non-ideal world. If one IC is not available, try
> to use another. If this take longer, more troublesome whatever, tell
> your boss you are not McGyver.
> And as someone else already stated, this lesson (about marketing blabla
> and utopia release dates) is well know nowadays. If you didn't attend
> this lesson before, you did now ;-)
> 
> Regards
> Falk


Article: 102093
Subject: Re: Quartus II 6.0 available
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Wed, 10 May 2006 15:28:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
> Leon <leon.heller@bulldoghome.com> wrote:
> >Quartus II 6.0 is now available, I downloaded the Web Edition
> >yesterday. I'm on the Altera mailing list but I don't remember seeing
> >any notification of the new version. It worked OK when I tried it on a
> >couple of small projects.

> Only the linux version missing then ;)

Altera should talk to Codeweavers. There are only few things that keep
Quartus from running flawless with wine, mostly sentinel and jtagserver
related. With these odds weeded out, altera could perhaps drop WindU for
their Unix releases too...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 102094
Subject: Re: CoolRunner XPLA3 getting axed?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 10 May 2006 17:38:31 +0200
Links: << >>  << T >>  << A >>
dp schrieb:

>>Besides, I don't think its thaaat bad.
> 
> 
> How many of your designed products have lived long enough
> to see a discontinued component.

Not so much, since Iam a bit too young to tell stories from the good ole 
days ;-) But I have seen it. About 4 years ago, I did a minor redesign 
because of discontinued parts. A half year ago, I did a major redesign 
on the same unit (all functions that were done using ASICs and FPGAs are 
now inside one little FPGA from brand A)

>>You can almost allways get the job done ...
> 
> So far I have been able to avoid the "almost". Doing a job
> means doing it within a time- and cost frame. When you have
> a reasonable number of working designs in your library,
> you will find out that unnecessary change of components
> only extends the frame.

Right. But this was not the point. The point was that the OP was 
complaining about delayed availibility of components that were announced 
ages ago (ok, lots of month ;-)
So NO EXISTING design uses ANNOUNCED devices.

Regards
Falk

Article: 102095
Subject: Re: Quartus II 6.0 available
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 10 May 2006 08:56:16 -0700
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:

>> Only the linux version missing then ;)
> 
> Altera should talk to Codeweavers. There are only few things that keep
> Quartus from running flawless with wine, mostly sentinel and jtagserver
> related. With these odds weeded out, altera could perhaps drop WindU for
> their Unix releases too...

My take is that this is a marketing decision
to charge extra (float license) for linux support.

Making the dongle work in linux is not a
very challenging technical problem for Altera.

       -- Mike Treseler

Article: 102096
Subject: Re: Quartus II 6.0 available
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Wed, 10 May 2006 16:11:53 GMT
Links: << >>  << T >>  << A >>
On a sunny day (10 May 2006 03:37:42 -0700) it happened "Leon"
<leon.heller@bulldoghome.com> wrote in
<1147257462.542035.316240@v46g2000cwv.googlegroups.com>:

>Quartus II 6.0 is now available, I downloaded the Web Edition
>yesterday. I'm on the Altera mailing list but I don't remember seeing
>any notification of the new version.
I did get an email announcing it.

> It worked OK when I tried it on a
>couple of small projects.
>
>Leon
>
>

Article: 102097
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: "Luke" <lvalenty@gmail.com>
Date: 10 May 2006 09:21:17 -0700
Links: << >>  << T >>  << A >>
The 16-bit cpu could access up to 256K of RAM and had 16 16-bit
registers.  I actually am able to fit 12 of these on one spartan 3 1000
chip, limited only by available block ram.  It was nifty, but if I
really needed that much specialized processing power it would make more
sense to build some custom logic in the FPGA to do it.


Article: 102098
Subject: Re: CoolRunner XPLA3 getting axed?
From: "Peter Alfke" <peter@xilinx.com>
Date: 10 May 2006 10:08:54 -0700
Links: << >>  << T >>  << A >>
There is ABSOLUTELY NO truth to this rumor. XPLA3 aka CoolRunner is
alive and kicking and finds increasing acceptance in the market.
Disappearance from our website and poor availability data from Avnet or
DigiKey have nothing to do with the health of the product line and its
long-time future.
Rumors like this can become self-fulfilling, that's why I jumped in
immediately.
Will publish additional convincing data soon.
Peter Alfke, Xilinx


Article: 102099
Subject: Re: CoolRunner XPLA3 getting axed?
From: Eli Hughes <emh203@psu.edu>
Date: Wed, 10 May 2006 13:31:01 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> There is ABSOLUTELY NO truth to this rumor. XPLA3 aka CoolRunner is
> alive and kicking and finds increasing acceptance in the market.
> Disappearance from our website and poor availability data from Avnet or
> DigiKey have nothing to do with the health of the product line and its
> long-time future.
> Rumors like this can become self-fulfilling, that's why I jumped in
> immediately.
> Will publish additional convincing data soon.
> Peter Alfke, Xilinx
> 


Thanks for the feedback Peter.  I  sincerely appreciate the feedback you 
and Austin give on this forum.  I really do like the 3.3v coolrunner parts!

-Eli



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