Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 104600

Article: 104600
Subject: minimal connections so that a xcv200e talks with pc
From: "blisca" <blisca@tiscali.it>
Date: Fri, 30 Jun 2006 23:18:01 +0100
Links: << >>  << T >>  << A >>
I'm still here,sorry if i post the same message 2 times,but really i'm
spending lot of hours daily trying to solve this problem

my self-built a cable III  works fine with
cpld's like xc95144xl(3,3V),i can recognize it ,readback,erase,blank check
and write.
Then i dared to connect it with a (scraped as ever) fpga,a virtex xcv200e
but the boundary scan chain does not see it at all.Plugging the cable III in
the cpld it still works fine

what i did was this :

i built a level shifter  for the TDO,because the cable is not expected to
work with such low levels,this 2 bjt level shifter works fine even with a 4
mhz square wave,and i think this is faster than any signal could ever move
through the parallel port(is it true?)

i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not
easy to test it (soldering wires on a bga as i do is even worse ...)but it
looks
that it should be enough for the core,correct???or i need to

i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the
ground in 3
points(A1,J1,N12)

i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level
amplifier)

I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same
result.....

I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing
boundary scan mode

using the debug chain utility i verified that the signals are working but i
noticed that there is no movement on TMS,and of course on TDO

there is something else missing?

Thank you to everyone in the group that will help me or just will read this

Diego




Article: 104601
Subject: Re: Problem to extend Xilinx GSRD Design
From: "Guru" <ales.gorkic@email.si>
Date: 30 Jun 2006 15:27:44 -0700
Links: << >>  << T >>  << A >>
I did some download and try the new MPMC2. Since I have Virtex4FX12
MiniModule I tried the MiniModule reference design
(v4fx12mm_ddr_idpp_100mhz.zip) before I tried to modify the GSRD2
reference design, which is bult for ML403
(ml403_ddr_idpoc_100mhz_gsrd.zip). The v4fx12mm reference design IS NOT
WORKING. I could not get anything from UART, which is like being blind
for me. I contacted support and Glenn Baxter said to me that the design
is thorougly tested. The design cannot work because there is at least
one error in ddr_mem_test.c - UartBaseAdr is assigned with no value. I
spend some more time on the design but still I couldn't get anything
from UART (must be some HW error). Some more mails to mr. Baxter did'n
help, so I quit trying and dedicate my time to my cores. I still wait
for the solution.
By the way: Glenn said that Linux support for GSRD2 is probably to be
expected at the end of June. Is that true? Will we finally get the
"real thing"?

Cheers,

Guru


Article: 104602
Subject: Re: EDK: Using DCR bus on ML310-based project
From: "Guru" <ales.gorkic@email.si>
Date: 30 Jun 2006 15:28:01 -0700
Links: << >>  << T >>  << A >>

my.king wrote:
> Hi,
>
> I'm working with the ML310 eval board. Is there anyone who has a
> working example on how to create a custom IP on the DCR bus (and
> accessing it from the PPC405)?
>
> Thanks.

I did it!  It is quite easy. Take a look at Xilinx PLBtoOPB bridge core
or similar IP with DCR bus.

Cheers,

Guru


Article: 104603
Subject: How to control the uart
From: "ZHI" <threeinchnail@gmail.com>
Date: 30 Jun 2006 16:52:58 -0700
Links: << >>  << T >>  << A >>
Here is my general idea.I generate a matrix in Matlab. I want to
transmit the numbers in matrix into FPGA. And these numbers will be
sent to an algorithm implemented FPGA board. The algorithm will deal
with these numbers and new result is sent back to PC(Matlab, I want to
compare the result from MATLAB).

I know transmitting these numbers to FPGA board. I need a UART. I have
one. I also have done the algorithms in FPGA. But I don't know how to
transmit the numbers from Matlab to FPGA. Exactly to say, I don't know
how to control uart. How does uart know the data come in? Shall i add
like "FF" file head to transmitting number? ...I am totally lost now. I
have no idea how to connect Matlab to FPGA. Please give me some
suggestions. Thanks.


Article: 104604
Subject: Re: How to control the uart
From: "radarman" <jshamlet@gmail.com>
Date: 30 Jun 2006 18:42:53 -0700
Links: << >>  << T >>  << A >>
ZHI wrote:
> Here is my general idea.I generate a matrix in Matlab. I want to
> transmit the numbers in matrix into FPGA. And these numbers will be
> sent to an algorithm implemented FPGA board. The algorithm will deal
> with these numbers and new result is sent back to PC(Matlab, I want to
> compare the result from MATLAB).
>
> I know transmitting these numbers to FPGA board. I need a UART. I have
> one. I also have done the algorithms in FPGA. But I don't know how to
> transmit the numbers from Matlab to FPGA. Exactly to say, I don't know
> how to control uart. How does uart know the data come in? Shall i add
> like "FF" file head to transmitting number? ...I am totally lost now. I
> have no idea how to connect Matlab to FPGA. Please give me some
> suggestions. Thanks.

Do a google search on "Matlab serial I/O". I came up with this rather
promising link in under 30 seconds.

http://www.math.carleton.ca/~help/matlab/MathWorks_R13Doc/techdoc/matlab_external/ch_seria.html

You will need some sort of control logic in the FPGA to handle the
UART, but if you are already implementing algo's in both MATLAB and
VHDL/Verilog, a simple state machine should be no problem.


Article: 104605
Subject: Re: Altium Designer LiveDesign Evaluation Kits (once again)
From: "radarman" <jshamlet@gmail.com>
Date: 30 Jun 2006 18:52:13 -0700
Links: << >>  << T >>  << A >>

Rene Tschaggelar wrote:
> burn.sir@gmail.com wrote:
>
> > Hi all,
> >
> > I know this has been discussed on the NG before, but it seems like
> > every time it is discussed someone hijacks the post and we end up with
> > no answers. But this will be the last one. I promise ;)
> >
> >
> > I need two identical boards with Xilinx and Altera parts on them for
> > some "fun" at home. I found this page on the net
> >
> > http://www.altium.com/forms/evaluation.aspx
> >
> > Which is this board, I assume:
> >
> > http://www.altium.com/files/livedesign/Live_design_features.pdf
> >
> >
> > $250 for 2 boards plus the download cable sounds nice, but i wonder if
> > there is a catch?
> >
> > * do the boards work with chip vendor software (ISE & Quartus) flows?
> > what about NIOS II and EDK?
> > * does the programming cable work with vendor supplied programmers?
> > * what is that 30-day license thingy they mention on their site? is the
> > board bricked after 30 days??
> > * someone mentioned these lack program flash, is that true? do i have
> > to re-program boards every time i turn them on?
> > * same cable for both boards? can i remove the cable while the board is
> > on, so i can program the other board?
> > * and so on...
> >
> >
> > to summarize, can I buy these boards instead of ordering a "Starter
> > kit" board from Xilinx and a "NIOS II" board from Altera? what would i
> > be missing?
>
> The altium boards are intended to work wit their tools.
> Their tools means the Altium designer, which uses the
> Altera and Xilinx web edition as driver. The altium designer
> produces a netlist or sort of that goes through the
> Altera/Xilinx tools.
> While the Altium designer has multiple cores, they are
> supported with compiler and source line debugger. The
> NIOS can be loaded, I assume, as blackbox, not as processor
> core. Meaning there won't be a compiler for it, nor a
> sourceline debugger.
> Having a look at both solutions may be worth the time.
> The cost are not necessarily that high when put in comparison
> to the overall project cost and the saved time.
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net

Actually, no - the boards are quite generic. They just don't have local
configuration memories on them. They should be quite usable as
development boards even if you decide not to license the Altium
software. Even Altium mentions that the boards are usable with the
ordinary tools on their website (which is why the boards are $99 and
you get to keep them)

Although I have since decided to go with another board, it should be
possible to attach a PLD to the "printer port" header, and load the
board with an SVF player (or equivalent for Altera) via JTAG.


Article: 104606
Subject: Re: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 30 Jun 2006 19:10:45 -0700
Links: << >>  << T >>  << A >>
On Fri, 30 Jun 2006 03:19:16 GMT, John_H <johnhandwork@mail.com>
wrote:

>PeterC wrote:
>> I'm considering various options to implement a tapped delay line in an
>> S3 device.
>> 
>> I believe that using the carry chain (and travelling through adjacent
>> slices) would give a much finer resolution than going through the LUTs.
>> 
>> I would like to know what granularity I can expect for this type of
>> delay line ?
>> 
>> What is the MUX delay, local interconnect delay, process/voltage/temp
>> variability for each?
>> As far as I know, Xilinx publish worst case (max) LUT delay values
>> only. 
>> 
>> Any info greatly appreciated.
>> 
>> PeterC.
>> 
>
>In my Spartan3E starter kit (3s500E-4) I'm getting an average of 450 ps 
>per LUT when using the fastest route between LUTs in a CLB.  The carry 
>chain gets about 100 ps per tap.  The way I tend to use the delay is a 
>broadside sample of the whole chain since muxing a signal back out tends 
>to be up to the whim of the routing.
>
>I do use a controlled injection of the source into the 8 LUTs at the 
>bottom of my chain giving pretty strong repeatability there.  I used a 
>method from XAPP 671 to get another half-LUT delay but I added it at the 
>front end.  Bottom line: I have 0-7.5 LUTs worth of programmable delay 
>averaging just over 200 ps for each half step along with about 100 ps 
>per tap up the carry chain.
>
>It was huge fun to do.  I recommend putting a frequency counter in your 
>design to extract the precise timing.  It's great to see the results.
>
>The changes over operating conditions aren't extreme.  I haven't seen 
>the numbers on the shot of freeze spray but from what I observed early 
>and the numbers I know now, I'd estimate less than 10% shift.  What I 
>*have* seen that's cool is a strain-based change in delay: I push on the 
>top of the chip with an eraser and the 5700 ps delay changes by about 
>10-15 ps.  I considered the Spartan3E for use as a load cell!


Now just close a servo loop on Vccint.

John


Article: 104607
Subject: Re: Problem to extend Xilinx GSRD Design
From: john.orlando@gmail.com
Date: 30 Jun 2006 20:33:50 -0700
Links: << >>  << T >>  << A >>

Guru wrote:
> I did some download and try the new MPMC2. Since I have Virtex4FX12
> MiniModule I tried the MiniModule reference design
> (v4fx12mm_ddr_idpp_100mhz.zip) before I tried to modify the GSRD2
> reference design, which is bult for ML403
> (ml403_ddr_idpoc_100mhz_gsrd.zip). The v4fx12mm reference design IS NOT
> WORKING.
<snip>
Out of curiousity: did you EVER have a GSRD implementation working on
the MiniModule?  I actually emailed Xilinx a while ago asking if this
reference design would work on the MiniModule, and I was told that it
would not due to several technical reasons (that were all enumerated at
the time, and made sense to me, though I don't have them in front of me
right now).  So, I'd be curious to hear if you had the original GSRD
working, and if you do in fact get the GSRD2 working.

Regards,
John O.
www.jrobot.net


Article: 104608
Subject: Re: Spartan3e starter kit vga mod
From: "JJ" <johnjakson@gmail.com>
Date: 30 Jun 2006 23:23:43 -0700
Links: << >>  << T >>  << A >>

Eric Crabill wrote:
> There is another related approach, which I initially saw in some C&T display
> controllers.  You can modulate pixel intensity across frames to generate a
> few more bits' worth of intensity.  If you get too greedy doing this, it
> flickers badly.  I think they called it temporal dithering.  If I recall,
> one use was to get pseudo 24-bit color depth from LCD panels that had 18-bit
> digital inputs.
>
> Eric
>

I think if I did this I would take a page from the audio DAC and use
random dithering.

One would want all pixels to appear to be indepedently dithered as if
they had their own dither function. In  practice a PRNG much greater in
bits than the extra fake analog bits would probably suffice. I would
suggest a 32b PRNG and have it in the system for all sorts of other
uses.

The digital value being output is either n or n+1 in proportion to the
extra bits, .n[-1], .n[-2], .n[-3] etc. So for a 3b extra resolution
simply compare those 3 lowest bits with the PRNG at any of 3b and if
>=, add 1 to n. Do the same with the other 2 colors at different bits from the PRNG and I would expect the flashing to be minimal.

If one paints the entire screen with the exact same enhanced color one
should see a perfectly speckled pattern frame by frame whose weight
matches the extra grey level and since it continuosly changes, should
be temporally smooth. I'd sure like to see the OP do that and see the
result. Ofcourse we would be seeing the temporal effect through the
camera.

John Jakson


Article: 104609
Subject: Re: Altium Designer LiveDesign Evaluation Kits (once again)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 30 Jun 2006 23:41:10 -0700
Links: << >>  << T >>  << A >>
radarman schrieb:

> Rene Tschaggelar wrote:
> > burn.sir@gmail.com wrote:
> >
> > > Hi all,
> > >
> > > I know this has been discussed on the NG before, but it seems like
> > > every time it is discussed someone hijacks the post and we end up with
> > > no answers. But this will be the last one. I promise ;)
> > >
> > >
> > > I need two identical boards with Xilinx and Altera parts on them for
> > > some "fun" at home. I found this page on the net
> > >
> > > http://www.altium.com/forms/evaluation.aspx
> > >
> > > Which is this board, I assume:
> > >
> > > http://www.altium.com/files/livedesign/Live_design_features.pdf
> > >
> > >
> > > $250 for 2 boards plus the download cable sounds nice, but i wonder if
> > > there is a catch?
> > >
> > > * do the boards work with chip vendor software (ISE & Quartus) flows?
> > > what about NIOS II and EDK?
> > > * does the programming cable work with vendor supplied programmers?
> > > * what is that 30-day license thingy they mention on their site? is the
> > > board bricked after 30 days??
> > > * someone mentioned these lack program flash, is that true? do i have
> > > to re-program boards every time i turn them on?
> > > * same cable for both boards? can i remove the cable while the board is
> > > on, so i can program the other board?
> > > * and so on...
> > >
> > >
> > > to summarize, can I buy these boards instead of ordering a "Starter
> > > kit" board from Xilinx and a "NIOS II" board from Altera? what would i
> > > be missing?
> >
> > The altium boards are intended to work wit their tools.
> > Their tools means the Altium designer, which uses the
> > Altera and Xilinx web edition as driver. The altium designer
> > produces a netlist or sort of that goes through the
> > Altera/Xilinx tools.
> > While the Altium designer has multiple cores, they are
> > supported with compiler and source line debugger. The
> > NIOS can be loaded, I assume, as blackbox, not as processor
> > core. Meaning there won't be a compiler for it, nor a
> > sourceline debugger.
> > Having a look at both solutions may be worth the time.
> > The cost are not necessarily that high when put in comparison
> > to the overall project cost and the saved time.
> >
> > Rene
> > --
> > Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> > & commercial newsgroups - http://www.talkto.net
>
> Actually, no - the boards are quite generic. They just don't have local
> configuration memories on them. They should be quite usable as
> development boards even if you decide not to license the Altium
> software. Even Altium mentions that the boards are usable with the
> ordinary tools on their website (which is why the boards are $99 and
> you get to keep them)
>
> Although I have since decided to go with another board, it should be
> possible to attach a PLD to the "printer port" header, and load the
> board with an SVF player (or equivalent for Altera) via JTAG.

its easier to convert SVF to ACE format using Xilinx tools (SVF2ACE)
and make the PLD to play pack ACE file :)

way simpler an ACE Player requires only
32 bit count register
3 - 8 bit registers (can be one if verify is not supported)
one command register (can be 3 bits only)
simple state machine

additional some logic to hold the address logic for external memory

no problem for a smallest micro or 128 macrocell PLD

ASFAIK all other JTAG bytecode players require more resources

Antti


Article: 104610
Subject: Cyclone-II Configuration via a PCI bus
From: "ColmF" <b1uesparx@hotmail.com>
Date: 1 Jul 2006 01:58:51 -0700
Links: << >>  << T >>  << A >>
Hi,

I've trawled around this group and on the web a little, but haven't
found anything to suit my purposes, so I thought I'd post here...

I'm designing a board with two FPGAs, both Cylone-II devices. One will
contain a PCI core and will always be programmed by a serial
configuration device that never changes. The other will also be loaded
by a (separate) serial configuration device, but I would like to be
able to change this configuration depending on the function required
for the board.

Ideally, I would implement a small core in the PCI FPGA. I would then
fetch the required configuration file from somewhere via the PCI
interface and store it in a local on-board memory. The PCI FPGA would
then stream the configuration file to the serial configuration device
for the other FPGA.

So, questions:
- Is it possible to do this in such a straighforward manner?
- Is there a core available to interface to the Active Serial interface
of the configuration device?
- What format does the configuration file need to be in?

It strikes me that this should be a simple task to achieve - or am I
totally wrong?

Thanks,

Colm.


Article: 104611
Subject: Re: Problem to extend Xilinx GSRD Design
From: "Guru" <ales.gorkic@email.si>
Date: 1 Jul 2006 03:35:36 -0700
Links: << >>  << T >>  << A >>

> Out of curiousity: did you EVER have a GSRD implementation working on
> the MiniModule?  I actually emailed Xilinx a while ago asking if this
> reference design would work on the MiniModule, and I was told that it
> would not due to several technical reasons (that were all enumerated at
> the time, and made sense to me, though I don't have them in front of me
> right now).  So, I'd be curious to hear if you had the original GSRD
> working, and if you do in fact get the GSRD2 working.
>
> Regards,
> John O.
> www.jrobot.net

Hi John,

You shocked me with your response. I have NEVER implemented an original
GSRD to work on MiniModule. I actually did not find it necessary since
I was waiting for GSRD2 (I tried to save some time). If there are some
technical limits that prevent that I would like to see them written,
because nobody told me yet,  that this is not possible. I only had the
original  TEMAC reference design working (using LL_TEMAC in a
CoreConnect style and lwip stack).

With regrets,

Guru


Article: 104612
Subject: register state when power on
From: "bjzhangwn" <bjzhangwn@126.com>
Date: 1 Jul 2006 03:39:37 -0700
Links: << >>  << T >>  << A >>
I want to know the registers state after the configurations(altera)


Article: 104613
Subject: Re: How to control the uart
From: Duane Clark <junkmail@junkmail.com>
Date: Sat, 01 Jul 2006 16:21:30 GMT
Links: << >>  << T >>  << A >>
ZHI wrote:
> ...
> I know transmitting these numbers to FPGA board. I need a UART. I have
> one. I also have done the algorithms in FPGA. But I don't know how to
> transmit the numbers from Matlab to FPGA. Exactly to say, I don't know
> how to control uart. How does uart know the data come in? ...

Every byte of data sent via the UART starts with a start bit and ends 
with a stop bit (in the most commonly used scheme, 1 start bit, 1 stop 
bit, no parity). In between transmission of data, the UART holds the 
stop bit level. UART receivers therefore know that no data is being sent 
until it receives a start bit, and it knows that the next 8 bits are data.

All this is handled by the hardware and is largely transparent to you. 
Within the FPGA, the UART receiver will provide a bit indicating that 
data has been received.

Article: 104614
Subject: Xilinx System Generator Part List Problem
From: patrik.camilleri@gmail.com
Date: 1 Jul 2006 10:00:05 -0700
Links: << >>  << T >>  << A >>
I'm using ISE WebPack 8.1.03i, System Generator 8.1.01, Matlab R14 SP3

The problem is related with the System Generator block which is placed
in Simulink to be able to generate a design. For some reason when I
click on the Part button to choose the device for which the design has
to be compiled the Part list for most of the Virtex devices is not
generated properly, e.g. xc4vsx35 is found under the xc4vsx25. For some
reason the hierarchy of the part list is not generated properly.

Hope somebody already had this problem and managed to solve is in some
way.

Regards,
Patrick


Article: 104615
Subject: Re: How to control the uart
From: "ZHI" <threeinchnail@gmail.com>
Date: 1 Jul 2006 10:09:02 -0700
Links: << >>  << T >>  << A >>
Thanks radarman and Duane Clark. I have read that link. It is quite
useful.
I want to make a simple test for transmission data between PC(matlab)
to FPGA(UART).  I can generate the UART.bit file and download into FPGA
board successfully.
Can I ask a question of user constraint file ? I have successfully
downloaded a LED flash into FPGA board before. I copied this exercise
from the CD enclosed with the FPGA board. I remember before I implement
it into FPGA board. I not only generate the .bit file also copied the
LED user constraint file in the CD. Actually I am not quite sure the
content of the constraint file. I just copied it. Now I want to
implement UART into FPGA board. I think it also needs one user
constraint file for implementing. I think the user constraint file is
generated automatically when the programming file is generated. But
when I open the .ucf file, it is blank. What is the problem? Shall i
write it by myself? I don't know how to connect the pin? Can you
explain the .ucf function for me clearly? And How does it work and how
does it generate? Actually I have not a clear thread of it. Any
suggestions are appreciated. Thanks again.
\zhi
Duane Clark wrote:
> ZHI wrote:
> > ...
> > I know transmitting these numbers to FPGA board. I need a UART. I have
> > one. I also have done the algorithms in FPGA. But I don't know how to
> > transmit the numbers from Matlab to FPGA. Exactly to say, I don't know
> > how to control uart. How does uart know the data come in? ...
>
> Every byte of data sent via the UART starts with a start bit and ends
> with a stop bit (in the most commonly used scheme, 1 start bit, 1 stop
> bit, no parity). In between transmission of data, the UART holds the
> stop bit level. UART receivers therefore know that no data is being sent
> until it receives a start bit, and it knows that the next 8 bits are data.
>
> All this is handled by the hardware and is largely transparent to you.
> Within the FPGA, the UART receiver will provide a bit indicating that
> data has been received.


Article: 104616
Subject: Re: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 1 Jul 2006 11:57:00 -0700
Links: << >>  << T >>  << A >>
blisca wrote:
> thank you for helping me
> ok,i admit that i did'nt read it ,jumping to soon to the chapter "boundary
> scan mode"..........but......being a newbie,and feeding the xcv200e through
> wires,how can i identify the bank2 VCCO?i mean where are these VCCO pins ?
>
>
Diego;
The Xilinx web site contains lots of dcumentation for their chips.
Table 6 in DS022-4.PDF, lists the XCV200E's pinouts for the PQ240
package.  This is only package that looks like it could be used by a
hobbiest.  All of the other packages are BGA.  Anyway, in DS022-4.PDF
(www.xilinx.com/bvdocs/publications/DS022-4.PDF), page 10 shows the pin
numbers for the chip's banks.  VCCO for bank 2 is on pins 176 and 165.

HTH
-Dave Pollum


Article: 104617
Subject: Re: Altium Designer LiveDesign Evaluation Kits (once again)
From: "radarman" <jshamlet@gmail.com>
Date: 1 Jul 2006 12:34:20 -0700
Links: << >>  << T >>  << A >>

Antti wrote:
> radarman schrieb:
>
> > Rene Tschaggelar wrote:
> > > burn.sir@gmail.com wrote:
> > >
> > > > Hi all,
> > > >
> > > > I know this has been discussed on the NG before, but it seems like
> > > > every time it is discussed someone hijacks the post and we end up with
> > > > no answers. But this will be the last one. I promise ;)
> > > >
> > > >
> > > > I need two identical boards with Xilinx and Altera parts on them for
> > > > some "fun" at home. I found this page on the net
> > > >
> > > > http://www.altium.com/forms/evaluation.aspx
> > > >
> > > > Which is this board, I assume:
> > > >
> > > > http://www.altium.com/files/livedesign/Live_design_features.pdf
> > > >
> > > >
> > > > $250 for 2 boards plus the download cable sounds nice, but i wonder if
> > > > there is a catch?
> > > >
> > > > * do the boards work with chip vendor software (ISE & Quartus) flows?
> > > > what about NIOS II and EDK?
> > > > * does the programming cable work with vendor supplied programmers?
> > > > * what is that 30-day license thingy they mention on their site? is the
> > > > board bricked after 30 days??
> > > > * someone mentioned these lack program flash, is that true? do i have
> > > > to re-program boards every time i turn them on?
> > > > * same cable for both boards? can i remove the cable while the board is
> > > > on, so i can program the other board?
> > > > * and so on...
> > > >
> > > >
> > > > to summarize, can I buy these boards instead of ordering a "Starter
> > > > kit" board from Xilinx and a "NIOS II" board from Altera? what would i
> > > > be missing?
> > >
> > > The altium boards are intended to work wit their tools.
> > > Their tools means the Altium designer, which uses the
> > > Altera and Xilinx web edition as driver. The altium designer
> > > produces a netlist or sort of that goes through the
> > > Altera/Xilinx tools.
> > > While the Altium designer has multiple cores, they are
> > > supported with compiler and source line debugger. The
> > > NIOS can be loaded, I assume, as blackbox, not as processor
> > > core. Meaning there won't be a compiler for it, nor a
> > > sourceline debugger.
> > > Having a look at both solutions may be worth the time.
> > > The cost are not necessarily that high when put in comparison
> > > to the overall project cost and the saved time.
> > >
> > > Rene
> > > --
> > > Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> > > & commercial newsgroups - http://www.talkto.net
> >
> > Actually, no - the boards are quite generic. They just don't have local
> > configuration memories on them. They should be quite usable as
> > development boards even if you decide not to license the Altium
> > software. Even Altium mentions that the boards are usable with the
> > ordinary tools on their website (which is why the boards are $99 and
> > you get to keep them)
> >
> > Although I have since decided to go with another board, it should be
> > possible to attach a PLD to the "printer port" header, and load the
> > board with an SVF player (or equivalent for Altera) via JTAG.
>
> its easier to convert SVF to ACE format using Xilinx tools (SVF2ACE)
> and make the PLD to play pack ACE file :)
>
> way simpler an ACE Player requires only
> 32 bit count register
> 3 - 8 bit registers (can be one if verify is not supported)
> one command register (can be 3 bits only)
> simple state machine
>
> additional some logic to hold the address logic for external memory
>
> no problem for a smallest micro or 128 macrocell PLD
>
> ASFAIK all other JTAG bytecode players require more resources
>
> Antti

Antti,
Could you point me to some more info on the ACE format and players? The
only info I seem to be able to dig up is on SystemACE - the Xilinx CF
reader. This sounds like a good use for a smallish CPLD, and something
I can try out on my Digilent XC2XL board.

Thanks!
-Seth


Article: 104618
Subject: R: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
From: "blisca" <blisca@tiscali.it>
Date: Sat, 1 Jul 2006 23:26:55 +0100
Links: << >>  << T >>  << A >>
thanl you , i am  discovering  that there are a lot of important pdfs that i
never had..........
Dave Pollum <vze24h5m@verizon.net> wrote in message
1151780220.701510.313740@b68g2000cwa.googlegroups.com...
> blisca wrote:
> > thank you for helping me
> > ok,i admit that i did'nt read it ,jumping to soon to the chapter
"boundary
> > scan mode"..........but......being a newbie,and feeding the xcv200e
through
> > wires,how can i identify the bank2 VCCO?i mean where are these VCCO pins
?
> >
> >
> Diego;
> The Xilinx web site contains lots of dcumentation for their chips.
> Table 6 in DS022-4.PDF, lists the XCV200E's pinouts for the PQ240
> package.  This is only package that looks like it could be used by a
> hobbiest.  All of the other packages are BGA.  Anyway, in DS022-4.PDF
> (www.xilinx.com/bvdocs/publications/DS022-4.PDF), page 10 shows the pin
> numbers for the chip's banks.  VCCO for bank 2 is on pins 176 and 165.
>
> HTH
> -Dave Pollum
>



Article: 104619
Subject: stable reset in fpga
From: "bjzhangwn" <bjzhangwn@126.com>
Date: 1 Jul 2006 20:51:45 -0700
Links: << >>  << T >>  << A >>
I want to know how I can reset the logic in fpga and make the least
metastable.I use 2 clock in fpga and if it is nessesary to make the
reset input signal synchronize under the clock?


Article: 104620
Subject: Re: stable reset in fpga
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 1 Jul 2006 21:09:54 -0700
Links: << >>  << T >>  << A >>

bjzhangwn wrote:
> I want to know how I can reset the logic in fpga and make the least
> metastable.I use 2 clock in fpga and if it is nessesary to make the
> reset input signal synchronize under the clock?

If you use an asynchronous reset signal while the clock is running,
then you must be concerned about the trailing end of Reset. Reset will
not go away everywhere at the same time, which means that some parts of
the circuit end the reset before a certain clock edge, others after
that edge. This can have ugly consequences.

The standard remedy is to augment (stretch) the asynchronous reset with
a local synchronous reset that lasts longer, but then of course ends
synchronously.
SRL16 shift registers are a popular and cheap way of doing that.
Peter Alfk, Xilinx


Article: 104621
Subject: component instantiation ISE7.1
From: "gary" <rgarik@yahoo.com>
Date: Sun, 02 Jul 2006 08:04:44 -0500
Links: << >>  << T >>  << A >>
hi,
    Iam trying to instantiate a component from my user_logic_ip.vhd :

signal h:std_logic_vector(0 to 31);
signal k:std_logic_vector(0 to 31);
component inv
port( x: in std_logic_vector(0 to 31);
      z: out std_logic_vector(0 to 31));
end component;
begin
 call: inv
   portmap(h,k);
iam giving these h & k values to slv_reg0 & slv_reg1 
because i want to give my input from 'C' and see my output on hyper
terminal.
iam using spartan-3 starter kit for download.
In ISE Synthesize is going fine but when iam implementing design following
warnings & errors are coming:

NgdBuild:889 - Pad net 'k<10>' is not connected to an external port in
   this design.  A new port 'k<10>' has been added and is connected to
this
   signal.
WARNING:NgdBuild:889 - Pad net 'k<4>' is not connected to an external port
in
   this design.  A new port 'k<4>' has been added and is connected to
this
   signal.
WARNING:NgdBuild:889 - Pad net 'k<6>' is not connected to an external port
in
   this design.  A new port 'k<6>' has been added and is connected to
this
   signal.

---------------------all k<0> to k<31>------------------------

ERROR:
NgdBuild:809 - output pad net 'k<10>' has an illegal load:
     pin I2 on block IP2Bus_Data<10>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<4>' has an illegal load:
     pin I2 on block IP2Bus_Data<4>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<6>' has an illegal load:
     pin I2 on block IP2Bus_Data<6>1 with type LUT3

--------------------all k<0> to k<31>------------------------

i dont understand what these errors mean......
can anybody help me...........
regards
gary




Article: 104622
Subject: Re: Altium Designer LiveDesign Evaluation Kits (once again)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 2 Jul 2006 06:21:33 -0700
Links: << >>  << T >>  << A >>
radarman schrieb:

> Antti wrote:
> > radarman schrieb:
> >
> > > Rene Tschaggelar wrote:
> > > > burn.sir@gmail.com wrote:
> > > >
> > > > > Hi all,

> Antti,
> Could you point me to some more info on the ACE format and players? The
> only info I seem to be able to dig up is on SystemACE - the Xilinx CF
> reader. This sounds like a good use for a smallish CPLD, and something
> I can try out on my Digilent XC2XL board.
>
> Thanks!
> -Seth

Hi Seth,

There is no public info on the ACE format. So you have 2 options:

Choice #1: You (or anyone else) can obtain it in some time. The actual
amount you would spend depends on your brain and mileage. For me the
target time was about one hour. You can try obtaining this info for fun
if you like using your brain. Dont feel bad if your target time is more
than one hour.

or

Choice #2: Get my brain. The explanation how I used my brain may come
handy now and later.

http://antti-brain.com

As of players - I have not implemented the player but inside the brain
snapshot are ACE dump and compress utilities with full source codes,
writing an player is trivial as well. Both the dump and compress
utilities did take about one hour each of time to write from scratch.
Note the ACE compress utility is only able to compress ACE files
generated by ISE/Impact version 8.1 or earlier, if Xilinx enhances its
ACE output generation in new releases of the ISE then the utility will
no longer be able to compress the ACE files.

Antti


Article: 104623
Subject: Re: How to comm with Altera JTAG UART (from custom host software)?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 2 Jul 2006 06:33:40 -0700
Links: << >>  << T >>  << A >>
Kolja Waschk schrieb:

> Hi,
>
> is there any way to communicate with software running on a NIOS2 SOPC
> through JTAG from custom software on a Host PC? maybe via JTAG UART etc...
>
> Would be nice if nios2-terminal provided a method to connect to the JTAG
> UART from own applications through Unix or TCP sockets, or something
> similar. Would be perfect if there was a public specification or source
> code example how to access a JTAG UART within a SOPC over JTAG?
>
> We currently design a device where a serial interface is used just for
> maintenance work. The same data could be exchanged via JTAG UART if only
> we knew how to access it from our own software (Piping to and from
> nios2-terminal isn't exactly what I'm looking for).
>
> Kolja
>
>
> --
> mr. kolja waschk - haubach-39 - 22765 hh - germany
> fon +49 40 889130-34 - fax -35 - http://www.ixo.de

Hi Kolja

http://www.altera.com/literature/ug/ug_virtualjtag.pdf

have you checked the above document?

Antti
Get my Brain http://antti-brain.com


Article: 104624
Subject: Re: Cyclone-II Configuration via a PCI bus
From: "Antti" <Antti.Lukats@xilant.com>
Date: 2 Jul 2006 06:48:00 -0700
Links: << >>  << T >>  << A >>

ColmF schrieb:

> Hi,
>
> I've trawled around this group and on the web a little, but haven't
> found anything to suit my purposes, so I thought I'd post here...
>
> I'm designing a board with two FPGAs, both Cylone-II devices. One will
> contain a PCI core and will always be programmed by a serial
> configuration device that never changes. The other will also be loaded
> by a (separate) serial configuration device, but I would like to be
> able to change this configuration depending on the function required
> for the board.
>
> Ideally, I would implement a small core in the PCI FPGA. I would then
> fetch the required configuration file from somewhere via the PCI
> interface and store it in a local on-board memory. The PCI FPGA would
> then stream the configuration file to the serial configuration device
> for the other FPGA.
>
> So, questions:
> - Is it possible to do this in such a straighforward manner?
> - Is there a core available to interface to the Active Serial interface
> of the configuration device?
> - What format does the configuration file need to be in?
>
> It strikes me that this should be a simple task to achieve - or am I
> totally wrong?
>
> Thanks,
>
> Colm.
Hi

you have several options 1:

1) implement some sort of JTAG or SPI logic inside the main PCI FPGA,
connect the config device of the second FPGA to that logic, the
drawback is that you need to use some custom software to reflash the
second config memory

2) implement LPT + byteblaster interface inside the first FPGA, then
windows would load default pci driver and you can use Altera tools to
access the second config memory

3) implement some other logic in the main FPGA

I have done tasks similar to 1,2 (well using Xilinx FPGAs but that
doesnt matter).

the LPT+byteblaster method is simple but, you would need to make the
PCI device to be either multi-function device or then dedicate BAR0 to
the virutal LPT port

the 'virtual PCI LPT + jtag cable' project is soon to be added the
brain-snapshot :)

and no, what you think should be simple task isnt so simple, the FPGA
configuration issues are still quite often a major PITA

Antti 
Get my Brain http://antti-brain.com




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search