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I am using 3 * gal22v20's cant change them. Clocks are all wired together and ripple out is connected to the enable of the next chip. After compiling the code the MSD decoder does not count correctly and appears to be taking 9/10 clk pluses to the enable causing it to run the fast on the 3rd chip. here is the original code there are no PCB error. Below that is a remodelled VHDL that is giving errors. Can anyone give me some insighty into this error. Thanks Rob library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity segment_cnt is port( clk,mr,en,pause, clk_in :in std_logic; segs :buffer std_logic_vector(6 downto 0); clk_out ut std_logic; rco : out std_logic ); end segment_cnt; architecture behav of segment_cnt is begin cnt_procrocess(clk, mr) begin if(mr='0') then segs <= "0000001"; elsif(clk'event and clk ='1') then if (pause = '0') then segs <= segs; elsif(en = '0' and pause = '1') then case segs is when "0000001" => -- 0 goto 1 segs<="1001111"; when "1001111" => -- 1 goto 2 segs<="0010010"; when "0010010" => -- 2 goto 3 segs<="0000110"; when "0000110"=> -- 3 goto 4 segs<="1001100"; when "1001100" => -- 4 goto 5 segs<="0100100"; when "0100100" => -- 5 goto 6 segs<="0100000"; when "0100000" => -- 6 goto 7 segs<="0001111"; when "0000111" => -- 7 goto 8 segs<="0000000"; when "0000000" => -- 8 goto 9 segs<="0001100"; when others => -- 9 goto 0 segs<="0000001"; end case; end if; end if; end process cnt_proc; clk_out <= clk_in; rco <= '1'when (segs = "0001100" and en ='0')else '0'; end behav; I have tried to add a loop in the VHDL to loop 10 time before the count starts here is that code and the error that it produced. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity segment_cnt is port( clk,mr,en,pause, clk_in :in std_logic; segs :buffer std_logic_vector(6 downto 0); count :buffer std_logic_vector(3 downto 0); clk_out ut std_logic; rco : out std_logic ); end segment_cnt; architecture behav of segment_cnt is begin cnt_procrocess(clk, mr) begin if(mr='0') then segs <= "0000001"; elsif(clk'event and clk ='1') then if (pause = '0') then segs <= segs; elsif(en = '0' and pause = '1') then count <= count +1; if (count ="1001") then count <= "0000"; else count <= "0000"; end if; end if; if(count = "1001" and pause = '1') then case segs is when "0000001" => -- 0 goto 1 segs<="1001111"; when "1001111" => -- 1 goto 2 segs<="0010010"; when "0010010" => -- 2 goto 3 segs<="0000110"; when "0000110"=> -- 3 goto 4 segs<="1001100"; when "1001100" => -- 4 goto 5 segs<="0100100"; when "0100100" => -- 5 goto 6 segs<="0100000"; when "0100000" => -- 6 goto 7 segs<="0001111"; when "0000111" => -- 7 goto 8 segs<="0000000"; when "0000000" => -- 8 goto 9 segs<="0001100"; when others => -- 9 goto 0 segs<="0000001"; end case; end if;end if; end process cnt_proc; clk_out <= clk_in; rco <= '1'when (segs = "0001100" and en ='0')else '0'; end behav; Design optimization (dsgnopt) Device fitting (pla2jed) Error: Logic equation for signal count(3).AR is redefining a banked expression. Error: Logic equation for signal count(2).AR is redefining a banked expression. Error: Logic equation for signal count(1).AR is redefining a banked expression. Error: Logic equation for signal count(0).AR is redefining a banked expression.Article: 109901
AG, See: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_six_easy&languageID=1 or http://tinyurl.com/gxjj9 Austin Analog_Guy wrote: >>Eli Bendersky wrote: >> >>What does this technique lack to be the perfect solution for resets in >>FPGA designs ? It seems that it evades all the common disadvantages of >>conventional sync and async resets. >> >> > > The only thing I see that this technique lacks is the ability to filter > (for noise, glitches) > the incoming reset signal. This approach can filter on the LO-HI > transition of reset, > but not on the HI-LO assertion. > > So, if there is any noise or glitching on the reset input resulting in > a HI-LO transition, all > logic in the FPGA is instantly reset (i.e. asynchronous reset). Most > designs I work with > use some form of analog circuitry to provide the main reset to the > FPGA. > > I do like the fact that reset will be applied even in the absence of a > clock. However, I have not yet implemented this technique because I am > not sure how to provide filtering on the HI-LO transition of the input > reset signal without requiring a clock. Can anyone help with this? > What are your ideas? >Article: 109902
> > Actually, both designs are _indentical_. I know that because we have > > some > > really tough tests for them. In addition, I spent 3-4 hours manually > > inspecting the code, the tests and all the simulation logs.. > > > > > > > > What happened is that the synthesis tool stopped optimising after > > a certain depth. At least, that is my theory... > > > > > > burns > > Just curiosity, have you been able to re-route the old design and got > the same result as before? Yes, I ran the same tool on both designs, same configuration, same options. I ran some isolated tests and it seems like the synthesis tool (Synplify Pro) does not have any problems with the VHDL records. So I guess that the problem is the deeper level of hierarchy that new modules introduce. Any ideas how to make Synplify to flatten (at least partially) the design? burnsArticle: 109903
Radarman, Thanks for the reply. Just wanted to clarify your response: > As for the voltages, 5V devices can see a 3.3V driver just fine. 3.3V > is well above the 2.5V threshold for TTL logic. The trouble is that a > 3.3V device can't interface directly with a 5V driver as it is beyond > the voltage tolerance of most parts. So you are saying even though I can send signals to the computer PS/2 port using 3.3V levels just fine, the signals I receive back will be too high for the Spartan board's components? radarman wrote: > vu_5421 wrote: > > Hello, > > > > I am relatively new to VHDL design, and I bought this board as a first > > time learning kit. > > > > I was mainly interested in the I/O expansion connector for this board. > > It appears that the connector has both 3.3V and 5V outputs. If I had > > wanted to interface the board with a PS/2 port for example (which uses > > 5V logic levels), how can I force the Spartan board to output 5V logic > > levels and not 3.3V output? > > > > I'm not too sure if this is even possible since the FPGA's voltage > > requirements is only 3.3v. > > > > Thanks for your help. > > I believe the S3 starter kit already has a PS/2 port, but I suppose if > you want both a mouse and a keyboard, you would need to add another. > > As for the voltages, 5V devices can see a 3.3V driver just fine. 3.3V > is well above the 2.5V threshold for TTL logic. The trouble is that a > 3.3V device can't interface directly with a 5V driver as it is beyond > the voltage tolerance of most parts. You can simply use a shottky > barrier diode to clamp the voltage at 3.3V, though. A lot of > development boards already include some I/O with clamping diodes, but > I'm not sure about the S3 starter kit board.Article: 109904
KJ wrote: > > The clock not running is the common rebuttal that keeps coming up but if the > clock isn't running then just what behaviour DO you expect out of that part? > ... On critical designs, I use an asynchronous reset/synchronous deassert to make sure the FPGA outputs are in a known state, and remain there until the internal logic has a clock and has been cleanly and synchronously reset. I also don't see how applying an asyncronous reset to internal logic adds anything, and don't bother with it.Article: 109905
For 5V to 3.3V interfacing: Just use a ~100 ohm series resistor. The S3 has clamp diodes to Vcco and ground, so you are not violating any specifications using the series resistor. http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf applies to Spartan 3, 3E as well. Many 5V TTL drivers do not really drive all the way to 5V, check to see if they are true CMOS output structures (then they do drive to 5V). If they are npn bipolar, or all nmos outputs, then they pull weakly to something less than 5V, and usually can not source more than a few milliamperes into the clamp diodes (and no resistor is needed, at all). AustinArticle: 109906
rob wrote: > I am using 3 * gal22v20's cant change them. > Clocks are all wired together and ripple out is connected to the enable > of the next chip. After compiling the code the MSD decoder does not > count correctly and appears to be taking 9/10 clk pluses to the enable > causing it to run the fast on the 3rd chip. here is the original code > there are no PCB error. Below that is a remodelled VHDL that is giving > errors. Can anyone give me some insighty into this error. The problem is rco is glitching. Since it is created from multiple signals, it can glitch depending on how these signals propagate through the logic. You should be able to see this with a logic analyzer. On hp analyzers, you needed to turn on glitch mode. But all three parts should be failing in the same way. Making rco depend on clk is left as an exercise for the reader. Not sure what you were trying to do with the remodeled VHDL, but it is the wrong approach. Alan NishiokaArticle: 109907
jacko wrote: > jacko wrote: > > jacko wrote: > > > hi > > > > > > MAX II EPM570T100C5 just fits at 68% utilization. > > > altera quotes $13.30 per chip. If i can get io in there, and possibly > > > change the way interrupts are done then bingo. 512 x 16 bit eeprom > > > onboard and an external ram and rom. > > > > Changed design to only mirror P reg on super/user interrupt toggle pin, > > and got down to 303 LEs in the MAX II EPM570T100C5. This gives more > > free space for IO and control. > > Got it down to 222 LEs on the MAX II, not sure how to export to lattice > devices from the altera tool, and how available is the lattice tool? > Is it free??? I don't believe the free version includes any simulation capability. I asked my vendor very nicely and they provided a free, licenced version. I believe the license runs out periodically, but they have given me an update and I expect they will continue to do so. Unlike the Altera tools, it is not keyed to the NIC or other machine attribute, so it is very easy to get working. Even though we have all the tools we need at work, I like to test new things at home and these free tools let me do that. It also lets me get around some of the work bureaucracy and gives me more freedom to try things.Article: 109908
Austin, Thanks for the comments. I did a search on Xilinx answers database and found this article: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19146 Answer Record: 19146 It pretty much reinforces what you had mentioned. Although I am still unsure on the result of the series resistor if the I/O pin was a bidirectional pin. I assume it would work fine for a 5V input signal (from PC PS/2 to Spartan3), but what about outputting the same signal to the PC? The article above quotes: "Spartan-3/-3E I/O can be made 5V-tolerant by using an external series current limiting resistor to limit the current into the upper clamp diode to 10 mA. This makes the input 5V-tolerant, but an I/O configured as an output still cannot drive 5 Volts and the resulting VOH does not meet the input specifications of the 5V device." Btw, it appears they would reccommend a 300ohm series resistor instead of a 100ohm. Thanks all for the help. Austin Lesea wrote: > For 5V to 3.3V interfacing: > > Just use a ~100 ohm series resistor. > > The S3 has clamp diodes to Vcco and ground, so you are not violating any > specifications using the series resistor. > > http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf > > applies to Spartan 3, 3E as well. > > Many 5V TTL drivers do not really drive all the way to 5V, check to see > if they are true CMOS output structures (then they do drive to 5V). If > they are npn bipolar, or all nmos outputs, then they pull weakly to > something less than 5V, and usually can not source more than a few > milliamperes into the clamp diodes (and no resistor is needed, at all). > > AustinArticle: 109909
Hi, In Xilinx spartan 3, is it possible to drive both LVDS and SSTL on the same bank with DCI turned on for both IO Standand, i.e SST2_II_DCI and LVDS_25_DCI on the same bank?Article: 109910
vu_ I prefer the ~100 ohms.* As for the other direction, previous post already answered that: a 3.3V cmos driver is more than sufficient, as the TTL hi level is 2.4 volts. Austin *The issue is how much current should you inject into the pmos body diode. The answer is that for the entire device, it shall be less than the JEDEC latchup specification of 200 mA, or else you risk activating the parasitic npnp structure, and causing destructive latchup. So, if a bus has 10 pins, that would be 10 X 20 mA (max) for each pin. 3.3v + 0.5v (diode) = 3.8v 5-3.8=1.2v 1.2v/10 mA = 120 ohms (for twenty IOs, all overdriven). If you have more than 20 IOs, then you should have more than 120 ohms. 300 ohms would allow for ~50 IO's, all driven at the same time high, strongly to 5.0 volts...if my math is right. 300 ohms/50=6 ohms. 1.2v/6ohms=200mA. Yes, I think that is exactly right.Article: 109911
yy, SSTL_II_DCI is a 2.5 V Vcco standard (I am assuming it is 2.5V SSTL). So is LVDS_25_DCI a 2.5V Vcco. That is what is required (same Vcco voltage, for two IO standards to co-exist in the same bank). Just watch your power dissipation from all those split terminations tied from 2.5V to ground. Each SSTLII_DCI is 200 ohms across 2.5V. Each LVDS_25_DCI is 100 ohms across 2.5V. Also make sure you have two 50 ohm resistors connected properly to the reference impedance pins for the bank. Vrn is the nmos reference, tied to Vcco thru the 50 ohms. Vrp is the pmos reference, tied to ground thru its 50 ohms. AustinArticle: 109912
Rob, it looks like you want to build a classical synchronous counter with ripple carry, hopefully without gating the clock. You should decode the terminal count and AND it with the incoming enable to create the enable for the next chip. Why do you make the outgoing enable =0 when in my mind it should be 1 ?? Advice: Run this with a slow clock first, to find basic errors (which I think you have). Peter Alfke, Xilinx, from home ===================== Alan Nishioka wrote: > rob wrote: > > I am using 3 * gal22v20's cant change them. > > Clocks are all wired together and ripple out is connected to the enable > > of the next chip. After compiling the code the MSD decoder does not > > count correctly and appears to be taking 9/10 clk pluses to the enable > > causing it to run the fast on the 3rd chip. here is the original code > > there are no PCB error. Below that is a remodelled VHDL that is giving > > errors. Can anyone give me some insighty into this error. > > The problem is rco is glitching. Since it is created from multiple > signals, it can glitch depending on how these signals propagate through > the logic. You should be able to see this with a logic analyzer. On > hp analyzers, you needed to turn on glitch mode. But all three parts > should be failing in the same way. > > Making rco depend on clk is left as an exercise for the reader. > > Not sure what you were trying to do with the remodeled VHDL, but it is > the wrong approach. > > Alan NishiokaArticle: 109913
"Austin Lesea" <austin@xilinx.com> wrote: > > Also make sure you have two 50 ohm resistors connected properly to the > reference impedance pins for the bank. Vrn is the nmos reference, tied to > Vcco thru the 50 ohms. Vrp is the pmos reference, tied to ground thru its > 50 ohms. > > Austin Vrp goes down and Vrn goes up. Vrp goes down and Vrn goes up. Vrp goes down and Vrn goes up....(repeat). Okay, Vrp goes down and Vrn goes up. "Did you guys check the Vrp/Vrn resistors?" "Yeah, twice" "Check'm again!" "Why?" "Check'm again" "Ooooops, I got one of'm wrong. I saw the 'N' of the diff pair and thought it was Vrn" "Ya got'm right, now?" "Yep" "Ya sure?" "Nope" "Check'm again" BobArticle: 109914
vu_5421 wrote: > "Spartan-3/-3E I/O can be made 5V-tolerant by using an external series > current limiting resistor to limit the current into the upper clamp > diode to 10 mA. This makes the input 5V-tolerant, but an I/O configured > as an output still cannot drive 5 Volts and the resulting VOH does not > meet the input specifications of the 5V device." The VOH might not meet the VIH spec for some 5v logic family, but in the real world it is almost certain to work if the distance isn't too great and the speed not blindingly fast (you resistor is after all mostly working against input capacitance). For a hobby project or experiment, that's likely enough. Otherwise, look at the specs of the actual receiver. Another thing to build confidence - try substituting a vastly larger series resistor. Keep increasing it until you get errors. Compare that value to the 100 or 300 ohms being considered, and you have some rough but practical idea of your margin (ie, if it works with a series resistor of a few K, 300 ohms isn't much to worry about)Article: 109915
Check the specifications for the PS/2 pins as output and as input. Vih min is the most critical parameter, the lowest voltage that is guaranteed to be recognized as a High logic input level. If it is well below 3.0 V, then you have no problem. If is higher, you ned som level-shifting arrangements. Peter Alfke ========== vu_5421 wrote: > Hello, > > I am relatively new to VHDL design, and I bought this board as a first > time learning kit. > > I was mainly interested in the I/O expansion connector for this board. > It appears that the connector has both 3.3V and 5V outputs. If I had > wanted to interface the board with a PS/2 port for example (which uses > 5V logic levels), how can I force the Spartan board to output 5V logic > levels and not 3.3V output? > > I'm not too sure if this is even possible since the FPGA's voltage > requirements is only 3.3v. > > Thanks for your help.Article: 109916
Ed McGettigan wrote: > The most likely problem that you are is that you are not setting up the > chain correctly. If you have only the 4VLX25 in the chain with a bit > file attached to it, this is wrong. You need to describe the chain as > seen from the System ACE part in iMPACT correctly or the ACE file won't > work as it has no information as to what device it is supposed to be > downloaded into. > > ML401 > ----- > Device #0 XCF32P > Device #1 XC4VLX25 <- Assign bit file here > Device #2 XC95144LX > > And make sure that you are using 8.1i-SP3 or above as there were some > issues with V-4 support in earlier versions. > > This was covered in a recent thread > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b734e6591d700376/e80ce592bf58ea4c?lnk=gst&rnum=3#e80ce592bf58ea4c Thanks Ed, right you are indeed. Next to the icon depicturing the System ACE chip I only had a vc4vlx25 icon. I'm so close, but ... do I really need the configuration for the other devices in the chain? I just want to bypass them, but if I right-click "Add Xilinx Device", then it seems I have to specify the configuration for it. In a vain attempt, I tried to read back the configuration of the xcf32p and xc95144xl, but for the xcf32p it never made it past 0%. I read the thread above, but it just say "add the missing devices". Clearly I'm missing something here. (BTW I'm using the most current WebPACK release 8.2.01i and the ML401). Thanks, TommyArticle: 109917
Tommy Thorn wrote: > Ed McGettigan wrote: > > The most likely problem that you are is that you are not setting up the > > chain correctly. If you have only the 4VLX25 in the chain with a bit > > file attached to it, this is wrong. You need to describe the chain as > > seen from the System ACE part in iMPACT correctly or the ACE file won't > > work as it has no information as to what device it is supposed to be > > downloaded into. > > > > ML401 > > ----- > > Device #0 XCF32P > > Device #1 XC4VLX25 <- Assign bit file here > > Device #2 XC95144LX > > > > And make sure that you are using 8.1i-SP3 or above as there were some > > issues with V-4 support in earlier versions. > > > > This was covered in a recent thread > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b734e6591d700376/e80ce592bf58ea4c?lnk=gst&rnum=3#e80ce592bf58ea4c > > Thanks Ed, right you are indeed. Next to the icon depicturing the > System ACE chip I only had a vc4vlx25 icon. > > I'm so close, but ... do I really need the configuration for the other > devices in the chain? I just want to bypass them, but if I right-click > "Add Xilinx Device", then it seems I have to specify the configuration > for it. In a vain attempt, I tried to read back the configuration of > the xcf32p and xc95144xl, but for the xcf32p it never made it past 0%. > I read the thread above, but it just say "add the missing devices". > > Clearly I'm missing something here. > > (BTW I'm using the most current WebPACK release 8.2.01i and the ML401). > > Thanks, > Tommy all other devices need to be in BYPASS (eg no config) but the during ACE file generation it required to know what devices are in chain so the ACE file can have proper JTAG header and trailer anttiArticle: 109918
Hi Austin, ...but the datasheet tells that there should be no more than one DCI with Split termination on the same bank? i mean what should be the assignment of the pin that is LVDS but in the SSTL_II bank? should it assign it to SSTL_II_DCI instead? Ayon kay Austin Lesea: > yy, > > SSTL_II_DCI is a 2.5 V Vcco standard (I am assuming it is 2.5V SSTL). > So is LVDS_25_DCI a 2.5V Vcco. > > That is what is required (same Vcco voltage, for two IO standards to > co-exist in the same bank). > > Just watch your power dissipation from all those split terminations tied > from 2.5V to ground. > > Each SSTLII_DCI is 200 ohms across 2.5V. Each LVDS_25_DCI is 100 ohms > across 2.5V. > > Also make sure you have two 50 ohm resistors connected properly to the > reference impedance pins for the bank. Vrn is the nmos reference, tied > to Vcco thru the 50 ohms. Vrp is the pmos reference, tied to ground > thru its 50 ohms. > > AustinArticle: 109919
Antti wrote: > all other devices need to be in BYPASS (eg no config) > but the during ACE file generation it required to know > what devices are in chain so the ACE file can have > proper JTAG header and trailer Finally. Thanks Antti. What I needed were two key files: - %XILINX%\xcfp\data\xcf32p_vo48.bsd and - %XILINX%\xc9500xl\data\xc95144xl_tq100.bsd It definitely wasn't obvious to me, but I should probably have perused the ref designs more careful; ml40x_bit2ace.bit had the secret sauce. Thanks all. Hopefully this may help others trying to ACE designs outside the EDK. TommyArticle: 109920
The way we do it in our development board products is to use a bus switch to protect the Spartan-3 with pullups to 5V on the keyboard side to ensure we make 5V CMOS levels. Using the bus switch, or a series resistor, is probably better than an active device as some lines are bi-directional using open drain style driving. Controlling an active driver can have a few issues if you are not very careful on these lines. Have a look at our schematics as to what we do. Follow link to our PS2 module on our module page http://www.enterpoint.co.uk/moelbryn/modules/modules.html to access them. Most keyboards etc with PS2 will be happy with TTL level capable of being driven by the Spartan-3 but occasionally we have seen some that need the higher CMOS levels. John Adair Enterpoint Ltd. vu_5421 wrote: > Hello, > > I am relatively new to VHDL design, and I bought this board as a first > time learning kit. > > I was mainly interested in the I/O expansion connector for this board. > It appears that the connector has both 3.3V and 5V outputs. If I had > wanted to interface the board with a PS/2 port for example (which uses > 5V logic levels), how can I force the Spartan board to output 5V logic > levels and not 3.3V output? > > I'm not too sure if this is even possible since the FPGA's voltage > requirements is only 3.3v. > > Thanks for your help.Article: 109921
Hi all, I have a microblaze processor that I've built using the EDK and afterwards simulated and it seems to work fine. Now I need to make two instances of this Microblaze system in my design. Can I use the same module and instantiate it twice or I maybe I need to make a copy of the system and name it differently. If I instance the same module twice I figured out that it will be problematic to fill the BRAM with code data. Can anyone help ? Thanks, Mordehay.Article: 109922
hi the features of S3A are so close to S3E that it makes one think - why? Why release a device that is so similar? I think I have maybe guessed the answer to this - S3A do have internal flash configuration ! That would explain it. It would also correlate to some announcments made 6 months ago about "spartan3 with flash". I hope I am guessing correctly! :) Hm if I think more, this would also explain why I initially assumed S3A doesnt support SPI loading - it has internal flash! I wonder if the internal flash is rewriteable from FPGA logic? If it is not then Xilinx is still behing Lattice, as Lattice XP2 FPGAs do allow the onchip flash access from user logic (ASFAIK). AnttiArticle: 109923
>the features of S3A are so close to S3E that it makes one think - why? >Why release a device that is so similar? >I think I have maybe guessed the answer to this - S3A do have internal >flash configuration ! That would explain it. It would also correlate to >some announcments made 6 months ago about "spartan3 with flash". >I hope I am guessing correctly! >:) >Hm if I think more, this would also explain why I initially assumed S3A >doesnt support SPI loading - it has internal flash! What load modes does it support? >I wonder if the internal flash is rewriteable from FPGA logic? If it is >not then Xilinx is still behing Lattice, as Lattice XP2 FPGAs do allow >the onchip flash access from user logic (ASFAIK). This would (hopefully) save pcb space.. Now a fpga that will reprogram itself would be something ;)Article: 109924
"Antti" <Antti.Lukats@xilant.com> wrote: >hi > >the features of S3A are so close to S3E that it makes one think - why? >Why release a device that is so similar? > >I think I have maybe guessed the answer to this - S3A do have internal >flash configuration ! That would explain it. It would also correlate to >some announcments made 6 months ago about "spartan3 with flash". > >I hope I am guessing correctly! >:) > >Hm if I think more, this would also explain why I initially assumed S3A >doesnt support SPI loading - it has internal flash! > >I wonder if the internal flash is rewriteable from FPGA logic? If it is >not then Xilinx is still behing Lattice, as Lattice XP2 FPGAs do allow >the onchip flash access from user logic (ASFAIK). Got any links where there is more information? An S3 with internal flash + copy protection is something I could use in a design which needs some work on the PCB anyway... -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
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