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Messages from 110875

Article: 110875
Subject: Re: Simple multiply in Xilinx?
From: "Alan Nishioka" <alan@nishioka.com>
Date: 24 Oct 2006 20:47:23 -0700
Links: << >>  << T >>  << A >>
Gary Spivey wrote:
> In the following module,
> module mult (output reg[7:0] z, input [3:0] a);
>     always @* begin
>        z = a*a;
>     end
> endmodule
>
> ModelSim returns 225 when a is 15, but the Xilinx implementation on a
> Spartan3 returns a 1 (-1 * -1). Does anybody know why Xilinx ISE is
> interpreting the four bit numbers as signed numbers rather than unsigned?

Xilinx ISE 8.1.03 returns 225 in pre and post simulation (ISE
simulator).
Are you running this on hardware or simulation?

Alan Nishioka


Article: 110876
Subject: Re: Simple multiply in Xilinx?
From: "Gary Spivey" <gspivey@georgefox.edu>
Date: Wed, 25 Oct 2006 04:30:32 GMT
Links: << >>  << T >>  << A >>
I did not simulate in Xilinx - it was implemented on a Digilent Spartan 3 
board.

-Gary

"Alan Nishioka" <alan@nishioka.com> wrote in message 
news:1161748043.570674.166420@f16g2000cwb.googlegroups.com...
> Gary Spivey wrote:
>> In the following module,
>> module mult (output reg[7:0] z, input [3:0] a);
>>     always @* begin
>>        z = a*a;
>>     end
>> endmodule
>>
>> ModelSim returns 225 when a is 15, but the Xilinx implementation on a
>> Spartan3 returns a 1 (-1 * -1). Does anybody know why Xilinx ISE is
>> interpreting the four bit numbers as signed numbers rather than unsigned?
>
> Xilinx ISE 8.1.03 returns 225 in pre and post simulation (ISE
> simulator).
> Are you running this on hardware or simulation?
>
> Alan Nishioka
> 



Article: 110877
Subject: XPS crashes while performing clock DRCs when I have DCR components
From: Jeff Cunningham <jcc@sover.net>
Date: Wed, 25 Oct 2006 00:56:09 -0400
Links: << >>  << T >>  << A >>
I am using XPS 8.2.01i to create a V4FX12 design for the the xilinx 
ML403 board. I used bsb to create a design with a 300 Mhz PPC, a 100 Mhz 
PLB and the PLB_DDR interface. No internal block ram. It got that to 
build just fine, after figuring out to comment out a line in 
etc/fast_runtime.opt to deal with no block ram, as specified in answer 
23657. Next, tried adding my own custom DCR bus, and the DCR based 
interrupt controller. When I do this, I got the following error:

...

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v1_12_a/data/ddr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/intc_core_v1_00_c/data/intc_core_v2_1_0.tc
l ...

Performing System level DRCs on properties...

Check platform configuration ...
plb_v34 (plb) - C:\dimatix\custom403M\system.mhs line 78 - 2 master(s) : 
1 slave(s)

dcr_v29 (dcr_v29_0) - C:\dimatix\custom403M\system.mhs line 197 - 1 
master(s) : 1 slave(s)

Check port drivers...

Performing Clock DRCs...

This application has discovered an exceptional condition from which it 
cannot recover.
make: *** [implementation/system.bmm] Error 1

Done!



I tried building a design up from scratch again, this time leaving out 
my custom peripheral and just adding the DCR interrupt controller. Again 
I get the same error. Does anyone have an idea what I could be doing 
wrong? Is the sys_clk_s signal the correct clock to use for the DCR bus? 
Some of the interrupt controller pins are not hooked up, but even before 
when they were hooked up I got this problem. It looks like the problem 
happens when it is doing a DRC on the clocks. I couldn't find anything 
searching the xilinx answer database. Thanks in advance for any hints 
you can offer.

Here is a copy of the mhs file:

# 
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.01 Build 
EDK_Im_Sp1.3
# Tue Oct 24 23:36:16 2006
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:	 virtex4
# Device:	 xc4vfx12
# Package:	 ff668
# Speed Grade:	 -10
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# Instruction Cache: 16 KB
# Total Off Chip Memory :  64 MB
# - DDR_SDRAM_32Mx32 =  64 MB
###############################################################################


  PARAMETER VERSION = 2.1.0


  PORT fpga_0_DD_SDRAM_64Mx32_DDR_Clk_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O
  PORT fpga_0_DDRSDRAM_64Mx32_DDR_Clkn_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O
  PORT fpga_0_DDR_DRAM_64Mx32_DDR_Addr_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]
  PORT fpga_0_DDR_SRAM_64Mx32_DDR_BankAddr_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]
  PORT fpga_0_DDR_SDAM_64Mx32_DDR_CASn_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O
  PORT fpga_0_DDR_SDRM_64Mx32_DDR_CKE_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O
  PORT fpga_0_DDR_SDRA_64Mx32_DDR_CSn_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O
  PORT fpga_0_DDR_SDRAM64Mx32_DDR_RASn_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O
  PORT fpga_0_DDR_SDRAM_4Mx32_DDR_WEn_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O
  PORT fpga_0_DDR_SDRAM_6Mx32_DDR_DM_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]
  PORT fpga_0_DDR_SDRAM_64x32_DDR_DQS_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]
  PORT fpga_0_DDR_SDRAM_64M32_DDR_DQ_pin = 
fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]
  PORT fpga_0_DDR_CLK_FB = dr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ 
= 100000000
  PORT sys_clk_pin = dcm_clk_, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc405_virtex4
  PARAMETER INSTANCE = ppc405_0
  PARAMETER HW_VER = 1.01.a
  BUS_INTERFACE JTAGPPC = jtagppc_0_0
  BUS_INTERFACE IPLB = plb
  BUS_INTERFACE DPLB = plb
  BUS_INTERFACE MDCR = dcr_v29_0
  PORT PLBCLK = sys_clk_s
  PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
  PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
  PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
  PORT RSTC405RESETCHIP = RSTC405RESETCHIP
  PORT RSTC405RESETCORE = RSTC405RESETCORE
  PORT RSTC405RESETSYS = RSTC405RESETSYS
  PORT CPMC405CLOCK = proc_clk_s
END

BEGIN jtagppc_cntlr
  PARAMETER INSTANCE = jtagppc_0
  PARAMETER HW_VER = 2.00.a
  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
END

BEGIN proc_sys_reset
  PARAMETER INSTANCE = reset_block
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_EXT_RESET_HIGH = 0
  PORT Ext_Reset_In = sys_rst_s
  PORT Slowest_sync_clk = sys_clk_s
  PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
  PORT Core_Reset_Req = C405RSTCORERESETREQ
  PORT System_Reset_Req = C405RSTSYSRESETREQ
  PORT Rstc405resetchip = RSTC405RESETCHIP
  PORT Rstc405resetcore = RSTC405RESETCORE
  PORT Rstc405resetsys = RSTC405RESETSYS
  PORT Bus_Struct_Reset = sys_bus_reset
  PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
  PARAMETER INSTANCE = plb
  PARAMETER HW_VER = 1.02.a
  PARAMETER C_DCR_INTFCE = 0
  PARAMETER C_EXT_RESET_HIGH = 1
  PORT SYS_Rst = sys_bus_reset
  PORT PLB_Clk = sys_clk_s
END

BEGIN plb_ddr
  PARAMETER INSTANCE = DDR_SDRAM_64Mx32
  PARAMETER HW_VER = 1.12.a
  PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
  PARAMETER C_PLB_CLK_PERIOD_PS = 10000
  PARAMETER C_REG_DIMM = 0
  PARAMETER C_DDR_TMRD = 20000
  PARAMETER C_DDR_TWR = 20000
  PARAMETER C_DDR_TRAS = 60000
  PARAMETER C_DDR_TRC = 90000
  PARAMETER C_DDR_TRFC = 80000
  PARAMETER C_DDR_TRCD = 30000
  PARAMETER C_DDR_TRRD = 15000
  PARAMETER C_DDR_TRP = 30000
  PARAMETER C_DDR_TREFC = 70300000
  PARAMETER C_DDR_TREFI = 7800000
  PARAMETER C_DDR_AWIDTH = 13
  PARAMETER C_DDR_COL_AWIDTH = 9
  PARAMETER C_DDR_BANK_AWIDTH = 2
  PARAMETER C_DDR_DWIDTH = 32
  PARAMETER C_MEM0_BASEADDR = 0xfc000000
  PARAMETER C_MEM0_HIGHADDR = 0xffffffff
  BUS_INTERFACE SPLB = plb
  PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
  PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
  PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
  PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
  PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
  PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
  PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
  PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
  PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
  PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
  PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
  PORT Clk90_in = clk_90_s
  PORT Clk90_in_n = clk_90_n_s
  PORT PLB_Clk_n = sys_clk_n_s
  PORT DDR_Clk90_in = ddr_clk_90_s
  PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN util_vector_logic
  PARAMETER INSTANCE = sysclk_inv
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_SIZE = 1
  PARAMETER C_OPERATION = not
  PORT Op1 = sys_clk_s
  PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
  PARAMETER INSTANCE = clk90_inv
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_SIZE = 1
  PARAMETER C_OPERATION = not
  PORT Op1 = clk_90_s
  PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
  PARAMETER INSTANCE = ddr_clk90_inv
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_SIZE = 1
  PARAMETER C_OPERATION = not
  PORT Op1 = ddr_clk_90_s
  PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
  PARAMETER INSTANCE = dcm_0
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLK90_BUF = TRUE
  PARAMETER C_CLKFX_BUF = TRUE
  PARAMETER C_CLKFX_DIVIDE = 1
  PARAMETER C_CLKFX_MULTIPLY = 3
  PARAMETER C_CLKIN_PERIOD = 10.000000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_DFS_FREQUENCY_MODE = HIGH
  PARAMETER C_DLL_FREQUENCY_MODE = LOW
  PARAMETER C_EXT_RESET_HIGH = 1
  PORT CLKIN = dcm_clk_s
  PORT CLK0 = sys_clk_s
  PORT CLK90 = clk_90_s
  PORT CLKFX = proc_clk_s
  PORT CLKFB = sys_clk_s
  PORT RST = net_gnd
  PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
  PARAMETER INSTANCE = dcm_1
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLK90_BUF = TRUE
  PARAMETER C_CLKIN_PERIOD = 10.000000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_DLL_FREQUENCY_MODE = LOW
  PARAMETER C_PHASE_SHIFT = 12
  PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
  PARAMETER C_EXT_RESET_HIGH = 0
  PORT CLKIN = ddr_feedback_s
  PORT CLK90 = ddr_clk_90_s
  PORT CLK0 = dcm_1_FB
  PORT CLKFB = dcm_1_FB
  PORT RST = dcm_0_lock
  PORT LOCKED = dcm_1_lock
END

BEGIN dcr_v29
  PARAMETER INSTANCE = dcr_v29_0
  PARAMETER HW_VER = 1.00.a
END

BEGIN dcr_intc
  PARAMETER INSTANCE = dcr_intc_0
  PARAMETER HW_VER = 1.00.b
  BUS_INTERFACE SDCR = dcr_v29_0
  PORT DCR_Clk = sys_clk_s
  PORT DCR_Rst = sys_bus_reset
END



Article: 110878
Subject: Stream cipher
From: "gen_vlsi" <jesuraj.vinoth@gmail.com>
Date: 25 Oct 2006 00:40:04 -0700
Links: << >>  << T >>  << A >>
Hi,

        Can anyone suggest a good stream cipher algorithm for hardware
implementation.


Article: 110879
Subject: Supported bus widths for RLDRAM on Virtex4?
From: Your name <sjalloq@hotmail.com>
Date: 25 Oct 2006 07:57:06 GMT
Links: << >>  << T >>  << A >>
Hi there,

I'm trying to decide on which FPGA vendor to use for a project out of 
Xilinx and Altera.  The one we chose will depend on a certain memory 
bandwidth being met so I'm interested in the maximum supported bus widths.

I'm currently heading down the RLDRAM route and have been trying to figure 
out how many devices are supported on the larger Virtex-4 devices.  Does 
anyone have any experience of implementing this memory on Xilix?  I've 
searched through the Xilinx doco and have come up with nothing concrete at 
all.  The Altera doco clearly states the number of devices supported for 
each device and is generally much better quality.

Any help appreciated.  SJ.

-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 110880
Subject: Xilinx MIG 1.6 doesn't launch
From: Your name <sjalloq@hotmail.com>
Date: 25 Oct 2006 08:03:49 GMT
Links: << >>  << T >>  << A >>
Hi there,

I've recently installed the Xilinx ISE toolset so that I can play with the 
Memory Interface Generator.  I followed the readme and installed ISE 8.1i, 
8.1i_SP3 and then MIG 1.6.  When I open CORE Generator and select MIG from 
the drop down list nothing happens. I get the "Customise" and "View Data 
Sheet" links but when I click on them nothing happens.

Is there another download that I've missed or is the Xilinx software just 
flaky?

Thanks.

-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 110881
Subject: Re: Xilinx MIG 1.6 doesn't launch
From: Shareef <sjalloq@hotmail.com>
Date: 25 Oct 2006 08:36:48 GMT
Links: << >>  << T >>  << A >>
Appologies for the missing information.  I am running on win32 so it's not 
the obvious.

Shareef.
 
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in
news:1161767431.105289.177190@b28g2000cwb.googlegroups.com: 

> You don't say on what platform your are.
> If it's not win32, then it's normal, MIG is only for windows.
> 
> If you're on win32, I have no idea then ...
> 
>  Sylvain
> 

-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 110882
Subject: V5LXT support for ISE released yesterday
From: "Antti" <Antti.Lukats@xilant.com>
Date: 25 Oct 2006 01:58:02 -0700
Links: << >>  << T >>  << A >>
silently - but its really available for downloads.

first you read 5 different answer records, then download 5
different updates, but then ISE should be patched to support
V5LXT designs!

Antti


Article: 110883
Subject: Re: Xilinx MIG 1.6 doesn't launch
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 25 Oct 2006 02:10:31 -0700
Links: << >>  << T >>  << A >>
You don't say on what platform your are.
If it's not win32, then it's normal, MIG is only for windows.

If you're on win32, I have no idea then ...

 Sylvain

Your name wrote:
> Hi there,
>
> I've recently installed the Xilinx ISE toolset so that I can play with the
> Memory Interface Generator.  I followed the readme and installed ISE 8.1i,
> 8.1i_SP3 and then MIG 1.6.  When I open CORE Generator and select MIG from
> the drop down list nothing happens. I get the "Customise" and "View Data
> Sheet" links but when I click on them nothing happens.
>
> Is there another download that I've missed or is the Xilinx software just
> flaky?
>
> Thanks.
> 
> -- 
> Posted via a free Usenet account from http://www.teranews.com


Article: 110884
Subject: Re: Survey on Quartus SOPC/Nios-II
From: "Francesco" <francesco.poderico@trendcomms.com>
Date: 25 Oct 2006 02:29:32 -0700
Links: << >>  << T >>  << A >>
If you go for Picoblaze,don't forgot do try the C compiler on
www.poderico.co.uk
and if you like, then send me an email I will send you the newer
version of the compiler and few more library (for example the LCD.h
library)

Regards,
Francesco

Chris wrote:
> I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx
> Spartan3E and PicoBlaze.  I need a soft core processor and I think PicoBlaze
> would be enough.  SOPC and Nios-II is very powerful but the learning curve
> looks like a potential nightmare to me.  In order to use SOPC I might have
> to get involved writing custom components to do the job and then one has to
> master the Avalon interface.  That looks like a lot of potential debugging
> time.
>
> The Xilinx solution seems more direct, and under my control, since PicoBlaze
> is stand alone and does not depend on so many bus interrelated components
> and SOPC infrastructure.  Easier and quicker to write direct interfaces.
> Nios seems to need much more of the SOPC (RAM,ROM,Avalon,etc) around it to
> work.
>
> Also, it seems like the Nios/SOPC solution is likely to require far more
> gates than a Xilinx/PicoBlaze implementation.
>
> I would be curious to know any of your experiences with SOPC/Nios-II.  I
> have very limited R&D time for this project.
> 
> Thanks,  Chris.


Article: 110885
Subject: Re: What should I do with std.textio.all of ModelSim
From: "KJ" <kkjennings@sbcglobal.net>
Date: Wed, 25 Oct 2006 09:56:50 GMT
Links: << >>  << T >>  << A >>
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1161739434.857182.201350@b28g2000cwb.googlegroups.com...
> Hi,
> I have a problem with textio library while compiling a file using
> ModelSim.
>
> I have use the library:
> use std.textio.all;    -- for Read(), Write()
>
> It had worked before and now I don't know why it generates an error:
> -- * Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> Unknown identifier "read_mode".
> -- ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112)
> FILE declaration was written using 1076-1993 syntax. Recompile using
> the -93 option.
>
> This is the line with noted error:
> -- changed for vhdl92 syntax:
>    file input : TEXT open read_mode is "STD_INPUT";            -- line
> 18
>
> I checked related *.mpf file and there is a line:
> [vcom]
> ; Turn on VHDL-1993 as the default. Normally is off.
> VHDL93 = 1
>
> So it is assumed that VHDL93 is specified. What should I do now to
> correct the error?

That line in the .MPF file is not quite the end of the story.  If you have a 
file in your project list you can change the properties to have it compile 
using either '87, '93 or '02 which will override the default.  Since that 
source file isn't typically in the list of files that you would normally 
compile it might be that this file got inadvertantly recompiled at some 
point using the '87 syntax.

Try dragging that source file over into the project workspace window and 
right click on it to manually change the property to be '93 syntax and 
recompile.  After that you can remove the source from the workspace.

KJ 



Article: 110886
Subject: Re: Microblaze uclinux Kernel panic
From: "Francesco" <francesco.poderico@trendcomms.com>
Date: 25 Oct 2006 03:16:50 -0700
Links: << >>  << T >>  << A >>
Hi David,
it was my fault.
I never had any experience in the past with linux...

I had this problem because I changed the auto-config.in file without
delete all the dependencies correctly...
After changing the auto-config.in file
My mistake was that I typed
make clean     and then
make config.

this is wrong in my opinion.. what I should have done is to type
make distclean  and then
make menuconfig

In this way I deleted not only the object file but even all the
dependencies and all my previous settings

after that I never ever had any kind of problem! I added and removed
MAC, GPIO, etc.
uclinux is running now!

I hope this help :-)

Francesco


David Ashley wrote:
> Francesco wrote:
> > Yestarday I manage to compile the kernel!
> > it is working now!!!
> > As first attempt I don't have the 10/100 MAC yet.
> > My next step will be to add a 10/100 MAC and try some network
> > applications.
>
> Um, do you think maybe you can share exactly what you
> did to fix the problem? :)
>
> -Dave
>
>
> --
> David Ashley                http://www.xdr.com/dash
> Embedded linux, device drivers, system architecture


Article: 110887
Subject: Re: DDR SDRAM access with MPMC2, Databus Width
From: "Mack" <disentis@gmx.li>
Date: 25 Oct 2006 04:41:13 -0700
Links: << >>  << T >>  << A >>
@Guru: I think PARAMETER C_PLB_0_PLB_NUM_MASTERS=3D2 is correct, when i
set the value to 1, then i get the implementation error:
logical net 'plb_Sl_MBusy<1>' has multiple driver(s):
     pin O on block plb2opb/plb2opb/BGO_MBusy<1>1 with type LUT3,
     pin O on block
mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0/mpmc2_ddr_p_100mhz_x16_hyb25d5121=
60bc_6_0/mpmc2_plb_if_0/_n08872
with type LUT2

@MM: There is only one memory chip on my eval board, so the databus
should be 16 bit.
Now i worked out that the original mpmc2 reference design
"v4fx12lc_ddr_idpp_100mhz" also have this memory problem. The same
behaviour, a write to 0x0 also appears at 0x0+8. I built it as a blank
XPS design importing system.mhs, system.ucf files and ipcores.
Now I=B4m quite confused if it is principally possible to interface a 16
bit memory correctly. I suppose there could be wrong parameter
settings.


Mack


Article: 110888
Subject: Re: Simple multiply in Xilinx?
From: "Alan Nishioka" <alan@nishioka.com>
Date: 25 Oct 2006 04:52:50 -0700
Links: << >>  << T >>  << A >>
Gary Spivey wrote:
> In the following module,
> module mult (output reg[7:0] z, input [3:0] a);
>     always @* begin
>        z = a*a;
>     end
> endmodule
>
> ModelSim returns 225 when a is 15, but the Xilinx implementation on a
> Spartan3 returns a 1 (-1 * -1). Does anybody know why Xilinx ISE is
> interpreting the four bit numbers as signed numbers rather than unsigned?

What results do you get for all the other numbers?  (8 * 8, for
example)

Alan Nishioka


Article: 110889
Subject: Re: What should I do with std.textio.all of ModelSim
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 25 Oct 2006 05:36:46 -0700
Links: << >>  << T >>  << A >>

KJ wrote:
> "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
> news:1161739434.857182.201350@b28g2000cwb.googlegroups.com...
> > Hi,
> > I have a problem with textio library while compiling a file using
> > ModelSim.
> >
> > I have use the library:
> > use std.textio.all;    -- for Read(), Write()
> >
> > It had worked before and now I don't know why it generates an error:
> > -- * Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> > Unknown identifier "read_mode".
> > -- ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112)
> > FILE declaration was written using 1076-1993 syntax. Recompile using
> > the -93 option.
> >
> > This is the line with noted error:
> > -- changed for vhdl92 syntax:
> >    file input : TEXT open read_mode is "STD_INPUT";            -- line
> > 18
> >
> > I checked related *.mpf file and there is a line:
> > [vcom]
> > ; Turn on VHDL-1993 as the default. Normally is off.
> > VHDL93 = 1
> >
> > So it is assumed that VHDL93 is specified. What should I do now to
> > correct the error?
>
> That line in the .MPF file is not quite the end of the story.  If you have a
> file in your project list you can change the properties to have it compile
> using either '87, '93 or '02 which will override the default.  Since that
> source file isn't typically in the list of files that you would normally
> compile it might be that this file got inadvertantly recompiled at some
> point using the '87 syntax.
>
> Try dragging that source file over into the project workspace window and
> right click on it to manually change the property to be '93 syntax and
> recompile.  After that you can remove the source from the workspace.
>
> KJ

Hi KJ,
Thank you very much.

What you said is what exactly I want.

Weng


Article: 110890
Subject: Re: What should I do with std.textio.all of ModelSim
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 25 Oct 2006 05:57:36 -0700
Links: << >>  << T >>  << A >>

Weng Tianxiang wrote:
> KJ wrote:
> > "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
> > news:1161739434.857182.201350@b28g2000cwb.googlegroups.com...
> > > Hi,
> > > I have a problem with textio library while compiling a file using
> > > ModelSim.
> > >
> > > I have use the library:
> > > use std.textio.all;    -- for Read(), Write()
> > >
> > > It had worked before and now I don't know why it generates an error:
> > > -- * Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> > > Unknown identifier "read_mode".
> > > -- ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112)
> > > FILE declaration was written using 1076-1993 syntax. Recompile using
> > > the -93 option.
> > >
> > > This is the line with noted error:
> > > -- changed for vhdl92 syntax:
> > >    file input : TEXT open read_mode is "STD_INPUT";            -- line
> > > 18
> > >
> > > I checked related *.mpf file and there is a line:
> > > [vcom]
> > > ; Turn on VHDL-1993 as the default. Normally is off.
> > > VHDL93 = 1
> > >
> > > So it is assumed that VHDL93 is specified. What should I do now to
> > > correct the error?
> >
> > That line in the .MPF file is not quite the end of the story.  If you have a
> > file in your project list you can change the properties to have it compile
> > using either '87, '93 or '02 which will override the default.  Since that
> > source file isn't typically in the list of files that you would normally
> > compile it might be that this file got inadvertantly recompiled at some
> > point using the '87 syntax.
> >
> > Try dragging that source file over into the project workspace window and
> > right click on it to manually change the property to be '93 syntax and
> > recompile.  After that you can remove the source from the workspace.
> >
> > KJ
>
> Hi KJ,
> Thank you very much.
>
> What you said is what exactly I want.
>
> Weng

Hi KJ,
It is still problem !!!

I moved the textio.vhd to the top of my project window, compiled it
with compilation property set at 1076-1993, everything worked well, but
compiling other vhdl files still generated the following errors:

- Loading package vital_timing
-- Loading package textio
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
Unknown identifier "read_mode".
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112) FILE
declaration was written using 1076-1993 syntax. Recompile using the -93
option.
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): VHDL Compiler
exiting

It seems that the compiler went to "-- Loading package textio" that
generated error information.

I recompiled the textio and got the information:
# Compile of textio.vhd was successful.

Recompiling my vhdl files still generated the same error information as
above.

What can I do to resolve the problem?

Thank you.

Weng


Article: 110891
Subject: Re: Camera link specification
From: "Gabor" <gabor@alacron.com>
Date: 25 Oct 2006 06:02:33 -0700
Links: << >>  << T >>  << A >>

ivan@gmail.com wrote:
> Thanks a lot, I am using VHDL and Xilinx XC2V1000. However because of
> lack number of I/O pins (I only have 30 pins for this purpose, because
> before it was designed to get image directly form camera and a little
> bit surprised when it come to me with PCMCIA framegrabber). Right now I
> am thinking to use small CPLD or FPGA only for camera. Now I am
> understand how to get the image data, but still have question about
> camera control. Does somebody know the signal that needs to be sent to
> controll the camera ?
>
> Again, thank you very much for all your help.
>
> -ivan

The standard method to control the camera via Camera Link uses
asynchronous serial communication at 9600 baud, 8-bits, no parity,
1 stop bit.  Camera manufacturers generally either publish their
protocol or supply control software that can be integrated with
any framegrabber using a standard Camera Link serial communication
.dll file.  The serial link uses LVDS levels, and is called SERTFG for
"serial to framegrabber" and SERTC for "serial to camera" to avoid
confusion associated with the standard TxD and RxD naming.  Some
camera manufacturers offer a .dll file to use a standard PC serial
port,
which will allow you to get the control program running with the least
software effort.  In this case you just need to have hardware to
translate
the serial (COMM port) from the PC from RS-232 to LVDS.

HTH,
Gabor


Article: 110892
Subject: Re: Camera link specification
From: "Gabor" <gabor@alacron.com>
Date: 25 Oct 2006 06:06:36 -0700
Links: << >>  << T >>  << A >>

Guru wrote:
> Why do you want to use a separate chip for LVDS to paralell? Is the
> frequency too high? Spartan3 (or other) has LVDS integrated in IOB.
>
> Cheers,
>
> Guru

I wouldn't recommend this with the Virtex 2 series.  The Camera Link
uses "Channel-Link" 7:1 serializers.  The DCM does not do a very good
job of multiplying the input clock by 7.  Also the frequency at the
individual serial inputs can be as much as 85MHz * 7 = 595 MHz,
so there isn't a lot of room for jitter on the sampling clock,
especially
if you consider the maximum allowed skew over the cable from the
camera.

just my 2 cents,
Gabor


Article: 110893
Subject: Re: What should I do with std.textio.all of ModelSim
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 25 Oct 2006 06:31:28 -0700
Links: << >>  << T >>  << A >>

Weng Tianxiang wrote:
> Weng Tianxiang wrote:
> > KJ wrote:
> > > "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
> > > news:1161739434.857182.201350@b28g2000cwb.googlegroups.com...
> > > > Hi,
> > > > I have a problem with textio library while compiling a file using
> > > > ModelSim.
> > > >
> > > > I have use the library:
> > > > use std.textio.all;    -- for Read(), Write()
> > > >
> > > > It had worked before and now I don't know why it generates an error:
> > > > -- * Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> > > > Unknown identifier "read_mode".
> > > > -- ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112)
> > > > FILE declaration was written using 1076-1993 syntax. Recompile using
> > > > the -93 option.
> > > >
> > > > This is the line with noted error:
> > > > -- changed for vhdl92 syntax:
> > > >    file input : TEXT open read_mode is "STD_INPUT";            -- line
> > > > 18
> > > >
> > > > I checked related *.mpf file and there is a line:
> > > > [vcom]
> > > > ; Turn on VHDL-1993 as the default. Normally is off.
> > > > VHDL93 = 1
> > > >
> > > > So it is assumed that VHDL93 is specified. What should I do now to
> > > > correct the error?
> > >
> > > That line in the .MPF file is not quite the end of the story.  If you have a
> > > file in your project list you can change the properties to have it compile
> > > using either '87, '93 or '02 which will override the default.  Since that
> > > source file isn't typically in the list of files that you would normally
> > > compile it might be that this file got inadvertantly recompiled at some
> > > point using the '87 syntax.
> > >
> > > Try dragging that source file over into the project workspace window and
> > > right click on it to manually change the property to be '93 syntax and
> > > recompile.  After that you can remove the source from the workspace.
> > >
> > > KJ
> >
> > Hi KJ,
> > Thank you very much.
> >
> > What you said is what exactly I want.
> >
> > Weng
>
> Hi KJ,
> It is still problem !!!
>
> I moved the textio.vhd to the top of my project window, compiled it
> with compilation property set at 1076-1993, everything worked well, but
> compiling other vhdl files still generated the following errors:
>
> - Loading package vital_timing
> -- Loading package textio
> ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> Unknown identifier "read_mode".
> ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112) FILE
> declaration was written using 1076-1993 syntax. Recompile using the -93
> option.
> ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): VHDL Compiler
> exiting
>
> It seems that the compiler went to "-- Loading package textio" that
> generated error information.
>
> I recompiled the textio and got the information:
> # Compile of textio.vhd was successful.
>
> Recompiling my vhdl files still generated the same error information as
> above.
>
> What can I do to resolve the problem?
>
> Thank you.
>
> Weng

Hi KJ,
I know why your method doesn't work after reading the library contents:
1. My design module bram64_512 is to use Xilinx block ram that was
generated by XilinxCore generator;
2. It has Library XilinxCoreLib that may need textio package;
3. When textio.vhd was deleted from package in library window, it
reappeared in the library window again next time the bram64_512 module
was compiled and still generated the same error information
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
Unknown identifier "read_mode".
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112) FILE
declaration was written using 1076-1993 syntax. Recompile using the -93
option.
** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): VHDL Compiler
exiting

Thank you.

Weng


Article: 110894
Subject: Single Bank Vs Multiple Banks in sdram
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 25 Oct 2006 07:56:31 -0700
Links: << >>  << T >>  << A >>
Hi All,
I was working with a design which stored data in a single bank in a
memory and it worked just fine. Now I have moved my design to a chip
with a smaller capacity (64Mb) so I need use multiple banks.

When I use banks 0 and 1 and try to display image from bank 0, the
image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3,
and when i try to display from bank 0,  the result is ok. Similarly if
I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it
is ok. Has anyone had a similar problem before?

Thanks
Subhasri


Article: 110895
Subject: Re: Single Bank Vs Multiple Banks in sdram
From: "Gabor" <gabor@alacron.com>
Date: 25 Oct 2006 08:03:23 -0700
Links: << >>  << T >>  << A >>

Subhasri krishnan wrote:
> Hi All,
> I was working with a design which stored data in a single bank in a
> memory and it worked just fine. Now I have moved my design to a chip
> with a smaller capacity (64Mb) so I need use multiple banks.
>
> When I use banks 0 and 1 and try to display image from bank 0, the
> image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3,
> and when i try to display from bank 0,  the result is ok. Similarly if
> I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it
> is ok. Has anyone had a similar problem before?
>
> Thanks
> Subhasri

It seems too obvious, but are you sure you're actually driving the
BA[0] address line?  The symptoms look like the line isn't switching...


Article: 110896
Subject: Re: Stream cipher
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Wed, 25 Oct 2006 08:23:25 -0700
Links: << >>  << T >>  << A >>
gen_vlsi wrote:
> Hi,
> 
>         Can anyone suggest a good stream cipher algorithm for hardware
> implementation.
> 

I'd think AES would be a good choice.

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 110897
Subject: Re: ISE 8.2 freeze
From: Gerhard Hoffmann <spamtrap@dk4xp.de>
Date: Wed, 25 Oct 2006 17:41:55 +0200
Links: << >>  << T >>  << A >>
On 24 Oct 2006 07:16:28 -0700, rponsard@gmail.com wrote:

>is that a known bug ?
>
>ISE 8.2 / win XP seems to freeze while synthesing design (no more mouse
>or menu/button action event response... looks like a threading bug)
>
>at the end of computation, it comes back to normal execution.

I don't know if it's a bug or a feature, but it is well known.

Sometimes it happens after just calling up ISE. 
100% CPU for an hour, no indication of what's going on.
Watching it work with the Windows task manager suggests
that the default project is being translated, even if not asked for.
(8.1 here with current service pack)

Gerhard


Article: 110898
Subject: Re: Single Bank Vs Multiple Banks in sdram
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 25 Oct 2006 08:44:41 -0700
Links: << >>  << T >>  << A >>

Gabor wrote:
> Subhasri krishnan wrote:
> > Hi All,
> > I was working with a design which stored data in a single bank in a
> > memory and it worked just fine. Now I have moved my design to a chip
> > with a smaller capacity (64Mb) so I need use multiple banks.
> >
> > When I use banks 0 and 1 and try to display image from bank 0, the
> > image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3,
> > and when i try to display from bank 0,  the result is ok. Similarly if
> > I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it
> > is ok. Has anyone had a similar problem before?
> >
> > Thanks
> > Subhasri
>
> It seems too obvious, but are you sure you're actually driving the
> BA[0] address line?  The symptoms look like the line isn't switching...

Yes I am pretty sure. I can see the lines switch in my post place and
route simulation.
I was just wondering..could this have anything to do with the refresh?


Article: 110899
Subject: Meta-stable problem with MAX-II ?
From: ghelbig@lycos.com
Date: 25 Oct 2006 08:49:45 -0700
Links: << >>  << T >>  << A >>
I'm trying to snag a 90nS pulse with a 16MHz clock.  On paper, it
should work just fine: 62.5 < 90.

What I see is that if the leading edge of the pulse is co-incident with
the leading edge of the clock, the pulse is not clocked in.  (Which I
think it should be; at least on the next clock edge.)

To make it more "interesting", it will then miss the next few pulses;
mayby 10 or so.

After that, it will go back to normal operation, clocking in the pulses
as intended.

Anyone else seen something like this?  Any pointers as to what to look
for?

Regards,
GH




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