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Messages from 113800

Article: 113800
Subject: Re: DCM start up
From: "Brian Davis" <brimdavis@aol.com>
Date: 22 Dec 2006 07:23:19 -0800
Links: << >>  << T >>  << A >>
Roger wrote:
>
> I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro.
> Sometimes after JTAG configuration the DCM just won't lock
>

Do you have a post-configuration startup reset for the DCM's ?

see Answer Record 11778:
    "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures
     correctly after PROG is pulsed, but DLL/DCM/DCI does
     not function correctly when reconfigured

 Also note, when configuring a device from JTAG that also has an
external configuration PROM, it is best to set the mode pins to JTAG,
and/or erase the PROM, to avoid weird configuration problems.
(Answer Records 9013, 16829, 22255)

Brian


Article: 113801
Subject: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
From: "Jon Beniston" <jon@beniston.com>
Date: 22 Dec 2006 07:36:53 -0800
Links: << >>  << T >>  << A >>

> >   Our main problem is when we connect the CF Card to the Board the
> > SYSTEM ACE ERROR light illuminates.  We have checked to make sure that
> > it is formatted correcly using mkdosfs, as recommended by Xilinx.  The
> > only thing loaded on the card is our .bin file.
> >
> >   Does anyone know what else could cause this?
> > 

You have been given the answer already!

Cheers,
Jon


Article: 113802
Subject: Re: Manually creating a LUT in VHDL
From: "David" <dpmontminy@gmail.com>
Date: 22 Dec 2006 08:29:50 -0800
Links: << >>  << T >>  << A >>
Thanks, all of your posts were very helpful.

David


Article: 113803
Subject: Re: Virtex-5 Webpack?
From: Austin <austin@xilinx.com>
Date: Fri, 22 Dec 2006 09:11:14 -0800
Links: << >>  << T >>  << A >>
Bud,

Thanks for letting us know that Altera has a university program, too.

As for newer devices, ask your professor to contact the XUP program, and 
then request what you would like.  We provide full versions of the 
software to Universities if they have a project that is suitable.

It may be that your institution already has what you need.

As a student, however, we can not just ship you anything you ask for, as 
we first need your academic representative to validate your requests.

Our Xilinx Research group also sponsors student projects, reseach, and 
thesis (as appropriate).  Please consider Xilinx for summer internships, 
as well (I always hire one or two, and it is not only summertime).  You 
may email your resume directly to me.  I will try to get it to the 
groups that may have requirements.

Austin (for Xilinx)

bkelly@altera.com wrote:

> My name is Bud Kelly and I am the Area Channel Manager for Altera based
> here in Chelmsford. We have a very comprehensive University Program,
> including software and boards, that I would be happy to discuss with
> you. I can be reached at bkelly@altera.com.
> 
> 
> jonas@mit.edu wrote:
> 
>>Hello! For a long time my lab purchased the lower-cost ISE Base-X kit,
>>which was recently discontinued and its functionality was rolled into
>>WebPack (which is available for free!) Base-X always seemed to contain
>>support for the two smallest of Xilinx's high-end devices. The latest
>>WebPack, however, does not contain support for the V5s. Is there a plan
>>to have V5 support in WebPack in the future?
>>
>>I know the standard Xilinx line on this is "If you're doing high-end
>>development, ISE tools are not going to be a big part of your cost" but
>>in our environment where we have a bunch of students doing development
>>on prototype boards, the license costs can add up quickly.
>>
>>Thanks, 
>>       ...Eric
> 
> 

Article: 113804
Subject: Re: DCM start up
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Fri, 22 Dec 2006 18:52:43 -0000
Links: << >>  << T >>  << A >>
Just read your replies. Lots of good stuff to try. I'll do some experiments.

Thanks very much for taking the time to reply.

Merry Christmas

Rog.

"Roger" <enquiries@rwconcepts.co.uk> wrote in message 
news:458b1cb2$0$8715$ed2619ec@ptn-nntp-reader02.plus.net...
> I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro. 
> Sometimes after JTAG configuration the DCM just won't lock (hence the 
> ChannelUp never happens either). Once it's decided not to work, doing the 
> reconfiguration again or resetting has no effect. If I then configure with 
> an old version of code (also with a power cycle) it works OK with old and 
> new code. Are there any tricks I should know about here either in the VHDL 
> or settings in the tools that anyone can tell me about please as I really 
> need to get around this problem?
>
> TIA,
>
> Rog.
> 



Article: 113805
Subject: Re: Simple questions on IDELAYCTRL vs DCM
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 22 Dec 2006 11:40:30 -0800
Links: << >>  << T >>  << A >>
>Do you have a case open?  Do you have a case number?

I had tried to call Xilinx during the time this was going on but it
appears they were closed or something as I could only get their
answering machine.   I wasn't seeing any posts here and needed to get
on with things.

I gave up on using this many stages and just added a 100MHz oscillator
to the board and used only one DCM to get to 200.  I added a 200Mhz
oscillator to the final design to get around the problem.  I ran the
test board with the 100MHz oscillator for a few weeks and saw no
problems with the idelay after makeing this change.

If there is a test you would like me to run or have any questions about
the tests I ran, feel free to ask.  It's not a cost sensitive design
and I have room to add an oscillator just for the idelay so it's not a
big problem for us.  My only fear now is if it would act up at random.


Article: 113806
Subject: Re: Virtex-5 Webpack?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 23 Dec 2006 08:48:30 +1300
Links: << >>  << T >>  << A >>
Austin wrote:
> Bud,
> 
> Thanks for letting us know that Altera has a university program, too.
> 
> As for newer devices, ask your professor to contact the XUP program, and 
> then request what you would like.  We provide full versions of the 
> software to Universities if they have a project that is suitable.
> 
> It may be that your institution already has what you need.

Nothing like the prospect of loosing the designs to Altera, to
snap Xilinx out of Doze mode :)

Problem is, Austin, that for every prospect that asks in this NG,
probably 99 others simply made the decision based on available tools.

[Some students might actually want to do homework, aka work at home?]

Others might be using smaller chips, but just want to build to V5, as
a training example - viz: "So, How much better IS this V5? "...

To me, Xilinx can chop V5 out of webpack, and mull the consequences.

-jg


Article: 113807
Subject: Re: Simple questions on IDELAYCTRL vs DCM
From: Austin <austin@xilinx.com>
Date: Fri, 22 Dec 2006 12:04:42 -0800
Links: << >>  << T >>  << A >>
Well,

Sorry about that, but the snowstorm in Colorado caused us to send those 
folks home before they were stranded.  San Jose and Singapore took on 
the extra call volume, which may be why you could not get through.

When my lab tested the DCM CLKFX output to the IDELAY ref clock, we 
tested a number of M and D values, but did not test all possible 
combinations.  It may be we needed to.  The folks who are responsible 
for the data sheet only allowed a table of the M and D values we tested 
to be used by the product.  So, what was your M and D value, and 
frequency of Clock IN?  Were you using the DCM for anything else (any 
other outputs connected)?  Was the CLKFB input used (it should not have 
been if all you needed was the CLKFX output, as using it would 
automatically turn on the DLL part of the DCM, and that might have 
created some issues (input clock frequency too low for the DLL in that 
mode).  How soon after the DONE went high was the DCM reset released? 
It may be that the oscillator had not stabalized yet.

Austin

lecroy7200@chek.com wrote:

>>Do you have a case open?  Do you have a case number?
> 
> 
> I had tried to call Xilinx during the time this was going on but it
> appears they were closed or something as I could only get their
> answering machine.   I wasn't seeing any posts here and needed to get
> on with things.
> 
> I gave up on using this many stages and just added a 100MHz oscillator
> to the board and used only one DCM to get to 200.  I added a 200Mhz
> oscillator to the final design to get around the problem.  I ran the
> test board with the 100MHz oscillator for a few weeks and saw no
> problems with the idelay after makeing this change.
> 
> If there is a test you would like me to run or have any questions about
> the tests I ran, feel free to ask.  It's not a cost sensitive design
> and I have room to add an oscillator just for the idelay so it's not a
> big problem for us.  My only fear now is if it would act up at random.
> 

Article: 113808
Subject: Re: Virtex-5 Webpack?
From: Austin <austin@xilinx.com>
Date: Fri, 22 Dec 2006 12:20:56 -0800
Links: << >>  << T >>  << A >>
Jim,

Dozing?  Hardly.

I am unsure where that poster posted, as the thread just magically 
appeared with the Altera reply.

As for students, we like to work with their professors, as trying to 
work with individual students is just not very smart.  As someone who 
has been both a student, and a professor, I have some empathy for each 
of them.

Austin


Article: 113809
Subject: Re: Virtex-5 Webpack?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 23 Dec 2006 10:58:25 +1300
Links: << >>  << T >>  << A >>
Austin wrote:

> Jim,
> 
> Dozing?  Hardly.
> 
> I am unsure where that poster posted, as the thread just magically 
> appeared with the Altera reply.

My news reader shows the OP fine, as 12/11/2006 4:57 a.m. ?
So sorry, no, this is not an Altera-sponsored ploy...

-jg




Article: 113810
Subject: Re: Virtex-5 Webpack?
From: Austin <austin@xilinx.com>
Date: Fri, 22 Dec 2006 14:08:55 -0800
Links: << >>  << T >>  << A >>
OK,

I missed the post on 12/11/2006.

My apologies to the student at MIT.

As I have stated before, I do answer personal emails.

And, they are perfectly free to use anyone's components.  I would rather 
they learn about Xilinx PLDs, but learning a competitor's PLD is just 
fine with me, too.

Austin

Article: 113811
Subject: Help with xilinx simulation?
From: <xx>
Date: Fri, 22 Dec 2006 22:54:48 -0000
Links: << >>  << T >>  << A >>
Hello all,
I am using xilinx ISE 8.2i , my program is as follows,

entity mod1 is
    Port ( a : in  STD_LOGIC;
           y : out  STD_LOGIC);
end mod1;

architecture Behavioral of mod1 is

begin
 y <= a;

end Behavioral;

I need to simulate this simple thing, I created a Test Bench Waveform, which
creates a simulation. I have a clock signal, a, which has 10 periods 100ns
each,
and an output, y, which is constantly zero. Can anyone explain this ?



Article: 113812
Subject: Re: Help with xilinx simulation?
From: "davide" <davide@xilinx.com>
Date: Fri, 22 Dec 2006 15:10:14 -0800
Links: << >>  << T >>  << A >>
What does your testbench stimulus of 'a' look like?  I am guessing it does 
not toggle and is always low.  Try toggling the input stimulus and see how 
'y' responds in the simulation.

-davide

<xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com...
> Hello all,
> I am using xilinx ISE 8.2i , my program is as follows,
>
> entity mod1 is
>    Port ( a : in  STD_LOGIC;
>           y : out  STD_LOGIC);
> end mod1;
>
> architecture Behavioral of mod1 is
>
> begin
> y <= a;
>
> end Behavioral;
>
> I need to simulate this simple thing, I created a Test Bench Waveform, 
> which
> creates a simulation. I have a clock signal, a, which has 10 periods 100ns
> each,
> and an output, y, which is constantly zero. Can anyone explain this ?
>
> 



Article: 113813
Subject: Re: Help with xilinx simulation?
From: <xx>
Date: Fri, 22 Dec 2006 23:55:12 -0000
Links: << >>  << T >>  << A >>
> What does your testbench stimulus of 'a' look like?  I am guessing it does
> not toggle and is always low.  Try toggling the input stimulus and see how
> 'y' responds in the simulation.

The stimulus is automatically applied by the Test Bench Waveofrm wizard,
it is a clock of 5 periods at 1000ns in total (5 periods). There seems to be
little yellow spikes where the clock positive edges are, I don't know what
these are supposed to be. I am supposed to get a clock on y as my module
simple assign y <=a, this is the problem, in the simulation the result is y
=0,
and there are yellow spikes. It's a .tbw file. Do you want me to post it as
an image?

>
> -davide
>
> <xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com...
> > Hello all,
> > I am using xilinx ISE 8.2i , my program is as follows,
> >
> > entity mod1 is
> >    Port ( a : in  STD_LOGIC;
> >           y : out  STD_LOGIC);
> > end mod1;
> >
> > architecture Behavioral of mod1 is
> >
> > begin
> > y <= a;
> >
> > end Behavioral;
> >
> > I need to simulate this simple thing, I created a Test Bench Waveform,
> > which
> > creates a simulation. I have a clock signal, a, which has 10 periods
100ns
> > each,
> > and an output, y, which is constantly zero. Can anyone explain this ?
> >
> >
>
>



Article: 113814
Subject: Re: timing?
From: "motty" <mottoblatto@yahoo.com>
Date: 22 Dec 2006 17:32:53 -0800
Links: << >>  << T >>  << A >>

This again?

You didn't use the advice from the last post.  Your 'always @(in)' is
NOT going to give you what you want.  Always blocks are an ABSOLUTELY
fudamental constuct in the Verilog HDL and you need to understand them.


Also, Verilog isn't like a software programming language.  You need to
understand the hardware you are trying to describe and then code that.
When I first started learning this I used to draw my circuit (using
flip-flops, logic gate, busses, etc) and then use Verilog to describe
the circuit.  I'm not saying you need to do that, but you need to a
least visualize what you are making.

And on this forum, people will be MUCH more responsive if you try
things that are suggested, try to learn on your own, and NOT ask if
someone will write code for you (like requesting someone to code a
testbench).

"(shouldn't be too difficult with just one input and one output)"  You
are right.  It is not too difficult for someone who has taken the
initiative and time to learn how.  The resources are out there.  You
know how to use the Internet apparently, so why not try doing some
research?

By the way, are you an engineer?  Trying to be an engineer?  What is
the purpose of this?

On another note, if your input frequency is within tolerance, you can
use a DCM in the FPGA to divide the clock for you.


Article: 113815
Subject: Re: Virtex-5 Webpack?
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 22 Dec 2006 18:06:57 -0800
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Others might be using smaller chips, but just want to build to V5, as
> a training example - viz: "So, How much better IS this V5? "...
>
> To me, Xilinx can chop V5 out of webpack, and mull the consequences.

I complained about this a long time ago to which Austin said "I don't
see the problem at all".

Since then I've been working on a project targeting a Cyclone and a
Spartan 3E in parallel and now I don't think I'll ever care about V5,
but just wait for Stratix-III. In my experience (everything fully up to
date),
- ISE is 5-10X *SLOWER* than Quartus II (seriously, I can post
details),
- ISE a lot less stable than Quartus,
- Spartan 3E are 10-15% slower than Cyclones,
- (Subjective) ISE is a lot clunky to use (fx. properties are spread
all over the place), and finally
- the free Quartus supports a least one device from every family.

I only regret that there aren't as many excellent development boards
for Altera as there are for Xilinx.

Tommy
PS: My obsession with free tools is not because I'm a cheap-skate; it
has to do with avoiding lock-in and the value of a design that can be
further developped by others for minimal cost.


Article: 113816
Subject: Re: Help with xilinx simulation?
From: <xx>
Date: Sat, 23 Dec 2006 03:08:19 -0000
Links: << >>  << T >>  << A >>
a picture is worth a 1000 words:

http://vhdlblog.blogspot.com/

click on the image to see full size



Article: 113817
Subject: Re: DSP or FPGA for high-speed image processing?
From: "kyori" <ggkyori@gmail.com>
Date: 22 Dec 2006 21:10:27 -0800
Links: << >>  << T >>  << A >>
Thanks for your advice and I am learning the rules.
Tim Wescott wrote:
> kyori wrote:
>
> > Hi,
> >
> > I am going to start a project of onboard high-speed CMOS image
> > processing.
> > I am goint to perform certain *block matching algorithm* or *Fourier
> > Transform* between successive frames and the fps would be 1000 or
> > more..
> >
> >
> > The interface between the CMOS camera and the board is standord
> > CamLink.
> > I've learned that both DSP and FPGA based circuits can do certain
> > onboard image processing tasks, and I'd like to know whick is better?
> > DSP or FPGA?
> >
> >
> > I know some corporations use FPGA based boards as development boards
> > for their cameras. And my cooperators have some DSP development
> > experiences. So, the question arises, and I want your suggestions. I'd
> > like to know the advantages of each choise and maybe the direction of
> > onboard realtime high-speed image processing.
> >
> >
> > Thanks!
> > Any help would be appreciated.
> >
> Please go to wikipedia and look up "cross post".  Compare what they have
> to say about cross posting with what they have to say about multiple
> posting.
>
> Then do it right.
>
> --
>
> Tim Wescott
> Wescott Design Services
> http://www.wescottdesign.com
>
> Posting from Google?  See http://cfaj.freeshell.org/google/
>
> "Applied Control Theory for Embedded Systems" came out in April.
> See details at http://www.wescottdesign.com/actfes/actfes.html


Article: 113818
Subject: Embedded Development Tools
From: "Andy" <ezembedded@gmail.com>
Date: 22 Dec 2006 21:14:31 -0800
Links: << >>  << T >>  << A >>
Hello,

Here is our company's web site www.ezEmbedded.com for your reference. I
am very happy to assist you on your project. Any question for our
products as well as our service, please feel free to contact me.

Merry Christmas!

Andy
EZ-EMBEDDED
www.ezEmbedded.com
info@ezEmbedded.com


Article: 113819
Subject: Re: DSP or FPGA for high-speed image processing?
From: "kyori" <ggkyori@gmail.com>
Date: 22 Dec 2006 21:18:28 -0800
Links: << >>  << T >>  << A >>
Hi,

Thanks for your reply.

256*256 frame (or even small) size will be ok.
Generally the algorithm is kind of correlation of two sucessive frames.

Best regards,
kyori

Martin Thompson wrote:
> "kyori" <ggkyori@gmail.com> writes:
>
> > Hi,
> >
>
> Hi,
>
> > I am going to start a project of onboard high-speed CMOS image
> > processing.
> > I am goint to perform certain *block matching algorithm* or *Fourier
> > Transform* between successive frames and the fps would be 1000 or
> > more..
> >
>
> What size of frame?  That's a lot of memory-bandwidth!
>
> >
> > The interface between the CMOS camera and the board is standord
> > CamLink.
>
> Do you mean Camera Link?  There's VGA resolution cameras that'll do
> 1000fps that way.  What's the end application?
>
> > I've learned that both DSP and FPGA based circuits can do certain
> > onboard image processing tasks, and I'd like to know whick is better?
> > DSP or FPGA?
> >
>
> It depends.  Sorry!
>
> However, I think a single DSP is going to struggle to do a 2D FT of
> even a VGA image at 1000 fps.  And once you go beyond a single DSP, my
> opinion is you might as well go to FPGA as you have a lot more
> flexibility in how you parallelise things then.
>
> >
> > I know some corporations use FPGA based boards as development boards
> > for their cameras. And my cooperators have some DSP development
> > experiences. So, the question arises, and I want your suggestions. I'd
> > like to know the advantages of each choise and maybe the direction of
> > onboard realtime high-speed image processing.
> >
>
> If you want to do *really* high speed processing, FPGAs are a sensible
> choice.  Assuming your algorithms are a) parallelisable and b)
> actually compute limited, not memory latency or bandwidth limited.
>
> Cheers,
> Martin
>
> --
> martin.j.thompson@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technology
> http://www.conekt.net/electronics.html


Article: 113820
Subject: Re: What next next big thing coming for HDL?
From: Bob Smith <bsmith@linuxtoys.org>
Date: Sat, 23 Dec 2006 05:51:41 GMT
Links: << >>  << T >>  << A >>
jjlindula@hotmail.com wrote:
> Hello, I''ve been talking with a co-worker about the HDL languages that
> are availabile these days, such as VHDL, Verilog, SystemVerilog, and
> AHDL. In our shop we've used AHDL because it was easy to learn and use
> and because we've decided to stay with Altera chips. My co-worker
> believes that in the future these languages will be passed over my
> better HDL's and that sparked my curiousity. What is the next big HDL
> that will catch on and grab people from these different HDL
> backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by
> something better? If so, what do you think it will be?

While far from the "next big thing", I'm getting ready to
convert a spreadsheet into an FPGA programming language.
I'm just getting started with FPGAs and I find I can't get
my C-like view of algorithms into Verilog (but, again, I
just getting started and don't really know Verilog).

The idea is to use the cells as registers and have the
"next state" be a function of the other registers (err,
cells) in the spreadsheet.

I've modified the open-source spreadsheet, sc, so that each
cell has two values, the current value and the next value.
To simulate a clock I calculate the next value for each
cell in the sheet, then go through it again copying the
next value to the current value.  I need to add two new
functions, one to read a value into a cell from a file,
and another to write a value.

I should be able to save/convert the spreadsheet as either
a C program or as RTL Verilog.  I figure the spreadsheet
will be slow but easy to debug, the C will be faster (but
not as fast as a hand coded C program), and the Verilog
will be fastest if it makes it into an FPGA.

I think the conversion from spreadsheet to Verilog will be
mechanical, so the big question is whether or not a
spreadsheet is a useful tool for expressing algorithms.


Suggestions, criticisms, and best of all "it's been done"
are all appreciated.

Bob


Article: 113821
Subject: Re: Virtex-5 Webpack?
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 23 Dec 2006 08:41:40 +0100
Links: << >>  << T >>  << A >>
"Tommy Thorn" <tommy.thorn@gmail.com> schrieb im Newsbeitrag 
news:1166839617.590263.257670@h40g2000cwb.googlegroups.com...
> Jim Granville wrote:
>> Others might be using smaller chips, but just want to build to V5, as
>> a training example - viz: "So, How much better IS this V5? "...
>>
>> To me, Xilinx can chop V5 out of webpack, and mull the consequences.
>
> I complained about this a long time ago to which Austin said "I don't
> see the problem at all".
>
> Since then I've been working on a project targeting a Cyclone and a
> Spartan 3E in parallel and now I don't think I'll ever care about V5,
> but just wait for Stratix-III. In my experience (everything fully up to
> date),
> - ISE is 5-10X *SLOWER* than Quartus II (seriously, I can post
> details),
> - ISE a lot less stable than Quartus,
> - Spartan 3E are 10-15% slower than Cyclones,
> - (Subjective) ISE is a lot clunky to use (fx. properties are spread
> all over the place), and finally
> - the free Quartus supports a least one device from every family.
>
> I only regret that there aren't as many excellent development boards
> for Altera as there are for Xilinx.
>
> Tommy
> PS: My obsession with free tools is not because I'm a cheap-skate; it
> has to do with avoiding lock-in and the value of a design that can be
> further developped by others for minimal cost.
>
Hi Thommy

thanks for good example - hope Xilinx will finally listen!

I can only add that dropping V5 from WebPack can be considered
as disappointing loyalty of te Xilinx BaseX customer - that is people
who did count on entry level paid xilinx tool to support at least one
device of the each family (all those who have ever had Base-X license)
those customer are now forced to obtain full version - what means
2.5 times more expenses per year. Or they can switch to Altera.
What is likely to happen.

hihi - I just recalled what I am getting for Christmas - I had one
wish free, and I wished an Stratix development board, and guess
what it is already purchased for me and possible already in transit.

Antti

























Article: 113822
Subject: IEEE fixed-point package FATAL_ERROR
From: "Manny" <mloulah@hotmail.com>
Date: 23 Dec 2006 00:18:42 -0800
Links: << >>  << T >>  << A >>
Hello,

Just started recently playing with a VHDL-1993 compatible fixed-point
package:
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html

After introducing minor modifications to the package, it compiled on
Xilinx ISE 8.1 sp3. However, now no matter how I use the function
"resize" in my code, I keep on getting this message:

FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.16 - This
application has discovered an exceptional condition from which it
cannot recover.  Process will terminate.  To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com

Process "Synthesize" failed

Was wondering by any chance whether anybody in here managed to go
around the issue. Any suggestions would be greatly appreciated. In the
mean time, headache is inevitable in FPGAs, alas!

Cheers,
-Manny


Article: 113823
Subject: Re: Simple questions on IDELAYCTRL vs DCM
From: "Antti" <Antti.Lukats@xilant.com>
Date: 23 Dec 2006 00:23:45 -0800
Links: << >>  << T >>  << A >>
Austin schrieb:

> Well,
>
> Sorry about that, but the snowstorm in Colorado caused us to send those
> folks home before they were stranded.  San Jose and Singapore took on
> the extra call volume, which may be why you could not get through.
>
> When my lab tested the DCM CLKFX output to the IDELAY ref clock, we
> tested a number of M and D values, but did not test all possible
> combinations.  It may be we needed to.  The folks who are responsible
> for the data sheet only allowed a table of the M and D values we tested
> to be used by the product.  So, what was your M and D value, and
> frequency of Clock IN?  Were you using the DCM for anything else (any
> other outputs connected)?  Was the CLKFB input used (it should not have
> been if all you needed was the CLKFX output, as using it would
> automatically turn on the DLL part of the DCM, and that might have
> created some issues (input clock frequency too low for the DLL in that
> mode).  How soon after the DONE went high was the DCM reset released?
> It may be that the oscillator had not stabalized yet.
>
> Austin
>

Austin,

the simple question gets more and more interesting - I had the
impression
that Xilinx did give green on CLKFX useage for IDELAYCTRL - without
any constraints

now it seems that CLKFX is OK, when
1) M/D from listed of "acceptable" ?
2) some other condition OK

I have 2 differen V4 DDR2 boards where IDELAYCTRL is used, both
boards have some trouble, in both cases CLKFX is used for 200mhz
calibrate clock. I assumed that this cant be the issue, but now I cant
rule this out anymore?

if an DDR2 memory controller has trouble because of mis-calibrated
IDELAY then for the Xilinx customer its rather hard to troubeshoot!

Of course I am able to create some test cases to see if the calibrate
works or not, but I would rather depend on reliable informatiom from
Xilinx that allows me to design the calibrate clock circuit in the way
that special troubleshooting is not needed.

Antti


Article: 113824
Subject: Re: What next next big thing coming for HDL?
From: Norbert Stuhrmann <stuhrmann@spamfence.net>
Date: Sat, 23 Dec 2006 13:48:50 +0100
Links: << >>  << T >>  << A >>
Hello,

jjlindula@hotmail.com schrieb:
> What is the next big HDL
> that will catch on and grab people from these different HDL
> backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by
> something better? If so, what do you think it will be?

Maybe SystemC for it's ability do to software/hardware co-design?

Regards,

  Norbert



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