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In article <qhejoz9n87.fsf@ruckus.brouhaha.com>, Eric Smith <eric@brouhaha.com> wrote: > "Pablo" <pbantunez@gmail.com> writes: > > Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 > > Evaluation Software. Now it has expired and I cannot design for > > hardware arquitecture. Does anybody resolve it?? That is, is some > > method or crack for this?? > > Yes, a crack for it is available from your Xilinx distributor, > for a fee. I disagree, tools should be free. You *still* have to buy their hardware. Sort of like how apple was in the old days with their OS. They knew they got your money via the hardware, so they gave away the OS for free. There was no reason to screw the customers twice. Chip dealers should do the same.Article: 115851
In article <1170834754.019178.292360@a34g2000cwb.googlegroups.com>, "Saqib" <engr.saqib.riaz@gmail.com> wrote: > Hi, I have recently purchased the Spartan-3E starter kit and I am > having trouble to > > configure the FPGA with what is in the NOR Flash. > > I am using the RS-232 programmer for NOR Flash available as Reference > Design. > > Reading back the data showed me that the NOR Flash is indeed loaded > with the program but it just can't get that into the FPGA on startup. > > Can anyone provide me with any help on this issue? > > Does i need to send the hardware back?? > > I am running ISE 8.2i. Not that this answers your question, but where did you buy it from? Im looking to get one of them myself.Article: 115852
"Sandip" <sandip.gaikwad@gmail.com> wrote in message
news:1172128018.769836.216140@k78g2000cwa.googlegroups.com...
>I want to generate a program in VHDL for generating registers which
> can be used then into a state machine.
> If anyone has a sample program to share, it will be very helpful.
>
Some queries are trivially easy....
process(Clock)
begin
if rising_edge(Clock) then
My_Register_Signal <= Something;
end if;
end process;
And since you've asked such a basic question, I'll now suggest that you
would be well served by finding a book that describes the VHDL language so
that you can make any progress on your project.
Kevin Jennings
Article: 115853Hello. I implemented floating point adder in virtex2-pro and now recomplied it in virtex4. There is no compile error in synthsis & implement. But the performance (speed) is a little reduced. So I want to improve the speed. Is there anyone who can let me know how to start ? I mean what part I should focus on.Article: 115854
Thanks for the answer everybody. It's a lot to take in for a newbie so i'll probably have to do a little research on the different stuff in John's reply but it's definitely a start. Thanks a lot, AmishArticle: 115855
lkjrsy@gmail.com wrote: > Hello. > > I implemented floating point adder in virtex2-pro and now recomplied > it in virtex4. > There is no compile error in synthsis & implement. But the performance > (speed) is a little reduced. > So I want to improve the speed. Is there anyone who can let me know > how to start ? > I mean what part I should focus on. Maybe some simple changes in the HDL-code can help and you don't even need to try different parts. The entire Virtex4-architecture (V5 as well) is optimized for synchronous resets. For example, some synthesis tools automatically infer the fast DPS48s for counters, but only if you use a synchronous reset, because the hard-macro is designed for a synchronous reset. If you have an asynchronous reset, the synthesis tools synthesize LUT-based counters, which use up more resources and could be slower. It's possible that the same applies for arithmetic functions you use in your floating point adder. -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 115856
"ziggy" <ziggy@fakedaddress.com> wrote in message
news:ziggy-D2B0F4.06284922022007@news.isp.giganews.com...
>> > Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1
>> > Evaluation Software. Now it has expired and I cannot design for
>> > hardware arquitecture. Does anybody resolve it?? That is, is some
>> > method or crack for this??
>> Yes, a crack for it is available from your Xilinx distributor,
>> for a fee.
>
> I disagree, tools should be free. You *still* have to buy their
> hardware.
No, you don't have to. It's a free world. (As in speech.) The software can
be used quite happily without the hardware. For example, you could design
and implement entire prototype systems, simulate them, check timing, and so
on, and then make the decision that your project is not viable and never buy
any parts at all. Or your company might fold before you have a chance to
bring the product to market.
> Sort of like how apple was in the old days with their OS. They knew they
> got your money via the hardware, so they gave away the OS for free.
> There was no reason to screw the customers twice.
Wow. When did charging money for goods or services become synonymous with
screwing someone over?
You can design for the Spartan-3E without the EDK/XPS software - you can use
the free Webpack version of ISE and write in VHDL/Verilog. That's a hell of
a generous offer - players like Xilinx and Altera have invested millions in
their mapping and place & route algorithms and all the other stuff that is
required for the FPGA design back-end, and they give that away for free.
Even if you have to pay full price to get access to the very largest and
latest devices, we're still not talking megabucks here - particularly
compared to the rest of the EDA world. FPGA vendors do not price small
development houses out of the market in the same way that ASIC vendors do.
EDK is an example of a "value add" product - you get accellerated design
time for processor-based SoC platforms, a whole bunch of peripheral IP, and
the MicroBlaze processor core as well.
Now, either you think that's worth paying for, or you go find some
alternative way of doing it (like putting together a system out of OpenCores
IP) that costs you less money. Your choice. Capitalism at work.
-Ben-
Article: 115857On 19 Feb, 18:55, "mahdi" <sagha...@gmail.com> wrote: > CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT IT? > HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? > THANK YOU ROC is the reset-on-configuration block, that outputs a pulse just after device programming. It is automatically inserted in to the netlist post-synthesis. To emulate this in simulation: (see the synthesis and verification guide) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; library UNISIM; use UNISIM.all; entity EX_ROC is port ( CLOCK, ENABLE : in std_logic; CUP, CDOWN : out std_logic_vector (3 downto 0) ); end EX_ROC; architecture A of EX_ROC is signal GSR : std_logic; signal COUNT_UP, COUNT_DOWN : std_logic_vector (3 downto 0); component ROC port (O : out std_logic); end component; begin U1 : ROC port map (O => GSR); UP_COUNTER : process (CLOCK, ENABLE, GSR) begin if (GSR = '1') then COUNT_UP <= "0000"; elsif (CLOCK'event AND CLOCK = '1') then if (ENABLE = '1') then COUNT_UP <= COUNT_UP + "0001"; end if; Synthesis and Verification Design Guide www.xilinx.com 257 1-800-255-7778 Simulating VHDL R end if; end process UP_COUNTER; DOWN_COUNTER : process (CLOCK, ENABLE, GSR, COUNT_DOWN) begin if (GSR = '1' OR COUNT_DOWN = "0101") then COUNT_DOWN <= "1111"; elsif (CLOCK'event AND CLOCK = '1') then if (ENABLE = '1') then COUNT_DOWN <= COUNT_DOWN - "0001"; end if; end if; end process DOWN_COUNTER; CUP <= COUNT_UP; CDOWN <= COUNT_DOWN; end A;Article: 115858
ziggy wrote: > In article <qhejoz9n87.fsf@ruckus.brouhaha.com>, > Eric Smith <eric@brouhaha.com> wrote: > >> "Pablo" <pbantunez@gmail.com> writes: >>> Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 >>> Evaluation Software. Now it has expired and I cannot design for >>> hardware arquitecture. Does anybody resolve it?? That is, is some >>> method or crack for this?? >> Yes, a crack for it is available from your Xilinx distributor, >> for a fee. > > I disagree, tools should be free. You *still* have to buy their > hardware. > > Sort of like how apple was in the old days with their OS. They knew they > got your money via the hardware, so they gave away the OS for free. > There was no reason to screw the customers twice. > > Chip dealers should do the same. And big oil companies should give us automobiles for free. We certainly pay for the use of the car over and over and over! Tools should be free only if there's no support for the tools and the development costs are minimal. Otherwise, wouldn't the cost for very few parts for the hobbyist be even further out of balance compared to large quantity purchases than they are already? People have to get paid.Article: 115859
On Feb 22, 5:06 am, "axr0284" <axr0...@yahoo.com> wrote: > Thanks for the answer everybody. It's a lot to take in for a newbie so > i'll probably have to do a little research on the different stuff in > John's reply but it's definitely a start. Thanks a lot, > Amish Amish, you never told us the criticality of your timing detector. If you can tolerate an 8 ns detection error, then the interesting solution suggested by John is not required. But if timing is critical, it is a really superb solution. Peter AlfkeArticle: 115860
Hello, all: My question is: Can MicroBlaze and OPB run at one clock frequency and the OPB block ram interface run at another? If it is possible, how can I relize it? Can I change the BRAM_clk someway? Or would you please refer me some useful document about this configuration? Thank you very much for your reply, DavidArticle: 115861
Hello, all: My question is: Can MicroBlaze and OPB run at one clock frequency and the OPB block ram interface run at another? If it is possible, how can I realize it? Can I change the BRAM_clk someway? Or would you please refer me some useful documents about this configuration? Thank you very much for your reply, DavidArticle: 115862
Make sure to be careful about DCM reset requirments. If your DUT clock comes & goes, the DCM will not work properly without resets after clock changes. John Providenza On Feb 21, 7:25 pm, Austin <aus...@xilinx.com> wrote: > dipu, > > Connect nothing to the CLKFB pin. Use of the CLKFB pin invokes the DLL > function (which you do not need, or can use at these low CLKIN frequency). > > Just run the CLKFX output to a BUFG, and go from there. > > AustinArticle: 115863
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1172157421.210544.161220@q2g2000cwa.googlegroups.com... > On Feb 22, 5:06 am, "axr0284" <axr0...@yahoo.com> wrote: >> Thanks for the answer everybody. It's a lot to take in for a newbie so >> i'll probably have to do a little research on the different stuff in >> John's reply but it's definitely a start. Thanks a lot, >> Amish > > Amish, > you never told us the criticality of your timing detector. If you can > tolerate an 8 ns detection error, then the interesting solution > suggested by John is not required. But if timing is critical, it is a > really superb solution. > Peter Alfke I agree that the approach I suggested may be significant overkill. I wouldn't suggest the approach for a newbie unless desperate for precision or very confident in the ability to tackle a problem full of nuance. Many seasoned engineers still don't design with the silicon target in mind, producing quite functional but less than optimal code; often the ability to retarget the code to a different family is justification enough to not think at the silicon level. The tast I suggested - to show what precision could be obtained - keeps the silicon at the forefront of most of the coding decisions. With 2X the 125 MHz clock Peter suggested (without a DCM!) you get good results without 2+ man-weeks of effort. If you could pull off the task I suggested in 2 days, I'd graduate you far beyond newbie. If you're interested in this type of technique for speed or precision, I'd suggest reading XAPP 671 that has a delay structure similar to the ring oscillator for high speed asynchronous data capture. - John_HArticle: 115864
On Feb 22, 2:06 am, "Sandip" <sandip.gaik...@gmail.com> wrote: > I want to generate a program in VHDL for generating registers which > can be used then into a state machine. > If anyone has a sample program to share, it will be very helpful. > > Thanks and regards, > sandip Many people will recommend Peter J. Asheden's book "The Designer's Guide to VHDL (2nd edition)", It was my first VHDL book and it was too overwhelming for me to read at the time. However, it's been a usefull reference book. At least a third of the book describes the author's CPU. Sundar Rajan's "Essential VHDL RTL Synthesis Done Right" used to be my favorite VHDL book. It keeps things simple, explains a lot about the VHDL code examples, and shows logic diagrams that a synthesis tool produces from each example. It does get into state machines, including a simple PCI bus state machine. However, it's very weak on simulating and debugging. And unlike many other VHDL books, there isn't code for a CPU! Pong P. Chu's "RTL Hardware Design Using VHDL" is now my favorite VHDL book. This is somewhat like Rajan's book, but Chu's book goes into more detail and covers a lot more topics, including Meally & Moore state-machines, clock synchronizing, and even sending info across clock domains. Like Rajan's book, this book also includes logic diagrams for the code examples. I think that this book would be ideal for a beginner. It's only assumption it that the reader already knows digital logic fundamentals. Its only flaws are a) the book's index is poor, b) when code is continued on the next page, and when there's a diagram on the next page for a new topic, the continued code comes after the diagram. This can be a little confusing. HTH -Dave PollumArticle: 115865
In news:er5ilv$8s8$1$8302bc10@news.demon.co.uk timestamped Sat, 17 Feb 2007 00:36:14 +0000, Tim <tim@nooospam.roockyloogic.com> posted: "> I checked the price of a component (not an F.P.G.A. though) we needed > on a few websites in December 2006. One of them was Avnet's and > Avnet's website had the engineering (prototype, commercial quality) > model priced at $11122.80 whereas Avnet's website had the radiation > hardened space qualified (better quality) version priced much less at > $3738. I performed this search due to miscommunication: we had > actually already bought the radiation hardened version before December > for far less than $5000 (though I do not know for how much exactly, > nor from whom). Impressive. And six significant figures in the $11122.80 pricing! What sort of component? As I recall, the most expensive Xilinx FPGA is around $9800." Just an imaging device: a Cypress STAR-1000: WWW.Cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=208&rpn=STAR-1000&ref=sch though what we actually bought was a Fillfactory STAR-1000 before Cypress acquired Fillfactory. Today, the space qualified one (CYIS1SM1000AA-HQC) is priced at $3115 on WWW.ArrowNAC.com/aws/pg_webc/0,4513,,00.html?application=SEARCH&event=1000&search_criteria=match_begins_with&match_in_stock_only=NO&7486=&rows_to_display=10&full_domain_name=www.arrownac.com&super_neda=4653&start_index=0&search_token=CYIS1SM1000AA-HQC and on HTTPS://WWW.EM.Avnet.com/pns/home/0,5533,CID=0&CCD=USA&SID=0&DID=DF2&LID=0&BID=DF2&CTP=PNS,00.html?ref=https://emwcs.avnet.com/webapp/wcs/stores/RedirectWCSLogon?langId=-1&storeId=500201&catalogId=500201&reLogon=https://www.em.avnet.com/auth/framelogin/&URL=RemoteAdvancedSearchView%3FlangId%3D%2D1%26storeId%3D500201%26catalogId%3D500201%26manufacturerPartNum%3DCYIS1SM1000AA-HQC at $3738. The prototyping one (CYIS1SM1000-EVAL) is priced at $9269 on WWW.ArrowNAC.com and $11122.80 on HTTPS://WWW.EM.Avnet.com . These are the same four prices on those websites when I checked in December 2006. Regards, Colin Paul GlosterArticle: 115866
On Feb 22, 6:17 pm, Sean Durkin <news_fe...@durkin.de> wrote: > lkj...@gmail.com wrote: > > Hello. > > > I implemented floating point adder in virtex2-pro and now recomplied > > it in virtex4. > > There is no compile error in synthsis & implement. But the performance > > (speed) is a little reduced. > > So I want to improve the speed. Is there anyone who can let me know > > how to start ? > > I mean what part I should focus on. > > Maybe some simple changes in the HDL-code can help and you don't even > need to try different parts. The entire Virtex4-architecture (V5 as > well) is optimized for synchronous resets. For example, some synthesis > tools automatically infer the fast DPS48s for counters, but only if you > use a synchronous reset, because the hard-macro is designed for a > synchronous reset. If you have an asynchronous reset, the synthesis > tools synthesize LUT-based counters, which use up more resources and > could be slower. > > It's possible that the same applies for arithmetic functions you use in > your floating point adder. > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that... Hi Sean, Thank you for this info... So, In Virtex 4 to utilize max benift of these cores, we need to make reset - sync signal using Dual Flop synchronizers? Regards, JKArticle: 115867
On Feb 22, 5:19 pm, simon.char...@bloomsbury-dsp.co.uk wrote: > On 19 Feb, 18:55, "mahdi" <sagha...@gmail.com> wrote: > > > CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT IT? > > HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? > > THANK YOU > > ROC is the reset-on-configuration block, that outputs a pulse just > after device programming. It is automatically inserted in to the > netlist post-synthesis. > > To emulate this in simulation: (see the synthesis and verification > guide) > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > library UNISIM; > use UNISIM.all; > entity EX_ROC is > port ( > CLOCK, ENABLE : in std_logic; > CUP, CDOWN : out std_logic_vector (3 downto 0) > ); > end EX_ROC; > architecture A of EX_ROC is > signal GSR : std_logic; > signal COUNT_UP, COUNT_DOWN : std_logic_vector (3 downto 0); > component ROC > port (O : out std_logic); > end component; > begin > U1 : ROC port map (O => GSR); > UP_COUNTER : process (CLOCK, ENABLE, GSR) > begin > if (GSR = '1') then > COUNT_UP <= "0000"; > elsif (CLOCK'event AND CLOCK = '1') then > if (ENABLE = '1') then > COUNT_UP <= COUNT_UP + "0001"; > end if; > Synthesis and Verification Design Guidewww.xilinx.com257 > 1-800-255-7778 > Simulating VHDL R > end if; > end process UP_COUNTER; > DOWN_COUNTER : process (CLOCK, ENABLE, GSR, COUNT_DOWN) > begin > if (GSR = '1' OR COUNT_DOWN = "0101") then > COUNT_DOWN <= "1111"; > elsif (CLOCK'event AND CLOCK = '1') then > if (ENABLE = '1') then > COUNT_DOWN <= COUNT_DOWN - "0001"; > end if; > end if; > end process DOWN_COUNTER; > CUP <= COUNT_UP; > CDOWN <= COUNT_DOWN; > end A; Thanks for your attention. This port is on xilinx fpgas. Is there an equvalent port on altera fpgas. ThanksArticle: 115868
Hi Is there a technique to 2x our input clock and as a general Is there a technique to create a clock with frequency of n*f_input_clk. (where n is a desired integer) Thank youArticle: 115869
Hi Can any body explain internal DCM and give me some information about it? Thank youArticle: 115870
mahdi wrote: > Thanks for your attention. > This port is on xilinx fpgas. > Is there an equvalent port on altera fpgas. No. Reset must be provided externally. Altenatively it is safe to assume that all registers are 0 after configuration. Best regards, BenArticle: 115871
mahdi wrote: > Hi > Is there a technique to 2x our input clock and as a general > Is there a technique to create a clock with frequency of n*f_input_clk. > (where n is a desired integer) > Thank you With Xilinx, use a DCM. With Altera use an ALTPLL. Any other construct for doubling a clock is very dependant on process, voltage and temperature, i.e. the clock shape will change with voltage and temperature, and has a wide spread between devices. Best regards, BenArticle: 115872
mahdi wrote: > Hi > Can any body explain internal DCM and give me some information about > it? Best to look that up on the Xilinx website. Best regards, BenArticle: 115873
Mahdi, Start by learning the DCM basics (i.e. the DLL). Read XAPP132: http://www.xilinx.com/bvdocs/appnotes/xapp132.pdf Once you have built this foundation, go to the Users Guide of the device family you wish to use. There will be a dedicated section on clock management. As an example, the Virtex-4 Users Guide (Chapter 2) has 50 pages on using the DCM. http://direct.xilinx.com/bvdocs/userguides/ug070.pdf You are bound to find the information you need for your project by reading this material. -David "mahdi" <saghaian@gmail.com> wrote in message news:1172168667.047884.243590@a75g2000cwd.googlegroups.com... > Hi > Can any body explain internal DCM and give me some information about > it? > Thank you >Article: 115874
Tell us more. Are you using Xilinx? Do you have a dev board? Are you using VHDL or Verilog In Xilinx you can use the Coregen wizard to generate what they call an .XCO file, or something like that. Input your clock frequency and click on the 2X output. "mahdi" <saghaian@gmail.com> wrote in message news:1172168667.047884.243590@a75g2000cwd.googlegroups.com... > Hi > Can any body explain internal DCM and give me some information about > it? > Thank you >
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