Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 117100

Article: 117100
Subject: Re: URGENT HELP NEEDED: LVDS
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 23 Mar 2007 00:45:03 -0500
Links: << >>  << T >>  << A >>
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message
news:1174626985.784318.16210@n76g2000hsh.googlegroups.com...
>
> This board INVERTS LVDS PAIRS ie: if I
> have an output {XP,XN} I get the input {XN,XP}. ({A,B}=A on P pin and
> B on N pin).

1. I doubt anyone can understand your description above. Are you trying to
say that the wires are crossed on the board?
2. Use a scope.

/Mikhail



Article: 117101
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: carlos.asmat@gmail.com
Date: 22 Mar 2007 23:25:59 -0700
Links: << >>  << T >>  << A >>
> Please report back if this library is useful and works for you.
> Maybe this helps XILINX to decide that they do not need to use windrvr
> for easy USB access, as most parts of my library are only there to
> provide a compatible replacement for windrvr functions and are not
> needed when directly accessing libusb from within an application
> program.
>
> Regards,
>   Michael

Hello

I have been trying to program a Xilinx spartan FPGA board using the
parallel port (jtag) and the ISE webpack 9.1i and I cannot get it to
work with windrvr.

I'm very new to linux but I undestand that you propose an alternative
to windrvr that seems to work well.

I've spent many hours trying to get the windrvr and your driver to
work without success.

Besides i cannot get the windrvr to wort, I don't know how to install
your driver. I downloaded the files compiled them, did export
LD_PRELOAD=/path/to/libusb-driver.so as stated in the README but it
doesn't work. I still get an error saying the windrvr module is not
loaded when I try to program the board.

I would really appreciate some help. I'm new to Linux and I use
Kubuntu 6.10.

Thanks a lot


Article: 117102
Subject: Re: URGENT HELP NEEDED: LVDS
From: "=?utf-8?B?R2FMYUt0SWtVc+KEog==?=" <taileb.mehdi@gmail.com>
Date: 22 Mar 2007 23:49:16 -0700
Links: << >>  << T >>  << A >>
On Mar 23, 8:45 am, "MM" <m...@yahoo.com> wrote:
> "GaLaKtIkUsT" <taileb.me...@gmail.com> wrote in message
>
> news:1174626985.784318.16210@n76g2000hsh.googlegroups.com...
>
>
>
> > This board INVERTS LVDS PAIRS ie: if I
> > have an output {XP,XN} I get the input {XN,XP}. ({A,B}=A on P pin and
> > B on N pin).
>
> 1. I doubt anyone can understand your description above. Are you trying to
> say that the wires are crossed on the board?
> 2. Use a scope.
>
> /Mikhail

They are not crossed like X. the problem is the following if we try
(using the loop back board) to get P pin on P pin and N pin on N pin
we will be obliged to cross the wires (make an X on the board). To
avoid this the guy ho made that loopback board decided to send the P
to N and N to P and says that the only problem will the inversion of
the logic levels.
I reformulate my question in more simple terms:
I LVDS pins are crossed what would be the result? only inversion of
logic levels or more?
Mehdi


Article: 117103
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: "Luzerne" <luzerne.ganhir@gmail.com>
Date: 23 Mar 2007 01:16:00 -0700
Links: << >>  << T >>  << A >>
On 23 mar, 07:25, carlos.as...@gmail.com wrote:
> I'm very new to linux but I undestand that you propose an alternative
> to windrvr that seems to work well.
> [...]
> I've spent many hours trying to get the windrvr and your driver to
> work without success.
> [...]
> I would really appreciate some help. I'm new to Linux and I use
> Kubuntu 6.10.

Here is my "step by step newbie" installation howto for Ubuntu Dapper
6=2E06 :)

Open a terminal (Application menu : Accessory > Terminal), where you
can enter the given commands (line starting with the $ prompt symbol).

We suppose we are in your prefered directory. For you it is probably
something like "/home/carlos". For this tutorial il will be replaced
by a generic "/path" :

$ pwd
/path

First, you donwload the program's archive in your prefered "/path/
Download" directory.

$ mkdir Download
$ wget "http://cvs.zerfleddert.de/cgi-bin/viewcvs.cgi/usb-
driver.tar.gz?view=3Dtar" -O Download/usb-driver.tar.gz

Now you go in your prefered work directory (for me it is called
"Travail" :) and you decompress the archive.

$ cd /path/Travail
$ tar zxvf /path/Download/usb-driver.tar.gz
$ cd usb-driver

First thing to do is to check if README or INSTALL files exist, and
_READ_ them.

$ ls -l
$ more README

Now you know what to do. First you check the required module are
loaded.

$ lsmod | grep parport
parport_pc             38340  1
parport                39560  3 ppdev,lp,parport_pc

If you get something like that, it's ok. You can compile.

$ make

You may get this kind of error :

gcc -fPIC -Wall usb-driver.c -o libusb-driver.so -ldl -lusb -lpthread -
shared
usb-driver.c:36:17: erreur: usb.h : Aucun fichier ou r=E9pertoire de ce
type

It's because you have not installed one of the required libusb and
libusb-dev library.
You can install libusb-dev this way :

$ sudo apt-get install libusb-dev

Now you can retry the compilation.

$ make
gcc -fPIC -Wall usb-driver.c -o libusb-driver.so -ldl -lusb -lpthread -
shared
gcc -fPIC -DDEBUG -Wall usb-driver.c -o libusb-driver-DEBUG.so -ldl -
lusb -lpthread -shared

This time, if everything goes right, you can try impact :) As
explained in the README, set the preload environnement variable (this
will be set only for the current terminal) :

$ export LD_PRELOAD=3D/path/Travail/usb-driver/libusb-driver.so

Now, you can run impact. But you may get an error :

Can't open /dev/parport0: Permission denied
LPT port is already in use. rc =3D 0h
Cable connection failed.
Reusing 79063641 key.
Reusing FD063641 key.

It means you have not the required right on the /dev/parport0 device.
You can check this this way :

$ ls -l /dev/parport0
crw-rw 1 root lp 99, 0 2007-03-16 07:48 /dev/parport0

A fast work arround solution is to change the owner of this device :

$ whoami
luzerne
$ sudo chown luzerne /dev/parport0

Before retrying to program a device with impact, it may be necessary
to disbale the eventual impact cable locking. This can be done this
way :

$ impact -batch
> setMode -bscan
> cleancablelock
> quit

Now, you can retry to program a device with impact. This was my "step
by step" personnal log.

http://www.chezmoicamarche.org / YMMV / HTH

Luzerne GANHIR


Article: 117104
Subject: Re: XST coverage
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 23 Mar 2007 08:28:13 GMT
Links: << >>  << T >>  << A >>

"none" <""doug\"@(none)"> wrote in message 
news:13046vmai7i5814@corp.supernews.com...
..snip
>
> I also would like to say again that I appreciate the presence of the
> ever enthusiastic Austin and the ever patient Peter on the newsgroup.

I fully agree with this. I suspect that Austin got some stick from the XST 
group about his posting but in my opinion he is a non-*bs* guy who knows his 
stuff and is not afraid to write about it in a public forum although in this 
case he might have been a bit harsh on XST.

I am glad to be a customer of a company that employs people like him and 
Peter!

Hans
www.ht-lab.com



Article: 117105
Subject: Re: Parallel Cable IV in Spartan 3E???
From: "Pablo" <pbantunez@gmail.com>
Date: 23 Mar 2007 01:28:18 -0700
Links: << >>  << T >>  << A >>
On Mar 22, 5:58 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> Actually, it's simpler: you don't have a valid VCC and GND hookup.  Get a
> volt meter.  If you have nothing else hooked up except VCC and GND to val=
id
> levels, you should get a green light.
>
> "Pablo" <pbantu...@gmail.com> wrote in message
>
> news:1174577212.710465.258760@o5g2000hsb.googlegroups.com...
> Yes, I know that led light must turn from ambar to green . That is the
> problem. The light doesn`t turn to green, so Parallel Cable IV doesn=B4t
> "feel" the reference problem. I suppose I have to configure spartan 3e
> to program from PC IV instead of USB.
>
> Regards

Thanks. it`s a good idea. I have worked with volt meters during three
years. I don`t know why I haven=B4t thought it before.


Article: 117106
Subject: Re: Using xilkernel with C++
From: "Guy Eschemann" <Guy.Eschemann@gmail.com>
Date: 23 Mar 2007 01:39:12 -0700
Links: << >>  << T >>  << A >>
Thanks, Markus.
It is indeed a linker issue, which was solved using extern "C". Still,
I'm wondering if there are any other issues when using xilkernel with C
++?
Guy.

On Mar 21, 8:44 am, Markus <n...@nowhere.org> wrote:
> Guy Eschemann wrote:
> > Hi,
> > is there a way to get the Xilkernel to run with a C++ application? I
> > didn't find any option for this in the XPS "Software Platform
> > Settings".
> > The problem I'm having is that my thread function ("TSK_Main", which
> > is declared in the C++ application) cannot be called from libxil.a,
> > which is a C library. This is the error message that I'm getting while
> > trying to build the C++ application:
> > ../../ppc405_0_sw_platform/ppc405_0/lib/libxil.a(init.o):(.sdata+0x0):
> > undefined reference to `TSK_Main'
> > Maybe someone knows a workaround for this?
>
> This seems to be a linker problem. The naming conventions for c and c++
> object files are different. You can declare C function in C++ with:
>
> extern "C" {
>   ... TSK_Main(...);
>
> }
>
> or vice versa
>
> extern "C++" {
>   ... TSK_Main(...);
>
> }
> > Many thanks,
> > Guy.



Article: 117107
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: Michael Gernoth <mike@gernoth.net>
Date: Fri, 23 Mar 2007 09:02:04 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 22 Mar 2007 23:25:59 -0700, carlos.asmat@gmail.com wrote:
> Besides i cannot get the windrvr to wort, I don't know how to install
> your driver. I downloaded the files compiled them, did export
> LD_PRELOAD=/path/to/libusb-driver.so as stated in the README but it
> doesn't work.

I suppose you replaced /path/to/ with the real path to the library and
started ISE or Impact from the shell where you did the LD_PRELOAD?
To make sure that this is the case, you can put the export line in
the settings.sh file generated by the ISE installer.

> I still get an error saying the windrvr module is not loaded when I
> try to program the board.

If you get that message, then the basic preloading of the library did
not work, as it should tell impact that the windrvr module is loaded.
What happens if you run "lsmod" after running the export LD_PRELOAD?
You should get the following output:

Module                  Size  Used by
windrvr6                   1  0
parport_pc                 1  0

Regards,
  Michael

Article: 117108
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: Michael Gernoth <mike@gernoth.net>
Date: Fri, 23 Mar 2007 09:05:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Thu, 22 Mar 2007 21:01:37 +0000 (UTC), Uwe Bonnes wrote:
> My configuration :
> * OS : Suse 10.2
> * cable : Home brewed parallel cable III derivat
> * Xilinx Tool : ISE Webpack 9.1 SP02
> * programmed chip : XC95XL72

Thanks Luzerne and Uwe for testing with a parallel cable. I am happy to
hear that it works for other people, too and that even the parallel
cable 4 works (in compatibility mode).

Regards,
  Michael

Article: 117109
Subject: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
From: "Fred" <fred@n0spam.com>
Date: Fri, 23 Mar 2007 09:13:24 -0000
Links: << >>  << T >>  << A >>

"Marc Randolph" <mrand@my-deja.com> wrote in message 
news:1174444522.570165.55480@p15g2000hsd.googlegroups.com...
> On Feb 15, 7:40 pm, Thomas Womack <twom...@chiark.greenend.org.uk>
> wrote:
>> In article <1171576522.086383.317...@h3g2000cwc.googlegroups.com>,
>>
>> spartan3wiz <magnus.wedm...@gmail.com> wrote:
>> >There is a major risk for me missing the point here, but I'll give it
>> >ago anyway! The original question takled about the ISE and Dual
>> >Cores.... why would you need Dual Core for ISE? It does never use more
>> >than one of them anyway!
>>
>> Because the fast (2.4GHz and above) Core 2Duochips get you 4MB of
>> level-2 cache which, if you're using ISE on only one core and not
>> doing anything very intensive in the background, is all available to
>> the ISE process.  Given how much of a boost people saw with 1MB-cache
>> versus 512k-cache AMD chips, and how memory-intensive FPGA compilation
>> is, I would expect 4MB to be distinctly useful.
>>
>> Tom
>
> Sorry for pulling a really old thread out for a follow-on, but I
> figured it would be better to keep the info together than spread
> across a bunch of threads.
>
> I'm sure that you are correct that 4 MB would provide super results,
> but even 2 MB appears to be more than enough to allow a laptop to be
> overwhelmingly faster than a desktop that was considered unbeatable
> when it was brand new:
>
> Pentium 4 at 3.2 GHz with 2 GB of RAM results:
>
> Loading device for application Rf_Device from file '2vp40.nph' in
> environment C:\Xilinx\Xilinx9.1i.
>   "benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
> fg676, speed -6
>
> Device Utilization Summary:
>
>   Number of BUFGMUXs                        9 out of 16     56%
>   Number of DCMs                            4 out of 8      50%
>   Number of External IOBs                 319 out of 416    76%
>      Number of LOCed IOBs                 319 out of 319   100%
>   Number of RAMB16s                       105 out of 192    54%
>   Number of SLICEs                      13951 out of 19392  71%
>
> Starting Placer
>
> REAL time consumed by placer: 11 mins 54 secs
> CPU  time consumed by placer: 11 mins 36 secs
> Writing design to file benchmarkT_top.ncd
>
> Total REAL time to Placer completion: 12 mins 4 secs
> Total CPU time to Placer completion: 11 mins 44 secs
>
> Starting Router
>
> Phase 1: 128932 unrouted;       REAL time: 12 mins 42 secs
> Phase 4: 20607 unrouted; (1604)      REAL time: 14 mins 32 secs
> Phase 5: 20609 unrouted; (0)      REAL time: 14 mins 40 secs
> Phase 7: 0 unrouted; (0)      REAL time: 16 mins 9 secs
> Phase 8: 0 unrouted; (0)      REAL time: 16 mins 54 secs
>
> Total REAL time to Router completion: 17 mins 8 secs
> Total CPU time to Router completion: 16 mins 39 secs
>
> All signals are completely routed.
>
> Total REAL time to PAR completion: 17 mins 58 secs
> Total CPU time to PAR completion: 17 mins 4 secs
>
> Peak Memory Usage:  792 MB
>
> ------   compared to  ---------
>
> T7200 (2 GHz mobile version of the Core 2 duo) with 2 GB of RAM
> results:
>
> Loading device for application Rf_Device from file '2vp40.nph' in
> environment C:\Xilinx\Xilinx91i.
>   "benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
> fg676, speed -6
>
> Device Utilization Summary:
>
>   Number of BUFGMUXs                        9 out of 16     56%
>   Number of DCMs                            4 out of 8      50%
>   Number of External IOBs                 319 out of 416    76%
>      Number of LOCed IOBs                 319 out of 319   100%
>
>   Number of RAMB16s                       105 out of 192    54%
>   Number of SLICEs                      13951 out of 19392  71%
>
> Starting Placer
>
> REAL time consumed by placer: 6 mins 12 secs
> CPU  time consumed by placer: 6 mins 9 secs
> Writing design to file benchmarkT_top.ncd
>
>
> Total REAL time to Placer completion: 6 mins 20 secs
> Total CPU time to Placer completion: 6 mins 14 secs
>
> Starting Router
>
> Phase 1: 128932 unrouted;       REAL time: 6 mins 37 secs
> Phase 4: 20607 unrouted; (1604)      REAL time: 7 mins 31 secs
> Phase 5: 20609 unrouted; (0)      REAL time: 7 mins 34 secs
> Phase 7: 0 unrouted; (0)      REAL time: 8 mins 24 secs
> Phase 8: 0 unrouted; (0)      REAL time: 8 mins 48 secs
>
> Total REAL time to Router completion: 8 mins 54 secs
> Total CPU time to Router completion: 8 mins 48 secs
>
> All signals are completely routed.
>
> Total REAL time to PAR completion: 9 mins 25 secs
> Total CPU time to PAR completion: 9 mins 4 secs
>
> Peak Memory Usage:  784 MB
>
>

Your comparison makes interesting reading.

How do you think the AMD dual processor chips compare with Intel's.  In many 
circles there seems to be an prejudice against AMD processors without any 
good reason.



Article: 117110
Subject: Re: multiple clock domain issues
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 23 Mar 2007 02:18:18 -0700
Links: << >>  << T >>  << A >>
On 23 Mrz., 02:26, "JK" <krishna.januman...@gmail.com> wrote:
> 1. Weather synchronizers are required for control signals only or for
> data signals also?

Depends.
Asume a 8 bit datapath, can you guarantee, that data is stable while
crossing the domains? What effect may corrupted data have on your
design?

> 2. Internal to FPGA, suppose 2 different clock domains are there - do
> signals crossing from one clock domain
>    to another need synchronizers?

Usually yes, unless you manage to bring them in phase (eg. with PLL).

> 3. How can we decide on a false path? suppose one signal is crossing
> from one clock domain to another can be
>    declared as a false path?

If timing is no issue, like databus if hand shake signals ensure the
data is stable while crossing the domains.




Article: 117111
Subject: Re: FPGA with 5V and PLCC package
From: jetmarc@hotmail.com
Date: 23 Mar 2007 02:53:43 -0700
Links: << >>  << T >>  << A >>
Herbert Kleebauer wrote:
> Atmel only offers a place and route tool. Therefore I asked if
> somebody can suggest a simple to use design software (with
> a schematic entry) for the Atmel FPGA's.

You might try the the SystemDesigner software that offers a complete
flow. It seems that there's a free download in the FPSLIC AT94K
section of the website.  You'd have to try if it lets you target an
AT40K FPGA (without the AVR portion).

I made bad experiences with the previous version of SystemDesigner
(v2.1).  The implementation was impossible for designs with high
device utilization.  The reason was that the place and route tool was
unable to resolve "short critical paths", ie signals that race with
the clock.  The tools only cared about "long critical paths" (signals
too slow for specified clock rate), trying different routes until they
disappeared.  For short paths it had no remedy but flag them in the
timing report.

Maybe the v3.0 tools are better. I wouldn't want to use v2.1 for a CPU
project and have to spend the last 15 minutes of the course on an
explanation about why their schematic is OK but the implementation
doesn't work.

Regards,
Marc


Article: 117112
Subject: problem while using if or case statements
From: ravipativishnu@yahoo.co.in
Date: 23 Mar 2007 03:26:27 -0700
Links: << >>  << T >>  << A >>
hai ,

i am vishnu, i am doing my project in verilog using state machine,
while using if or case statements i am getting some  error . i have
coded like this

s4 : begin
        if ( {gsr,gsy,gsb} ==  000 )
                  begin
                        count <= 0;
                        nextstate <= s5;

                  end
        else if ( {gsr,gsy,gsb}  ==  001 | 010 | 011 | 100 | 101 |
110 )
                  begin
                        phaseerror <= 1;
                        count <= 0;
                  end
        else
                  begin
                        generatoron <= 1;
                        count <= 0;
                  end
        end

Warning: Reduced register "generatoron~reg0" with stuck data_in port
to stuck value GND

in this case it is not going to the else part, if i have used only the
if -else then it is working properly,but i need to have all the three
conditions which i have specified in the code above.

i have tried using case statements also

s4 : case ( {gsr,gsy,gsb} )

       000    :  begin
                        count <= 0;
                        nextstate <= s5;

                  end

       001    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       010    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       011    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       100    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       101    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       110    :   begin
                      phaseerror <= 1;
                       count <= 0;
                    end

       111  :    begin
                        generatoron <= 1;
                        count <= 0;
                  end

        default : begin
                   generatoron <= 0;
                   phaseerror <= 0;
                  end
          endcase


Warning (10199):  case item expression is ignored because it never
applies

for 000 and 001 the case expression is executing ,for remaining i.e
(010.........111) it is giving the above warning.

i am not understanding where the problem lies

regards
vishnu


Article: 117113
Subject: Flash memmory model
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 23 Mar 2007 03:50:25 -0700
Links: << >>  << T >>  << A >>
Hi all,
   In my new firm we are planning to develop a flash model. What i
want to know is that is there any need for such an activity. My
feeling is that all the vendors will provide a beautifull timing model
for their products. Then is there any thing we can do in developing a
new model. Is there anything usefull in developing a parameterizable
general purpose model. Is there any suggestion from you people?
   Also what could be the best language to use for the modeling
(timing models) verilog or system verilog??
regards
Sumesh V S


Article: 117114
Subject: Re: problem while using if or case statements
From: Joseph Samson <jsamson@the-company-name.com>
Date: Fri, 23 Mar 2007 07:40:52 -0400
Links: << >>  << T >>  << A >>
ravipativishnu@yahoo.co.in wrote:
> hai ,
> 
> i am vishnu, i am doing my project in verilog using state machine,
> while using if or case statements i am getting some  error . i have
> coded like this
> 
> s4 : begin
>         if ( {gsr,gsy,gsb} ==  000 )

You didn't show us how you declared gsr, gsy and gsb. I'm assuming that 
they are single bit. You aren't telling Verilog the radix of your 
constants. The correct syntax would be:

if ( {gsr,gsy,gsb} ==  3'b000 )

and

I'm not sure if this is even syntactically correct, and if it is, 
whether it evaluates in the way you think:

else if ( {gsr,gsy,gsb}  ==  3'b001 | 3'b010 | 3'b011 | 3'b100 | 3b'101|
		3'b110 )

You probably mean

else if (  ({gsr,gsy,gsb}  ==  3'b001) || ({gsr,gsy,gsb}  ==  3'b010)
	|| ({gsr,gsy,gsb}  ==  3'b011) || ({gsr,gsy,gsb}  ==  3'b100)
         || ({gsr,gsy,gsb}  ==  3'b101) || ({gsr,gsy,gsb}  ==  3'b110))


Finally, in your case statement, please assign the same set of signals 
in every case. In case 3'b000, you assign count and nextstate; in case 
3'b001, you assign phaseerror and count. What happens with nextstate? 
Verilog will synthesize the logic such that nextstate <= nextstate in 
case 3'b001. You should make that explicit, both as a benefit to the 
readers (and debuggers) of your code, and to prevent unnecessary logic 
like latches from being generated in combinatorial expressions.


---
Joe Samson
Pixel Velocity

Article: 117115
Subject: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
From: David Brown <david@westcontrol.removethisbit.com>
Date: Fri, 23 Mar 2007 12:48:04 +0100
Links: << >>  << T >>  << A >>
Fred wrote:
> "Marc Randolph" <mrand@my-deja.com> wrote in message 
> news:1174444522.570165.55480@p15g2000hsd.googlegroups.com...
>> On Feb 15, 7:40 pm, Thomas Womack <twom...@chiark.greenend.org.uk>
>> wrote:
>>> In article <1171576522.086383.317...@h3g2000cwc.googlegroups.com>,
>>>
>>> spartan3wiz <magnus.wedm...@gmail.com> wrote:
>>>> There is a major risk for me missing the point here, but I'll give it
>>>> ago anyway! The original question takled about the ISE and Dual
>>>> Cores.... why would you need Dual Core for ISE? It does never use more
>>>> than one of them anyway!
>>> Because the fast (2.4GHz and above) Core 2Duochips get you 4MB of
>>> level-2 cache which, if you're using ISE on only one core and not
>>> doing anything very intensive in the background, is all available to
>>> the ISE process.  Given how much of a boost people saw with 1MB-cache
>>> versus 512k-cache AMD chips, and how memory-intensive FPGA compilation
>>> is, I would expect 4MB to be distinctly useful.
>>>
>>> Tom
>> Sorry for pulling a really old thread out for a follow-on, but I
>> figured it would be better to keep the info together than spread
>> across a bunch of threads.
>>
>> I'm sure that you are correct that 4 MB would provide super results,
>> but even 2 MB appears to be more than enough to allow a laptop to be
>> overwhelmingly faster than a desktop that was considered unbeatable
>> when it was brand new:
>>
>> Pentium 4 at 3.2 GHz with 2 GB of RAM results:
>>
>> Loading device for application Rf_Device from file '2vp40.nph' in
>> environment C:\Xilinx\Xilinx9.1i.
>>   "benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
>> fg676, speed -6
>>
>> Device Utilization Summary:
>>
>>   Number of BUFGMUXs                        9 out of 16     56%
>>   Number of DCMs                            4 out of 8      50%
>>   Number of External IOBs                 319 out of 416    76%
>>      Number of LOCed IOBs                 319 out of 319   100%
>>   Number of RAMB16s                       105 out of 192    54%
>>   Number of SLICEs                      13951 out of 19392  71%
>>
>> Starting Placer
>>
>> REAL time consumed by placer: 11 mins 54 secs
>> CPU  time consumed by placer: 11 mins 36 secs
>> Writing design to file benchmarkT_top.ncd
>>
>> Total REAL time to Placer completion: 12 mins 4 secs
>> Total CPU time to Placer completion: 11 mins 44 secs
>>
>> Starting Router
>>
>> Phase 1: 128932 unrouted;       REAL time: 12 mins 42 secs
>> Phase 4: 20607 unrouted; (1604)      REAL time: 14 mins 32 secs
>> Phase 5: 20609 unrouted; (0)      REAL time: 14 mins 40 secs
>> Phase 7: 0 unrouted; (0)      REAL time: 16 mins 9 secs
>> Phase 8: 0 unrouted; (0)      REAL time: 16 mins 54 secs
>>
>> Total REAL time to Router completion: 17 mins 8 secs
>> Total CPU time to Router completion: 16 mins 39 secs
>>
>> All signals are completely routed.
>>
>> Total REAL time to PAR completion: 17 mins 58 secs
>> Total CPU time to PAR completion: 17 mins 4 secs
>>
>> Peak Memory Usage:  792 MB
>>
>> ------   compared to  ---------
>>
>> T7200 (2 GHz mobile version of the Core 2 duo) with 2 GB of RAM
>> results:
>>
>> Loading device for application Rf_Device from file '2vp40.nph' in
>> environment C:\Xilinx\Xilinx91i.
>>   "benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
>> fg676, speed -6
>>
>> Device Utilization Summary:
>>
>>   Number of BUFGMUXs                        9 out of 16     56%
>>   Number of DCMs                            4 out of 8      50%
>>   Number of External IOBs                 319 out of 416    76%
>>      Number of LOCed IOBs                 319 out of 319   100%
>>
>>   Number of RAMB16s                       105 out of 192    54%
>>   Number of SLICEs                      13951 out of 19392  71%
>>
>> Starting Placer
>>
>> REAL time consumed by placer: 6 mins 12 secs
>> CPU  time consumed by placer: 6 mins 9 secs
>> Writing design to file benchmarkT_top.ncd
>>
>>
>> Total REAL time to Placer completion: 6 mins 20 secs
>> Total CPU time to Placer completion: 6 mins 14 secs
>>
>> Starting Router
>>
>> Phase 1: 128932 unrouted;       REAL time: 6 mins 37 secs
>> Phase 4: 20607 unrouted; (1604)      REAL time: 7 mins 31 secs
>> Phase 5: 20609 unrouted; (0)      REAL time: 7 mins 34 secs
>> Phase 7: 0 unrouted; (0)      REAL time: 8 mins 24 secs
>> Phase 8: 0 unrouted; (0)      REAL time: 8 mins 48 secs
>>
>> Total REAL time to Router completion: 8 mins 54 secs
>> Total CPU time to Router completion: 8 mins 48 secs
>>
>> All signals are completely routed.
>>
>> Total REAL time to PAR completion: 9 mins 25 secs
>> Total CPU time to PAR completion: 9 mins 4 secs
>>
>> Peak Memory Usage:  784 MB
>>
>>
> 
> Your comparison makes interesting reading.
> 
> How do you think the AMD dual processor chips compare with Intel's.  In many 
> circles there seems to be an prejudice against AMD processors without any 
> good reason.
> 

It is just a prejudice - it's well over a decade since there was any 
conceivable technical reason for considering AMD processors to be cheap 
inferior processors.  But remember, it is not the processor alone that 
make a system fast and stable.

The Intel Core 2 chips have more in common with the current AMD devices 
than they do with the P4 cores.  The P4's were very much designed to get 
a high clock rate, and suffered from (amongst other things) very long 
pipelines and therefore poor performance when there were many branches. 
  The Core 2, like the AMD cores, aim for lower clock rates but more 
instructions per cycle.  For a lot of code, this turns out to be much 
more efficient.

There is not a huge difference between Opterons and Core 2 cores at the 
moment - Core 2 is somewhat ahead on single thread speed, and is a bit 
better value for money for mid range processors, while the Opteron 
scales much better with multiple sockets (it does not suffer from the 
FSB bottleneck).  I expect AMD to take the lead again once their next 
core is out, but it's nice to see Intel with the top spot for speed 
after so many years - competition is good for everyone.

For FPGA design, popular opinion has it that the cache memory is 
particularly critical.  I don't actually do much FPGA design, so I can't 
comment on that theory.  But if you are looking for raw speed, with 
little regard for the lifetime of the pc, then it's easy to overclock 
the processor speed, but you can't add cache at that easily.


Article: 117116
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: Sean Durkin <news_mar07@durkin.de>
Date: Fri, 23 Mar 2007 12:52:59 +0100
Links: << >>  << T >>  << A >>
Grant Likely wrote:
> Brilliant!  Seems to work for me.  I can't test it fully right now
> because impact complains with "ERROR:iMPACT:583 - '2': The idcode read
> from the device does not match the idcode in the bsdl File." when I
> try to download to my ml403 board (which happens when I use the kernel
> driver too).
In that case, try lowering the speed in the cable setup menu. The ID
code problem often happens when the cable speed is too high.
Initializing the JTAG chain works most of the time, but after that
transfers fail. Lowering the speed fixes that for me in most cases.

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 117117
Subject: Custom IP ports to be used as GPIOs
From: "Sandip" <sandip.gaikwad@gmail.com>
Date: 23 Mar 2007 05:04:04 -0700
Links: << >>  << T >>  << A >>
Hi,

I have attached my custom IP to the OPB bus. The Custom IP contains
ports which should directly interact with the outside world. I have
ML403 board. I want to connect these ports to these GPIOs. So I edited
the system.ucf file to contain these ports and with oppropriate GPIO
names. Generation Netlist was successfull. But it gave error during
bitstream generation. The errors specified that the nets that put in
the system.ucf file was unable to recognise.

Can anyone help me in connecting the custom IP ports to the GPIO pins.

Thanks and regards,
Sandip


Article: 117118
Subject: EDK and Custom Peripheral: error occur when generating bitstream
From: "Allen" <lphplab@gmail.com>
Date: 23 Mar 2007 05:13:46 -0700
Links: << >>  << T >>  << A >>
hi all,

first, i am sorry for my poor English.

i use EDK 7.1i and ISE 7.1i.

imported custom peripheral with PLB Master Interface ( not from IFIP )
into my .xps project after overcame several problems.

In the step " generate netlist " there has no error or warning.

but in the step "Generate Bitstream",i got a error message "ERROR!!
NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2
abort.

already search this problem in xilix's answer database and tried
modify the parameter of C_BaseAddr, but it is still stuck here.

does anyone meet this problem before?

thanks in advance.


Article: 117119
Subject: Re: EDK and Custom Peripheral: error occur when generating bitstream
From: Zara <me_zara@dea.spamcon.org>
Date: Fri, 23 Mar 2007 13:33:44 +0100
Links: << >>  << T >>  << A >>
On 23 Mar 2007 05:13:46 -0700, "Allen" <lphplab@gmail.com> wrote:

>hi all,
>
>first, i am sorry for my poor English.
>
>i use EDK 7.1i and ISE 7.1i.
>
>imported custom peripheral with PLB Master Interface ( not from IFIP )
>into my .xps project after overcame several problems.
>
>In the step " generate netlist " there has no error or warning.
>
>but in the step "Generate Bitstream",i got a error message "ERROR!!
>NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2
>abort.
>
>already search this problem in xilix's answer database and tried
>modify the parameter of C_BaseAddr, but it is still stuck here.
>
>does anyone meet this problem before?
>
>thanks in advance.


I always got that messaghe when I had some signal with two outputs
connected to it. That seems your case, in your plb address bus, master
interface. 

Best regards,

Zara

Article: 117120
Subject: Re: Austin the Altera Mole
From: "Paul" <pauljbennett@gmail.com>
Date: 23 Mar 2007 06:05:26 -0700
Links: << >>  << T >>  << A >>
What's with all the xilinx altera rivalry in the world?  I mean.. I
can seem THEM being rivals... being competitors and stuff.... but why
US, the users?  We'd be far better off if we just picked whatever part
was best for our individual application.  At work, I've generally used
xilinx - just because they have best fit the applications I was
looking for.  When I'm mucking around with a project at home, Altera
is usually better because I can get much more FPGA in a QFP package
that I stand a chance at soldering by hand.  Brand loyalty seems so
silly to me... why? to avoid learning another one of those wildly
difficult tool sets? (psst... I'm joking... neither is too
challenging!)   Anywho...   does anyone actually have a legitimate
reason for brand loyalty?  Or is it just the PC/Mac/Linux crap
rehashed?



On Mar 22, 10:47 am, Austin Lesea <aus...@xilinx.com> wrote:
> Paul,
>
> Thanks for this morning's good laugh.
>
> Wondered where you were hiding.
>
> Welcome back.
>
> Austin



Article: 117121
Subject: Re: Custom IP ports to be used as GPIOs
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 23 Mar 2007 06:10:44 -0700
Links: << >>  << T >>  << A >>
On Mar 23, 7:04 am, "Sandip" <sandip.gaik...@gmail.com> wrote:
> Hi,
>
> I have attached my custom IP to the OPB bus. The Custom IP contains
> ports which should directly interact with the outside world. I have
> ML403 board. I want to connect these ports to these GPIOs. So I edited
> the system.ucf file to contain these ports and with oppropriate GPIO
> names. Generation Netlist was successfull. But it gave error during
> bitstream generation. The errors specified that the nets that put in
> the system.ucf file was unable to recognise.
>
> Can anyone help me in connecting the custom IP ports to the GPIO pins.
>
> Thanks and regards,
> Sandip

I don't know anything about your board or OPB bus, but the net names
in the UCF file _must_ match the names in your top level HDL (VHDL or
Verilog) or you will get the error message.
-Dave Pollum


Article: 117122
Subject: Re: Flash memmory model
From: "Gabor" <gabor@alacron.com>
Date: 23 Mar 2007 06:12:22 -0700
Links: << >>  << T >>  << A >>
On Mar 23, 6:50 am, "vssumesh" <vssumesh_a...@yahoo.com> wrote:
> Hi all,
>    In my new firm we are planning to develop a flash model. What i
> want to know is that is there any need for such an activity. My
> feeling is that all the vendors will provide a beautifull timing model
> for their products. Then is there any thing we can do in developing a
> new model. Is there anything usefull in developing a parameterizable
> general purpose model. Is there any suggestion from you people?
>    Also what could be the best language to use for the modeling
> (timing models) verilog or system verilog??
> regards
> Sumesh V S


I would guess that there is a place for third party models for
any device that has multiple manufacturers.  If for example I
want to design a board to work with standard devices from Intel,
Toshiba, and Atmel, it would be easier if I had a model that
represented the worst case timing from all three suppliers,
rather than running a simulation for each chip maker.  This
gets even more useful in designs using multiple parts where
I might need to use a matrix of tests with mixes of different
vendor models.  The third party model would also make life
easier when the different vendors don't use the same port names
on their models, requiring me to make a wrapper for each model
to simplify inclusion into my testbench.

A feature that could prove valuable would be a model that
somehow automates the merger of multiple vendor models and
thus allows immediate updates when a vendor model changes.

Right now I'm only using Verilog, but I'm probably not your
best prospective customer for this product.  However if you
don't need the features of SV, a Verilog model could be used
in either environment.

Just my 2 cents,
Gabor


Article: 117123
Subject: Re: Virtex-II block RAM problem
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 23 Mar 2007 13:15:50 +0000
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> writes:

> Martin Thompson wrote:
>> Dmitry Teytelman <dimtey@moc.liamg> writes:
>>
>>> Hello Daniel,
>>>
>>> On Thu, 22 Mar 2007, Daniel S. wrote:
>>>
>>>> Would the unimportant warnings in question happen to be the one
>>>> about PAR/MAP getting confused between PAD and IOB FFs timing
>>>> constraints? I am glad I saw this thread because I was about to make
>>>> the very same mistake to get rid of those warnings too!
>>> I added FFS(*) to the constraint to get rid of the following warning
>>> in the translation report:
>>>
>>> WARNING:XdmHelpers:662 - Period specification "TS_clk_ctrl_aclk4_dcm"
>>> references the TNM group "clk_ctrl_aclk4_dcm", which contains both
>>> pads and synchronous elements. The timing analyzer will ignore the
>>> pads for this specification. You might want to use a qualifier
>>> (e.g. "FFS") on the TNM property to remove the pads from this group.
>>>
>>
>> I reckon that warning ought to end with "... but you probably don't
>> as this might break all sorts of other
>> things unless you really understand what this does"
>>
>> :-)
>>
>> Xilinx: How about
>> a) A better warning
>> b) the ability to say "NOPADS" on the TNM property (or NOFFS, NORAMS
>> etc...)
>>
>> Cheers,
>> Martin
>
> I know the EXCEPT can be used to define timing groups but I'm not sure
> about the TNM_NET.  I'd be interested to see if
>

I knew there was something like that, but my quick reread of the
constraints guide didn't point me at it - thanks!

<snip>
> The syntax
>
>   NET myclk TNM_NET = FFS(*) LATCHES(*) MULTS(*) RAMS(*) myclk;
>
> (and any othere synchronous elements I've forgotten) 

and therein lies the problem :-)  Using EXCEPT would allow the tools
to remember for you (we hope..)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 117124
Subject: Re: URGENT HELP NEEDED: LVDS
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 23 Mar 2007 06:20:26 -0700
Links: << >>  << T >>  << A >>
On Mar 23, 1:49 am, "GaLaKtIkUs=E2=84=A2" <taileb.me...@gmail.com> wrote:
> On Mar 23, 8:45 am, "MM" <m...@yahoo.com> wrote:
>
> > "GaLaKtIkUsT" <taileb.me...@gmail.com> wrote in message
>
> >news:1174626985.784318.16210@n76g2000hsh.googlegroups.com...
>
> > > This board INVERTS LVDS PAIRS ie: if I
> > > have an output {XP,XN} I get the input {XN,XP}. ({A,B}=3DA on P pin a=
nd
> > > B on N pin).
>
> > 1. I doubt anyone can understand your description above. Are you trying=
 to
> > say that the wires are crossed on the board?
> > 2. Use a scope.
>
> > /Mikhail
>
> They are not crossed like X. the problem is the following if we try
> (using the loop back board) to get P pin on P pin and N pin on N pin
> we will be obliged to cross the wires (make an X on the board). To
> avoid this the guy ho made that loopback board decided to send the P
> to N and N to P and says that the only problem will the inversion of
> the logic levels.
> I reformulate my question in more simple terms:
> I LVDS pins are crossed what would be the result? only inversion of
> logic levels or more?
> Mehdi


If the loop-back board crosses the wires, then I assume that
  out-N --> loop board --> in-P and out-P --> loop-board --> in-N.
If this is true, then yes, the signal is inverted.  Make a simple test
to verify this.
-Dave Pollum




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search