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Hi everyone, A quick update (I haven't been through everything yet, after all it's supposed to be a weekend...): I checked all the FX60 erratas, there are no (known) ones concerning the DCMs. I tried the same design on an identical board, showed exactly the same behaviour, so there really is something wrong with the design and not with the chip. I checked my VHDL code over and over again, couldn't find any errors, but I will do the same in FPGA editor as well, just to be sure. Furthermore I will try to reset the first DCM after config is done and see if that helps matters. And then I think I will admit defeat and try to source the 200 MHz externally. I also opened a WebCase, maybe that gets me some more information. Nevertheless, big thanks already to everybody who helped. Cheers, Michael

Hi I found one article in FPGA 2006 conference. They calculated "number of logic blocks" x "area of each block". They state that the area ratio is around 33 for logic, for a number of benchmarks. Then probably I also need information on LUT (or slice) actual size. If anyone knows how to obtain this information, let me know. Thank you in advance.

Hi I manually made one MACRO (.nmc file), in V2P30, ISE 8.2.03, for 16-bit AND function using 8 slices. Every LUT was manually programmed by "A1 * A2" Strangely, after place and route (PAR), I observe that some of LUTs in the MACRO are modified by "A1 * A3" or "A2 * A4" Though it is still "16-bit AND" function, I do not understand who, why, how change these PIN information. Is it because of routing congestion? Does anyone have this experience?

On Apr 29, 7:56 am, MNiegl <Michael.Ni...@cern.ch> wrote: > Hi everyone, > > A quick update (I haven't been through everything yet, after all it's > supposed to be a weekend...): > I checked all the FX60 erratas, there are no (known) ones concerning > the DCMs. > I tried the same design on an identical board, showed exactly the same > behaviour, so there really is something wrong with the design and not > with the chip. > I checked my VHDL code over and over again, couldn't find any errors, > but I will do the same in FPGA editor as well, just to be sure. > > Furthermore I will try to reset the first DCM after config is done and > see if that helps matters. And then I think I will admit defeat and > try to source the 200 MHz externally. I also opened a WebCase, maybe > that gets me some more information. > > Nevertheless, big thanks already to everybody who helped. > > Cheers, > Michael It's been a while since I looked into this (Virtex II series) so I'm not sure about V4. However in the other DCM's there was a "high frequency" mode that needed to be specified for the DLL to work at higher frequencies. The HF mode also disabled the CLK2X output. Could it be you need to use HF mode after some frequency (higher than 160 but less than 200 MHz)? Another thought. If you wait for the first DCM to lock before releasing GSR, do you really reset the second DCM? How do you initialize the SRL16 to ensure you get a minimum reset length if the first DCM is locked after config? Normally without an INIT attribute the SRL would come up all zeroes after config. If your reset signal is active high you'd want to init the SRL to all ones. HTH, Gabor

Let me repeat: There is no proportionality. A LUT, when translated to an ASIC, can be anything between a single inverter, or more than a dozen gates, or it can be a 16-bit RAM, which is well over a hundred gates. Do you really want to use an average of those numbers? Also, for most ASIC designs, the chip area is less important than the development and mask-making cost. For a modern process, that will be millions of dollars. That often dwarfs the manufacturing cost per chip. Peter Alfke On Apr 29, 5:14 am, Pasacco <pasa...@gmail.com> wrote: > Hi > > I found one article in FPGA 2006 conference. > > They calculated "number of logic blocks" x "area of each block". > > They state that the area ratio is around 33 for logic, for a number of > benchmarks. > > Then probably I also need information on LUT (or slice) actual size. > > If anyone knows how to obtain this information, let me know. > > Thank you in advance.

Hello all. I'm new to FPGA and I need a little help with connecting Dallas 1-wire temperture DS18B20 sensor. I used that sensor many times with ARM and AVR MCU but never with FPGA. What I want to know is how to connect it? DS needs to have an external pull up resistor. So sometimes I need to release line so that line is pulled high. DS and FPGA can only drive line low, high must come from pull up. So..how to do that? How to use IN/OUT pin that I can "realase"? To MCU I would simple say "pin input" and it would be released, but in VHDL I define in entity pin : inout STD_LOGIC; Hmm..any ideas? Thanks.

I'm designing a debounce filter using Finite State Machine. The FSM behavior is it follows the inital input bit and thinks that's real output until it receives 3 consecutive same bits and it changes output to that 3 consecutive bit until next 3 consecutive bits are received. A reset will set the FSM to output 1s until it receives the correct input and ouput. This is the test sequence with input and correct output. 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) The state diagram I came up has 6 states and it's named SEE1, SEE11, SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in the input. Because it just came from SEE1 and before SEE1, it came from SEE000, so at SEE1 it can not change ouput to 1 which is what I have specified that state's ouput to be. Anyone knows how to solve this problem? Or maybe there's other better ways to design the state diagram? Thanks, Anson

My suggestion: Feed the input into a 3-bit shift register. Detect all-ones (111) and used that signal to set a latch, detect all-zeros (000) and use that signal to reset a latch. The latch is your de-bounced signal. Peter Alfke On Apr 29, 11:32 am, Anson.Stugg...@gmail.com wrote: > I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? > > Thanks, > > Anson

On Apr 29, 11:45 am, Peter Alfke <a...@sbcglobal.net> wrote: > My suggestion: > Feed the input into a 3-bit shift register. > Detect all-ones (111) and used that signal to set a latch, > detect all-zeros (000) and use that signal to reset a latch. > The latch is your de-bounced signal. > Peter Alfke > > On Apr 29, 11:32 am, Anson.Stugg...@gmail.com wrote: > > > > > I'm designing adebouncefilter using Finite State Machine. TheFSM > > behavior is it follows the inital input bit and thinks that's real > > output until it receives 3 consecutive same bits and it changes output > > to that 3 consecutive bit until next 3 consecutive bits are received. > > A reset will set theFSMto output 1s until it receives the correct > > input and ouput. > > > This is the test sequence with input and correct output. > > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > > the input. Because it just came from SEE1 and before SEE1, it came > > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > > have specified that state's ouput to be. > > > Anyone knows how to solve this problem? Or maybe there's other better > > ways to design the state diagram? > > > Thanks, > > > Anson- Hide quoted text - > > - Show quoted text - Thanks Peter for the suggestion. But my problem is coming up with the state diagram for this FSM. How can I implement what you suggested on a state diagram? Thanks. Anson

Anson.Stuggart@gmail.com wrote: > maybe there's other better > ways to design the state diagram? I wouldn't use a state diagram at all. Just a 4 bit shift_left. The value "0111" sets the output. "1000" clears it. -- Mike Treseler

Anson.Stuggart@gmail.com wrote: > I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? I'm not sure I understand your terminology, but I am assuming that that state neames mean: SEE1 = output = 0 after 1 has been input 1 times in a row. SEE11 = output = 0 after 1 has been input 2 times in a row. SEE111 = output = 1 after 1 has been input 3 times in a row (or a 1 is input after 0 has been input less than 3 times in a row). SEE0 = output = 1 after 0 has been input 1 times in a row. SEE00 = output = 1 after 0 has been input 2 times in a row. SEE000 = output = 0 after 0 has been input 3 times in a row (or a 0 is input after 1 has been input less than 3 times in a row). If this is the case, then the 12 transitions are: before input after SEE1 1 SEE11 SEE1 0 SEE000 SEE11 1 SEE111 SEE11 0 SEE000 SEE111 1 SEE111 SEE111 0 SEE0 SEE0 1 SEE111 SEE0 0 SEE00 SEE00 1 SEE111 SEE00 0 SEE000 SEE000 1 SEE1 SEE000 0 SEE000

On Apr 29, 12:32 pm, Anson.Stugg...@gmail.com wrote: > I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? A counter counts toward 3 as long as the input state stays the same. Any change resets the counter to zero. On reaching 3, the counter enables the last occurring input state to be latched to the output. That is, instead of counting ones or zeros, count all clocks, with any input change resetting the counter. -- John

Peter Alfke wrote: > My suggestion: > Feed the input into a 3-bit shift register. > Detect all-ones (111) and used that signal to set a latch, > detect all-zeros (000) and use that signal to reset a latch. > The latch is your de-bounced signal. That is exactly the way I do it with PIC code, a whole port at a time, in parallel. I also generate additional bytes that indicate a change of state of any of the port inputs from 1 to 0 and 0 to 1. This single shot bits are very handy to have on the shelf when a program development needs one. So the storage requirement is i byte each for 8: state of raw inputs, previous state of inputs, twice previous state of inputs, debounced inputs, debounced inputs that have just transitioned to 1, debounced inputs that have just transitioned to 0. I don't have the code handy, but I seem to remember that it took only something like 18 instructions to maintain this table of bytes servicing an 8 bit port.

On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote: > Anson.Stugg...@gmail.com wrote: > > I'm designing a debounce filter using Finite State Machine. The FSM > > behavior is it follows the inital input bit and thinks that's real > > output until it receives 3 consecutive same bits and it changes output > > to that 3 consecutive bit until next 3 consecutive bits are received. > > A reset will set the FSM to output 1s until it receives the correct > > input and ouput. > > > This is the test sequence with input and correct output. > > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > > the input. Because it just came from SEE1 and before SEE1, it came > > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > > have specified that state's ouput to be. > > > Anyone knows how to solve this problem? Or maybe there's other better > > ways to design the state diagram? > > I'm not sure I understand your terminology, but I am > assuming that that state neames mean: > > SEE1 = output = 0 after 1 has been input 1 times in a row. > > SEE11 = output = 0 after 1 has been input 2 times in a row. > > SEE111 = output = 1 after 1 has been input 3 times in a row > (or a 1 is input after 0 has been input less than 3 > times in a row). > > SEE0 = output = 1 after 0 has been input 1 times in a row. > > SEE00 = output = 1 after 0 has been input 2 times in a row. > > SEE000 = output = 0 after 0 has been input 3 times in a row > (or a 0 is input after 1 has been input less than 3 > times in a row). > > If this is the case, then the 12 transitions are: > > before input after > SEE1 1 SEE11 > SEE1 0 SEE000 > SEE11 1 SEE111 > SEE11 0 SEE000 > SEE111 1 SEE111 > SEE111 0 SEE0 > SEE0 1 SEE111 > SEE0 0 SEE00 > SEE00 1 SEE111 > SEE00 0 SEE000 > SEE000 1 SEE1 > SEE000 0 SEE000- Hide quoted text - > > - Show quoted text - That's it John...Thanks a lot...you're the man!

[Removed all language groups] Anson.Stuggart@gmail.com wrote: > I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. That's an unusual brief - is this homework ? > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) No, it is a partial test sequence. The spec mentions reset, but the test does not. > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? There is probably a better way to specify the state operation :) Normally, digital debounce is done with something like a saturating counter and a toggle or JK result stage. -jg

On Apr 29, 2:14 pm, Pasacco <pasa...@gmail.com> wrote: > Hi > > I found one article in FPGA 2006 conference. > > They calculated "number of logic blocks" x "area of each block". > > They state that the area ratio is around 33 for logic, for a number of > benchmarks. > > Then probably I also need information on LUT (or slice) actual size. > > If anyone knows how to obtain this information, let me know. > > Thank you in advance. Why don't you synthesize to an ASIC directly? I am sure that your university has access to a commercial synthesis tool like design compiler. But there are also some free academic tools available. Than you can choose a technology and the tool will tell you the chip area for your design. Cell libraries for some technologies are availale on line for free, for others you need to sign an NDA with eurochip or mosis. Kolja Sulimma

Anson.Stuggart@gmail.com wrote, On 29/04/07 19:32: > I'm designing a debounce filter using Finite State Machine. The FSM <snip> > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? You need to decide whether you will be implementing it in hardware or software. If hardware, which I suspect from all the groups other than comp.lang.c when why are you cross-posting to a C language group? If software, then why post to all the other groups? Either way your selection of groups has to be wrong. Personally I would suggest implementing it in HW rather than SW (although I have implemented debounce in SW a couple of times when the HW design was broken). Follow-ups set to exclude comp.lang.c, and I would like to request that others replying in other parts of the thread exclude comp.lang.c unless they are posting C related answers to this problem. -- Flash Gordon

In news:OroYh.16855$Kd3.13348@newssvr27.news.prodigy.net timestamped Fri, 27 Apr 2007 15:14:54 GMT, Joseph Samson <jsamson@the-company-name.com> posted: "How fortunate for me that this thread has evolved into a discussion about emacs. I am using Xemacs in Windows with the verilog mode. I want to insert spaces in place of tabs. I put (setq-default indent-tabs-mode nil); in my custom.el and in verilog.el, but tabs are not being implemented as spaces in my verilog files (but they are implemented as spaces in other files). Any ideas?" I do not know, but it would seem that you could try making the value of verilog-tab-always-indent to be nil ... from WWW.Veripool.com/verilog-mode-faq.html#3electab :"[..] How do I prevent tab from automatically indenting? Set the verilog-tab-always-indent variable to nil. [..] [..]" If that is not sufficient, you might have an unpleasant time trying to cope with all of the parts of the mode's file related to tabs when choosing what to delete/rewrite. I agree that indenting with tabs is a bad idea, which is more evidence that Emacs is not configured by default to be a good source code editor. Regards, C. P. G.

Anson.Stuggart@gmail.com writes: > I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? This question has nothing to do with the C programming language. Why did you post to comp.lang.c? Followups redirected. -- Keith Thompson (The_Other_Keith) kst-u@mib.org <http://www.ghoti.net/~kst> San Diego Supercomputer Center <*> <http://users.sdsc.edu/~kst> "We must do something. This is something. Therefore, we must do this." -- Antony Jay and Jonathan Lynn, "Yes Minister"

> I'm designing a debounce filter using Finite State Machine. The FSM > behavior is it follows the inital input bit and thinks that's real > output until it receives 3 consecutive same bits and it changes output > to that 3 consecutive bit until next 3 consecutive bits are received. > A reset will set the FSM to output 1s until it receives the correct > input and ouput. > > This is the test sequence with input and correct output. > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > the input. Because it just came from SEE1 and before SEE1, it came > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > have specified that state's ouput to be. > > Anyone knows how to solve this problem? Or maybe there's other better > ways to design the state diagram? > Debouncing can come in several flavors, and from what I can gather from your description, the debouncing should be focussed on changing the debounced representation of the input. Something like shown below where the OUT FF is a conditional toggle using the EXOR feedback and conditioned to toggle or remain-the-same as a function of the three input states prior to the active clock edge, all different from OUT causing a toggle and one or more the same as OUT preventing the toggle: View in a fixed-width font such as Courier. . . . . .--------------------+----------------+->OUT . | | | . | __ | __ ----- | . IN>---+-----------|--\ \ \ __ '-\ \ \ | | | . | | | | >------| \ | | >|D Q|-' . | +--/ /__/ .----| >--/ /__/ | | . | | | .-|__/ | | . | | | | clk-> | . | ----- | | | | | . | | | | __ | | ----- . '-|D Q|-+-|--\ \ \ | | . | | | | | | >-' | . clk-> | | +--/ /__/ | . | | | | | . ----- | | | . .---------' | | . | ----- | | . | | | | __ | . '-|D Q|---|--\ \ \ | . | | | | | >----' . clk-> | '--/ /__/ . | | . ----- . . .

Peter Alfke <alfke@sbcglobal.net> writes: > I remember well that all real TTL LS devices have an effective two- > diode drop on the output. That was the part I wasn't sure about. > Then the question is whether 5 V minus 1.4 V is higher than your 3.3 > V, and really higher than your 3.3 V plus a diode drop. > You can easily try it out, and measure the current flowing into the > FPGAinput when the LS output is High. Probably is it les than a few > microamps. > But then the question is about tolerances: can your 5V bw high while > your 3.3 V is low, Yes. That would have to be taken into account. > and what about the start-up condition? Oooh, I hadn't considered that. > The resistor pck avoids all these headaches. I wasn't trying to avoid the resistor, just trying to determine whether the value could be lower. I don't actually need it to be lower, but I wanted to understand the actual requirement. Even with 300 ohms, won't there be a problem if the 5V comes up first, or there is a fault and the Vcco isn't present? If the 5V is really 5.5V and Vcco is at/near 0V, the TTL output could be as much as 4.1V above Vcco. That would allow 11.7 nA, while answer record 19146 suggests that the current through the protection diode should not be more than 5.51 mA. To limit the current to 5.51 mA, the resistor would need to be 635.2 ohms (680 ohm 5%). That seems pretty high, but since TTL is slow stuff anyhow, it looks like it won't introduce enough delay to be a problem. Should answer record 19146 be revised to cover startup and Vcco fault conditions? Or is it safe to allow the I/O pin to power Vcco through the clamp diodes provided that it doesn't rise above Vcco(max)? Thanks, Eric

I think 5 mA is an unnecessaily low limit. 10 mA is pefectly safe, even if it lasts forever. Don't forget, there is also a diode drop between the input and Vcco. The resistor value is a trade-off between speed (low resistor value) and "safety" (high value) Pick 300 to 1000 Ohm, any value will be ok. Consider the input a 10 pF load and put the resistor close to it.. Then 1kilohm means a 10 ns time constant... Peter Alfke On Apr 29, 3:09 pm, Eric Smith <e...@brouhaha.com> wrote: > Peter Alfke <a...@sbcglobal.net> writes: > > I remember well that all real TTL LS devices have an effective two- > > diode drop on the output. > > That was the part I wasn't sure about. > > > Then the question is whether 5 V minus 1.4 V is higher than your 3.3 > > V, and really higher than your 3.3 V plus a diode drop. > > You can easily try it out, and measure the current flowing into the > > FPGAinput when the LS output is High. Probably is it les than a few > > microamps. > > But then the question is about tolerances: can your 5V bw high while > > your 3.3 V is low, > > Yes. That would have to be taken into account. > > > and what about the start-up condition? > > Oooh, I hadn't considered that. > > > The resistor pck avoids all these headaches. > > I wasn't trying to avoid the resistor, just trying to determine whether > the value could be lower. I don't actually need it to be lower, but > I wanted to understand the actual requirement. > > Even with 300 ohms, won't there be a problem if the 5V comes up first, > or there is a fault and the Vcco isn't present? If the 5V is really > 5.5V and Vcco is at/near 0V, the TTL output could be as much as 4.1V > above Vcco. That would allow 11.7 nA, while answer record 19146 > suggests that the current through the protection diode should not be > more than 5.51 mA. To limit the current to 5.51 mA, the resistor > would need to be 635.2 ohms (680 ohm 5%). That seems pretty high, > but since TTL is slow stuff anyhow, it looks like it won't introduce > enough delay to be a problem. > > Should answer record 19146 be revised to cover startup and Vcco fault > conditions? Or is it safe to allow the I/O pin to power Vcco through > the clamp diodes provided that it doesn't rise above Vcco(max)? > > Thanks, > Eric

On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote: > Anson.Stugg...@gmail.com wrote: > > I'm designing a debounce filter using Finite State Machine. The FSM > > behavior is it follows the inital input bit and thinks that's real > > output until it receives 3 consecutive same bits and it changes output > > to that 3 consecutive bit until next 3 consecutive bits are received. > > A reset will set the FSM to output 1s until it receives the correct > > input and ouput. > > > This is the test sequence with input and correct output. > > > 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > > 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > > > The state diagram I came up has 6 states and it's named SEE1, SEE11, > > SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > > the input. Because it just came from SEE1 and before SEE1, it came > > from SEE000, so at SEE1 it can not change ouput to 1 which is what I > > have specified that state's ouput to be. > > > Anyone knows how to solve this problem? Or maybe there's other better > > ways to design the state diagram? > > I'm not sure I understand your terminology, but I am > assuming that that state neames mean: > > SEE1 = output = 0 after 1 has been input 1 times in a row. > > SEE11 = output = 0 after 1 has been input 2 times in a row. > > SEE111 = output = 1 after 1 has been input 3 times in a row > (or a 1 is input after 0 has been input less than 3 > times in a row). > > SEE0 = output = 1 after 0 has been input 1 times in a row. > > SEE00 = output = 1 after 0 has been input 2 times in a row. > > SEE000 = output = 0 after 0 has been input 3 times in a row > (or a 0 is input after 1 has been input less than 3 > times in a row). > > If this is the case, then the 12 transitions are: > > before input after > SEE1 1 SEE11 > SEE1 0 SEE000 > SEE11 1 SEE111 > SEE11 0 SEE000 > SEE111 1 SEE111 > SEE111 0 SEE0 > SEE0 1 SEE111 > SEE0 0 SEE00 > SEE00 1 SEE111 > SEE00 0 SEE000 > SEE000 1 SEE1 > SEE000 0 SEE000 Hi John, It is not that I'm saying the table is wrong (since I'm new to this and trying to learn) but how do you say: SEE1 with input 0 goes to SEE11 state? because then our state must be SEE01! Any comment?

Amit wrote: > On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote: >> Anson.Stugg...@gmail.com wrote: >>> I'm designing a debounce filter using Finite State Machine. The FSM >>> behavior is it follows the inital input bit and thinks that's real >>> output until it receives 3 consecutive same bits and it changes output >>> to that 3 consecutive bit until next 3 consecutive bits are received. >>> A reset will set the FSM to output 1s until it receives the correct >>> input and ouput. >>> This is the test sequence with input and correct output. >>> 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) >>> 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) >>> The state diagram I came up has 6 states and it's named SEE1, SEE11, >>> SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in >>> the input. Because it just came from SEE1 and before SEE1, it came >>> from SEE000, so at SEE1 it can not change ouput to 1 which is what I >>> have specified that state's ouput to be. >>> Anyone knows how to solve this problem? Or maybe there's other better >>> ways to design the state diagram? >> I'm not sure I understand your terminology, but I am >> assuming that that state neames mean: >> >> SEE1 = output = 0 after 1 has been input 1 times in a row. >> >> SEE11 = output = 0 after 1 has been input 2 times in a row. >> >> SEE111 = output = 1 after 1 has been input 3 times in a row >> (or a 1 is input after 0 has been input less than 3 >> times in a row). >> >> SEE0 = output = 1 after 0 has been input 1 times in a row. >> >> SEE00 = output = 1 after 0 has been input 2 times in a row. >> >> SEE000 = output = 0 after 0 has been input 3 times in a row >> (or a 0 is input after 1 has been input less than 3 >> times in a row). >> >> If this is the case, then the 12 transitions are: >> >> before input after >> SEE1 1 SEE11 >> SEE1 0 SEE000 >> SEE11 1 SEE111 >> SEE11 0 SEE000 >> SEE111 1 SEE111 >> SEE111 0 SEE0 >> SEE0 1 SEE111 >> SEE0 0 SEE00 >> SEE00 1 SEE111 >> SEE00 0 SEE000 >> SEE000 1 SEE1 >> SEE000 0 SEE000 > > Hi John, > > It is not that I'm saying the table is wrong (since I'm new to this > and trying to learn) but how do you say: SEE1 with input 0 goes to > SEE11 state? because then our state must be SEE01! The 6 states are defined above the transition table. There is no SEE01 state, because there is no reason to keep track of that sequence. If you are at SEE1 a single 1 input has been seen since the output was decided to be zero), and a zero arrives, you just go back to state SEE000 (the one where the output was decided to be changed to zero) since the required 3 1s in a row cannot occur till at least a single 1 arrives. Any zero arriving before that triple 1 is received just starts the count over.

On Apr 29, 5:45 pm, John Popelish <jpopel...@rica.net> wrote: > Amit wrote: > > On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote: > >> Anson.Stugg...@gmail.com wrote: > >>> I'm designing a debounce filter using Finite State Machine. The FSM > >>> behavior is it follows the inital input bit and thinks that's real > >>> output until it receives 3 consecutive same bits and it changes output > >>> to that 3 consecutive bit until next 3 consecutive bits are received. > >>> A reset will set the FSM to output 1s until it receives the correct > >>> input and ouput. > >>> This is the test sequence with input and correct output. > >>> 1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) > >>> 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output) > >>> The state diagram I came up has 6 states and it's named SEE1, SEE11, > >>> SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in > >>> the input. Because it just came from SEE1 and before SEE1, it came > >>> from SEE000, so at SEE1 it can not change ouput to 1 which is what I > >>> have specified that state's ouput to be. > >>> Anyone knows how to solve this problem? Or maybe there's other better > >>> ways to design the state diagram? > >> I'm not sure I understand your terminology, but I am > >> assuming that that state neames mean: > > >> SEE1 = output = 0 after 1 has been input 1 times in a row. > > >> SEE11 = output = 0 after 1 has been input 2 times in a row. > > >> SEE111 = output = 1 after 1 has been input 3 times in a row > >> (or a 1 is input after 0 has been input less than 3 > >> times in a row). > > >> SEE0 = output = 1 after 0 has been input 1 times in a row. > > >> SEE00 = output = 1 after 0 has been input 2 times in a row. > > >> SEE000 = output = 0 after 0 has been input 3 times in a row > >> (or a 0 is input after 1 has been input less than 3 > >> times in a row). > > >> If this is the case, then the 12 transitions are: > > >> before input after > >> SEE1 1 SEE11 > >> SEE1 0 SEE000 > >> SEE11 1 SEE111 > >> SEE11 0 SEE000 > >> SEE111 1 SEE111 > >> SEE111 0 SEE0 > >> SEE0 1 SEE111 > >> SEE0 0 SEE00 > >> SEE00 1 SEE111 > >> SEE00 0 SEE000 > >> SEE000 1 SEE1 > >> SEE000 0 SEE000 > > > Hi John, > > > It is not that I'm saying the table is wrong (since I'm new to this > > and trying to learn) but how do you say: SEE1 with input 0 goes to > > SEE11 state? because then our state must be SEE01! > > The 6 states are defined above the transition table. There > is no SEE01 state, because there is no reason to keep track > of that sequence. If you are at SEE1 a single 1 input has > been seen since the output was decided to be zero), and a > zero arrives, you just go back to state SEE000 (the one > where the output was decided to be changed to zero) since > the required 3 1s in a row cannot occur till at least a > single 1 arrives. Any zero arriving before that triple 1 is > received just starts the count over. Thank you so much for your answer but before I complete the reading I have a problem with this: >If you are at SEE1 a single 1 input has been seen since the output was decided to be zero), and a zero arrives Question: let's say we are at SEE1 and input is 1. How should I know the system expects 0? why not 1? Regards, amit

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