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Messages from 119275

Article: 119275
Subject: Re: Xilinx EDK: Slow OPB write speeds
From: Guru <ales.gorkic@email.si>
Date: 16 May 2007 01:30:15 -0700
Links: << >>  << T >>  << A >>
On May 15, 5:19 pm, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote:
> Antti wrote:
> > it all depends how efficient the memory controller and bus arbitration
> > really is.
> > in some cases the memory performance can be rather low.
>
> > Antti
>
> Antti, thanks for the input. I realise this is a bit difficult to answer
> without some real specific peripheral info, but can you suggest a faster
> method of interfacing a peripheral?
>
> I guess PLB is faster, but this will limit it to PPC use, or microblaze
> via a bus bridge, but I guess that will be slower still.
>
> Is some kind of DMA approach the only way to improve transfer rates?
>
> Thanks
> Andy

The PARAMETER C_INCLUDE_BURST_SUPPORT = 1 is  for the OPB_DDR or
OPB_SDRAM peripherals. But I realised that you may not want to write
directly to RAM.
DMA aproach is a right solution if you want a really fast transfer,
especially if you use burst support. Otherwise listen to Zara (he
taught me to design one).

Regards,

Guru

Where


Article: 119276
Subject: Re: Global ressource problem
From: Alan Myler <amyler@eircom.net>
Date: Wed, 16 May 2007 09:37:44 +0100
Links: << >>  << T >>  << A >>
Amine.Miled@gmail.com wrote:

> Hi
> 
> i'm developping an architecture using Libero and Actel FPGA, i had a
> problem with global ressources, I had 8 global ressources and the
> FPGA contains only 6, is there any way to oblige the compiler to not
> consider some signals as global ressources,
> synthesysing tool used: Synplify,
> 
> regards,
> A.
> 


The simply answer is yes. But first perhaps you can expalin what you 
want to use the global resources for? If you want 8 clocks for exampe 
then you will need to consider what Synplify will synthesise instead of 
a global buffer.

What Actel family are you using?

Alan





Article: 119277
Subject: Re: Xilinx EDK: Slow OPB write speeds
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Wed, 16 May 2007 10:49:10 +0200
Links: << >>  << T >>  << A >>
Hi,

You can use a MCH based memory controller like mch_opb_sdram for DMA like 
transfer from your module to the external memory.

The MCH protocol which is based on FSL is fairly simple and will allow to 
cacheline reads from memory.

Göran Bilski

"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message 
news:f2cj1a$gc5$1@netty.york.ac.uk...
> Antti wrote:
>
>> it all depends how efficient the memory controller and bus arbitration
>> really is.
>> in some cases the memory performance can be rather low.
>>
>> Antti
>>
>
> Antti, thanks for the input. I realise this is a bit difficult to answer
> without some real specific peripheral info, but can you suggest a faster
> method of interfacing a peripheral?
>
> I guess PLB is faster, but this will limit it to PPC use, or microblaze
> via a bus bridge, but I guess that will be slower still.
>
> Is some kind of DMA approach the only way to improve transfer rates?
>
> Thanks
> Andy 



Article: 119278
Subject: Re: Lockup with Xilinx mch_opb_ddr
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Wed, 16 May 2007 10:50:46 +0200
Links: << >>  << T >>  << A >>
Hi,

I would advice to get the latest version of EDK and ip cores.
There might be a bug which is fixed in the latest versions.

Göran Bilski

"Georg Acher" <acher@in.tum.de> wrote in message 
news:f2a6ko$1pa$1@news.lrz-muenchen.de...
> Hi,
>
> I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze 
> design.
> Beside the Microblaze, another bus master is accessing the DDR. Since I 
> need to
> avoid some deadlocks over the OPB-Bus, I've added a third MCH to the 
> mch_opb_ddr,
> which my bus master is using. The protocol is also simpler and a bit 
> faster than
> OPB, so it sounds like a good choice just for RAM-access. In principle it 
> works,
> but it hangs during heavy traffic :-(
>
> This happens usually during a read from my side, where the read address is 
> put on
> the MCH2 along with "control"=0 and "write"=1 for one clock. But no 
> "exists"
> appears, the Microblaze is dead, even DDR-RAM access over JTAG fails. On 
> the
> DDR-side no access can be seen, only the refresh runs.
>
> When I swap "my" MCH with the instruction cache-MCH, the lockup appears 
> much
> earlier.
>
> I already made sure that no address outside of the DDR-area is accessed, 
> the
> timing looks good, too. I thought that one can't do anything wrong with 
> just two
> control signals... To me, it looks like an arbitration issue when the 
> whole
> controller stops.
>
> Is there something special to know about the MCH/XCL and its usage? Are 
> there
> issues with more than 2 MCH channels?
>
> -- 
>         Georg Acher, acher@in.tum.de
>         http://www.lrr.in.tum.de/~acher
>         "Oh no, not again !" The bowl of petunias 



Article: 119279
Subject: Re: Video scaler for Spartan 3E?
From: "Ken Soon" <csoon@xilinx.com>
Date: Wed, 16 May 2007 17:10:41 +0800
Links: << >>  << T >>  << A >>
ok... I guess i better start small anyway since I really new to this.
Well I'm going to take a DSP module in school soon so it will definitely 
help me along.

(the higher the utilization the more difficult it is to place and route it 
at a higher speed).
Yes so true. I kept getting timing constraint problem for my current video 
scaler project.
Well though i learnt that timing delay could be reduced by adding output 
registers to fit the timing constraint.

Oh yah consulted my colleague who said that my video scaler (polyphase 
actually, did i mention it before?) is good in a sense that it consumes 
lesser resources.
Well I could be working on this project further on, though i will still need 
to understand some of the theory in video scaling as well.

Well really thank alot for the time and effort to advise me and give me some 
direction.

Oh by the way, can I ask if that once i kind of burn the chip and little 
smoke came off, is the chip spoilt? The board's power indicators are fine 
and I programmed successfully into the chip through a parallel IV cable but 
nothing was displayed though. No self-test or whatsoever is available 
though...so scared...

"Paul" <pauljbennett@gmail.com> wrote in message
news:1178889638.696406.114280@h2g2000hsg.googlegroups.com...
>I definately was not saying that linear interpolation results will be
> "very" poor...  in fact... I'd bet some commercial scalers do it that
> way....  At any rate... I'd be cautious of shooting for the stars -
> you're better off with an obtainable project...  Here's some
> considerations...
>
> 640x480 = 307200points... which, if you're talking about RGB input,
> means 307200 points of Red, Green & Blue each....   307200points x
> 60fps = 18.4MSample/s per color... lets assume you're processing the
> three colors independently... I know the Spartan3 development boards
> have 50MHz clocks on them.  I probably wouldn't try to push a Spartan
> design much past 100MHz unless it was a VERY empty part (the higher
> the utilization the more difficult it is to place and route it at a
> higher speed).  Now, assuming 100MHz, processing 3 colors
> independently, that basically means you can do 5 "operations" in a
> sample time... if you want to double your output rate (i.e. - scale up
> to 1280x960) that may be as low as 2.5 operations, depending what the
> operation is and if it needs to be done at the higher or lower rate.
> In short what that gets down to is that anymore operations than that
> must be done in different "blocks" of the design (i.e. they use more
> resources).  And that is going to quickly run you up against the limit
> in terms of the number of multipliers in the spartan probably.
>
> Now those are all TOTALLY ballpark, off the cuff numbers.  My gut
> instinct would be that linear interpolation will be NO problem at all
> in the spartan at 100MHz, I'd bet you could even do it at those
> resolutions at 50MHz.  But my other gut instinct there is also that
> any real significant amount of processing beyond linear interpolation
> is going to get really tight, really quick.  I think as a student
> you're better off not trying to attempt a really tightly packed
> design.  The reason I say that is that to get a really tight design to
> place and route correctly and meet timing you need to really know all
> the ins and outs of the software tools (the Xilinx software).  You
> have to set all sorts of settings, possibly go in an manually place
> critical parts of the design, etc... etc....    And that's REALLY not
> what you want to be spending your time on as a student.  Your purpose
> is to learn about the logical part of FPGA design, and that's going to
> be tricky enough on its own - I really wouldnt recommend working
> yourself into that tight a position... You're really going to have a
> lot on your plate with this design as it is.
>
> At any rate.. that's my advice..   anyone else is welcome to
> disagree...
>
>
>
>
> On May 11, 1:14 am, "Ken Soon" <c...@xilinx.com> wrote:
>> Yeh Kolja, I will definitely start with something simple first.
>> Since I haven't begin to understand the concept of coefficient and
>> upsampling.
>>
>> Ah thanks Paul, for taking out the time to explain some concept. (trying
>> to
>> digest all of them though >_<)
>> Well, interpolation is basically creating more datapoints between the
>> original fixed datapoints right?
>> Linear interpolation ar. I hope i can progress not from linear
>> interpolation
>> as it seems that the results i will be getting should be very poor.
>> But I will have to see how far i will be able to go from linear
>> interpolation. hope to be able to scale some video input from a vcd
>> players.
>> Though i will have to worry about the I/O of the boards and other
>> hardware
>> related issues.
>> Will check out the DSP books that you recommended too! :)
>>
>> "Paul" <pauljbenn...@gmail.com> wrote in message
>>
>> news:1178285538.481886.251680@l77g2000hsb.googlegroups.com...
>>
>>
>>
>> > OK... think time domain signal...  say your signal x = [1 10 5 3] and
>> > you want to upsample this to twice the sampling frequency....  if you
>> > did a simple linear interpolation you'd get x_upsampled = [1 5.5 10
>> > 7.5 5 4 3 ?]  that last datapoint{?} is kinda arbitrary, presumably
>> > you'd just set it to 3.   However, signals are defined as a sum of
>> > sinusoids, and generally they fit that model fairly well - when you
>> > have something that doesn't, it takes more sinusoids to fit it.. thats
>> > the general theory behind a fourier transform, right?  So linear
>> > interpolation isn't really you're best solution.  You can
>> > mathematically prove that if you had an infinitely long signal, and an
>> > infinitely perfect low pass filter, the "perfect" upsampling is done
>> > by inserting zeros  x_zero = [1 0 10 0 5 0 3 0], and low pass
>> > fitlering it.  Obviously, neither the infinite sequence or the perfect
>> > LPF is realistic.  If you do the math (or plug it into matlab), the
>> > FFT of x (shfited to place zero frequency in the center), X=[-7 -4+7j
>> > 19 -4-7j]  If you take the FFT of x_zero, X_ZERO = [19   -4-7j   -7
>> > -4+7j  19   -4-7j   -7   -4+7j]    Note, this is simply X repeated.
>> > So how do you get back your correct frequency spectrum?  An ideal LPF
>> > returns X_UPSAMPLE=[0    0   -7 -4+7j 19 -4-7j   0   0].   Now note
>> > this... if you use matlab and take the inverse FFT of this (the
>> > shifted version of this actually)  you get [1.0000    5.8107
>> > 10.0000    8.6391    5.0000    3.6893    3.0000    0.8609]
>> > Actually... you get this divided by 2  (you need to multiply by your
>> > upsampling facor, that comes out in the math) with a risidual
>> > imaginary part due to the fact that it's an even length sequence, so
>> > you just look at the real part.   Point being however, note that the
>> > interpolated values are NOT what you get using straight linear
>> > interpolation.  this is because this method takes into account the
>> > curvature of the rest of the sequence and stuff.
>>
>> > That being said.... for this project, I would imagine that simple
>> > linear interpolation is plenty adequate!  A 2 dimensional version of
>> > this example above would be quite tricky and take a lot of processing
>> > power.  But read the chapter in your DSP book on upsampling - it will
>> > cover all this :-)  Actually, not positive, but the stock, every
>> > college in the world uses, oppenheim & shaeffer signals & systems book
>> > MIGHT even go into it in one of the later chapters.
>>
>> >> >   How accurate do your interpolations need to be?  Think basic 1-
>> >> > dimensional DSP.. how do you upsample a signal?  insert zeros
>> >> > between
>> >> > samples and LPF, right?  Or do the same thing in the F-domain by
>> >> > zero
>> >> > padding the ends of the FFT and inverse-FFT'ing.  Either of these
>> >> > methods in 2 dimensions is going to be a lot of computation and a
>> >> > lot
>> >> > of taking stuff in and out of memory in different orders.   DDR
>> >> > memories like you to take stuff out in the same order you put them
>> >> > in... they slow down big time when you try to jump around..  So if
>> >> > you
>> >> > do this, you will need to some up with some clever methods of read
>> >> > out
>> >> > pieces from DDR in the incorrect order, and then re-reading from a
>> >> > local, smaller, block ram in the order you actually want.  This will
>> >> > take careful planning and a lot of simulation, even an experienced
>> >> > designer would have a tricky time with this and probably get it
>> >> > wrong
>> >> > in simulation the first shot.
>>
>> >> Woah, ok I'm totally lost in here. But no problem, I will take note of
>> >> these
>> >> points and consult my profs or someone- Hide quoted text -
>>
>> - Show quoted text -
>
>




Article: 119280
Subject: Re: Video scaler for Spartan 3E?
From: Antti <Antti.Lukats@googlemail.com>
Date: 16 May 2007 02:27:07 -0700
Links: << >>  << T >>  << A >>
On 16 Mai, 11:10, "Ken Soon" <c...@xilinx.com> wrote:
> ok... I guess i better start small anyway since I really new to this.
> Well I'm going to take a DSP module in school soon so it will definitely
> help me along.
[]
> Oh by the way, can I ask if that once i kind of burn the chip and little
> smoke came off, is the chip spoilt? The board's power indicators are fine
> and I programmed successfully into the chip through a parallel IV cable but
> nothing was displayed though. No self-test or whatsoever is available
> though...so scared...
>
> "Paul" <pauljbenn...@gmail.com> wrote in message
>
> news:1178889638.696406.114280@h2g2000hsg.googlegroups.com...

yes, smoke is rather bad usually :(

when really visible smoke comes, its usually really some dead things
on board already, possible plastic housing cracked or some trace
burned.
sometimes before smoke comes you can feel with the nose, that
something smells like hot, in that case the damage may be not fatal.
real smoke is usually fatal.

the only hope that the damage is reversible is if there was some PCB
trace burned (and all chips are ok), but the PCB trace burn doesnt
make smoke, only some bad smell and sometimes visible light for short
time. oh well depend on PCB and power supply, I guess PCB tracks can
make smoke also..

as soon as something burns, better take immediate visual and smell
observation, to see what burned, if PCB looks burnt, or if some IC has
plastic cracked on top (reverse volcano where waporized silicium comes
out)..

Antti
http://code.google.com/p/s3astarter/


Article: 119281
Subject: how to delay a signal in virtex FPGA
From: michel.talon@gmail.com
Date: 16 May 2007 03:29:44 -0700
Links: << >>  << T >>  << A >>
Hi all,

I've to delay a signal without using clock. So I want to use
propagation time across logic functions like AND but, when I will
synthetize my design, ISE will symplify and remove all my AND gates..
I also look in the virtex primitives but I don't find any wich reach
my purpose ( only IDELAY, but restrict to input signals ).
So, if anyone have an idea or experience on that..

Thank you by advance,

Best regards,  Michel.


Article: 119282
Subject: Re: how to delay a signal in virtex FPGA
From: Antti <Antti.Lukats@googlemail.com>
Date: 16 May 2007 03:37:45 -0700
Links: << >>  << T >>  << A >>
On 16 Mai, 12:29, michel.ta...@gmail.com wrote:
> Hi all,
>
> I've to delay a signal without using clock. So I want to use
> propagation time across logic functions like AND but, when I will
> synthetize my design, ISE will symplify and remove all my AND gates..
> I also look in the virtex primitives but I don't find any wich reach
> my purpose ( only IDELAY, but restrict to input signals ).
> So, if anyone have an idea or experience on that..
>
> Thank you by advance,
>
> Best regards,  Michel.

you should not do what you are trying todo, but if needed you can
one possibility is to make hard-macros and use them
there are tricks also possible. but as said, those methods should not
be used
as the results are hard to keep constant over implementation runs
(unless full hardmacro and dedicated routing, and even then)

Antti



Article: 119283
Subject: Re: how to delay a signal in virtex FPGA
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 16 May 2007 10:38:22 GMT
Links: << >>  << T >>  << A >>
Michel Talon posted:

"I've to delay a signal without using clock. [..]"

Would something like
intermediary_storage_of_delayed_signal <= original_input_signal;
delayed_output_signal <= intermediary_storage_of_delayed_signal;
be acceptable?

Regards,
Colin Paul Gloster

Article: 119284
Subject: Re: how to delay a signal in virtex FPGA
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Wed, 16 May 2007 12:41:24 +0200
Links: << >>  << T >>  << A >>
Hi,

I think you need to add more information around your question in order to be 
able to give you a better answer.

Delaying something without a clock for a long time (> few ns) is hard since 
you don't have any control whatsoever on the delay time.
If you just want small delays, I would use a long carry-chain since there is 
no routing delay between the carry-elements and you can control the delay 
amount a little by deciding where to tap-off the carry-chain.
Still you have variations on the delay due to temp/volt/process corners.

If you don't care about the delay time (which sounds weird to me), you can 
force placements on primitives by RLOCing them.
You have to instantiate the primitives in your HDL and give the RLOC values.
With VHDL you can create a "for generate loop" which would place an 
arbitrary number of these primitives.
These primitives will not be touched by the synthesize tool or the PAR 
tools.

Göran Bilski

Unless you talking about very long time (> a few ns) which would be very 
hard to do


<michel.talon@gmail.com> wrote in message 
news:1179311384.251800.19730@l77g2000hsb.googlegroups.com...
> Hi all,
>
> I've to delay a signal without using clock. So I want to use
> propagation time across logic functions like AND but, when I will
> synthetize my design, ISE will symplify and remove all my AND gates..
> I also look in the virtex primitives but I don't find any wich reach
> my purpose ( only IDELAY, but restrict to input signals ).
> So, if anyone have an idea or experience on that..
>
> Thank you by advance,
>
> Best regards,  Michel.
> 



Article: 119285
Subject: Unable to scan JTAG chain
From: mohan <kulkarku@math.net>
Date: 16 May 2007 03:57:45 -0700
Links: << >>  << T >>  << A >>
I am using max 7000s series cpld.i am using altera byte blaster cable.
i am getting error as "unable to scan device chain .cann't scan jtag
chain".
what is meaning of this error?
what i need to do,to programme CPLD


Article: 119286
Subject: Re: how to delay a signal in virtex FPGA
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Wed, 16 May 2007 12:04:26 +0100
Links: << >>  << T >>  << A >>
On 16 May 2007 03:29:44 -0700, michel.talon@gmail.com wrote:

>Hi all,
>
>I've to delay a signal without using clock. So I want to use
>propagation time across logic functions like AND but, when I will
>synthetize my design, ISE will symplify and remove all my AND gates..
>I also look in the virtex primitives but I don't find any wich reach
>my purpose ( only IDELAY, but restrict to input signals ).
>So, if anyone have an idea or experience on that..

As Antti has said, this is a thoroughly bad idea.

But if you really, really must.... send the signal out through
a pad, and back in through a different pad (having linked
the two pads together with an external wire, of course).
Choosing the right I/O standard and drive characteristics
gives you a limited amount of control over the delay; and
because it's going out of the part, the optimizer won't 
take anything away.

It's still a rubbish thing to do, though.  How much
delay?  Can you get the desired effect with phase-shifted
clock from a DCM?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 119287
Subject: NIOS2 GNU tools under Windows Vista
From: alessandro.strazzero@gmail.com
Date: 16 May 2007 04:47:17 -0700
Links: << >>  << T >>  << A >>
Anyone have tried to run NIOS2 tools chain (especially gcc) under
Windows Vista ?
If I try I get the "fork_copy" error on some "C" modules.

Any idea ?

Best regards

/Alessandro


Article: 119288
Subject: Re: Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory
From: rmeiche <rmeiche@gmx.de>
Date: 16 May 2007 04:49:39 -0700
Links: << >>  << T >>  << A >>
On 15 Mai, 18:47, Alan Nishioka <a...@nishioka.com> wrote:
> On May 15, 9:16 am, rmeiche <rmei...@gmx.de> wrote:
>
> > I've some problems with reading from my sd-ram. On my FPGA is a Xilinx
> > Virtex 2 XC2V1000 chip and I want to use the ram for greater software-
> > applications. The first problem was, that the fpga has only 2 pins for
> > the SD-RAM DataMask but this was solved with a little glue logic.
>
> You have a big problem.  You need all the data mask pins so you can
> write only certain bytes in a word without changing the other bytes in
> the word.
>
> > If I check the addresses with the debugger then it points out that the
> > software only writes 32Bit or 8Bit NOT 16Bit words.
> > But if I write 8,16 or 32Bit words with the debugger and then read
> > them everything functions very well.
>
> I am guessing the debugger is doing a read-modify-write of the entire
> word.  You could make the hardware also do this, but that would be
> difficult.
>
> You could also write software that only accesses 32 bit words.  I
> think microblaze (You didn't say what processor) only accesses 32 bit
> words.
>
> Alan Nishioka

Thanks for your answer. Perhaps "read-modify-write" could be a
possibillity why the debugger can write and read correctly. I'm going
to check this.
I forgot to mention that if the Stack is executed in the cache, I get
the right output on my terminal. The same happens if the Stack is
executed in RAM and the executable file is Load to the cache.
But if everything is executed in RAM it doesn't function.


Article: 119289
Subject: Re: ise project navigator can't dereference edk pcores from XilinxProcessorIPLib
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 16 May 2007 13:00:37 +0100
Links: << >>  << T >>  << A >>
On Tue, 15 May 2007 19:00:05 +0200, "L. Schreiber" <l.s.rockfan@web.de>
wrote:

>First of all. Thanks for the bus macro advise.
>
>
>The second problem still remains. After creating a system with base 
>system builder wizard from EDK's XPS and generating its netlist(s), I 
>wanted to join the vhdl-files from the hdl-directory to a new ISE 
>project. Unfortunatelly ISE doesn't know anything about the imported 
>library modules that the "system" modules refere to. These library 
>modules can be found inside a subdirectory of the EDK installation 
>directory (.../edk/hw/XilinxProcessorIPLib/pcores).
>
>How can ISE be made known, where it should look up those "mysterious" 
>;-) unknown vhdl-modules?
>
>Can I set something like a PATH variable for such librarys?

"Macro Search Path" under "Translate Properties".
(Right click on "Implement Design" and select "Properties" then the
"Translate" tab, or right click on "Translate" and select Properties.)

- Brian


Article: 119290
Subject: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 16 May 2007 13:07:51 +0100
Links: << >>  << T >>  << A >>
On Tue, 15 May 2007 16:57:50 -0600, Kevin Neilson
<kevin_neilson@removethiscomcast.net> wrote:

>koustav79@gmail.com wrote:
>> Hello,
>> 
>>       I am graduate student in the Dept. of Computer Sc. & Engg. in
>> USF.
>> We are using a Digilent XUP2vpPro board for one of our research
>> projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM
>> to Xilinx virtex 2 Pro FPGA. 
>> 
>You can see what parts are on the DIMM (e.g., Micron, Infineon) and then 
>  figure out what the row size is from that.  You can also get good HDL 
>simulation models from Micron.  They are somewhat slow, but accurate. 
>You instantiate one DRAM model for each DRAM chip on the DIMM.
>-Kevin

Following up to second the recommendation on the Micron datasheets and
models, though they seem to omit VHDL models for some newer devices.
Hynix cover that base though.

If you can't find the info you need from Kingston, why not go to
Micron/Crucial for the DIMM itself? Micron fully specify them, and
Crucial sell them online ... I have seen DIMMs with a Micron label on
one side and a Crucial label on the other...

- Brian

Article: 119291
Subject: Re: how to delay a signal in virtex FPGA
From: michel.talon@gmail.com
Date: 16 May 2007 05:31:53 -0700
Links: << >>  << T >>  << A >>
First, thank for all your answers,
in facts, I'm designing an emulator for an hardware microcontroler. So
I've to embed microcontroler sources ( originaly coded for hardware IC
design ) in my virtex FPGA.
One of the goal of the project is to preserve microcontroleur
functionality and mechanisms ( to obtain a real emulation ), this why
I can't use a clock to delay my signal.
This signal must be delayed by about 50ns. I know this is a large time
without use of clock, and that's all my problem..

best regards, Michel Talon.


Article: 119292
Subject: Re: how to delay a signal in virtex FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 16 May 2007 14:00:33 +0100
Links: << >>  << T >>  << A >>
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:4ool439h6v0sv835pio48qlkd3lggjs398@4ax.com...
>
> As Antti has said, this is a thoroughly bad idea.
>
> But if you really, really must.... send the signal out through
> a pad, and back in through a different pad (having linked
> the two pads together with an external wire, of course).
> Choosing the right I/O standard and drive characteristics
> gives you a limited amount of control over the delay; and
> because it's going out of the part, the optimizer won't
> take anything away.
>
> It's still a rubbish thing to do, though.  How much
> delay?  Can you get the desired effect with phase-shifted
> clock from a DCM?
> -- 
> Jonathan Bromley, Consultant
>
...or, if you don't like wire, you can use an unbonded IOB. Send a signal to 
the IOB's output pin and get the signal back from the same IOB's input pin 
with the IDELAY turned on. No wire required! I would never do this though. 
Ahem!
HTH, Syms.
p.s. You don't _have_to use an unbonded IOB, but it saves worrying about 
what might be connected to it. 



Article: 119293
Subject: Re: how to delay a signal in virtex FPGA
From: michel.talon@gmail.com
Date: 16 May 2007 06:06:05 -0700
Links: << >>  << T >>  << A >>
On 16 mai, 12:04, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On 16 May 2007 03:29:44 -0700, michel.ta...@gmail.com wrote:
>
> >Hi all,
>
> >I've to delay a signal without using clock. So I want to use
> >propagation time across logic functions like AND but, when I will
> >synthetize my design, ISE will symplify and remove all my AND gates..
> >I also look in the virtex primitives but I don't find any wich reach
> >my purpose ( only IDELAY, but restrict to input signals ).
> >So, if anyone have an idea or experience on that..
>
> As Antti has said, this is a thoroughly bad idea.
>
> But if you really, really must.... send the signal out through
> a pad, and back in through a different pad (having linked
> the two pads together with an external wire, of course).
> Choosing the right I/O standard and drive characteristics
> gives you a limited amount of control over the delay; and
> because it's going out of the part, the optimizer won't
> take anything away.
>
> It's still a rubbish thing to do, though.  How much
> delay?  Can you get the desired effect with phase-shifted
> clock from a DCM?
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

First, thank for all your answer,
In fact I'm designing an emulator for an onchip microcontroler. The
goal of the project is to obtain the same mecanisms and functionality
for the emulator to reach a real emulation.
I've to carry microcontroler IC design sources to virtex FPGA without
modify them or just a little.
The signal I've to delay is embedded in one of the lowest hierarchical
module and I can't input a clock to this module.
The signal must be delayed by 20ns minimum, but accuracy is not
required.

I know this is not a good thing for FPGA, but I've not better
solution, and this all my problem..

Thank,

Best regards, Michel Talon.


Article: 119294
Subject: Re: Unable to scan JTAG chain
From: Gabor <gabor@alacron.com>
Date: 16 May 2007 06:11:28 -0700
Links: << >>  << T >>  << A >>
On May 16, 6:57 am, mohan <kulka...@math.net> wrote:
> I am using max 7000s series cpld.i am using altera byte blaster cable.
> i am getting error as "unable to scan device chain .cann't scan jtag
> chain".
> what is meaning of this error?
> what i need to do,to programme CPLD


This message indicates that the byte blaster hardware is unable
to determine the devices in your chain.  The chain is a loop
going from the byte-blaster to TDI of the first device,
through that device to its TDO to TDI of the next device ...
finally back to the byte-blaster from the last TDO.  Usually
the message means there is a mis-connection somewhere
or a device that is missing power.  The mis-connection
may also be in one of the bused signals, TMS, TCK.

I'm not familiar with the byte blaster as I generally work
with Xilinx or Lattice, but there could also be an issue
of power getting to the byte-blaster itself or an issue
with its connection to your computer.  The error
message is not very specific.

HTH
Gabor


Article: 119295
Subject: CML output swing for V5
From: Test01 <cpandya@yahoo.com>
Date: Wed, 16 May 2007 06:28:03 -0700
Links: << >>  << T >>  << A >>
As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential voltage from the Xilinx FPGA?

Test01

Article: 119296
Subject: Re: clock wide pulse transfer b/w clock domains
From: Paul <pauljbennett@gmail.com>
Date: 16 May 2007 07:09:51 -0700
Links: << >>  << T >>  << A >>
General rule of thumb is that you want 2 registers to cross between
clock domains, follow that rule to deal with any metastability
issues.  Now you just have the problem that your first clock domain is
faster and you might not catch it with the slower domain.

Personally, my approach here would be to "hold" the signal in your
CLK_FAST with an enabled register until you receive some sort of feed
back that you've grabbed it in CLK_SLOW, bearing in mind that those
feedback / feedforward signals should all be double registered to
prevent metastability.  Also keep in mind that an enabled register
does NOT count as one of your two "synchronization" registers, because
an enabled register is actually implemented as a register with a mux
in front of it - only direct D-to-Q connections with NO combinational
logic count for clock domain crossing issues.  Now, depending upon the
timing of it all, this could end you up with more than 1 clock pulse
width.  Assuming that you know your input pulses are spaced far enough
apart that you KNOW it's not ACTUALLY multiple pulses, then a simple
edge detect will fix this problem for ya.

The ideal behind the metastability stuff is that if you clock a signal
exactly at the transisition the output of the flop has some
probability of floating somewhere between 0 and 1 for some amount of
time.  Adding any combinatorial logic extends that amount of time.
The idea of having 2 registers is that you reduce your probability of
a metastable event because even if you hit that .01% chance of it
remaining metastable for long enough to create a problem at the first
register, you got another .01% on your side at the second register.
(Note: .01% is much higher than it really is.. but remember, if you're
clocking signals in the MHz range, those tiny probabilities add up
REAL quick!)

On May 16, 1:35 am, himassk <hima...@gmail.com> wrote:
> Hi,
>
> Please suggest me how to transfer a single clockwide pulse from high
> frequency clock domain and create a single clockwide pulse in a slow
> clock domain?
> What are different methods available?
>
> Thanks in advance.
>
> Regards,
> Himassk.



Article: 119297
Subject: Re: Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory
From: rmeiche <rmeiche@gmx.de>
Date: 16 May 2007 07:42:07 -0700
Links: << >>  << T >>  << A >>
I've checked if the debugger makes a read-modify-write. The debugger
doesn't make this because first we had a failure
in our glue logic. At that time we had only the possibillity to write
32Bit words and we tried a 8Bit write via the debugger
and that didn't function.


Article: 119298
Subject: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
From: "mahalingamv@gmail.com" <mahalingamv@gmail.com>
Date: 16 May 2007 07:52:16 -0700
Links: << >>  << T >>  << A >>
Hi all,

As I can see most of you are suggesting the use of EDK for memory DDR
access.

But Is there any way to combine some hardware coded in VHDL  from ISE
and memory controller using EDK

so these two work together to acheive the desired functionality.

its like edk memory controller reads data from ddr and gives it to the
FPGA
and fpga processes the information and produces the result.

thanks for your reply.

Mahalingam


Article: 119299
Subject: Mutiple MAC on OPB Bus
From: Venu <get2venu@gmail.com>
Date: 16 May 2007 08:08:55 -0700
Links: << >>  << T >>  << A >>
Hi,

Is there any constraint regarding the number of Ethernet MAC that you
can place on the OPB Bus? I have attempting to put 2 MACs on the Bus,
but as soon as a instantiate the second MAC and attempt to generate
bitstream, I get the following error: address space overlap! This
error is generated by PlatGen

I am certain address overlap that this is not the problem , because I
have gone through the entire address map of my system. No two
peripherals are assigned the same address space.

When I had only a single MAC in the system , with address 40c0_0000 to
40c0_ffff , things were working perfectly . But as soon as instantiate
the second MAC with address 42c0_0000 to 42c0_ffff, this problem
creeps up.

The PLB2OPB Bridge is from 0x00000000 to 0x7FFFFFFF, so that entire
range can be used by peripherals on the OPB Bus.


Thanks
Venu




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