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On May 28, 10:26 am, "Silver" <K.Pisan...@gmail.com> wrote: > Hi everyone, > > I tried to figure this one out myself but it turns out not so easy for > someone with this lack of experience like mine. I'm writing a PC app that > will issue JTAG commands over paralell port to some unspecific FPGA at the > moment, running let's say some cipher algorithm. I want to use my app to set > input levels with JTAG and observe how it changes output signals. In order > to impose signal levels over JTAG with my application I have to somehow > "halt" the main FPGA clock if I want to do it in an exact moment and here's > my question: is the FPGA clock stopped when TAP controller is in some > specific state, concerning JTAG BSR operations or do I have to do it myself There is no JTAG state that stops the FPGA clock (and since an FPGA is programmable there is no way for JTAG to know what a clock is) JTAG was designed to run independently of the operation of the chip. Some processors use it for in system debug. Using JTAG boundary scan, you can control any input pin (including clock) and read any output pin. This would work in non-realtime (very limited by how fast you can run JTAG). If you want to run faster, perhaps you should set up some protocol between the FPGA and your PC. Alan NishiokaArticle: 119951
On May 29, 2:32 pm, "Silver" <K.Pisan...@gmail.com> wrote: > Let me rephrase the question: assuming that TAP controller is in some other > state than TEST_LOGIC/RESET is it right that whole FPGA is now clocked with > TCK clock instead of system main clock? No. JTAG is designed to be non-intrusive unless you tell it to intrude. Alan Nishioka alan@nishioka.comArticle: 119952
Hi all, Can anyone suggest simple algorithms for implementation of finding the inverse of a matrix (4 X 4)? Even information of IP Cores for such functionality will be greatly appreciated. Thanks in advance, Venkat.Article: 119953
I am reading Cyclone II device handbook. A concept, register packing, confuses me. I know if we use the LUT and register in a Logic Element to implement unrelated function we call that is a register packing; but if we use the output of LUT as the input of the register, i mean a function is implemented by both the LUT and the register, is that called register packing? If we only use the register in a LE, is that called register packing? Also, in the databook it is said that register packing and synchronous load(Does the load signal just like a preset signal? )cannot be used simultaneously, why? thanks leonArticle: 119954
On May 29, 6:49 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Pablo Bleyer Kocik wrote: > > >>http://www.latticesemi.com/Mico8 > > >>-jg > > > Jim, the link is broken. > > Oops, try > > http://www.latticesemi.com/mico8 > > On the page that jumps to, they tabulate > > Device LUTs Registers SLICEs f MAX (MHz) > > I thought a similar simple summary would be good for your core, too? LOL. It never occurred to me to change the uppercase M to a lowercase. ;-) The implementation depends very much on the device and post-route tweaking, but for Xilinx devices I get ~200 slices and speeds around 100MHz for PB3. Regards.Article: 119955
On 29 Mai, 16:32, greywol...@hotmail.it wrote: > On 29 Mag, 14:14, Newman <newman5...@yahoo.com> wrote: > > > > > On May 29, 9:17 am, greywol...@hotmail.it wrote: > > > > Hi, > > > > I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, > > > somebody can help me? > > > > Thanks. > > > link to a Virtex II Pro articlehttp://www.xilinx.com/publications/xcellonline/xcell_48/xc_linux48.htm > > > Your question is too general. Are you thinking about running linux on > > a PPC in a Virtex4 FX part. You will need to configure and adapt a > > kernel (OS). > > > -Newman > > I'm working with a board MPC8548CDS-like (PowerPC). Connected to > processor local bus and with pci express there is a Virtex 4 > (xc4vfx60). > > -Marco I suggest that you configure the FPGA to do something that has exising drivers in the kernel. The simplest to implement would be /dev/nil. If you have a PCIe core for the FPGA a parallel port or timer should also be simple to do. If you are a little more ambitious you could implement a frame buffer graphics card. In all these cases you can use existing drivers without modification. Kolja SulimmaArticle: 119956
On 2007-05-30, moogyd@yahoo.co.uk <moogyd@yahoo.co.uk> wrote: > On 25 May, 14:19, Andreas Ehliar <ehl...@lysator.liu.se> wrote: >> You might also be able to improve your results by varying your timing >> constraints slightly instead of using a separate cost table. (I've recently >> played with a design which would meet timing with a cycle time constraint >> of 4.8 ns, fail at 4.9 ns and succeed again at 5.0 ns. ) >> > > This is certainly something I do with ASIC synthesis tools (synopsys). > It was quite easy using the TCL command interface, which I don't think > is available using ISE (please correct eme if I am wrong). There actually is a TCL command interface available in the current ISE version. (I think it was added in ISE 8.2.) Some documentation is available in the $XILINX/doc/usenglish/books/docs/dev/dev.pdf file of your ISE installation. You can either use the TCL prompt in Project Navigator or use xtclsh directly it seems. Is your experience regarding timing constraints for ASIC synthesis/backend tools the same as mine in regards to FPGA synthesis/backend tools? > One of the problems I am finding with the (admittedly free) Xilinx > tools is poor command line and scripting capabilities. Real engineers > don't use GUI's ;-) I actually don't find the Xilinx command line tools that limiting if you have a decent framework to use. If you are interested I have a Makefile based flow for synthesizing an FPGA design available for download on my homepage which could serve as inspiration. Look for the PPC405 based design on http://www.da.isy.liu.se/~ehliar/stuff/ (No EDK is needed for this design.) /AndreasArticle: 119957
Hello Leon, Register packing refers to the use of the LUT and FF in a Logic Element (LE) at the same time. There are four ways this can happen in Cyclone II FPGAs (and Cyclone, Cyclone III, and Stratix device architectures). Refer to Figure 2-2 in the handbook (http:// www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf). 1. The simplest example is a LUT whose output feeds a register -- you can place the register in the same LE, absorbing the connection. 2. The next, which the data book defines as register packing, is the use of a LUT and a register for independent functions. This means using up to a 3-input LUT function plus an independent FF. Or if you happen to have a 4-LUT that shares an input with a FF, you could pack those together. The downside of these packings is that the software must be careful in what it chooses to pack -- taking two things that don't have anything in common and forcing them into the same spot in the chip could result in bad performance. 3. A FF that drives a LUT. Notice the FF can directly drive the third input of the LUT. So the software can choose to pack a FF with its fanout instead of its fanin. 4. If you have FFs in a register chain, this is a special version of (2). The FF can receive its input directly from the FF above it, and meanwhile the 4-LUT can be used for something else. This architectural flexibility requires smart software (Quartus II) to work well. There are register packing options that allow you to control how aggressively the tool tries to pack logic with registers -- but usually you don't have to. The default Auto mode tells the software to pack as much as it thinks it needs to. This means that usually, it will perform packings of logic & registers that want to be together (cases 1 and 3), and might happen to use cases 2 & 4 opportunistically. However, if Quartus notices that you're running out of LEs, it will start doing more of the type 2 and 4 packings. One consequence of this is that your "push-button" LE count doesn't reflect the minimum # of LEs your design can take. A somewhat out-of-date explanation of the architecture & results can be found in a CICC paper I wrote (http://www.altera.com/literature/cp/ cyclone-lc-hp-fpga-423.pdf). Since then, the wizs in the Fitter team have signficantly improved Quartus II's ability to pack registers without impacting design performance. To answer your second question, look again at Figure 2-2. The FF data input comes from a bunch of goo -- but if you are using the "packed register" mode as defined in the databook (my #2 above), you can see that you bypass the synchronous load logic. So a register that uses a synchronous load cannot be packed with an independent LUT. Regards, Paul Leventis Altera Corp.Article: 119958
Thanks for that Eric ! Anyone know if there is a list of what Xilinx chips work with what versions of ISE ? I am becoming more and more frustrated with www.xilinx.com , now I find myself using google and site search to find things I need. Anyway, I would like to find out if I can use the LX50T with the free 9.1 version or the 8.x version. Also downloading a package of 1.5GB and the same size again for an update it pretty annoying ! Thanks ! claireArticle: 119959
On 25 May, 14:19, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-05-25, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > > Consider a shell script which launches PARs one at a time ( for bonus > > points, n at a time on a multi-core machine!), each with a separate cost > > table entry (-t nn). > > You might also be able to improve your results by varying your timing > constraints slightly instead of using a separate cost table. (I've recently > played with a design which would meet timing with a cycle time constraint > of 4.8 ns, fail at 4.9 ns and succeed again at 5.0 ns. ) > > /Andreas This is certainly something I do with ASIC synthesis tools (synopsys). It was quite easy using the TCL command interface, which I don't think is available using ISE (please correct eme if I am wrong). One of the problems I am finding with the (admittedly free) Xilinx tools is poor command line and scripting capabilities. Real engineers don't use GUI's ;-)Article: 119960
On 25 May, 15:05, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On 24 May 2007 04:35:28 -0700, moo...@yahoo.co.uk wrote: > > >Hi, > > >I was hoping that someone could point me at a useful document or other > >link. > >Our FPGA build flow is currently scripted for a single iteration P&R. > >Unfortunately, we are now starting to get some hold violations. > >If I run a multipass P&R, approximately 50% of the iterations will > >yeild successful timing (Timing Score = 0). > > >Ideally, what I want is a method of saying : Iterate until timing met, > >with a maximum of n > > MPPR may not be the best idea here; > (a) because you have to "kill" it when done, and handle the resulting > file renamings yourself, and > (b) because when a PAR aborts with the famous "portability errors", it > also kills MPPR instead of starting the next pass at PAR. So you find > out next morning, MPPR stopped about ten minutes after you left the > office. Unless PAR has become 100% reliable since 7.1... > > Consider a shell script which launches PARs one at a time ( for bonus > points, n at a time on a multi-core machine!), each with a separate cost > table entry (-t nn). > > The script will have to look at each .PAR file (once the PAR has > completed) and search for "all constraints were met" or the appropriate > phase. > > - Brian Brian, Gabor Thanks for pointing me in this direction. I will update my scripts to use a manual multi-pass P&R approach. It definitely provides a more flexible and (hopefully) controllable route. Thanks for all the help. StevenArticle: 119961
On May 25, 12:20 pm, Pablo <pbantu...@gmail.com> wrote: > I have a SMT338 board. This is a FPGA module and now I want to add a > DDR SDRAM to my system. I have the ucf file provided by the company > but in this file I don't find ddr_feedback clock. What it means?. I > suppose that this pin is neccesary, but there is no pin called > "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" > y "ckn" but these signals are used by the fpga to the ddr. > > Has anyone the solution?. > > Regards The extra pin is used for DCM feedback which compensates logic delay. It is connected to the same DDR in as clk. For more info about clocking variations see the OPB_DDR (or PLB_DDR) datasheet. Cheers, guruArticle: 119962
On May 30, 12:29 am, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi Dave, > > Dave wrote: > > I bought an SZ010 board for use in a PVR project, thinking the EDK/Linux > > design would provide a fast development route. In the end this proved > > impractical, simply because uCLinux running on a Microblaze (which maxes out > > at about 52MHz in this case) doesn't provide good enough network > > performance - from memory, an ftp test was clocking in at around 3 mbits/s. > > The Suzaku's interface to the off-chip MAC-PHY has no DMA capability, > which goes a long way to explaining the poor ethernet throughput you > describe. With the Xilinx EMAC, and DMA, checksum offload and all bells > and whistles we've hit 50mbit/sec with MicroBlaze / uClinux systems in > netperf tests. > > Just to put the record straight... > > Regards, > > John Hi John, That is a very good performance! Is it possible that you publish the design on the web to avoid building from a scratch? cheers, GuruArticle: 119963
On 30 Mai, 11:11, "Claire Murphy" <clairemurphs...@hotmail.com> wrote: > Thanks for that Eric ! > > Anyone know if there is a list of what Xilinx chips work with what versions of ISE ? I am becoming more and more frustrated withwww.xilinx.com, now I find myself using google and site search to find things I need. > > Anyway, I would like to find out if I can use the LX50T with the free 9.1 version or the 8.x version. > > Also downloading a package of 1.5GB and the same size again for an update it pretty annoying ! > > Thanks ! claire no you can not use free tools. so your initial investment to use ML505 is 3200 USD (ISE+ED) AnttiArticle: 119964
On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote: > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > maverick schrieb:> Hi there, > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me > > > from using ChipScope pro on this board to debug my design. Is it > > > possible somehow to tap the jtag ports internally and route them to > > > GPIOs which are available on th board! In that case, I will insert the > > > ChipScope Pro core in my design in the normal fashion and will put > > > that part of the code in the design that will tap the JTAG ports > > > internally and will map them to other GPIOs? > > > > Farhan > > > sure, get it here: > > >http://code.google.com/p/fpga-tools/downloads/list > > > Antti > > Hi Antti, > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd > file. Unfortunately, I am a Verilog writer and do not have much > exposure to VHDL code. What I have understood from the code is, I have > to instantiate this primitive into my design and map the IO to FPGA > IOs. It will make my life easy if you can demonstrate it by making > required changes in the following simple counter code as it is not > clear to me how would I make the chipscope logic communicate to this > primitive. In the following code, assume that I have to monitor 8-bit > counter reg in chipscope pro. > just use the VHDL in your verilog design should be no issue all modern synthesis tools support mixed language designs. AnttiArticle: 119965
Thanks for the tip Antti. I thought the webpack works with some Virtex5's <http://www.xilinx.com/ise/logic_design_prod/webpack.htm> So I guess I am out of luck, and I will need to shell out a few more $$'s Antti you have been a great help !Article: 119966
For my design I must use two DCMs in series. How do I best use the CLKIN, RST, CLKFX and the LOCKED pin of the DCM? Should i AND togheter the CLKFX and LOCKED before connecting it to the CLKIN of the following DCM? I read that the CLKFX can give glitches, spikes, or other spurious movement when LOCKED is low. How should I do to avoid these entering the rest of my design that are clocked from the second DCM?Article: 119967
"Tool" <tool@tim.com> wrote in message news:465d637f$0$90272$14726298@news.sunsite.dk... > For my design I must use two DCMs in series. How do I best use the CLKIN, > RST, CLKFX and the LOCKED pin of the DCM? > > Should i AND togheter the CLKFX and LOCKED before connecting it to the > CLKIN of the following DCM? > > I read that the CLKFX can give glitches, spikes, or other spurious > movement when LOCKED is low. How should I do to avoid these entering the > rest of my design that are clocked from the second DCM? > > Tool, Connect the LOCKED signal from the first DCM to the reset of the next DCM via an inverter. HTH, Syms.Article: 119968
"Symon" <symon_brewer@hotmail.com> wrote in message news:f3jpjn$ots$1@aioe.org... > "Tool" <tool@tim.com> wrote in message > news:465d637f$0$90272$14726298@news.sunsite.dk... >> For my design I must use two DCMs in series. How do I best use the CLKIN, >> RST, CLKFX and the LOCKED pin of the DCM? >> >> Should i AND togheter the CLKFX and LOCKED before connecting it to the >> CLKIN of the following DCM? >> >> I read that the CLKFX can give glitches, spikes, or other spurious >> movement when LOCKED is low. How should I do to avoid these entering the >> rest of my design that are clocked from the second DCM? >> >> > Tool, > Connect the LOCKED signal from the first DCM to the reset of the next DCM > via an inverter. > HTH, Syms. BTW, I'm not sure that cascading DCMs, especially when you're using the CLKFX output of the first DCM, is such a bright idea. Try searching the CAF archive for more info. Include 'jitter' in your keywords. If you post your specific application, someone clever/experienced will probably suggest an alternative that'll save you from a world of hurt. Syms.Article: 119969
On May 30, 8:10 am, "Symon" <symon_bre...@hotmail.com> wrote: > "Tool" <t...@tim.com> wrote in message > > news:465d637f$0$90272$14726298@news.sunsite.dk...> For my design I must use two DCMs in series. How do I best use the CLKIN, > > RST, CLKFX and the LOCKED pin of the DCM? > > > Should i AND togheter the CLKFX and LOCKED before connecting it to the > > CLKIN of the following DCM? > > > I read that the CLKFX can give glitches, spikes, or other spurious > > movement when LOCKED is low. How should I do to avoid these entering the > > rest of my design that are clocked from the second DCM? > > Tool, > Connect the LOCKED signal from the first DCM to the reset of the next DCM > via an inverter. > HTH, Syms. Don't worry about glitches, spikes, etc. while the DCM reset is asserted. No need to add an AND gate to the clock. In fact gating the clock is really bad practice in an FPGA in general. The only reasonable clock gating scheme in the Spartan 3 series is to use the BUFGMUX as a clock multiplexer. Even so, I'd be very careful when connecting DCM's in series. Why do you need to do it? Is it just to get the right frequency or are you expecting some phase relationship to the external clock signal at the output of the second DCM? Remember that DCM's, even the CLKFX portion, are not really phase-locked loops. Jitter will only add as you go through the system. More layers give more jitter and less jitter tolerance. Just my 2 cents, GaborArticle: 119970
What about an async reset coming to the process generating the read addresses? I guess this might also violate setup/hold on w.r.t. the BRAM, corrupting memory contents, or did I get this wrong ? /PontusArticle: 119971
On May 29, 8:10 pm, jon...@gmail.com wrote: > I recently built a prototype using a xilinx spartan-iie specifically > the xc2s150e-fgg456 which is programmed with an xcf02s prom. I have > the prom connected first in the jtag chain. I am unable to detect the > fpga. If i "tap" the tdo of the prom i can detect and program it fine, > but the tdo of the fpga is always floating. I found an error in my > design where the program pin, which is connected to the cf pin on the > prom, is pulled high with a 4k7 resistor. I have tried pulling it low > to no avail. The Program pin is active low, so pulling it high is the right thing to do. > I am able to access the tdo solderball from the side, so > i know it is not a bad connection. Also, while programming the prom, > the fpga seems to randomly pull outputs high/low about once every > second. I'm not sure how this is possible, but it would indicate to me > that the data stream is able to cause a reset of the chip. Does anyone > know how i can get further information on the problem, or have any > ideas what the problem could be? Thanks in advance for any help. Make sure you have all of the JTAG connections to the FPGA. A bad TMS connection for instance could cause the FPGA to enter a boudary scan test mode rather than program mode. This could also explain why you can't initialize the chain with the FPGA in place. Also check all of the power supplies to the FPGA. You need core power and also Vcco for the appropriate banks. Look at the data sheet to see which supply runs the TDO pin. And double check the PROG_B pin connection to be sure it is on the CF output of the prom. Make sure the mode pins of the FPGA are set for master serial or JTAG mode (master serial if you want it to boot up from the PROM, JTAG mode really just disables other modes so you can debug the JTAG problem easier). HTH, GaborArticle: 119972
On 30 May, 10:49, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-05-30, moo...@yahoo.co.uk <moo...@yahoo.co.uk> wrote: > > > On 25 May, 14:19, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > SNIP > Is your experience regarding timing constraints for ASIC > synthesis/backend tools the same as mine in regards to FPGA > synthesis/backend tools? > > > /Andreas Hi Andreas, Thanks for the links - I'll have a look at it. As for the ASIC synthesis tools,. my primary experience is with synopsys dc_shell, and varying the timing constraints slightly definitely improves the overall QOR. Unfortunately it's a bit of a black-art. e.g. If you missed timing by 5%, and then tightened the constraints by 5%, you would miss timing by 5% of the new constraints, so are meeting your original contraints. StevenArticle: 119973
Peter wrote: > > Brian, there is a perfect cure: disable the clock. > Using a BUFGCE, instead of the BRAM enable input, would help startup any BRAMs with buried-in-IP enables. But real world clocking systems that monitor DCM status, or perform automatic clock failovers, CAN NOT USE ENABLE (OR AN ENABLED CLOCK) TO PROTECT BLOCK ROM CONTENTS!!! Unless, of course, you have mastered the obscure art of Psychic Hardware Design, and can design clock enable logic that knows ahead of time when the DCM will unlock, the DRO suffer a phase hit, or the clock recovery PLL hiccup :) BrianArticle: 119974
On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote: > > > > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > maverick schrieb:> Hi there, > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me > > > > from using ChipScope pro on this board to debug my design. Is it > > > > possible somehow to tap the jtag ports internally and route them to > > > > GPIOs which are available on th board! In that case, I will insert the > > > > ChipScope Pro core in my design in the normal fashion and will put > > > > that part of the code in the design that will tap the JTAG ports > > > > internally and will map them to other GPIOs? > > > > > Farhan > > > > sure, get it here: > > > >http://code.google.com/p/fpga-tools/downloads/list > > > > Antti > > > Hi Antti, > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd > > file. Unfortunately, I am a Verilog writer and do not have much > > exposure to VHDL code. What I have understood from the code is, I have > > to instantiate this primitive into my design and map the IO to FPGA > > IOs. It will make my life easy if you can demonstrate it by making > > required changes in the following simple counter code as it is not > > clear to me how would I make the chipscope logic communicate to this > > primitive. In the following code, assume that I have to monitor 8-bit > > counter reg in chipscope pro. > > just use the VHDL in your verilog design should be no issue > all modern synthesis tools support mixed language designs. > > Antti- Hide quoted text - > > - Show quoted text - Thanks Antti for the reply, Yes, I am aware of the feature of mixed language synthesis. But here, I am more interested to know how to use these soft BSCAN primitives in the case where I need to use Chip SCope pro as well. Kindly modify the sample program I posted earlier to show the changes required to incorporate BSCAN primitive to use chip scope pro using GPIOs. Thanks
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