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Hi Ben, I tried what you suggested and it didnt seem to do the trick. Any other suggestions? On Jul 16, 12:48 am, Ben Twijnstra <ben.twijns...@gmail.com> wrote: > Kiran wrote: > > Hi All, > > I am new to Quartus II, and am trying to run a functional > > simulation. I am using the "Vector Waveform Editor" and put in input > > nodes and some of the output nodes that I want to see. However, when > > I run the functional simulation, I do not see the waveforms for some > > of the input/output nodes. The warnings say: "Can't find node <X> for > > functional simulation. Ignored vector source file node." The warning > > for the inputs is: "Can't find signal in vector source file for input > > pin <X>." > > > How do I fix this error? Thanks in advance. > > Hi Kiran, > > This warning occurs when after synthesis, the node you intend to see is > buried inside a logic element or is optimized away completely. > > The best thing to do is to go to the Assignment Organizer (Ctrl+Shift+A) and > do the following: > > In the "To" field, add the name of the node that disappeared in the > simulation. In the "Assignment Name" field, choose the "Implement as output > of logic cell", and in the "Value" field, choose "On". > > Do this for all the nodes that disappeared (buses and wildcards are OK when > entering the assignment) an you should be OK. > > PS: Have a look athttp://www.niosforum.com/forum- It's a specialized forum > for Altera users, and lots of people from Altera themselves are posting > answers and suggestions there. > > Best regards, > > BenArticle: 122201
devices wrote: > "John_H" <newsgroup@johnhandwork.com> wrote in message > news:13a9hnjl693afc@corp.supernews.com... > > >>>>>>>>>As for the I2C Master, assuming no clock stretching >>>>>>>>>is issued by the Slave, > > >>This is a bad assumption. The common situations that include delays must >>have the SCL clock stretching from the slave. Without that clock >>stretching, there's no idea when b1 or b2 start. The SCL holdoff is >>explicitly to allow for slave latency. > > > For the sake of generality, the clock stretching not only applies > to a byte level, it also applies to a bit level. Fortunately common > situations are not general situations or it would mean that every > i2c slave device would be always slower with respect to its > specifications. So i can always take into account the latency as > a preliminary step. But what i was investigating on was the possibility > of the master to introduce a delay. Clock stretching is a means whereby a Slave tells the master to 'pause' - it has no real meaning in a Master context. To any slave, it is just a wider SCL pulse, and slaves only have a min time spec [unless you also have lock-out watchdogs, but they are rare] Even Slave Clock stretching is rare. It is in the spec, but not often used. i2c speeds are very slow by modern silicon standards, so slow-down-more is not often a problem ! Serial EE proms, have chosen a polling system for their 'wait' requirements. -jgArticle: 122202
Kiran wrote:
> Hi Ben, I tried what you suggested and it didnt seem to do the trick.
> Any other suggestions?
Use the ModelSim-Altera Web Edition simulator instead:
http://www.altera.com/products/software/products/model/eda-ms.html
-- Mike Treseler
Article: 122203svenand a écrit : > I am using the Xilinx ML403 board. It is not cheap but it has > everything on board. I am > writing a tutorial on how to use this board to implement my own > design. Read more here: > http://www.fpgafromscratch.com > > Sven > > Thnx Sven, It looks very interesting !!Article: 122204
Hi Aziz, Aziz wrote: > I have been trying to write a watchdog interrupt handler and have not > been successful in coming up with a working code. I would like to use > watch-dog timer on OPB bus of microblaze system to count the number of > clock cycle each phase of your software code takes. Unless you need clock cycle accuracy, you might be better off doing software intrusive code profiling as supported by the MicroBlaze and GCC / gprof tools. Search the Platform Studio online help for "profile" to see how it's done - pretty easy. I used this just recently to resolve a performance issue in some standalone code - interpreting gprof output takes a little practise but isn't hard - it's starndard stuff so lots of web resources. Regards, John From pcw@freeby.mesanet.com Mon Jul 23 15:52:41 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.megapath.net!news.megapath.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 23 Jul 2007 17:52:40 -0500 From: "Peter C. Wallace" <pcw@freeby.mesanet.com> Subject: Bizarre Xilinx configuration problem Date: Mon, 23 Jul 2007 15:52:41 -0700 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.07.23.22.52.40.47835@freeby.mesanet.com> Newsgroups: comp.arch.fpga MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 30 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.80.14.42 X-Trace: sv3-yj3iC9mzWvW5QubIyyxJFUhoatg6JpHjWivT50VEqisFPPu6v0CebcfRWt0h65zBDoZ2pBKrT74C0zq!sLVoyar5MU99VTJgwJJKDmDAV75xv0DDMztCNWvBg6Wq8tReqgjZ66XtZK9T0ew0Goj7En2dQomo!ScQEc+z0NDp0zx7c X-Complaints-To: abuse@megapath.net X-DMCA-Complaints-To: abuse@megapath.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.35 Xref: prodigy.net comp.arch.fpga:134083 Bringing up a new FPGA board I have encountered a very bizarre problem: If I enable a specific pin as an output, the FPGA fails to configure. This pin can be grounded, tied high, or used as an input without problem so its not the state of the pin that matters, but how it is connected inside the FPGA. Just making it an output (even if tristated and never enabled) will make configuration fail. Details: Part is Spartan3 XC3S400-TQ144 Pin that cannot be an output is pin 12 Two cards/FPGA chips have identical problem Parallel config method FPGA configuration fails with /INIT and DONE low - as if a CRC error occured If I assign the output that would go to pin 12 elsewhere, there is no problem and everything else works, including all the other pins in the same I/O bank as pin 12. Has anyone ever seen anything like this? -- pulling out what left of my hair trying to see how this could happen... Peter WallaceArticle: 122205
"MM" <mbmsv@yahoo.com> wrote in message news:5gk5bbF3ed1jcU1@mid.individual.net... > "cpope" <cepope@nc.rr.com> wrote in message > news:46a4a3e7$0$31280$4c368faf@roadrunner.com... > > > > Does anyone have a working two channel fir example with testbench that I > > can > > use as a reference? Any ideas on why the channels would be misaligned? > > I don't have an answer for you, but I did a 2-channel interpolating FIR > using the FIR Compiler and it worked fine. At the moment I am implementing > both 8-channel decimation and 8-channel interpolation filter, but again > using the compiler. I believe the compiler has less bugs than the MAC FIR... > > > /Mikhail > > > Thanks for the suggestion. I switched to fir compiler and I got the same result though. Was interesting that output actually appears to be registered now. (It only changes with the rdy line where before it changed many times even though I had 'register output' selected both times.) Is there a restriction on filter length? I am using 65 taps symmetric. Maybe the odd length is causing a problem with the decimate by 2 structure? Thanks, ClarkArticle: 122206
Hi: I have used Icarus Verilog 0.8.4 on Suse Linux 9.1 to create a .vcd file from a testbench. The .vcd file is shown below. I also installed GtkWave 3.0.29 and used the command: > gtkwave dual-fps.vcd to attempt to display the waveforms from my .vcd file. GtkWave opens with a nice window and a time axis, but no waveforms. It has a text box which states: VCD loaded successfully. [12] facilities found. Regions formed on demand. And another graphic box which is labeled "signals" which shows "time" but not any of the other signals. Is there something wrong with my .vcd file, or Gtkwave? Perhaps if someone can make the .vcd file display in their viewer, or alternately send me a .vcd file they know works in GtkWave, I can figure out which end the problem is on. Thanks. ----------------------------------- dual-fps.vcd: $date Mon Jul 23 15:30:30 2007 $end $version Icarus Verilog $end $timescale 1s $end $scope module test $end $var wire 1 ! fps1 $end $var wire 1 " fps2 $end $var wire 1 # mod1 $end $var wire 1 $ mod2 $end $var reg 1 % tim $end $var reg 1 & trig $end $scope module DFM1 $end $var wire 1 $ Mod2 $end $var wire 1 % Timer $end $var wire 1 & Trig $end $var reg 1 ! FPS1 $end $var reg 1 " FPS2 $end $var reg 1 # Mod1 $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars 0& 0% 1$ 0# 0" 0! $end #5 1! 1& #6 1% #10 0& #15 1" 0! 1& #20 0& #25 0$ 1# 0" 1& #30 0& #35 1$ 0# 1& #40 0& #45 0$ 1# 1& #50 0& #55 1$ 0# 1& #60 0& #65 0$ 1# 1& #70 0& #80 0% #85 1" 1& #86 1% #90 0& #95 1! 0" 1& #100 0& #105 1$ 0# 0! 1& #110 0& #115 0$ 1# 1& #120 0& #125 1$ 0# 1& #130 0& #135 0$ 1# 1& #140 0& #145 1$ 0# 1& #150 0& #165 0$ 1# 1& #170 0& -- Good day! ________________________________________ Christopher R. Carlen Principal Laser&Electronics Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 122207
Peter, Have you checked that this pin is not a dual use pin (also used for configuration)? Austin From pcw@freeby.mesanet.com Mon Jul 23 17:30:01 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.megapath.net!news.megapath.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 23 Jul 2007 19:30:01 -0500 From: "Peter C. Wallace" <pcw@freeby.mesanet.com> Subject: Re: Bizarre Xilinx configuration problem -- oops never mind Date: Mon, 23 Jul 2007 17:30:01 -0700 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.07.24.00.30.00.988277@freeby.mesanet.com> Newsgroups: comp.arch.fpga References: <pan.2007.07.23.22.52.40.47835@freeby.mesanet.com> <f83fgr$od52@cnn.xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 19 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.80.14.42 X-Trace: sv3-FcR2rGWuHsFO8sb8BJs0Qo8x6odXH+BslE42r5L6VL7gL5V/1aki6Ew2UixBP8b1+evT87di2SWQ49q!iKMREs9wY6JY57N/mPZI0HBadxGbLFlCQYtao70X8xn4X/Eup2HoQbGEU7vh+azM/wYSibvX8v72!/kefMgFLRiameg7O1w== X-Complaints-To: abuse@megapath.net X-DMCA-Complaints-To: abuse@megapath.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.35 Xref: prodigy.net comp.arch.fpga:134087 On Mon, 23 Jul 2007 17:01:49 -0700, austin wrote: > Peter, > > Have you checked that this pin is not a dual use pin (also used for > configuration)? > > Austin No, its just a regular pin (which is why we were so confused that it mattered), BUT Looks like its a problem with our USB configurator, We hacked our configurator CPLD so we could configure via a parallel port and that works fine. Must be we are corrupting the last few bytes of configuration data somehow. Sorry for the trouble. Peter WallaceArticle: 122208
"cpope" <cepope@nc.rr.com> wrote in message news:46a534bf$0$29665$4c368faf@roadrunner.com... > > "MM" <mbmsv@yahoo.com> wrote in message > news:5gk5bbF3ed1jcU1@mid.individual.net... > > "cpope" <cepope@nc.rr.com> wrote in message > > news:46a4a3e7$0$31280$4c368faf@roadrunner.com... > > > > > > Does anyone have a working two channel fir example with testbench that I > > > can > > > use as a reference? Any ideas on why the channels would be misaligned? > > > > I don't have an answer for you, but I did a 2-channel interpolating FIR > > using the FIR Compiler and it worked fine. At the moment I am implementing > > both 8-channel decimation and 8-channel interpolation filter, but again > > using the compiler. I believe the compiler has less bugs than the MAC > FIR... > > > > > > /Mikhail > > > > > > > > Thanks for the suggestion. I switched to fir compiler and I got the same > result though. Was interesting that output actually appears to be registered > now. (It only changes with the rdy line where before it changed many times > even though I had 'register output' selected both times.) > > Is there a restriction on filter length? I am using 65 taps symmetric. Maybe > the odd length is causing a problem with the decimate by 2 structure? > > Thanks, > Clark > > Actually, nevermind. I had an extra clock in the input mux so the I and Q were on different phases into the fir. -ClarkArticle: 122209
Thank you for your help. Fatih GunesArticle: 122210
Hello, I have a block ram in my edk design.It is connected to lmb bram controller.I want to connect this controller to microblaze.Do i need an another lmb bus to connect microblaze or can i connect lmb controller to microblaze with auto-generated "dlmb " lmb bus of microblaze.If i connect with data bus ,what should i do about instruction lmb bus. Best wishes, Fatih GunesArticle: 122211
Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: > Is there something wrong with my .vcd file, or Gtkwave? Did you try to: click on the + in the SST window click on DFM1 select all the signal names which appered in the Signals window click Insert Looks fine in gtkwave on my machine. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122212
Hello. I now have 53bit corgen adder in my design. In order to upgrade the speed, I will do something about 53 bit adder. so Is there anyone who know which one between Corgen and DSP48 is faster? ps If there is none..... I will test them.Article: 122213
> I have a block ram in my edk design.It is connected to lmb bram > controller.I want to connect this controller to microblaze.Do i need an > another lmb bus to connect microblaze or can i connect lmb controller to > microblaze with auto-generated "dlmb " lmb bus of microblaze.If i connect > with data bus ,what should i do about instruction lmb bus. Like that : http://home.peufeu.com/nik/fpga/XPS_1.pngArticle: 122214
hello, we are trying to compile a v5 sx95t running 9.2 on linux red hat 9, but we are unable to pass the map step (ngdbuild went fine) any clue ? cheers Vincent Release 9.2.01i - Map J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Using target part "5vsx95tff1136-1". FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of library </common/soft/xilinx9.2i_lnx/virtex5/bin/lin/libMapRain.so> failed due to /common/soft/xilinx9.2i_lnx/virtex5/bin/lin/libMapRain.so: undefined symbol: _ZN17pktba_TaskManager9openPCubeEP13XCad_CadModelP7Xdm_TxnRPK10Xdm_DesignR9pk sba_Log. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at http://www.xilinx.com/support. make[1]: *** [module_top_map.ncd] Error 91Article: 122215
> >> I have a block ram in my edk design.It is connected to lmb bram >> controller.I want to connect this controller to microblaze.Do i need an >> another lmb bus to connect microblaze or can i connect lmb controller to >> microblaze with auto-generated "dlmb " lmb bus of microblaze.If i connect >> with data bus ,what should i do about instruction lmb bus. > > > Like that : > http://home.peufeu.com/nik/fpga/XPS_1.png > Thank you for your help.But i want to connect a second bram to microblaze.How can i do that?Article: 122216
On Tue, 24 Jul 2007 12:31:20 +0200, mfgunes <mfgunes@yahoo.com> wrote: >> >>> I have a block ram in my edk design.It is connected to lmb bram >>> controller.I want to connect this controller to microblaze.Do i need > an >>> another lmb bus to connect microblaze or can i connect lmb controller > to >>> microblaze with auto-generated "dlmb " lmb bus of microblaze.If i > connect >>> with data bus ,what should i do about instruction lmb bus. >> >> >> Like that : >> http://home.peufeu.com/nik/fpga/XPS_1.png >> > > Thank you for your help.But i want to connect a second bram to > microblaze.How can i do that? Ah, OK You can change the size of the BRAM (if you just need more space) instead of adding another one... Microblaze has 2 LMBs (data and instruction). You cannot add more LMBs, but you can connect several cores to each since it's a bus, not a P2P link. If you want to add another block of BRAM, instantiate 2 new lmb_bram_controllers, connect them to your LMBs (data & instruction) and to the new BRAM block.Article: 122217
"Gabor" <gabor@alacron.com> wrote in message news:1185213106.689869.270290@m3g2000hsh.googlegroups.com... >>Just out of curiosity, whay would you want to add delays >>from the master? I don't want the master to explicitly add delays. I'm rewriting the i2c master module and i get caught by the same question again "What if the user module of the i2c core didn't provide the next data fast enough? (i also considered a fifo). I know that 100/400Khz are slow enough compared to the user mode clk speed, but i believe in black boxes or what object oriented approaches call incapsulation. The user module doesn't have to depend on its child module implementation when possible and viceversa. So i'm figuring out whether i can make the core robust such that it can recover in cases of delayed data arrival. That said, even with a robust core the user module will implement things such that delays don't happen. see you, GaborArticle: 122218
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:46a51c8d$1@clear.net.nz... > Serial EE proms, have chosen a polling system for their 'wait' > requirements. > > > -jg Yeah, i notice the Ack polling in Microchip's seeproms. By the way, are royalties still due to Philips? Or have the copyrights expired. Just curious, i read something about it time ago. bye, JimArticle: 122219
Hi everybody, I've a problem with the mdio_0 signal of the hard temac available in the virtex4. Writting to the PHY is good but reading gives erroneous results. With an oscilloscope I can see that the voltage does not excess 1V (3.3V expected) during the read phase, during write phase I have 3.3V. A conflict with the FPGA is possible because the PHY is alone on the management bus. Is it possible that the tristate into the FPGA does not work ? Any ideas ? Thank you.Article: 122220
Koustav wrote: > I am trying to use the EDK based video decoder design provided by > Digilent. But when I am trying to buid the netlist I get the following > licensing error from the FLEX . I have purchased the video decoder > board. Do we have to purchase the license of this IP as well? > > Anybody has any past experiences in using this IP or some way to use > the video decoder for capturing S-video inputs? > > Thanks in advance for your help. > > INFO:coreutil - Valid license for feature opb_iic_v1 not found. > You may use the customization GUI for this core but you will > not be able to generate any implementation or simulation files. > Contact Xilinx to obtain a full license for this LogiCORE. For more > information please refer to www.xilinx.com/ipcenter/ipevaluation/ > FLEXlm Error: No such feature exists (-5,21) > ERROR:MDT - opb_iic (i2c) - C:\video_capture_rev_1_1\system.mhs line > 193 - > invalid license or no license found! Some of the IP cores that are included in Xilinx EDK require an extra license before they can be used. In the "IP Catalog" windows these cores are tagged with a special symbol, a padlock. Usually, an evaluation license is provide with these cores, so they can be implemented and tested. However, this licenses will expire some months after the release of the EDK version. So, if Your EDK version is too old, all Your evaluation licenses have expired. As far as I know, new eval. licenses can be requested via the Xilinx website. Best reagards, AndreasArticle: 122221
Hi, I have to record some events immediately atfer configuration of my FPGA (Spartan-3 1500). Chipscope's ILA and ICON are included and work well. Unfortunately, I'm not fast enough to hit F5 in time and arming the ILA in this way:-(. How can it be armed earlier, but that would mean during core generation. The FPGA is configured by a micro controller via JTAG. After finishing the configuration this micro access the FPGA and I've to record these cycles. Of course, I *have'nt* access to the micro's code. Thanks TomArticle: 122222
Thank you for your fast reply.But i need a empty port on bram.If i connect all of the ports (2 of them )to lmb controllers.I cant get a empty port on bram to connect my user implemented logic.I want a empty port(maked external) on bram.Can i connect bram to microblaze (with 1 lmb controller) using only one port?Article: 122223
mfgunes schrieb: > Thank you for your fast reply.But i need a empty port on bram.If i connect > all of the ports (2 of them )to lmb controllers.I cant get a empty port on > bram to connect my user implemented logic.I want a empty port(maked > external) on bram.Can i connect bram to microblaze (with 1 lmb > controller) using only one port? You can connect one port of BRAM with one lmb_bram controller which in turn is attached to one of the LMB buses of your MicroBlaze. If you choose the DLMB the MicroBlaze will see additional data memory. Do not forget to assign an appropriate address range to the BRAM. The other port of the BRAM can be connected to your custon IP. I have an design with two MicroBlazes which communicate over such an shared BRAM. Each MicroBlaze is connected to one BRAM port over its dlmb. EDK 8.1 complains about "unusual number of BRAMs", and the Block Diagram report gets screwed up but otherwise the system works fine. Best regards, AndreasArticle: 122224
Especially at your bit-width, the LUT based adder will be much faster. ---Matthew Hicks > Hello. > > I now have 53bit corgen adder in my design. > In order to upgrade the speed, I will do something about 53 bit adder. > so Is there anyone who know which one between Corgen and DSP48 is > faster? > ps If there is none..... I will test them. >
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