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On 21 Aug, 12:58, Manny <mlou...@hotmail.com> wrote: > Hi, > > Well the subject says it all. Just wondering how does Spartan-3A DSP > compares to Cyclone III in terms of power efficiency. I know the > spartan is 90nm and hence should be less favourable. However, does it > by any means at least approach the power performance of the cyclone? > > Thanks, > -Manny Hi Manny, Depends if you are working utlizing the suspend mode in Spartan3. Then at least static power will be more or less the same. For running, TSMC lowpower 65 nm will do the trick for Altera. So it all comes down to your power budget. Regards FredrikArticle: 123251
Hi, I'm trying to implement some control circuits in Mcode. I want to have the inputs and the outputs of the circuits to be flopped. I'm having trouble finding guidance in the documentation as to how I might do this. Could anybody help. As you may have surmised, I am new to System Generator. PhilArticle: 123252
Manny, Request the C3 vs S3A power comparison slides from your FAE. To me, while running (dynamic + static), it seems to be a wash (roughly equal, with S3A slightly better). When not running, S3A has power savings modes, so it is a clear winner if you decide to use one or both of the modes). Of course, it isn't hard to create a design where one, or the other shows an advantage for dynamic+static power. This slide set attempts to have a apples to apples comparison: you judge how careful we were to make things "the same." In general, the 90nm node for medium performance transistors is less leaky (less static power), and also has more dynamic power than 65nm. 65nm is generally leakier, unless performance is lessened by increasing the Vt's of the core transistors. In fact, at 65nm, even the gates leak (this static current is independent of temperature). The steepness of the increase in static current of 65nm is much greater than at 90nm with increasing junction temperature. Be sure to use a die temperature that is in keeping with your real application. AustinArticle: 123253
Hi, I want use ChipScope with MicroBlaze but I can't find tutorial or etc. I use EDK 8.1 and ChipScope 8.1. Any body has a source about it or link? ThanksArticle: 123254
Pasacco wrote:
> Problem was that
> ---------------------------
> If there is single global system clock, the overhead (by having only
> one global clock) becomes bigger and bigger.
> ---------------------------
True if the logic domains are not interconnected.
Otherwise maintaining synchronization also
requires significant overhead and intellectual investment.
> My question was that
> -----------------------------
> Can FPGA come up with "Globally Asynchronous, Locally Synchronous
> (GALS)" design style that ASIC tends to do?
> If yes, how?
> -----------------------------
global buffers, handshakes, fifos, etc.
-- Mike Treseler
Article: 123255
On Aug 21, 10:17 am, Phil <philguilleme...@alumni.uwaterloo.ca> wrote:
> Hi,
>
> I'm trying to implement some control circuits in Mcode. I want to
> have the inputs and the outputs of the circuits to be flopped. I'm
> having trouble finding guidance in the documentation as to how I might
> do this. Could anybody help.
>
> As you may have surmised, I am new to System Generator.
>
> Phil
Here is my attempt at a 2 input mux with a reset. It seems to work,
but I'm not sure if there is a more appropriate way of registering the
inputs and outputs.
function [mux_out] = mux(a_in, b_in, sel_in, rst)
persistent a_flop, a_flop = xl_state(0, {xlUnsigned, 8, 0});
persistent b_flop, b_flop = xl_state(0, {xlUnsigned, 8, 0});
persistent mux_o, mux_o = xl_state(0, {xlUnsigned, 8, 0});
%---------------------------------------------------------------
% Mux
%---------------------------------------------------------------
if rst
mux_o = 0;
mux_out = 0;
else
mux_out = mux_o;
if sel_in
mux_o = b_flop;
else
mux_o = a_flop;
end
end;
if rst
a_flop = 0;
b_flop = 0;
else
a_flop = a_in;
b_flop = b_in;
end;
Article: 123256I avoid multi-cycle constraints like the plague as well. They bring in too many opportunities to make a mistake that will bite you later.Article: 123257
hi i have wrote the program for nios processor. when i am trying to complie it, i am getting the follwing errors. can anyone help me out in rectificing the errors **** Build of configuration Debug for project ucosii_tutorial_0_syslib **** make -s all Compiling smsc_mem.c... /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c: In function `mac2ip': /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:46: error: `LAN91C111_BASE' undeclared (first use in this function) /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:46: error: (Each undeclared identifier is reported only once /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:46: error: for each function it appears in.) /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:46: error: `LAN91C111_LAN91C111_REGISTERS_OFFSET' undeclared (first use in this function) /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c: In function `s91_port_prep': /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:93: error: `LAN91C111_BASE' undeclared (first use in this function) /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:93: error: `LAN91C111_LAN91C111_REGISTERS_OFFSET' undeclared (first use in this function) /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ UCOSII/src/iniche/smsc_mem.c:94: error: `LAN91C111_IRQ' undeclared (first use in this function) make: *** [obj/iniche/smsc_mem.o] Error 1 Build completed in 43.25 seconds i am using UCOS/OSII Rtos and using the simple socket server demo and made the necessary changes to suit to my designArticle: 123258
Eddie H wrote: > I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this. > Sounds like a 3 resistor solution to me. FWIR ECL biased like you describe, is symmetric about 0V, so you put a pull-down resistor to -2.5V to give the -ve ECL swing, and then ratio the resistors to give an equal positive ECL swing, and a resistor to GND allows the total swing to be reduced, and also to lower the drive impedance. Chuck it into spice, and solve iteratively. -jgArticle: 123259
On Aug 21, 12:33 pm, sriman <srima...@gmail.com> wrote: > hi > > i have wrote the program for nios processor. when i am trying to > complie it, i am getting the follwing errors. can anyone help me out > in rectificing the errors > > **** Build of configuration Debug for project ucosii_tutorial_0_syslib > **** > > make -s all > Compiling smsc_mem.c... > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c: In function `mac2ip': > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:46: error: `LAN91C111_BASE' undeclared > (first use in this function) > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:46: error: (Each undeclared identifier is > reported only once > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:46: error: for each function it appears > in.) > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:46: error: > `LAN91C111_LAN91C111_REGISTERS_OFFSET' undeclared (first use in this > function) > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c: In function `s91_port_prep': > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:93: error: `LAN91C111_BASE' undeclared > (first use in this function) > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:93: error: > `LAN91C111_LAN91C111_REGISTERS_OFFSET' undeclared (first use in this > function) > /cygdrive/f/altera/61/ip/sopc_builder_ip/altera_avalon_lan91c111/ > UCOSII/src/iniche/smsc_mem.c:94: error: `LAN91C111_IRQ' undeclared > (first use in this function) > make: *** [obj/iniche/smsc_mem.o] Error 1 > Build completed in 43.25 seconds > > i am using UCOS/OSII Rtos and using the simple socket server demo and > made the necessary changes to suit to my design You made one too many changes: The LAN91C111 module is either missing from your NIOS core, or you re-named it. There is a very specific hardware configuration needed for NIOS-uCos; you have to have certain cores, and they must have the correct names. G.Article: 123260
First, I will disclose that I work for Altera. My advice is to try the comparisons yourself and you will find out which family is best for you. Altera has made it very easy to verify power consumption claims yourself using the Cyclone III FPGA Starter Kit. It provides an application note and circuitry to easily measure Cyclone III FPGA static and dynamic power consumption. http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html. You can also purchase the EP3C120 device for measurement using your own board. A board including the largest Cyclone III EP3C120 is in development. In the interest of providing both sides of the story I will provide some responses to the claims below. On Aug 21, 8:12 am, austin <aus...@xilinx.com> wrote: > Manny, > > Request the C3 vs S3A power comparison slides from your FAE. > > To me, while running (dynamic + static), it seems to be a wash (roughly > equal, with S3A slightly better). Using the power estimator results from both vendors does not substantiate this claim. For example, looking at static power only, The Cyclone III EP3C120 has roughly 119K logic elements and 3,888 kits of memory while its static power consumption is just 0.169 whether it is active or suspended. The Xilinx XC3SD3400A has 23,872 slices which is roughly equivalent to just 48K logic elements and has 2268 kbits of memory. Static power for the low power version of this part in active mode is 0.451W. In suspend mode it drops to 0.234W while the part is suspended. These comparisons used the latest versions of both spreadsheet estimators and assume 85C junction temperature and still air. > When not running, S3A has power savings modes, so it is a clear winner > if you decide to use one or both of the modes). Altera devices include an ALTCLKCNTRL function that can be used to shut off clock networks to lower power consumption. Altera users are not penalized with higher static power consumption when the clocks resume operation. This function provides fine grained control over what is shut on/off and how much power savings is achieved. You can shut down the whole part or just selected functions/clocks which provides a lot of flexibility. > Of course, it isn't hard to create a design where one, or the other > shows an advantage for dynamic+static power. This slide set attempts to > have a apples to apples comparison: you judge how careful we were to > make things "the same." > In general, the 90nm node for medium performance transistors is less > leaky (less static power), and also has more dynamic power than 65nm. > > 65nm is generally leakier, unless performance is lessened by increasing > the Vt's of the core transistors. In fact, at 65nm, even the gates leak > (this static current is independent of temperature). In general these statements are true if nothing is done to mitigate these issues. However, the Altera Cyclone III architecture is built on TSMC's low power process and uses an intelligent selection of low Vt's for fast performance only where speed critical. In non-speed critical circuits slower, higher Vt transistors are used. Altera also uses low Vt transistors coupled with longer channel lengths to get a balance between good performance and low leakage. > The steepness of the increase in static current of 65nm is much greater > than at 90nm with increasing junction temperature. Be sure to use a die > temperature that is in keeping with your real application. > > Austin The proof is in the pudding. Regardless of what Austin or I say, perform your own comparisons and I am confident you will be impressed by the combination of relatively higher performance, higher functionality, and lower power consumption Cyclone III FPGAs deliver. Regards, RobArticle: 123261
<Eddie H> wrote in message news:eea8c30.5@webx.sUN8CHnE... > Brian, > > I am sorry I am not able to understand your suggestion. I have the source > device postive rail connected to 3.3V and negative rail connected to 0V. > The source device generates TTL compatible signal. My real target device > positive rail is connected to 0.8V and negative rail is connected -2.5V. > Thus I can not not connecte the 3.3V TTL signal directly to the traget > device and need to do the voltage translation. > > I was thinking about using a device from analog device beween the source > and target device at the following link. > > <http://www.analog.com/en/prod/0,2877,ADUM1411,00.html> > > Eddie Hi Eddie, I'm interested in where you ended up with such an awkward system? I wonder why the two sections cannot share a ground. Anyway, download LTspice and load in the stuff below after saving it as 'level_shift.asc' or whatever. PNP and three resistors. Adjust the resistors to suit your voltage needs. You can get a full output range to the most negative rail. HTH., Syms. Version 4 SHEET 1 880 680 WIRE 176 48 -320 48 WIRE -320 80 -320 48 WIRE 176 112 176 48 WIRE 16 160 -16 160 WIRE 112 160 96 160 WIRE -80 176 -208 176 WIRE -208 208 -208 176 WIRE 176 240 176 208 WIRE 176 336 176 320 WIRE 256 336 176 336 WIRE 272 336 256 336 WIRE 176 352 176 336 WIRE 176 464 176 432 FLAG -80 208 0 FLAG -208 288 0 FLAG -320 160 0 FLAG 176 544 0 FLAG 256 336 Vout SYMBOL Digital\\buf -80 112 R0 WINDOW 3 0 0 Invisible 0 SYMATTR InstName A1 SYMATTR Value Vhigh=3.3 SYMBOL voltage -208 192 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 3.3 0 1n 1n 1u 2u) SYMBOL pnp 112 208 M180 SYMATTR InstName Q2 SYMBOL voltage -320 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 3.3 SYMBOL res 112 144 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 160 224 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 160 336 R0 SYMATTR InstName R3 SYMATTR Value 270 SYMBOL voltage 176 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value -2.5 TEXT -234 420 Left 0 !.tran 100usArticle: 123262
On Aug 21, 11:21 am, icegray <iceg...@gmail.com> wrote: > Hi, > I want use ChipScope with MicroBlaze but I can't find tutorial or etc. > I use EDK 8.1 and ChipScope 8.1. Any body has a source about it or > link? > > Thanks Well, what exactly are you trying to do? You can use ChipScope in an EDK project with MicroBlaze no problem. Are you asking if you can use ChipScope to look at MicroBlaze signals? If so, the only ones you could hook up are the ports exposed through the IP core itself. More info from you would help.Article: 123263
Eddie, it would really help YOU if you would answer the questions that Gabor put to you: What speed, any dc component, and how many channels? Also, if the receiving device is ECL, you do not need a lot of voltage swing... There are many ways to solve your design problem, but it is impossible to recommend any one if you don't tell us the details. Peter Alfke On Aug 21, 6:14 am, "Eddie H" <> wrote: > Brian, > > I am sorry I am not able to understand your suggestion. I have the source device postive rail connected to 3.3V and negative rail connected to 0V. The source device generates TTL compatible signal. My real target device positive rail is connected to 0.8V and negative rail is connected -2.5V. Thus I can not not connecte the 3.3V TTL signal directly to the traget device and need to do the voltage translation. > > I was thinking about using a device from analog device beween the source and target device at the following link. > > <http://www.analog.com/en/prod/0,2877,ADUM1411,00.html> > > EddieArticle: 123264
On Aug 14, 4:25 am, backhus <n...@nirgends.xyz> wrote: > Hi, > > look at:realpath(/include) failed, No such file or directory > Your host system probably has noincludefolder in the root directory. > > Something (maybe aninclude-path variable) is missing in your setup. > Look at your makefiles for something like: > > $THE-MISSING-PATH-WITH-THE-UNKNOWN-VARIABLE-NAME/include > > If the path variable is empty the resuling path is /includewhich is > terribly wrong of course. It should be something like > > /home/devel/uclinux/src/uClinux-2.4.x/include > > and > > this line: make[3]: *** [fastdep] Error 1 > tells you where to look at first. > > Good luck > Eilert > > kobela...@gmail.com schrieb: > > > what's wrong with following word??? > > > [root@localhost uClinux-dist]# make dep > > make ARCH=microblaze CROSS_COMPILE=mb- -C linux-2.4.x dep > > make[1]: Entering directory `/home/devel/uclinux/src/uClinux-2.4.x' > > rm -f .depend .hdepend > > make _sfdep_arch/microblaze/kernel _sfdep_arch/microblaze/mm > > _sfdep_arch/microblaze/lib _sfdep_arch/microblaze/xilinx_ocp > > _sfdep_arch/microblaze/platform/uclinux-auto _sfdep_kernel > > _sfdep_drivers _sfdep_mmnommu _sfdep_fs _sfdep_net _sfdep_ipc > > _sfdep_lib _sfdep_crypto _FASTDEP_ALL_SUB_DIRS="arch/microblaze/kernel > > arch/microblaze/mm arch/microblaze/lib arch/microblaze/xilinx_ocp arch/ > > microblaze/platform/uclinux-auto kernel drivers mmnommu fs net ipc lib > > crypto" > > make[2]: Entering directory `/home/devel/uclinux/src/uClinux-2.4.x' > > make -C arch/microblaze/kernel fastdep > > make[3]: Entering directory `/home/devel/uclinux/src/uClinux-2.4.x/ > > arch/microblaze/kernel' > > /home/devel/uclinux/src/uClinux-2.4.x/scripts/mkdep -D__KERNEL__ -I/ > > home/devel/uclinux/src/uClinux-2.4.x/include -Wall -Wstrict- > > prototypes -Wno-trigraphs -O1 -g -fno-strict-aliasing -fno-common - > > DPLATFORM=uclinux-auto -O3 -fno-builtin -DNO_MM -DNO_FPU -D__ELF__ - > > DMAGIC_ROM_PTR -DUTS_SYSNAME=\"uClinux\" -D__linux__ -I/include-mxl- > > barrel-shift -mno-xl-soft-div -mno-xl-soft-mul -I/home/devel/uclinux/ > > src/uClinux-2.4.x/arch/microblaze/xilinx_ocp -nostdinc -iwithprefix > >include-- bug.c crtinit.S entry.S exceptions.c head.S highres_timer.c > > hw_exception_handler.S init_microblaze_timer.c intv.S irq.c mach.c > > mach.h mbvanilla.c memcons.c microblaze.c microblaze_defs.c > > microblaze_defs.h microblaze_intc.c microblaze_ksyms.c > > microblaze_timer.c process.c procfs.c ptrace.c semaphore.c setup.c > > signal.c syscalls.c time.c xmbserial.c xmbserial.h > .depend > >realpath(/include) failed, No such file or directory > > make[3]: *** [fastdep] Error 1 > > make[3]: Leaving directory `/home/devel/uclinux/src/uClinux-2.4.x/arch/ > > microblaze/kernel' > > make[2]: *** [_sfdep_arch/microblaze/kernel] Error 2 > > make[2]: Leaving directory `/home/devel/uclinux/src/uClinux-2.4.x' > > make[1]: *** [dep-files] Error 2 > > make[1]: Leaving directory `/home/devel/uclinux/src/uClinux-2.4.x' > > make: *** [dep] Error 2 I'm having the same problem! How did you resolve it?Article: 123265
Pasacco wrote: > Hi again :) > I would like to ask two more things. > > 1. > I am looking for literature about : > How to obtain the "growth rate of number of wires". > For example, 1.5 or 1.2 or 1.6.... > > Could you please provide a pointer? > (for example, book, paper, web, ....) > > 2. > I would like to obtain p value. > Again, if you have pointer, please let me know. > > Method that I have in mind is that: > In FPGA Editor, simply count number of wires between neighbor CLBs. > These things are general observations and tendencies. Much like Moore's law, there is no hard science behind them: they just turn out that way due to engineering/marketing/economic/etc. reasons. For FPGAs, routing resources are simply scaled to compromise between the routability and performance targets requested by customers, manufacturability, engineering mindset, company policies, marketing spin, expected market developments and countless other variables. If synthesis tools reported unused wires, I bet many FPGA customers would start complaining about the cost of having so much "dead copper" even in fully routed FPGAs... I bet current designs use far less than 25% of all routing and this figure actually sinks as devices scale up.Article: 123266
By choosing to implement in an FPGA, you must accept the limitations of the architecture of the target device, including the number of permitted clocks. This may restrict the design style to some extent. In an ASIC you (generally speaking) have no such restrictions, but the up-front cost and turn-around times are much increased. >> IP should have a clock port and a clock enable >> port. So, if you need to integrate several bits of IP, you can use one clock >> with different enables. > >Thank you but I do not get the point. > >Problem was that >--------------------------- >If there is single global system clock, the overhead (by having only >one global clock) becomes bigger and bigger. >--------------------------- > >My question was that >----------------------------- >Can FPGA come up with "Globally Asynchronous, Locally Synchronous >(GALS)" design style that ASIC tends to do? >If yes, how? >----------------------------- > >Thank you again > >Article: 123267
I'm trying to get the Cypress Ez-host working in peripheral mode on a Xilinx ML401 development board. The example code I have is for the actual cypress development board, but I don't see why anything should be different. When I program the USB controller chip with an HID example, and plug in a usb cable to a pc - windows says the usb device does not function correctly. Can anyone point me in the right direction? ThanksArticle: 123268
Hi,
I have a VHDL design which has no reset, within the design
are statements that rely on the last know state of a signal i.e sig_a
<= not sig_a, sig_a has not had an initial value declared in the
signal region, hence it's value is X, there are numerous occurrences
of this within the design. The design has been place and routed and
works ok on the board as in the real world all signals have a default
value. I can not change the RTL code, I therefore need to force all
signals in the design to a known state, I understand that force only
works on 1 signal at a time. Does anybody know how to force all nets,
or have any better ideas than using force?
Thanks
Jon
Article: 123269I have a design on a Spartan 3 2000. It uses nearly all slices, two thirds of the FF and LUTs. Also all BlockRam and all BlockMultiplier are used. The design uses three clock. A 40 Mhz clock for configuration and registers, 80 Mhz for data processing, and 160 Mhz for internal processing in certain blocks. The problem is that the device becomes hot, so hot, that you can burn your fingers. I measured up to 104 =B0C on the FPGA Ituses nearly 1.3 W. I have alredy implemeted ClockEnables everywhere possible. Also on RAMs. I have already sythesized with Power Reduction option. The Device can't have a active cooling, like a fan. Does anybody have some advice how to further reduce the power ? 25 % would be great.Article: 123270
On Aug 22, 10:19 am, tgschw...@tiscalinet.ch wrote: > I have a design on a Spartan 3 2000. It uses nearly all slices, two > thirds of the FF and LUTs. Also all BlockRam and all BlockMultiplier > are used. > The design uses three clock. A 40 Mhz clock for configuration and > registers, 80 Mhz for data processing, and 160 Mhz for internal > processing in certain blocks. > > The problem is that the device becomes hot, so hot, that you can burn > your fingers. I measured up to 104 =B0C on the FPGA Ituses nearly 1.3 W. > I have alredy implemeted ClockEnables everywhere possible. Also on > RAMs. I have already sythesized with Power Reduction option. > > The Device can't have a active cooling, like a fan. > > Does anybody have some advice how to further reduce the power ? 25 % > would be great. Try using the enabled clock buffers to create a safe, gated clock if you have a large quantity of registers using the same enable. Also, how are you generating your separate clocks? Try using fewer DCMs, by manually dividing clocks (i.e. selectively disabling some enabled clock buffers, etc.) As always, look for opportunities to shut off (disable clock) on anything that is not used all the time. What does your IO look like? Can you soften your drive strengths, and/ or reduce slew rates? Do you have any opportunities to use distributed rams instead of flops? I once had a design with a bunch of simple UARTs. I modified the design to TDM the UARTs using distributed ram, and reduced logic and power consumption drastically. AndyArticle: 123271
On Aug 22, 9:45 am, witten...@googlemail.com wrote: > Hi, > > I have a VHDL design which has no reset, within the design > are statements that rely on the last know state of a signal i.e sig_a > <= not sig_a, sig_a has not had an initial value declared in the > signal region, hence it's value is X, there are numerous occurrences > of this within the design. The design has been place and routed and > works ok on the board as in the real world all signals have a default > value. I can not change the RTL code, I therefore need to force all > signals in the design to a known state, I understand that force only > works on 1 signal at a time. Does anybody know how to force all nets, > or have any better ideas than using force? > > Thanks > > Jon You don't want to force nets, since then they cannot be overridden in simulation (unless you force and then release them). You could just add initializers to the signal and variable declarations, but that means modifying the code, although it could be done with a script in most cases. I don't suppose we need to tell you that having neither reset nor initializers is a bad design practice, even when it "works" in FPGA hardware. This is one case where a two-state optimization on the simulator would be worth its weight in gold. AndyArticle: 123272
On 2007-08-22, Ray Andraka <ray@andraka.com> wrote: > You can use the BUFGMUXs to gate your clocks if needed, however most > designs need the clocks running, and gating clocks brings its own set of > problems. Your post got me thinking about dynamically reconfiguring an FPGA to save power. I wonder how much power you can save by reconfiguring an FPGA so that an unused block is not there as compared to just turning off the clock to that block. Is the static power consumption of an empty slice the same as the static power consumption of a configured slice with static inputs? /AndreasArticle: 123273
On Aug 22, 4:10 am, alle...@gmail.com wrote: > I'm trying to get the Cypress Ez-host working in peripheral mode on a > Xilinx ML401 development board. The example code I have is for the > actual cypress development board, but I don't see why anything should > be different. When I program the USB controller chip with an HID > example, and plug in a usb cable to a pc - windows says the usb device > does not function correctly. > > Can anyone point me in the right direction? > > Thanks This is actually quite tricky! I'm not sure where the EZ part of the name came from. What you have to do essentially is: 1) Write some C code to implement your USB Peripheral. This C-Code will run on the EZ-Host's internal processor. The EZ-USB development kit (free download from Cypress website) has some example C-Code and other stuff the get you started (but it's still not EZ, the example fail to explain what the code is really doing and the documentation is pretty hard to follow). 2) Then once you have this C-Code, compile it, and then dump it to a binary file. This binary file is then dumped to a C sytle array, so every byte in the array is the hex representation of every byte in the binary file. There are some utilities provided to help with this in the cypress development kit. This binary file must be uploaded to the EZ-Host. This is done from the FPGA. I believe the ml401 keyboard demo does this - it does the following: Using he opb_emc peripheral, it connects to the EZ-Host using the HPI interface protocol. There is C-Code in some of example which implements some of the HPI protcocol commands (again, not easy if you are not familiar with it, and some of the HPI instructions are NOT in the cypress documentation, but only exist in header files in some of the examples, so a lot of digginf is required). Once you have HPI communication mastered, and know how to write to the EZ-Host program memor, you upload the contents of the compiled binary file. The best thing to do is to write some C-Routines that essentially implement a function you pass start address, data and length to the C function and it will figure out the necessary HPI commands to upload to the EZ- Host. Then pass the C-array version of the binary file to this - tell the EZ-Host to re-boot, and viola - you have the EZ-Host doing whatever you wrote the C code to do - be a peripheral, be a host, be 2 peripherals, whatever. I suggest you try upload some of the example C-Code that comes with the EZ-Host development kit. You can then use some of the example demo applications that will do things like loop-back tests between the peripheral and the PC. You have to install usb drivers into your system too - so windows knows what the peripheral is, etc. The development kit comes with some example drivers for this too - ones than can talk to the peripheral and determine what way its configured - but it can only do it if the driver has been told it can operate for a given vendorID and productID that the peripheral is setup as (I was unable to find a generic USB "spy" program that would simply interrogate and debug any attached USB device - which made the debug process all the more painful. Once you have the ability to upload a program to the EZ-Host you are definitely doing well! To make a long story short - this is tricky. Not EZ. Maybe if you are experienced in USB it is EZ! But trying to do what you are doing really turned me off using the EZ-Host. Because after wading through the docs and finally getting something up and running, I was able to achieve about 40Kbytes data transfer rate to my "peripheral". I was happy I had a proof of concept, but that was all. I abandoned it in favour of a really easy USB-FIFO chip, which comes with drivers and all you need to get data streaming between an FPGA and a host computer. Unfortunately I don't have that project to hand right now - but it can be done. And maybe even with the right software written for the EZ- Host and uploaded you can get it to run faster than my paltry 40Kbytes/ sec (it should be capable of 900Kbytes/sec..or so). Best of luck, and I hope this has helped a bit!Article: 123274
wittenjon@googlemail.com wrote:
> I have a VHDL design which has no reset, within the design
> are statements that rely on the last know state of a signal i.e sig_a
> <= not sig_a, sig_a has not had an initial value declared in the
> signal region, hence it's value is X, there are numerous occurrences
> of this within the design. The design has been place and routed and
> works ok on the board as in the real world all signals have a default
> value.
If it's working ok, why the interest in simulation?
If it isn't working ok, you'll have to change the code anyway.
> I can not change the RTL code, I therefore need to force all
> signals in the design to a known state, I understand that force only
> works on 1 signal at a time. Does anybody know how to force all nets,
> or have any better ideas than using force?
You could add a reset to the code for simulation
and make a wrapper entity that ties reset to ground for synthesis.
-- Mike Treseler
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