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I am working now for some days on a strange behaviour of a fpga. The design is complete synchron. I have the problem that when I change in a state machine a signal, then the design doesn't function any more. The problem is a can not locate where it come from, because when I add some debug information the design works again. In Simulation I can't see something wrong. Has anybody an idea what could be wrong?Article: 123501
Jim,
On 2007-08-28, Jim Lewis <jim@synthworks.com> wrote:
|--------------------------------------------------------------------------|
|"Weng, |
|[..] |
| |
|[..] |
| |
|I noted that in your code you mixed orif mixed with elsif (copied below), |
|was this intentional? One hand, these could convey exactly what I want |
|(because there are many cases like this), OTOH, it could be a mistake. |
|Hence the intent is ambiguous and during a design review, one would have |
|to pay particular attention to this and ask questions about your intent |
|and its validation. A copy of your code is below. |
| |
|If(E0 = '1') then |
|State_A <= E0_S; |
|Orif(E1 = '1') then |
|State_A <= E_S; |
|Orif(E2 = '1') then |
|State_A <= E2_S; |
|elsIf(E3 = '1') then |
|State_A <= E3_S; |
|Orif(E4 = '1') then |
|State_A <= E4_S; |
|Orif(E5 = '1') then |
|State_A <= E5_S; |
|elsIf(E6 = '1') then |
|" |
|--------------------------------------------------------------------------|
Yes,
Weng really did intend to have both orif branches and elsif branches
in a single if statement (see
news:1188325844.164564.136940@z24g2000prh.googlegroups.com
). I think the intention would be clearer with different
indentation. E.g.
If(E0 = '1') then
State_A <= E0_S;
Orif(E1 = '1') then
State_A <= E_S;
Orif(E2 = '1') then
State_A <= E2_S;
elsIf(E3 = '1') then
State_A <= E3_S;
Orif(E4 = '1') then
State_A <= E4_S;
Orif(E5 = '1') then
State_A <= E5_S;
elsIf(E6 = '1') then
--...
|--------------------------------------------------------------------------|
|"[..] |
| |
|[..] The danger in adding new keywords is that they may |
|conflict with a name (signal, ...) already used in someone's design |
|and cause an old design to be a syntax error in the new language |
|revision. This generally does not please people and means they |
|have to add special handling for the file (compile flags). |
| |
|[..]" |
|--------------------------------------------------------------------------|
A newly introduced reserved word would be guaranteed to not conflict
with old code by not being possible to misinterpret as a basic
identifier (basic_identifier ::= letter { [ underline ]
letter_or_digit), e.g. by starting with an underline or by containing
a percentage sign.
Best regards,
Colin Paul
Article: 123502Hi, You should be able to use the plb_bram_if_cntlr. You might need to look at the size of the data busses, The BRAM implemented will not handle different sizes on the two ports. Göran "Pablo" <pbantunez@gmail.com> wrote in message news:1188373871.351555.63150@r29g2000hsg.googlegroups.com... > Hi, I have implemented a core to write/read to a Bram_Block (using one > of the two ports). The another port is used by Microblaze with a > lmb_bram_if_cntlr core to read those values which had been modified by > my custom core. Of course, I use a lmb bus. > > Now, I want to create a design with PowerPC and I suppose I must use a > plb bus to access to the bram_block. With this assumption, PowerPC > would use a plb_bram_if_cntlr core to read from the bram (this works > fine), but my custom core cannot modify the contents of the bram. > > What's wrong?. Is plb bus very different from lmb?. Could I use a lmb > bus with PowerPC instead of Microblaze? > > Best Regards >Article: 123503
Folks, the functionality you are talking about is available in VHDL 2006 via the use of PSL in assertions. Essentially it is not about describing a function, but about restricting the domain of that function. This should not be mixed with the specification of the functions behaviour, especially if you take formal verification into account. Kolja SulimmaArticle: 123504
Hi, Now, I learn xflow of xilinx. I want to generate a function simulation output file. For the example vhdl file: watchvhd, according to the Development System Reference Guid, I use the command: xflow -p xc2vp2-7fg256 -fsim modelsim_vhdl.opt stopwatch It generates a file: func_sim.vhdl My question is: How can I use it in Modelsim? Thanks in advanceArticle: 123505
On Aug 28, 7:25 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> He's trying to ensure the enable signal gets to all the FFs in time. This
> should happen anyway as long as he keeps the instance 'en' out of his
> timegroup 'tgrp_en' (...)
The example which I began with shows exactly why this isn't true.
> I think there's a flaw in his logic, in that the enable doesn't necessarily
> attach to the .CE pins. It can go to regular logic depending on the
> synthesisers 'day_of_week' input. :-) Also, CE pins get used for other
> things the synthesiser decides on.
... which is exactly what my recent suggestion should solve.
Eli
Article: 123506<eli.billauer@gmail.com> wrote in message news:1188385141.383406.123560@19g2000hsx.googlegroups.com... > On Aug 28, 7:25 pm, "Symon" <symon_bre...@hotmail.com> wrote: > >> He's trying to ensure the enable signal gets to all the FFs in time. This >> should happen anyway as long as he keeps the instance 'en' out of his >> timegroup 'tgrp_en' (...) > > The example which I began with shows exactly why this isn't true. > Hi Eli, I think you've misinterpreted what's happening. In your original example, the 'cnt' signals don't need to get back to the clock enable input in one cycle. Only the signal 'en' does. As long as 'en' gets to the FFs in time, whatever the CNT signals are doing does not matter a jot. This is your mistake :- "This is all nice, but now we have a path from cnt[15:0] (a.k.a. "tgrp_en") to itself, which has to be finished in one single clock: >From the values of cnt[15:0], through the logic which does cnt! =16'hffff, and back to the flip-flops' CE. After all, the CE must meet timing for every clock. On the other hand, the multi-path constraint allows 4 clocks for this path." HTH., Syms.Article: 123507
On Aug 29, 6:08 am, markus.j...@de.bosch.com wrote: > I am working now for some days on a strange behaviour of a fpga. > The design is complete synchron. > I have the problem that when I change in a state machine a signal, > then the design doesn't function any more. > The problem is a can not locate where it come from, because when I > add > some debug information the design works again. > In Simulation I can't see something wrong. > > Has anybody an idea what could be wrong? 1. An input signal that is not synchronized to the state machine clock. -- Make sure all state machine inputs are properly synchronized to the clock. 2. Violating setup/hold times. -- Do static timing analysis KJArticle: 123508
On Aug 27, 2:04 pm, "onenanome...@gmail.com" <onenanome...@gmail.com> wrote: > A nice collection of VLSI interview questions can be found athttp://digitalelectronics.blogspot.com/ > > Also contributors are welcome. I try to post some technical interview questions on my blog as well - with solutions. http://asicdigitaldesign.wordpress.com/ There are also some more difficult questions which are related to digital design but are too hard to qualify as interview questions (IMHO) - these are tagged as "puzzles". thanks, NirArticle: 123509
On Aug 29, 8:19 am, KJ <Kevin.Jenni...@Unisys.com> wrote: > On Aug 29, 6:08 am, markus.j...@de.bosch.com wrote: > > > I am working now for some days on a strange behaviour of a fpga. > > The design is complete synchron. > > I have the problem that when I change in a state machine a signal, > > then the design doesn't function any more. > > The problem is a can not locate where it come from, because when I > > add > > some debug information the design works again. > > In Simulation I can't see something wrong. > > > Has anybody an idea what could be wrong? > > 1. An input signal that is not synchronized to the state machine > clock. -- Make sure all state machine inputs are properly synchronized > to the clock. This is less likely if the design works when you add debug unless you added a synchronizing stage along with the debug logic. > 2. Violating setup/hold times. -- Do static timing analysis > This is important. Run timing analysis with "Report Uncovered Paths" checked. Very often designs that magically fix themselves on re-build have an error due to unconstrained or improperly constrained paths. Also if you don't immediately find a problem looking at the static timing report, you can try post P&R simulation with the failing design. > KJArticle: 123510
On Aug 29, 1:25 am, "vsurdu...@gmail.com" <vsurdu...@gmail.com> wrote: > On Aug 29, 5:43 am, Jimb...@gmail.com wrote: > > > > > > > I'm developing an embedded PPC405 system on a Xilinx FPGA and Im > > hoping I can get some insight on this problem. > > > I'm using the PLB_DDR2 xilinx ip core to interface two DDR2 memory. > > Currently I can read/write to DDR2 memory through the XMD/JTAG debug > > port. I then do a soft reset of the system by an "rst" command through > > the xmd command prompt. All my internal registers reset correctly and > > I can read/write to them. Hovvever, if i then try to read/write to > > DDR2, the system crashes and i get weird values back. A soft reset > > will bring back register access, but I have to reprogram the FPGA in > > order to get DDR2 read/write capability. > > > It seems like for some reason the DDR2 controller is not being reset > > with the rest of the system. > > > Thanks for any suggestions on this. > > Just asking: the DDR2 memories are properly routed ? What kind of > terminators are onboard? If active terminators used are they > programmed correctly in the FPGA ? > Probably through the jtag the W/R sequence to DDR2 is slower and > everything it's ok.- Hide quoted text - > > - Show quoted text - Ah, I think i said that in a confusing way. The processor is executing instructions (reading/writing to DDR2 using the plb_ddr2 core), im just loading instructions to the proc via the jtag chain with XMD debug command prompt instead of loading code into block ram. So I'm fairly confident that the hardware is correct (or at least correct enough to write reliably to the DDR2 BEFORE a soft system reset. Also, some info i may not have given initially: Im using the xilinx reset module typically instantiated with EDK. It's driving my plb and opb bus resets. As far as i can tell, the plb reset is the only reset signal going to the plb_ddr2 core.Article: 123511
On Aug 29, 12:51 pm, Pablo <pbantu...@gmail.com> wrote: > Hi, I have implemented a core to write/read to a Bram_Block (using one > of the two ports). The another port is used by Microblaze with a > lmb_bram_if_cntlr core to read those values which had been modified by > my custom core. Of course, I use a lmb bus. > > Now, I want to create a design with PowerPC and I suppose I must use a > plb bus to access to the bram_block. With this assumption, PowerPC > would use a plb_bram_if_cntlr core to read from the bram (this works > fine), but my custom core cannot modify the contents of the bram. > > What's wrong?. Is plb bus very different from lmb?. Could I use a lmb > bus with PowerPC instead of Microblaze? > > Best Regards Hi Pablo, I want to ask u how u are able to read the block ram by microblaze. U said u had used lmb_bram_if_cntlr core to read the BRAM. then r u using the same lmb bus used by microblaze to access data( in instruction). Then in C code which instruction u had used to read BRAM data. Would u please explain ur design Thanks and regards, HarshadaArticle: 123512
I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Area as an FPGA resource there's an option to initialize it by using memory eritor. However, this would be very time consuming, as my memory is 16Kwords deep. Is there some way to just reference an external text file, or excel sheet at least automatically read/paste an external file for this purpose? and also How to combine both block memory and distributed memory (using lut) to use as one memrory of 16k?Article: 123513
Hi, I'd like to set up block rams(16k) to acts as a ROM lookup table after initialization. After establishing the Memory Area as an FPGA resource there's an option to initialize it by using memory eritor. However, this would be very time consuming, as my memory is 16Kwords deep. Is there some way to just reference an external text file, or excel sheet at least automatically read/paste an external file for this purpose? and also How to combine both block memory and distributed memory (using lut) to use as one memrory of 16k? that is , I want 2 implenet 2 memory of size 16kX8 in fpga spartan-3 one a6X8 take 8 block ram out of 12 block ram available in fpga? then when I tried to use only LUT as ram of size 16kX8 the resourses are not enough.so can u tell me hoe to combine remainning 4 blokc ram and LUTs to implement one more memory of size 16kX8 please mail to me at vkmselva@gmail.comArticle: 123514
Hello, I'm trying to understand exactly what the behavior of the OSERDES is ... I'm using a 4:1 DDR mode for both data and tristate. I send clk_2x to CLK and clk_1x to CLK_DIV. (both derived from a PLL on v5 / DCM on v4). When I look at the behavioral simulation, I don't see the results that I expect from the documentation. And even in the documentation, depending on what page I read, I understand something different ... So does some one which one is right ? Let say clk_0 has a 10 ns period, clk_2x 5 ns period and that both have rising edge at 0 ns. I set a data[3:0] on the D1-D4 input of OSERDES at t = -2 ns ... when will I see D1 appear on the OQ port ? - In the virtex 5 useguide page 385 (table 8-9) they say the latency is 1 CLKDIV and 1 CLK. So I would expect the D1 to appear at t = 15 ns ( captured at t=0ns, the first rising edge of CLKDIV after I set the data, then wait 1 CLKDIV cycle, then wait 1 CLK cycle ) - In the virtex 5 userguide page 347 (figure 8-15) I see an example and it would seem I should see D1 at the first edge of CLK after 1 CLKDIV has passed ... So that would be t = 12.5 ns ( captured at t=0ns, the first rising edge of CLKDIV after I set the data, then wait 1 CLKDIV, then the first edge of CLK is a falling one, at 12.5 ns ) - When I do a simulation, I see the data at t = 5 ns ... So can someone shed some light on the situation please ? Thanks, SylvainArticle: 123515
"selva kumar" <vkmselva@gmail.com> wrote in message news:1188394422.404984.221600@r23g2000prd.googlegroups.com... > I'd like to set up block rams(16k) to acts as a ROM lookup table after > initialization. After establishing the Memory Area as an FPGA > resource there's an option to initialize it by using memory eritor. > However, this would be very time consuming, as my memory is 16Kwords > deep. Is there some way to just reference an external text file, or > excel sheet at least automatically read/paste an external file for > this purpose? > Hi, Google 'data2mem' . Or, look up the BlockRAM in the libraries guide and learn how to initialise it in your HDL. HTH., Syms.Article: 123516
On Aug 29, 9:33 am, selva kumar <vkmse...@gmail.com> wrote: > I'd like to set up block rams(16k) to acts as a ROM lookup table after > initialization. After establishing the Memory Area as an FPGA > resource there's an option to initialize it by using memory eritor. > However, this would be very time consuming, as my memory is 16Kwords > deep. Is there some way to just reference an external text file, or > excel sheet at least automatically read/paste an external file for > this purpose? > > and also How to combine both block memory and distributed memory > (using lut) to use as one memrory of 16k? Taking a guess, sounds like you are programming for a Xilinx device. If so, you can use Xilinx's ISE's coregen (Core Generator) to create a 16KW Block Ram. Go under Memories -> RAM & ROM -> Block Memory Generator. Through the wizard there will be a option to initialize the memory using the values from a text file.Article: 123517
JimboD2@gmail.com wrote: > > Also, some info i may not have given initially: Im using the xilinx > reset module typically instantiated with EDK. It's driving my plb and > opb bus resets. As far as i can tell, the plb reset is the only reset > signal going to the plb_ddr2 core. > Could the reset signal not be the proper length/format for the DDR controller? I just mention this because I had a DSOCM design where using the sys_rst_s signal didn't work, but did when I switched it to sys_bus_reset.Article: 123518
On Aug 29, 6:33 am, selva kumar <vkmse...@gmail.com> wrote: > I'd like to set up block rams(16k) to acts as a ROM lookup table after > initialization. After establishing the Memory Area as an FPGA > resource there's an option to initialize it by using memory eritor. > However, this would be very time consuming, as my memory is 16Kwords > deep. Is there some way to just reference an external text file, or > excel sheet at least automatically read/paste an external file for > this purpose? > > and also How to combine both block memory and distributed memory > (using lut) to use as one memrory of 16k? If you are using Verilog and XST for synthesis, you can use $readmemh or $readmemb to intialize the memory from a file at compile time. HOWEVER... I currently have a WebCase pending with Xilinx. XST occassionally crashes when I do this with the dreaded Portability error message. Very helpful. So - use this with caution, XST may cause you grief. One workaround I've used (yuck) is to add a second port to the memory (write port) and tie its write enable and address to 0. Good luck, John ProvidenzaArticle: 123519
On Aug 29, 9:22 am, Jeff Cunningham <j...@sover.net> wrote: > Jimb...@gmail.com wrote: > > > Also, some info i may not have given initially: Im using the xilinx > > reset module typically instantiated with EDK. It's driving my plb and > > opb bus resets. As far as i can tell, the plb reset is the only reset > > signal going to the plb_ddr2 core. > > Could the reset signal not be the proper length/format for the DDR > controller? I just mention this because I had a DSOCM design where using > the sys_rst_s signal didn't work, but did when I switched it to > sys_bus_reset. Ok, I think I found a fix. Setting the "autocalibration" option to false on both of my DCMs to the DDR2 core seems to have solved the problem. ( See this post: http://groups.google.com/group/comp.arch.fpga/msg/c6707d13feb794ad?hl=en&)Article: 123520
"Zorjak" <Zorjak@gmail.com> wrote in message news:1188286393.929728.116820@d55g2000hsg.googlegroups.com... > > You se that I have one output pin called "test". It has only one > driving 'Z' (end of the process). But in my compilaton report I have > the same waring as with bidir pin. (Pin test has Vcc driving its > datain port). It's like that there is no problem if the pin is > biderctional or not. It is something with this "High Impedanse" as I > seee it. I am not shure about anything. > Move your test <= Z line out of the process. Remember that a process fires only when there is an event on any of the signals on its sensitivity list. The processes are mostly used for describing synchronous circuits such as flip-flops. When combinatorial processes are used as is the case in your design it is very easy to get confused and synthesize something totally unexpected. When you do use processes remember to define default values for all the signals/variables... /MikhailArticle: 123521
On Aug 28, 6:35 am, Paul Leventis <paul.leven...@gmail.com> wrote: > Hello Sanjay, > > Our experience is that the PLL's power consumption is fairly low as > compared to the clock network it is driving in most cases. To get a > sense for the amount of power the PLL consumes as a function of the > VCO frequency, download a copy of the Early Power Estimator > spreadsheet for the device you are interested in (http://www.altera.com/support/devices/estimator/pow-powerplay.jsp). > > For a more detailed analysis, grab a copy of Quartus and fire up a toy > design with the PLL in it, and run it through the PowerPlay Power > Analyser. The PLL models for 90 nm and 65 nm devices take into > account your VCO frequency, M/N values, and counter settings. > > Regards, > > Paul Leventis > Altera Corp. I tried to use the Altera spreadsheet for Stratix3 device as that is what I am targetting at present. It seems like the PLL power requirement changes only with the VCO frequency. But I am guessing this does not say much as the VCO frequency will change depending upon the input frequency assuming output frequency is kept the same.Article: 123522
selva kumar <vkmselva@gmail.com> wrote: >Hi, > I'd like to set up block rams(16k) to acts as a ROM lookup table >after initialization. After establishing the Memory Area as an FPGA >resource there's an option to initialize it by using memory eritor. >However, this would be very time consuming, as my memory is 16Kwords >deep. Is there some way to just reference an external text file, or >excel sheet at least automatically read/paste an external file for >this purpose? You can initialize the memory from the UCF file. You can write a program which outputs the initialisers in UCF format and paste these into the UCF file. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 123523
On Aug 29, 3:13 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
> Jim,
>
> On 2007-08-28, Jim Lewis <j...@synthworks.com> wrote:
>
> |------------------------------------------------------------------------=
--=AD|
> |"Weng, =
|
> |[..] =
|
> | =
|
> |[..] =
|
> | =
|
> |I noted that in your code you mixed orif mixed with elsif (copied below)=
, |
> |was this intentional? One hand, these could convey exactly what I want =
|
> |(because there are many cases like this), OTOH, it could be a mistake. =
|
> |Hence the intent is ambiguous and during a design review, one would have=
|
> |to pay particular attention to this and ask questions about your intent =
|
> |and its validation. A copy of your code is below. =
|
> | =
|
> |If(E0 =3D '1') then =
|
> |State_A <=3D E0_S; =
|
> |Orif(E1 =3D '1') then =
|
> |State_A <=3D E_S; =
|
> |Orif(E2 =3D '1') then =
|
> |State_A <=3D E2_S; =
|
> |elsIf(E3 =3D '1') then =
|
> |State_A <=3D E3_S; =
|
> |Orif(E4 =3D '1') then =
|
> |State_A <=3D E4_S; =
|
> |Orif(E5 =3D '1') then =
|
> |State_A <=3D E5_S; =
|
> |elsIf(E6 =3D '1') then =
|
> |" =
|
> |------------------------------------------------------------------------=
--=AD|
>
> Yes,
>
> Weng really did intend to have both orif branches and elsif branches
> in a single if statement (seenews:1188325844.164564.136940@z24g2000prh.go=
oglegroups.com
> ). I think the intention would be clearer with different
> indentation. E.g.
> If(E0 =3D '1') then
> State_A <=3D E0_S;
> Orif(E1 =3D '1') then
> State_A <=3D E_S;
> Orif(E2 =3D '1') then
> State_A <=3D E2_S;
>
> elsIf(E3 =3D '1') then
> State_A <=3D E3_S;
> Orif(E4 =3D '1') then
> State_A <=3D E4_S;
> Orif(E5 =3D '1') then
> State_A <=3D E5_S;
> elsIf(E6 =3D '1') then
> --...
>
> |------------------------------------------------------------------------=
--=AD|
> |"[..] =
|
> | =
|
> |[..] The danger in adding new keywords is that they may =
|
> |conflict with a name (signal, ...) already used in someone's design =
|
> |and cause an old design to be a syntax error in the new language =
|
> |revision. This generally does not please people and means they =
|
> |have to add special handling for the file (compile flags). =
|
> | =
|
> |[..]" =
|
> |------------------------------------------------------------------------=
--=AD|
>
> A newly introduced reserved word would be guaranteed to not conflict
> with old code by not being possible to misinterpret as a basic
> identifier (basic_identifier ::=3D letter { [ underline ]
> letter_or_digit), e.g. by starting with an underline or by containing
> a percentage sign.
>
> Best regards,
> Colin Paul
Hi Colin,
Thank you for your support.
You are the first big canon who gave full support behind the keyword
'orif' and gets full understanding of its meaning.
My fighting for 'orif' recognition is not for my personal purpose, it
is in the interest of HDL industry and academic world.
You help clear up 3 things:
1=2E Indent two separate mutually exclusive groups to avoid confusion.
I have never thought about it.
2=2E "Weng really did intend to have both orif branches and elsif
branches
in a single if statement "
I have really done it in 'orif' definition:
"Where keyword 'elsif' can be used in a VHDL code, there keyword
'orif' can be used.", but failed to mention that directly. It seems to
me that it is a reality and may never be mentioned specifically.
I thought that "if...elsif..." statement structure was created by IBM
in 1953 when designing Fortran language to meet software requirements:
sequential comparison, one after another.
In hardware world, HDL language must have a similar mainstream
language structure to meet the 0-1 out of N selections in parallel.
That was where keyword 'orif' came from.
In my experiences, 'orif' is much easier than zero_one_hot() to use in
practise in the same way as engineers rarely use single signal names
to replace equations in if() or elsif().
3=2E "A newly introduced reserved word would be guaranteed to not
conflict
with old code"
Jim's opinion is that if you introduce a new keyword 'orif', then even
though 'orif' doesn't conflict with 'elsif', but it certainly would
conflict with old signal name orif. This can never be avoided. But his
new function name zero_one_hot() still has the same possibility to
conflict with old signal function name zero_one_hot() if someone had
used it before, but he never mentioned his same possibility.
I would like to add more information.
1=2E 'case' statement is a special case with keyword 'orif', in other
words, all 'case' statement can be written using keyword 'if...orif'
structure.
Example:
case two_bits is
when "00" =3D>
...
when "01" =3D>
...
when "10" =3D>
...
when others =3D>
...
end case;
if(two_bits =3D "00") then
...
orif(two_bits =3D "01") then
...
orif(two_bits =3D "10") then
...
else <-- equivalent to "when others =3D>"
...
end if;
2=2E Andy mentioned that he may be able to find something that is beyond
the capability of 'orif', but within capability of zero_one_hot().
Andy, you never have a chance to do so with signals.
Reason: you have to implement an assign statement to reflect their
mutually exclusive property, then you must use one of two conditional
branch statements: case statement or if statement that are within
'orif' range.
Mutually exclusiveness is not used for combinational signals.
I don't have any idea if mutually exclusive property applies to
variables.
3=2E As keyword 'orif' definition says, 'orif' only provides information
about mutually exclusive property among a group of conditions.
Compilers can do what they think is the best strategy as they want.
But for FPGA, the 'orif' perfectly refers to carry chain structure in
both Xilinx and Altera (I am not familiar with other FPGA products),
it is a wonderful thing, but should not be a burden or a blame, as
Jonathan indicated.
Weng
Article: 123524<markus.jank@de.bosch.com> wrote in message news:1188382135.257124.155580@r29g2000hsg.googlegroups.com... > > I have the problem that when I change in a state machine a signal, Clarify please what kind of signal and how you change it. > then the design doesn't function any more. Again, what exactly do you mean here? You can try using directed routing when adding your debugging stuff (again, what is it?) to preserve the failing path(s). /Mikhail
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